B.Tech.

, 5th Semester, Solved papers, Dec 2015 81

MICROPROCESSING & INTERFACING

Dec 2015
Paper Code: EE-309-F

Note: Attempt five questions in all, selecting one question from each section. Q. No. 1 is
compulsory.
Q.1.(a) Define Memory Segmentation. (4)
Ans. Memory segmentation is the division of a computer’s primary memory into segments
or sections. In a computer system using segmentation, a reference to a memory location includes
a value that identifies a segment and an offset within that segment. Segments or sections are
also used in object files of compiled programs when they are linked together into a program
image and when the image is loaded into memory.
Some of the advantages of memory segmentation in the 8086 are as follows:
(i) With the help of memory segmentation a user is able to work with registers having
only 16-bits.
(ii) By memory segmentation the various portions of a program can be of more than
68kb.
(iii) The data and the users code can be stored separately allowing for more flexibility.
(iv) Also due to segmentation the logical address range is from 0000H to FFFFH the
code can be loaded at any location in the memory.
Q.1.(b) Describe the purpose of program Counter in 8085. (4)
Ans. Program counter is a 16 bit resistor. This resistor is a memory pointer. The function
of program counter is to point to the memory location from which the next instruction is to be
executed. When a program is to be executed, it is first entered into the memory locations. Now
the program counter is loaded by the address of the first instruction to be executed. Once the
first instruction is executed, the program counter is automatically incremented to point to the
address of next instruction. The process is repeated till the end of the program.

Q.1.(c) Describe the purpose of Trap flag in 8086. (4)

Ans. The trap flag (TF) : Setting TF puts the processor into single step mode for
debugging. In single stepping, microprocessor executes a instruction and enters into single step
ISR.
After that user can check registers or memory contents, if found ok, he/she will proceed
further, else necessary action will be taken. This utility is, to debug the program. If
TF = 1, the CPU automatically generates an internal executes instruction by instruction, allowing
a program to be inspected as it executes instruction by instruction.
Used by debuggers for single step operation.
TF = ‘1’ – Trop on, TF = ‘0’ – Trap off.

Q.1.(d) Explain Register Addressing Mode in 8086. (4)

Ans. Register addressing mode : In this mode of addressing, data is in the register,
and instruction specifies the particular register as shown in Fig.
82 Microprocessing & Interfacing

This addressing mode is normally preferred because the instructions are compact and
fastest executing of all instruction forms. The reason why it is fastest executing is just because,
all the register reside on chip, therefore data transfer is within the chip and external bus is not at
all required.

Instruction
Opcode Register Address R
Registers

Operand

Fig. : Register addressing

Registers may be used as source operands, destination operands or both.

The register may be 8/16 bit.
e.g. MOV AX, BX
The instruction copies the contents of BX register to AX register.

Q.1.(e) What is programmable Interval Timer. (4)

Ans. There are two types of programmable interval timer are generally used. Intel 8253
is a programmable Interval Timer/Counter which can generate accurate time delays and
waveforms ranging from 0 Hz to 2 MHz using software control. 8254 is its upgraded version
which can operate with higher clock frequency range (DC – 8 MHz) and it is pin to pin compatible
with 8253.

Unit – I

Q.2.(a) Explain the purpose of following instructions in 8085.

(i) RIM
(ii) SIM
(iii) RRC
(iv) XCHG
(v) DADRp (10)
Ans. (i) RIM : Read interrupt mask.
This is multipose instruction used to read the status of interrupts RST 7.5, RST 6.5,
RST 5.5, and read serial data input pin. The instruction loads 8 bits in the accumulator in the
following format.
B.Tech., 5th Semester, Solved papers, Dec 2015 83

Fig. : RIM Instruction format

(ii) SIM : Set interrupt mask.
This is a multipurpose instruction used to control interrupts and serial data output
pin. The instruction interprets the accumulator contents as follows :

Fig. : SIM Instruction format

(iii) RRC : Rotate accumulator right.
This instruction rotates the contents of accumulator right by 1 bit. D7 will be transferred
to D6, D6, to D5 and so on D1 to D0, D0 to D7 as well as to the carry flag.

Fig. : RRC Instruction format

Operation : Accululator : Dn 1  Dn ( n  0 to 6)
D0  D7 , D0  Cy

(iv) XCHG : Exchange the contents of HL, with DE pair.

This instruction exhanges contents of H reg. With D reg. and L reg. With E reg.
Operation : H  D, L  E
84 Microprocessing & Interfacing

(v) DADRp : Add the specified register pair to HL pair.

This instruction adds the contents of specified register pair to HL pair and stores the
result in HL pair. The example of Rp are SP, BC, DE and HL. Only carry flag is modified to
reflect the result of operation.
Operation : RP + HL  HL

Q.2.(b) Subtract the 16 bit number in memory locations 2002H and 2003H from
the 16 bit number in memory locations 2000H and 2001H. The most significant eight
bits of the two numbers are in memory locations 2001H and 2003H. Store the result in
memory location 2004H and 2005H with the most significant byte in memory location
2005H. (10)
Ans. Sample problem
(2000H) = 19H
(2001H) = 6AH
(2002H) = 15H
(2003H) = 5cm
Result = 6A 19H–5C 15H= OE04H
(2004H) = 04H
(2005H) = OEH
B.Tech., 5th Semester, Solved papers, Dec 2015 85

Program
LHLD 2000H  Get first 16 bit number in HL.
XCHG  Save first 16 bit number in DE.
LHLD 2002H  Get second 16 bit number.
MOV A, E  Get lower byte of the first number.
SUB L  Substract lower byte of the second number.
MOV L, A  Store result in L register.
MOV A, D  Get higher byte of the first number.
SUB H  Subtract higher byte of second number with borrow.
MOV H, A  Store 16 bit result in memory locations 2004H and 2005H.
SHLD 2004  Store 16 bit result in memory locations 2004H and 2005H.
HLT  Terminate program execution.

Q.3.(a) Explain pin diagram of 8085 and describe various signals. (10)
Ans. Refer Q.3(b) of paper Dec. 2011.

Q.3.(b) Discuss in detail 8085 interrupts. (10)

Ans. Refer Q.3(a) of paper Dec. 2011.

Unit – II

Q.4.(a) Explain flag manipulation instruction of 8086 in detail. (10)

Ans. Refer Q.5(b) of paper Dec. 2011.

Q.4.(b) Describe 8086 Microprocessor architecture with its block diagram.(10)

Ans. Refer Q.4(a) of paper Dec. 2011.

Q.5.(a) Explain instructions formats of 8086 microprocessor in detail. (10)

Ans. Refer Q.5(a) of paper Dec. 2012.

Q.5.(b) Explain the purpose of EU and BIU in 8086. (10)

Ans. BUS Interface Unit (BIU) : The BIU interface 8086 to the outside word. It
provides a
full 16 bit bidirectional data bus and 20bit address bus. The BIU is responsible for performing all
external bus operations as given below :
(i) It sends address of the memory or I/O.
(ii) It fetches instruction from memory.
(iii) It reads data from port/memory.
(iv) It writes data into port/memory.
(v) It supports instruction queuing.
(vi) It provides the address location facility.
The BIU has a dedicated order. The main function of this order is to produce 20 bit
physical address. The bus control logic of the BIU generates all bus control signals such as
READ and WRITE for memory and I/O.
86 Microprocessing & Interfacing

Instruction Queue : To speed up program execution, the BIU fetches six instruction
bytes ahead of time from memory. These prefetched instruction bytes are held for the execution
unit in a group of registers called queue. With the help of queue it is possible to fetch next
instruction while current instruction is in execution. There are number of instructions in 8086
which need a quite large number of clock cycles for execution. During this execution time the
BIU fetches the next instruction or instructions from memory into the instruction queue instead
of remaining idle. The BIU continues this process as long as the queue is not full. Due to this,
execution unit gets, the ready instruction in the queue and instruction fetch time is eliminated
(while decoding or executing an instruction EU does not requir e use of the
buses).
This system has the advantage over the 8085 because, while the EU is executing an
instruction, the BIU is fetching and storing in the queue the next instructions.
The BIU’s instruction queue is based on first in first out (FIFO). So that the EU gets the
instructions for execution in the order they are fatched. If the queue is full and EU does not
request BIU for accessing memory, the BIU does not perform any bus cycle. On the other hand,
if the queue is not full and even through the EU does not request BIU for accessing the memory
the BIU can fill the queue on its own. If the EU interrupts the BIU, the BIU Ist completes the
prefetching and then attains to the service of the EU.
In case of JUMP and CALL instruction, instruction already fetched in queue are of no
use. Hence, in these cases queue is dumped and newly formed by loading instructions from new
address specified by JUMP or CALL instruction.
Execution Unit (EU) : The EU of 8086 tells the BIU from where to fetch instructions
or data, decodes instrcuction and executes instructions. It contains :
(i) Control Circuitary
(ii) Instruction Decoder
(iii) Arithmetic Logic Unit (ALU)
(iv) Flag register
(v) General purpose registers.
(vi) Pointers and Index registers.
The central circuitry in the EU directs the internal operation. A decoder in the EU
translates the instructions fetched from memory into a series of actions which the EU performs.
ALU is 6 bit. If can add, subtract, AND, OR, XOR, increment, decrements complement and
shift binary numbers.
More about Queue : In the beginning, the CS : IP is loaded with the required address
from which the execution is to be started. In the initial condition the queue will be empty and the
microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code, if
the CS : IP address is odd, and two bytes at a time, if the CS : IP address is even. The first byte
is a complete opcode in case of some instructions(one byte opcode instructions), the remaining
part of opcode may lie in the second byte. But invariably the first byte of an instruction is an
opcode. These opcodes along with data are fetched and arranged in the queue. When the first
byte from the queue goes for decoding and interpretation, one byte in the queue becomes empty
and subsequently the queue is up dated.
(i) The microprocessor does not perform the next fetched operation till at least two
bytes of the instruction queue are emptied. The instruction execution cycle is never broken for
B.Tech., 5th Semester, Solved papers, Dec 2015 87

fetch operation. After decoding the first byte the decoding circuit decides whether the instruction
is of single opcode byte or double opcode byte. If the single opcode bytes, the next bytes are
treated as data bytes depending upon the decoded instruction length. Otherwise, the next byte in
the queue is treated as the second byte of the instruction opcode.
(ii) The queue is updated after every byte is read from the queue but the fetch cycle is
entreated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently
executing the fetched instructions. Fig. shows the queue operation.

Fig : Queue operation

Unit – III

Q.6.(a) Write the purpose of following instruction in 8086 with example. (10)
(i) LOOP
(ii) RET
(iii) AAM
(iv) MOVSB
Ans. (i) LOOP : This instruction is used to repeat a series of instructions some number
of times. The number of times the instruction sequence is to be repeated is loaded into CX. Each
time loop executes CX is decremented by 1.
 If CX  0 execution will jump to destination specified by label.
 If CX = 0 execution will go to the next instruction after loop.
(ii) RET : It POPs a word (16–bit) from the top of the stack into the IP (near return)
and places it in Ip and CS or 32–bit number (far return) and places it in IP and CS. The execution
starts where from it left the main program. Its object code is C3. The stack has 0003H = IP. CS
= 1000H. the new address = 10000H = 0003H in Fig.
88 Microprocessing & Interfacing

Fig. : Near RET

(iii) AAM : Numerical data coming into a computer from a terminal through keyboard is
usually in ASCH code. The numbers 0 to 9 are represented by ASCH codes 30 H to 39 H.
Before multiplying two ASCH digits, the upper nibble bits of each need to be masked.
This leaves unpacked BCD in each byte. After the two unpacked BCD digits are multiplied, the
AAM instruction is used to adjust the product of two unpacked BCD digits in AX.
It works only on registor AL.
It is used after multiflying the two unpacked BCD numbers.
(iv) MOVSB (Move string) : This instruction copies a byte or a word from a location
in the data segment to a location in the extra segment.
The offset of the source byte/word in the DS must be SI register.
The offset of the destination in ES must be in DI register.
After byte or word is moved, SI and DI are automatically adjusted to point to the next
source and next destination.
Q.6.(b) Explain directives used in assembly language program ? (10)
Ans. Assumbler directories : Assumbler directives are statements which give direction
to the assembler to perform the task of assembly process. These are not translated into machine
code.
Commonly used assembler directive in 8086 assembly language programming are explained
below :
(i) ASSUME : The assume directive is used to tell the assembler the name of the logical
segment it should used for a specified segment. The statement ASSUME CS:CODE for example
tells the assembler that the instructions for a program are in a logical segment named CODE.
The statement ASSUME DS: DATA tells the assembler that for any program instruction which
B.Tech., 5th Semester, Solved papers, Dec 2015 89

refers to the data segment, it should use the logical segment called DATA. If, for example, the
assembler reads the statement MOV AX, [BX] after it reads this ASSUME, it will know that the
memory location referred to by [BX] is in the logical segment DATA.
(ii) ALIGN : The align directive is used to align the next segment at an address divisible
by specified number. The general syntax for this directive is as shown below :
ALIGN n
where n can be 2, 4, 8 or 16
(iii) CODE : The code directive is used to provide shortcut in definition of the code
segment. General syntax for this directive is as shown below :
.code [name]
The name is optional.
(iv) DATA : The data directive is used to provide shortcut in definition of the data
segment.
(v) GROUPS : A program may contain several segments of the same type i.e. code,
data, or stack. The purpose of the GROUP is to collect them all under one hut, so that they reside
within one segment, usually a data segment.
Format : Name GROUP Seg–name,......., Seg–name.
(vi) LENGTH : It is an operator which tells the assembler to determine the number of
elements in some named data item such as a string or array.
(vii)MACRO and ENDM : The macros in the program can be defined by MACRO
directive. ENDM directive is used along with the MACRO directive. ENDM defines the end of
the macro.
(viii) NAME : The name directive is used at the start of a source program to give
specific names, to each assembly module.
(ix) OFFSET : It is an operator which tells the assembler to determine the offset or
displacement of a named data item (variable) from the start of the segment which contains.
(x) ORG : It is an assembler that uses a location counter to account for its relative
position in a data or code segment.
Format : ORG expression
(xi) PAGE : The PAGE directive help to control the format of a listing of an assembled
program. At the start of a program the PAGE directive specifies the maximum number of lines
to list on a page and the maximum number of characters on a line.
Format : PAGE [length], [width]
(xii) ENDP : ENDP directive is used along with the PROC directive. ENDP defines
the end of the procedure.
(xiii) TYPE : It is an operator which tells assembler to determine the type of specified
variable. Assembler determines the type of specified variable in number of bytes. For byte type
variable the assembler gives a value of 1. For word type variable the assembler gives a value of
2 and for double word type variable the assembler gives a value of 4.

Q.7. Write an ALP of 8086 to add series of N 16 bit numbers. (20)

Ans. Program statement : Write an ALP to add a block of N numbers. Assume the
result to be 16 bit.
90 Microprocessing & Interfacing

Explanation :
 Consider that a block of N bytes is present at source location.
 Let the number of bytes N = 10 for example.
 We have to add these N bytes.
 We will initialize this as count in the CX register.
 We know that source address is in the SI register. This SI register will act as pointer.
 Clear the direction flag.
 Using ADD instruction add the contents, byte by byte of the block.
 Increment SI to point to next element.
 Decrement the counter and add the contents till all the contents are added.
 Result is stored in AX.

Fig. : Flowchart
B.Tech., 5th Semester, Solved papers, Dec 2015 91

Algorithm :
Step I : Initialise the data segment.
Step II : Initialise SI as pointer with source address.
Step III : Initialise CX register with count.
Step IV : Initialise direction flag to zero.
Step V : Add data, word by word.
Step VI : Increment pointer i.e. SI by 2 as 16 bit addition.
Step VII : Decrement counter CX.
Step VIII : Check for count in CX, if not zero goto step V
else goto step IX.
Step IX : Store the result of addition.
Step X : Stop.

Flowchart : Refer flowchart.

Program :

Label Instruction Comment

.model small
.data
series db 0111H, 0231H, 0341H, 0456H, 0578H,
06ABH, 0733H, 0845H, 0976, OA12H
count dw OAH
.code
mov ax, @data initialise data segment
mov ds, ax
mov ax, 0
mov si, offset blk 1 initialise pointer
mov cx, count initialise counter
cld df = 0
I1: add ax, [si] add numbers
inc si increment pointer
inc si increment pointer
dec count decrement counter
jnz l1 check if all nos are added
end
Result : AX = 39FCH
92 Microprocessing & Interfacing

Unit – IV

Q.8. Explain the working of 8255 in mode 2 and BSR Mode. Also explain how
the contents of control registers are interpreted in BSR and I/O mode. (20)
Ans. Working of 8255 in mode 2 : In this mode group A is used as input and output
i.e. for transmitting and receiving data from peripheral through 8255 as shown in fig.(a).
The transfer of data is achieved by port C handshake signals. The group B can be in
Mode 0 or Mode 1.
The bi-directional data is transferred through port A so it consists of input and output
latch.
The Mode 2 is combination of Mode 1 input and output both at a time to port A.
The interrupt signals of input and output mode are combined to generate common
interrupt signal to CPU. The internal organization of these signals is as shown in fig. (b).
The different handshake signals used are OBFA , ACK A ,STBA , IBFA and INTERA. 2
handshake signals are used for output operation, 2 are used for input operation and one is common
to both.
Output operation :
OBF (Output buffer full) : This is an active low output signal generated by 8255.
When CPU writes data to output port 8255 will enable OBF signal to indicate peripheral that
data is available in output buffer.

Fig. (a) : Mode 2 interfacing Fig. (b) : PA, PB and PC in mode 2

ACK (Acknowledge) : This is an active low input signal for 8255. When the peripheral
detects OBF signal, it reads data from 8255 port and makes ACK = 0 and the ACK signal is
used to acknowledge 8255 that data is read from port so 8255 will remove OBF signal to
indicate output buffer is empty.
B.Tech., 5th Semester, Solved papers, Dec 2015 93

Input operation :
STB (strobe) : This is an active low input signal. When the peripheral writes data to
input buffer, it generates a signal STB to indicate 8255 that it has written data.
IBF (Input buffer full) : When data is available in input buffer 8255 will enable IBF
signal to indicate that data is available in input buffer.
INTR (Interrupt request) : This is an output signal given by 8255 to request CPU
service.
The INTR is generated in two different conditions input and output.
The interrupt is generated for input mode when IBF = 1, STB = 1 and INTE1 = 1 and for
output mode when OBF = 1, ACK = 1 and INTE2 = 1. The INTE1 and INTE2 are set/reset using
BSR mode, port C bits used are PC6 and PC4 respectively.
The logical equation will be,
INTRA = INTE1.ACK A .OBFA  INTE 2 .STBA .IBFA
The timing diagram of Mode 2 bi-directional data transfer for data transfer from peripheral
to CPU and CPU to peripheral are as shown in Fig. (c).
The mode 2 also supports both modes of data transfer i.e. Interrupt drive I/O and status
driven I/O. The port C is used as status word and its definitions are as follows :
OBFA INTE1 IBFA INTE2 INTR A x x x

Fig. ( c) : Timing diagram of mode 2

Working of 8255 in BSR : The BSR is a Port C bit set reset mode. The mode used
eight bits of Port C only. The individual bit of Port C can be set or reset by writing control word
in the control register.
The control word format of BSR mode is as shown in Fig.(d)(i) and mode selection
formal is in fig.(d)(ii).
94 Microprocessing & Interfacing

The pin of Port C, i.e., Bit 0 to Bit 7 to set or rest is chosen using Bit select bits b3b2b1,
i.e., D3, D2 and D1, of control word register. The bit to set or reset is decided by bit S/R, i.e., D0.
The BSR mode affects only one bit of Port C at a time. The bit set using BSR mode remains set
unless and until you change the bit. The bit to be set/reset is decided by control word. So to set
any bit of Port C, bit pattern is loaded in control register. Even though a BSR mode is selected it
will not affect I/O mode.

D7 D6 D5 D4 D3 D2 D1 D0
0 X X X b3 b2 b1 S/R

Mode Mode Port C Port C bit

Bit select
b3 b2 b1 Set/Reset
0 0 0 Bit 0 1 = Set
0 = Reset
0 0 1 Bit 1
0 1 0 Bit 2
0 1 1 Bit 3
1 0 0 Bit 4
1 0 1 Bit 5
1 1 0 Bit 6
1 1 1 Bit 7

Fig : (d)(i )

Control Word :

D7 D6 D5 D4 D3 D2 D1 D0
I/O
I/O Mode

BSR Mode Mode 0 Mode 1 Mode 2

(bit Set Reset) Simple I/O Handshake I/O Bidirectional data
For Port C for ports for ports A and or B bus for port A
No effect on A, B and C Port C bits are used Port B : either in mode
I/O mode for handshake 0 or 1 Port C bits are
used for handshake

Fig : (d)(ii)

Q.9.(a) Explain pin diagram of 8237 DMA controller. (10)

Ans. Refer Q9(a) of paper Dec. 2014.
B.Tech., 5th Semester, Solved papers, Dec 2015 95

Q.9.(b) Explain BSR and I/O modes of 8255 PPI chips. (10)
Ans. BSR mode : It is a bit Set/Reset mode. This mode is concerned only with 8 bits of
port C. A control word with bit D7= 0 is recognized as BSR control word. It does affect any
previously transmitted control word with bit D7= 1 and thus the I/O operations of port A and port
B are not affected by a BSR control word. In the BSR mode, the individual 8 bits of port C can
be used for applications such as on/off switch.
BSR Control Word : The BSR control word written in the control register, sets or
resets one bit at a time as shown in fig.

Fig. : Bit Set/Reset Control Word

I/O modes : There are three I/O modes of operation :

(1) mode 0 – Basic I/O
(2) Mode 1 – Strobed I/O
(3) Mode 2 – Bi-directional I/O
The I/O modes are programmed using control register. The control word format of I/O
modes is as shown in fig.
Function of each bit is as follows :
(i) D7 : When the bit D7 = 1 then I/O mode is selected, if D7 = 0 then BSR mode is
selected . The function of bits D0 to D6 is dependent on mode (I/O mode or BSRmode).
(ii) D6 and D5 : In I/O mode the bits D6 and D5 specifies the different I/O modes for
group A i.e. Mode 0, Mode 1 and Mode 2 for port A and port C upper.
(iii) D4 and D3 : In I/O mode the bits D4 and D3 selects the port function for group A.
If these bits = 1 the respective port specified is used as input port. But if bit = 0, the port is used
as output port.
(iv) D2 : In I/O mode the bit D2 specifies the different I/O modes for group B i.e. Mode
0 and Mode 1 for port B and port C lower.
96 Microprocessing & Interfacing

(v) D1 and D0 : In I/O mode the bits D1 and D0 selects the port function for group B.
If these bits = 1 respective port specified is used as input port. But if bit = 0, the port is used as
output port.
From the above explanation you can observe that all the 3 modes i.e. Mode 0, Mode 1
and Mode 2 are only for group A ports, but for group B only 2 modes i.e. Mode 0 and Mode 1 are
provided.
When 8255 is reset, it will clear control word register contents and all the ports are set to
input mode. The ports of 8255 can be programmed for other modes by sending appropriate bit
pattern to control register.

Fig. : I/O modes control word format