Seat No.

: ________

Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTERIV(New) EXAMINATION SUMMER 2016

Subject Code:2141001
Subject Name:Microprocessor and Interfacing
Time:10:30 AM to 01:00 PM
1.
2.
3.

Date:30/05/2016
Total Marks: 70

Instructions:
Attempt all questions.
Make suitable assumptions wherever necessary.
Figures to the right indicate full marks.

------------------------------------------------------------------------------------------------------------------Reference Book:
B1) Title: Microprocessor Architecture, Programming, and Applications with the 8085
Auther: Ramesh Gaonkar
Publication: PENRAM (PRI)
Edition: 6th
B2) Title: Microprocessor and Interfacing
Auther: Douglas V Hall
Publication: Mc Graw Hill
Edition: Revised Second Edition.
PAPER SOLUSION
MARKS

Q.1

Short Questions
14
1
What is the use of bidirectional buffer in 8085?
Ans.1.
Bidirectional 8-bit buffer i.e. Data bus buffer is used to interface the 8259A to
the 8085 data bus. Control words and status information are transferred through
the data bus buffer.
2
Define the function of parity flag in 8085.
Ans.2. Parity flag is used to indicate the parity of result. If lower order 8-bits of the
result contains even number of 1s, the Parity Flag is set to one and for odd
number of 1s, the Parity Flag is reset i.e. zero.
3
What is clock signal?
Ans.3. The "clock" is the heart beat of any processor...
The processor executes one thing at "a time": the time is given by the clock.
The clock is just an oscillator running 0,1,0,1,0... Each time the clock changes
level, the processor executes ONE instruction.
4
Define machine cycle.
Ans.4. Machine cycle is defined as the time required completing one operation of
accessing memory, I/O or acknowledging an external request.

Usually machine cycle consists of 3 to 6 T-states. In this article let us discuss

about their different types and how they are being classified.

Types of machine cycle

There are various types of machine cycles which are classified based onStatus
signals (IO/M, S1 and S0) ,Control Signals (RD, WR, INTA).
The different types of machine cycle available in 8085 microprocessor are:
Opcode Fetch
Memory Read
Memory write
I/O Read
I/O Write
INTR Acknowledge
Bus Idle

Write instruction which rotate accumulator left with carry.

RAL
Rotate accumulator left through carry
Each binary bit of the accumulator is rotated left by one position through the
Carry flag.
Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least
significant position D0.
CY is modified according to bit D7.
Before Execution of RAL

After Execution of RAL

What is the value of SP after execution of PUSH D instruction. (SP=3000,

DE=8050).

Ans.6.

SP: 2FFE

7
Ans.7.

What is direct addressing mode? Give an example.

In this mode, the address of the operand is given in the instruction itself.
Example: LDA 2500 H
Load the contents of memory location 2500 H in accumulator
LDA is the operation.
2500 H is the address of source.

Accumulator is the destination.

How many bytes instruction HLT has?

Ans.8.

HLT is 1 byte Instruction.

How many T-States are required for LXI instruction?

Ans.9.

LXI Required 10 T-State.

10

If memory has 8192 memory locations, then how many address

lines are required?

Ans.10. If memory has 8192 memory locations, then 13 address lines are
required.
11
If the memory size is 256 x 1 bits. How many chips are required
to make up-to 1 Kbyte of memory?
Ans.11. For 1Kbyte of memory 4 numbers of memory size is required of
256 x 1 bits memory sizes each.
12
What is the total number of T-States required to execute below program.
MVI C,05H
Back: DCR C
JNZ Back
MVI C, 05 H
BACK DCR C
JNZ BACK

7 T-States
4 T-States
10 T-States

The first instruction initializes the loop counter and is executed only once
requiring only 7 T-States.
The following two instructions form a loop that requires 14 T-States to
execute and is repeated 32 times until C becomes 0.
Tdelay= TO+ TL
TO= 7 T-States Delay of the MVI instruction

13

TL= (14 X 32) -3 = 445 T-States 14 T-States for the 2 instructions repeated 32
times (0516= 3210) reduced by the 3 T-States for the final JNZ.
Tdelay= TO+ TL
= 7 + 445
= 552
Which interrupt has the highest priority?

Ans.13. TRAP interrupt has the highest priority

14

Explain the instruction: EI

Ans.14. EI: Enable Interupts.

The interrupt enable flip-flop is set and all interrupts are enabled. No flags are
affected. After a system reset or the acknowledgement of an interrupt, the
interrupt enable flipflop is reset, thus disabling the interrupts. This instruction
is necessary to reenable the interrupts (except TRAP).

Q.2.

(a)

Describe the instruction with example and also show the contents of
Register / memory locations before and after execution of instruction:
XTHL

Ans.

XTHL :

03
Exchange HL with top of stack

The contents of L register are exchanged with the location pointed out by the contents of
the SP.
The contents of H register are exchanged with the next location (SP + 1).

Q.2. (b)
04

Show the diagram to generate control signal using NAND gate in 8085.

Ans.
Generating Control signals: The Mp provides RD and WR signals to initiate read and
rite
cycle. Because these signals are used both for reading / writing memory or
reading writing an input/output device, it is necessary to generate separate read and write
signals for memory and I/O devices. 8085 provides IO/M signal to indicate that initiated
cycle is for I/O
device or for memory device. Using IO/M signal along with RD
and WR, it is possible to generate four signals shown below.
MEMR (Memory Read)
: To read data from memory
MEMW
(Memory Write)
: To write data in memory
IOR (I/O Read)
: To read data from I/O devices
IOW (I/o Write)
: To write data in I/O devices.

We know that for OR gate, When the both inputs are low then only output is low. The
signal IO/M signal goes low for memory operation. This signal is logically OR-ed with
RD and WR to get MEMR and MEMW signals. When both RD and IO/M signals go
low, MEMR signals in goes low. Similarly when both WR and ME/MW signal goes low.
To generate IO/R and IO/W signals for I/O operation, IO/M signal is first inverted and
then Logically OR-ed with RD and WR signals.

Same truth table can be implemented using 3:8 decoder.

In 8085 four control signals states can be represented by

1) Memory Read

2) Memory Write

3) IO Read

4) IO Write

Q.2 (c) Write 8085 assembly language program for Modulo-10 down counter. After count
00H, the count should go back to repeat the sequence. Provide 1 Sec delay between
count and display the count at an output port 01H. The clock frequency is 1 MHz.
Show timing calculations assuming suitable value of T states for various
instructions.
Ans.

Ref. Book: B1/Ch#8/Pg#285

OR

Q.2 (c) Write 8085 assembly language program to perform the following, a2 + b2,
where a and b are 8-bit binary numbers.
MVI B, Data#1

; Data #1 is stored in register B

MOV C, B

; Copy of Data #1 is made in register C

MVI D, Data#2

; Data #2 is stored in register D

MOV E,D

; Copy of Data #2 is made in register E

XRA A

; Accumulator content is cleared

Again: ADD B
DCR C
JNZ Again

; A2 is calculated by repeated Addition

07

MOV H, A

; Calculated A2 value is stored in register H

XRA A

; Accumulator content is cleared

Loop: ADD D
DCR E

; B2 is calculated by repeated Addition

JNZ Loop
ADD H
content H

; A2+ B2 is determined, by adding result in A and register

STA 4200H

; Result is stored in memory location 4200H

Q.3

(a)

Sr.

Compare memory mapped I/O and I/O mapped I/O.

I/O mapped I/O

Memory mapped I/O

No.

IO is treated IO.

IO is treated as memory.

16-bit device address

Data transfer between any

purpose register and I/O port.

The memory map (64K) is shared

between I/O device and system memory

More hardware is required to decode 16bit address

Arithmetic or logic operation can

directly performed with I/O data

Memory Instructions are used.

Memory control signals are used.

Arithmetic and logic operations can be

performed on data.

10

Ans.

8-bit device address

general-

Data transfer b/w register and IO.

Q.3. (b)

03

be

Data is transfer only between accumulator

and I.O port.
The I/O map is independent of the memory
map; 256 input device and 256. output
device can be connected
Less hardware is required to decode 8-bit
address
Arithmetic or logical operation cannot be
directly performed with I/O data
Special Instructions are used like IN, OUT.

Special control signals are used.

Arithmetic and logic operations can not be

performed on data.
Data transfer b/w accumulator and IO.

Show only memory map for the 8085 microprocessor such that it should
contain 8 kbyte of EPROM and 8 kbyte of RAM.
04

8Kbyte of EPROM and 8Kbyte of RAM required 13 address line. (213= 8192 =
8Kbyte)

Memory
ICs

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address

Starting
address
of 8KB

0000H

1FFFH

2000H

3FFFH

EPROM
End
address
of 8KB
EPROM
Starting
Address
of 8KB
RAM
End
address
of 8KB
RAM
Q.3

(c)

Draw timing diagram for DAD instruction.

07

OR

Q.3

(a)

What is the difference between absolute decoding and linear decoding.

Explain with example.

03

Memories can be interfaced in two ways:

1. Absolute / Complete / full decoding (exhaustive decoding):
IN Absolute decoding technique, all the higher address lines are decoded to select the
memory chip, and memory chip is selected only for the specified logic levels on these
higher order address line; no other logic levels can select the chip.
Figure shows the memory interface with absolute decoding. This addressing technique
is normally used in large memory systems.
Memory Map:
Memory
ICs

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address

Starting
address
of

0000H

03FFH

2000H

23FFH

EPROM
End
address
of
EPROM
Starting
Address
of RAM
End
address
of RAM

2. Linear / Partial decoding:

In small systems, hardware for the decoding logic can be eliminated by using
individual high- order address lines to select memory chips. This referred to as linear
decoding.
Figure shows the addressing of RAM with Linear decoding technique. This technique is
also called Partial Decoding.
It reduces cost of decoding circuit, but it has a drawback of multiple addresses.
9shadow addresses)
Following figure shows the addressing of RAM with lines decoding technique. A15
address line is directly connected to the chip select signal of EPROM and after
inversion it is connected to the chip select signal of RAM. Therefore, when the status
of A15 line is 'one' RAM gets selected.
The status of the other address lines is not considered, since those address lines are
not used for generation of chip select signals.

Memory
ICs

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address

Starting
address
of

0000H

03FFH

8000H

83FFH

EPROM
End
address
of
EPROM
Starting
Address
of RAM
End
address
of RAM

Q.3

(b)

Draw memory system and show memory map for the microprocessor 04
system such that it should contain 2 kbyte of EPROM and 2 kbyte of
RAM with starting addresses 0000H and 6000H

Ans.

EPROM ans RAM are of size 2Kbyte, so it required 211=2048 =2Kbyte, 11 address
lines.

Memory Map:
Memory
ICs

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address

Starting
address
of 2KB

0000H

07FFH

6000H

67FFH

EPROM
0000H
End
address
of 2KB
EPROM
Starting
Address
of 2KB
RAM
6000H
End
address
of 8KB
RAM

Q.3

(c)

Draw timing diagram for STA instruction.

07

STA means Store Accumulator -The contents of the accumulator is stored in the
specified address(526A).
The opcode of the STA instruction is said to be 32H. It is fetched from the memory
41FFH(see fig). - OF machine cycle
Then the lower order memory address is read(6A). - Memory Read Machine Cycle
Read the higher order memory address (52).- Memory Read Machine Cycle
The combination of both the addresses are considered and the content from accumulator
is written in 526A. - Memory Write Machine Cycle
Assume the memory address for the instruction and let the content of accumulator is
C7H. So, C7H from accumulator is now stored in 526A.

Q.4

(a)

Draw control word format for Bit Set/Reset for 8255 IC.

03

Ans.
Bit set/reset Mode (BSR Mode).
The Bit Set/Reset (BSR) mode is applicable to port C only. Each line of port C (PC 0 - PC7) can
be set/reset by suitably loading the control word register. BSR mode and I/O mode are
independent and selection of BSR mode does not affect the operation of other ports in I/O mode.

D7 bit is always 0 for BSR mode.

Bits D6, D5 and D4 are don't care bits.

Bits D3, D2 and D1 are used to select the pin of Port C.

Bit D0 is used to set/reset the selected pin of Port C.

Selection of port C pin is determined as follows:

B3 B2 B1 Bit/pin of port C selected
0

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

As an example, if it is needed that PC5 be set, then in the control word,

1. Since it is BSR mode, D7 = '0'.
2. Since D4, D5, D6 are not used, assume them to be '0'.
3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
4. PC5 has to be set, hence, D0 = '1'.

Thus, as per the above values, 0B (Hex) will be loaded into the Control Word Register (CWR).
D7 D6 D5 D4 D3 D2 D1 D0
0

Q.4

(b)

Write a program to initialize 8255 in the configuration given below:

Port A as simple input, Port B as simple output, Port CL as output and Port CU as
input. Assume address of the control word register of 8255 as 83H.
Ans.

04

Required MD control word:

Required program segment for the configuration:

MVI A, 98H
OUT 83H
Q.4 (c)

Consider that 4 LEDs are connected to port CL of 8255 chip. Address of

port C is 82H and control register is 83H. Write a program to flash 4 LEDs
10 times. Assume persistence of vision to be 0.1 seconds. Consider operating
frequency 2.5 MHz.
07

LXI SP, 2000 H

MVI A, 90H
OUT 83H
BACK:
IN PA : [Read status
ANI 01
JNZ BACK
MVI B, 0AH
AGAIN:
MVI A, 00H
OUT 82H
CALL Delay
MVI A, FFH
OUT 82H
CALL Delay
DCR B
JNZ AGAIN
JMP BACK
Delay subroutine:
Delay:
LXI D, Count
Back:
DCX D
MOV A, D

: Initialize stack pointer

: Initialize 8255
: of push
: button]
: Initialize counter
: Load data to light LEDs
: Send data on port C
: Call. Delay of 0.1 sec
: Load data to switch off LEDs
: Send data on port C
: Call Delay of 0.1 sec
: Decrement count
: If not zero repeat
: Jump back to read status

ORA E
JNZ Back
RET

OR
Q.4

(a)

Draw control word format for I/O mode of 8255.

03

Q.4

(b)

Write a BSR control word subroutine only to set PC7 and PC3 and reset
them after 10ms delay. (do not calculate for delay)
04

Ans.

Ref. Book: B1/Ch#15/Pg#467

Q.4

(c)

Write a program to generate square wave using digital to analog converter

0808.

Q.5

(a)

07

State any three features of 8259 programmable interrupt controller. 03

Ans. The 8259A is a programmable interrupt controller designed to work with Intel
microprocessor 8080 A, 8085, 8086, 8088.
The 8259 A interrupt controller can
1) Handle eight interrupt inputs. This is equivalent to providing eight interrupt pins on
the processor in place of one INTR/INT pin.
2) Vector an interrupt request anywhere in the memory map. However, all the eight
interrupt are spaced at the interval of either four or eight location. This eliminates
the major drawback, 8085 interrupt, in which all interrupts are vectored to
memory location on page 00H.
3) Resolve eight levels of interrupt priorities in a variety of modes.
4) Mask each interrupt request individually.
5) Read the status of pending interrupts, in service interrupts, and masked interrupts.
6) Be set up to accept either the level triggered or edge triggered interrupt request.
7) Mine 8259 as can be cascade in a master slave configuration to handle 64 interrupt

inputs.
Q.5 (b)

What are the function of below pins of 8251 USART

04

1. DSR', DTR', RTS', CTS'.

Ans.
1. DSR (Input terminal):
This is an input port for MODEM interface. The input status of the terminal can be
recognized by the CPU reading status words.
2. DTR (Output terminal):
This is an output port for MODEM interface. It is possible to set the status of DTR by a
command.
3. RTS (Output terminal):
This is an output port for MODEM interface. It is possible to set the status RTS by a
command.
4. CTS (Input terminal):
This is an input terminal for MODEM interface which is used for controlling a transmit
circuit. The terminal controls data transmission if the device is set in "TX Enable" status
by a command. Data is transmitable if the terminal is at low level.
Q.5 (c)

Draw and explain the functional block diagram of 8253 timer IC.

07

Ans.
Fig. shows the block diagram of 8253/54. It includes three counters, a data bus buffer,
Read/Write control logic, and a control register. Each counter has two input signals
CLOCK and GATE and one output signal OUT.

Data Bus Buffer :

This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the system
data bus. The Data bus buffer has three basic functions.
1. Programming the modes of 8253/54.

2. Loading the count registers.

3. Reading the count values.
Read/Write Logic: The Read/Write logic has five signals : , , and the address
lines A0 and A1. In the peripheral I/O mode, the , and signals are connected to
and , respectively. In memory-mapped I/O, these are connected to and
. Address lines A0 and A1 of the CPU are usually connected to lines A0 and A1
of the 8253/54, and is tied to a decoded address. The control word register and
counters are selected according to the signals on lines A0 and A1 .
A1
A0
Selection
0
0
Counter 0
0
1
Counter 1
1
0
Counter 2
1
1
Control Word Register
Control Word Register: This register is accessed when lines A 0 and A 1 are at logic 1.
It is used to write a command word which specifies the counter to be used (binary or
BCD), its mode, and either a read or write operation.
Counters: These three functional blocks are identical in operation. Each counter consists
of a single, 16 bit, pre-settable, down counter. The counter can operate in either binary or
BCD and its input, gate and output are configured by the selection of modes stored in the
control word register. The counters are fully independent. The programmer can read the
contents of any of the three counters without disturbing the actual count in process.
OR
Q.5

(a)

State any three features of Intel 8086 Microprocessor.

03

Ans.
o 8086 is a 16bit processor. Its ALU, internal registers works with 16bit binary
word
o 8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits
or 8 bit at a time
o 8086 has a 20bit address bus which means, it can address upto 220 = 1MB
memory location
o Frequency range of 8086 is 6-10 MHz
(b)
Ans.

What are the advantages of Memory segmentation in 8086

04

Ref. Book: B2/Ch#2/Pg#2.14

(c)

Draw and explain the functional block diagram of interrupt controller IC

8259.

07
Ans.
The 8259A is a Programmable interrupt controller designed to work with Intel
microprocessor 8080 A, 8085, 8086, 8088.
The 8259 A interrupt controller can
1) Handle eight interrupt inputs. This is equivalent to providing eight interrupt pins on
the processor in place of one INTR/INT pin.

2) Vector an interrupt request anywhere in the memory map. However, all the eight
interrupt are spaced at the interval of either four or eight location. This
eliminates the
major drawback, 8085 interrupt, in which all interrupts are vectored to memory location
on page 00H.
3) Resolve eight levels of interrupt priorities in a variety of modes.
4) Mask each interrupt request individually.
5) Read the status of pending interrupts, in service interrupts, and masked interrupts.
6) Be set up to accept either the level triggered or edge triggered interrupt request.
7) Mine 8259 as can be cascade in a master slave configuration to handle 64 interrupt
inputs.
Functional Description:
The 8259 A has eight interrupt request inputs, TR2 IR0. The 8259 A uses its INT output
to interrupt the 8085A via INTR pin. The 8259Areceives interrupt acknowledge pulses
from the at its input. Vector address used by the 8085 A to transfer control to the service
subroutine of the interrupting device, is provided by the 8259 A on the data bus. The
8259A is a programmable device that must be initialized by command words. After
initialization the 8259 A mode of operation can be changed by operation command
words from the microprocessor.

Data bus buffer: This 3- state, bidirectional 8-bit buffer is used to interface the 8259A to
the system data bus. Control words and status information are transferred through the
data bus buffer.
Read/Write & control logic: The function of this block is to accept OUTPUT
commands from the CPU. It contains the initialization command word (ICW) register
and operation command word (OCW) register which store the various control formats
for device operation. This function block also allows the status of 8159A to be
transferred to the data bus.
Interrupt request register (IRR): IRR stores all the interrupt inputs that are requesting
service. Basically, it keeps track of which interrupt inputs are asking for service. If an
interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit
in the IRR will be set.

Interrupt mask register (IMR): The IMR is used to disable (Mask) or enable
(Unmask) individual interrupt inputs. Each bit in this register corresponds to the interrupt
input with the same number. The IMR operation on the IRR. Masking of higher priority
input will not affect the interrupt request lines of lower priority. To unmask any interrupt
the corresponding bit is set 0.
In service register (ISR): The in service registers keeps tracks of which interrupt inputs
are currently being serviced. For each input that is currently being serviced the
corresponding bit will be set in the in service register. Each of these 3-reg can be read as
status reg.
Priority Resolver: This logic block determines the priorities of the set in the IRR. The
highest priority is selected and strobed into the corresponding bit of the ISR during
INTA pulse.
Cascade buffer/comparator: This function blocks stores and compare the IDS of all
8259As in the reg. The associated 3-I/O pins (CAS0-CAS2) are outputs when 8259A is
used a master.
Master and are inputs when 8259A is used as a slave. As a master, the 8259A sends the
ID of the interrupting slave device onto the cas2-cas0. The slave thus selected will send
its pre- programmed subroutine address on to the data bus during the next one or two
successive pulses.