Unit - V
Unit - V
UNIT - V
Introduction
The primary function of the microprocessor (MPU) is to accept data from input devices such as keyboards and A/D converters, read instructions, and send the results to output devices such as LEDs, printers, and video monitors. These input and output devices are called either peripherals or I / Os; memory can be viewed as a special type of I / O. Designing logic circuits (hardware) and writing instructions (software) to enable the microprocessor to communicate with these peripherals is called interfacing, and the logic circuits are called I / O ports or interfacing devices. The microprocessor (MPU) communicates with the peripherals in either of two formats: asynchronous or synchronous. Similarly, it transfers data in either of two modes: parallel I / O or serial I / O. The 8085 identifies peripherals either as memory mapped I / O or peripheral I / O based on their interfacing logic circuits. In peripheral I / O, peripheral is identified with an 8-bit address. The 8085 has two instructions IN and OUT to implement data transfer between the microprocessor and peripherals. These are 2-byte instructions; the second byte specifies the address or the port number of a peripheral. The instruction IN transfers (copies) data from an input device to the accumulator, and the instruction OUT transfers data from accumulator to an output device.
5.1
Objective
This lesson provides you the detailed study about 8080A and 8085 interrupt, Concepts of serial I/O, Synchronous and Asynchronous transmission, Programmable interface devices, 8185/8186 programmable I/O ports and timer and the 8279 Programmable Keyboard/Display interface. Towards end of this lesson student can understand the applications of microprocessors and a temperature monitoring system.
5.2
5.2.1
Content
The 8080A Interrupt
The 8080A interrupt process is controlled by the Interrupt Enable flip-flop, which is internal to the processor and can be set or reset by using software instructions. If the flip-flop is enabled and the input to the interrupt signal INT (pin 14) goes high, the microprocessor is interrupted. This is a maskable interrupt and can be disabled. The 8080A has only one interrupt signal; it does not have a nonmaskable interrupt. The 8085 has an interrupt signal called INTR (pin 10), functionally identical with the 8080A interrupt. However, the 8085 has additional interrupt signals as well. To avoid confusion, we will refer to the interrupt process that is common to both the processors as the 8080A interrupt. The best way to describe the 8080A interrupt process is to compare
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Fig 5.2 8085 Timing of the Interrupt Acknowledge Machine Cycle an Execution
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The 8085 has five interrupt inputs (Figure 5.3). One is called INTR, which is identical with the INT input in the 8080A. The other four are automatically vectored (transferred) to specific locations on memory page 00H without any external hardware. They do not require the INTA signal or an input port; the necessary hardware is already implemented inside the 8085. These interrupts and their call locations are as follows: Interrupts 1. 2. 3. 4. TRAP RST 7.5 RST 6.5 RST 5.5 Call Locations 0024H 003CH 0034H 002CH
The TRAP has the highest priority, followed by RST 7.5, 6.5, 5.5, and INTR, in that order.
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Fig 5.3 The 8085 Interrupts and Vector Locations TRAP TRAP, a nonmaskable interrupt known as NMI, is analogous to the smoke detector described earlier: It has the highest priority; it need not be enabled; and it cannot be disabled. It is level and edge sensitive, meaning that the input should go high and stay high to be acknowledged. It cannot be acknowledged again until it makes a transition from high to low to high. Figure 5.3 shows that when this interrupt is triggered, the program control is transferred to location 0024H without any external hardware or the interrupt enable instruction EI. TRAP is generally used for such critical events as power failure and emergency shut-off. RST 7.5, 6.5,and 5.5 These maskable interrupts (shown in Figure 5.4) are enabled under program control with two instructions: EI (Enable Interrupt) described earlier, and SIM (Set Interrupt Mask) described below: Instruction. SIM: Set Interrupt mask
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Fig 5.4 Interpretation of the Accumulator Bit Pattern The mnemonic SIM is confusing. The wording Set Interrupt Mask implies that the instruction masks the interrupts. However, the instruction must be executed in order to use the interrupts. The process required to enable these interrupts can be likened to a switchboard controlling three telephone extensions in a company. Let us assume these phone extensions are assigned to the president (RST 7.5), the vice-president (RST 6.5) and the manager (RST 5.5), in that priority, and are monitored by their receptionist according to the instructions given. The protocols are placing a telephonic call to one of the executives and of interrupting the microprocessor using RST 7.5, 6.5, and 5.5 can be compared as follows: Placing a telephone call 1. The switchboard is functional and all telephones lines are open. Interrupting 8085 (Figure 5.4) 1. The interrupt process is enabled. The instruction EI sets the Interrupt Enable flip-flop, and one of the inputs to the AND gates is set to logic 1 (Figure 5.3). These AND gates activate the program
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2. An appropriate bit pattern is loaded into the accumulator. 3. If bit D3 = 1, the respective interrupts are enabled according to bits D2 D0 4. RST 7.5, 6.5, and 5.5 are being Monitored. 5. If bit D3 = 0, bits D2 D0 have no effect on previous conditions. 6. Bit D4 = 1, this resets RST 7.5
4. The receptionist is on duty, and send calls through for whomever is available. 5. The receptionist is busy typing. Phone calls can be received directly According to previous instructions. 6. No calls for the president now. Call back later.
This analogy can be extended to the interrupt INTR, which is viewed as one telephone line shared by eight engineers with a switchboard operator (external hardware) who rings the appropriate extension. The entire interrupt process (except TRAP) is disabled by resetting the Interrupt Enable flip-flop (Figure 5.3). The flip-flop can be reset in one of the three ways: by instruction DI, system Reset, or by recognition of an interrupt request. Figure 5.3 shows that these three signals are ORed and the output of the OR gate is used to reset the flip-flop. TRIGGERING LEVELS These interrupts are sensitive to different types of triggering as listed below: 1. RST 7.5. This is positive edge sensitive and can be triggered with a short pulse. The request is stored internally by the D flip-flop (Figure 5.3) until the microprocessor responds to the request or until it is cleared by Reset or by bit D4 in SIM instruction.
2. RST 6.5 and RST 5.5. These interrupts are level sensitive, meaning that the triggering level should be on until the microprocessor completes the execution of the current instruction. If the microprocessor is unable to respond to these requests immediately, they should be stored or held by external hardware. Example. Enable all the interrupts in an 8085 system. Instructions.
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Fig 5.5. Interpretation of the Accumulator Bit Pattern for the RIM Instruction Instruction RIM: Read Interrupt Mask
1. This is a1-byte instruction 2. This instruction loads the accumulator with eight bits indicating the current status of the interrupts masks, the interrupt enable, pending interrupts, and serial input data. See Figure 5.5. Assuming the microprocessor is completing an RST 7.5 interrupt request, check to see if RST 6.5 is pending. If it is pending, enable RST 6.5 without affecting any other interrupts; otherwise, return to the main program.
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NEXT:
The instruction RIM checks for a pending interrupt. Instruction ANI 20H masks all the bits except D5 to check pending RST 6.5. If D5 = 0, the program control is transferred to the main program. D5 = 1 indicates that RST 6.5 is pending. Instruction ANI 0DH sets D1 = 0 (RST 6.5 for SIM), instruction ORI sets D3 = 1 (this is necessary for SIM to be effective), and instruction SIM enables RST 6.5 without affecting any other interrupts. The JMP instruction transfers the program to the service routine (SERV) written for RST 6.5. 5.2.3 Concepts in Serial I/O
The basic concepts concerning the serial I/O mode can be classified into the categories as shown; they will be discussed in the following sections. 1. 2. 3. 4. 5. I/O requirements Alphanumeric codes Transmission format Serial transmission standards Software vs. programmable hardware approaches
I/O Requirements The 8085/8080A MPU identifies a serial I/O peripheral in the same manner that it identifies any other peripheral through a decoder port address and the control signals IOR and IOW. The control signal IOR is used to receive data, IOW is used to transmit data, as shown in Figure 5.6. Similarly, the memory-mapped I/O technique can be employed using the memory-related control signal MEMR and MEMW. The primary differences between parallel I/O and
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Fig 5.6 Block Diagram: Serial I/O and Control Signals serial I/O are the number of data lines and the number of bits transferred by the I/O instructions. The 8085/8080A MPU can transfer bits serially under various conditions depending upon the type of peripheral and its interfacing logic. Serial I/O data transfer can be unconditional, with the status check, or with the interrupt. Alphanumeric Codes A computer is a binary machine; in order to communicate with the computer in alphabetic letters and decimal numbers, translation codes are necessary. The commonly used code known as ASCII, the American Standard Code for Information Interchange. It is a 7-bit code with 128(27) combinations, and each combination from 00H to 7FH is assigned to a letter, a decimal number, a symbol, or a machine command. For example, hexadecimals 30H to 39H represent numerals 0 to 9; 41H to 5AH represent capital letter A through Z; 21H to 2FH represent various symbols; and the initial codes 00H to 1FH represent machine commands such as Carriage Return (CR) or Line Feed (LF). Devices that use ASCII characters include ASCII terminals, teletype machine (TTY), and printers. When the key 9 is pressed on an ASCII terminal, the computer receives 39H in binary, and the system programs translate ASCII characters into appropriate binary or BCD numbers. Another code, called EBCDIC (Extended Binary Coded Decimal Interchange Code), is widely used in IBM computer. This is an 8-bit code representing 256 combinations; however, several combinations are not being used. Transmission Format A transmission format is concerned with issues such as synchronization, direction of data flow, speed, errors, and medium of transmission (telephone lines for example).
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Serial communication occurs either in synchronous or asynchronous format. In the asynchronous format, a receiver and a transmitter are synchronized; a block of characters is transmitted along with the synchronization information, as in Figure 16.2(a). This format is generally used for high-speed transmission (more than 20k bits/second).
Fig 5.7 Transmission Format: Synchronous (a) and Asynchronous (b) The asynchronous format is character-oriented. Each character carries the information of the START and the STOP bits, shown in Figure 5.7(b). When no data are being transmitted, a receiver stays high at logic 1, called MARK; logic 0 is called SPACE. Transmission begins with one START bit (low), followed by a character and one or two STOP bits (high). This is also known as framing. Figure 5.7(b) shows the transmission of eleven bits for an ASCII character in the asynchronous format: one START bit, eight character bits, and two STOP bits. The format shown in Figure 5.7(b) is similar to Morse code, but the dots and dashes are replaced by logic 0s and 1s. The asynchronous format is generally used in low speed transmission (less than 20 k bits/second.) SIMPLEX AND DUPLEX TRANSMISSION Serial communication also can be classified according the direction and simultaneity of data flow.
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Fig 5.8 Communication between Two Computers Using Modems Computers can exchange information over telephone lines by using two modem one on each side (Figure 5.8). A calling computer (or a terminal) contacts a receiving computer through a telephone number, and a communication link is established after control signals have been exchanged between computers and modems. A typical process of communication is shown in Figure 5.8. A parallel word is converted into serial bits; in turn, they generate two audio frequencies according to logic 0 or 1, and these audio frequencies are transmitted over telephone lines. At the receiving end, audio frequencies are converted back into 0s and 1s, and serial bits are converted into a parallel word that can be read by the receiver computer. 5.2.5 Programmable Interface Devices
A programmable interface device is designed to perform various input/output functions. Such a device can be set up to perform specific functions by writing an instruction (or instructions) in its internal register, called the control register. Furthermore, functions can be changed anytime during execution of the program by writing a new instruction in the control register. These devices are flexible, and multifunctional. They are widely used in microprocessor-based products. The I/O functions of a programmable device are determined through software instructions. The MPU writes an appropriate instruction (or instructions) in the device to define its I/O functions. The functions performed by the interfacing I/O devices, are as follows: 1. A latch is used as an output port to hold and display data. 2. A tri-state buffer is used as an input port to read data from devices such as a keyboard or data converters.
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The 8155/8156 is a device with two sections: the first is 256 bytes of R/W memory, and the second is a programmable I/O. Functionally, these two sections can be viewed as two independent chips. The I/O section includes two 8-bit parallel I/O ports (A and B), one 6-bit port (C), and a timer (Figure 5.9). All the ports can be configured simply as input/output ports -- similar to the 8212. Ports A and B also can be programmed in the handshake mode, each port using three signals as handshake signals from port C. The
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Fig 5.9 8155 Pin Configuration and Block Diagram CONTROL LOGIC The control logic of the 8155 is specifically designed to eliminate the need for externally demultiplexing lines AD7 -- AD0 and generating separate control signals for memory and I/O. Figure 14.5 shows five control signals; all except the Chip Enable (CE) are input signals directly generated by the 8085. 1. CE -- Chip Enable: This is a master Chip Select signal connected to the decoded highorder bus.
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Fig 5.10
Expanded Block Diagram of the 8155 (a) and Its I/O Address: Selection (b)
To communicate with peripherals through the 8155 the following steps are necessary: 1. Determine the addresses (port numbers of the registers and I/Os) based on the Chip Enable logic and address lines AD0, AD1, and AD2. 2. Write a control word in the control register to specify I/O functions of the ports and the timer characteristics. 3. Write I/O instructions to port addresses to communicate with peripherals. Page 182
By combining five high-order address lines with three low-order address lines (A2 - A0), the port numbers in Figure 14.8 will range from 20H to 25H, as shown below. A15 A14 A13 0 0 1 status register (2H) A7 A6 A5 A4 A3 A12 0 A11 0 AD2 0 0 0 0 1 1 AD1 0 0 1 1 0 0 AD0 Addresses Ports 0 = 20H -- Control 1 0 1 0 1 = = = = = 21H -22H -23H -24H -25H -or
This raises a question: How is it possible to combine five high-order address lines with three low-order address lines to generate a port address? To find an answer to this question, examine the execution of either the IN or OUT instruction. When these instructions are executed, the high-order and low-order address buses carry the same information. In this case, the logic levels required on lines A 15 to A11 for the Chip Enable are also duplicated on the address lines from A7 through A3, as shown above.
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Fig 5.11 Interfacing 8155 I/O Ports CONTROL WORD Writing a control word in the control register can configure the I/O ports and the timer. The control register bits are defined as shown in Figure 5.12. In this control word, outputs are defined with logic 1 and inputs with logic 0. The first two LSBs, D0 and D1, determine I/O functions of ports A and B; and the MSBs, D 7 and D6, determine timer functions. Bits D4 and D5 are used only in the interrupt mode to enable or disable internal flip-flops of the 8155. These bits do not have any effect on the Interrupt Enable flip-flop (INTE) of the MPU. The next section shows an application of the 8155 to design two output ports for the SDK-85 system. An application of the 8155 in the handshake mode is illustrated later. Illustration: Interfacing Seven-Segment LED Output Ports Using the 8155 PROBLEM STATEMENT 1. Design two seven-segment LED displays using ports A and B of the 8155. 2. Write initialization instructions and display data bytes at each port. HARDWARE DESCRIPTION Figure 5.13 shows two seven-segment output ports: port A with the Hewlett Packard HP 5082/7340, and port B with the Fairchild FND 507, and 9370. The HP 5082 includes an internal decoder/driver, while the FND 507 is driven by a separate decoder/driver 9370.
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Fig 5.12 Control Word Definition in the 8155 (a) and Table of Port C Bit Assignments (b)
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Fig 5.13 Interfacing 8155 I/O Ports with Seven-Segment LEDs Both are functionally similar; however, a seven-segment display with an internal built-in decoder/driver is more expensive. The decode logic is the same as that used in the previous discussion; therefore, the port addresses are as follows: Control Register = 20H Port A = 21H Port B = 22H CONTROL WORD To configure ports A and B as outputs, the control word is as follows:
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PROGRAM DESCRIPTION The instruction MVI A, 03H initializes ports A and B as simple output ports, and the following instructions display data BYTE1 and data BYTE2 at ports A and B, respectively. The 8155 Timer The timer section of the 8155 has two 8-bit registers; fourteen bits are used for counter, two bits for the timer mode, and it requires a clock as an input. This 14-bit down-counter provides output in four different modes, as described below. Figure 5.14 (a) shows two registers for a 14-bit count, one for LSB (low significant byte) and one for MSB (most significant byte). The most significant bits M2 and M1 are used to specify the timer mode.
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Fig 5.14 Timer Loading Format (a) and Modes (b) To operate the timer, a 14-bit count and mode bits are loaded in the registers. An appropriate control word starts the counter, which decrements the count at each clock pulse. The timer outputs vary according to the mode specified (Figure 5.14(b)). The timer can be stopped either in the midst of counting, or at the end of a count (applicable to Modes 1 and 3). In addition, the actual count at a given moment can be obtained by reading the status register. These details will be described later. Illustration: Designing a Square Wave Generator Using the 8155 Timer PROBLEM STATEMENT Design a square wave generator with a pulse width of 100 s by using the 8155 timer. Set up the timer in Mode 1 if the clock frequency is 3 MHz. Use the same decode logic and the port addresses as in Example1 (Figure 5.11).
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Assuming the same decode logic for the 8185 Chip Enable line as in Example 1, the port addresses for the timer registers are Timer LSB = 24H Timer MSB = 25H The least significant byte, 5EH (of the count 025EH), should be loaded in the timer register with address 24H. The most significant byte is determined as follows: M2 0 M1 1 T13 0 T12 0 T11 0 T10 0 T9 1 T8 0 = 42H
Timer Mode 1
MSB
Therefore, 42H should be loaded in the timer register with the address 25H. Control Word. Assuming the same configuration for ports A and B as before, only bits D7 and D6 should be set to 1 to start the counter (see control word definition in Figure 14.8). Therefore, Control Word: 1100 0011 = C3H Initialization Instructions MVI A, 5EH OUT 24H MVI A, 42H OUT 25H MVI A, C3H OUT 20H HLT ; LSB of the count ; Load the LSB timer register ; MSB of the count ; Load the MSB timer register ; Start the timer
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Fig 5.15 8155 with Handshake Mode CONTROL SIGNALS IN HANDSHAKE MODE When both ports A and B are configured in the handshake mode, port A uses the lower three signals of port C (PC0, PC1, and PC2), and port B uses the upper three signals (PC3, PC4, and PC5) as shown in Figure 5.15. The functions of these signals are as follows: 1. STB (Strobe Input): This is an input handshake signal from a peripheral to the 8155. The low on this signal informs the 8155 that data are strobed into the input port. 2. BF (Buffer Full): This is an active high signal, indicating the presence of a data byte in the port. 3. INTR (Interrupt Request): This signal is generated by the rising edge of the STB signal if the interrupt flip-flop (INTE) is enabled. This signal can be used to interrupt the MPU. 4. INTE (Interrupt Enable): This is an internal flip-flop used to enable or disable the interrupt capability of the 8155. Bits D4 and D5 control the interrupts for port A and port B, respectively, in the control register. These control signals can be used to implement either interrupt I/O or status check I/O. INPUT Figure 5.16(a) shows the sequence of events and timing in data input to the 8155; they can be described as follows: Page 190
Fig 5.16 Timing Waveforms of the 8155 I/O Ports with Handshake: Input Mode (a) and Output Mode (b) 2. The falling edge of the STB sets signal BF (Buffer Full) high, informing the peripheral to wait. 3. When the STB goes high, the rising edge of the STB can generate signal INTR if the internal interrupt flip-flop INTE is set. The interrupt flip-flops are set or reset by the control word. 4. The last step is to transfer data from the 8155 input port to the MPU. This can be done either by interrupting the MPU with the INTR signal or by checking the status of signal BF. The MPU can check the status by reading the status register (described later). When the MPU reads data, the INTR and BF signals are reset. When the BF signal goes low, it informs the peripheral that the port is empty, and the device is ready for the next byte.
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Fig 5.17 Status Word Definition Illustration: Interfacing I/O Ports in Handshake Mode Using the 8185
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PROBLEM STATEMENT Design an interfacing circuit using the 8155 to read and display data from an A/D converter to meet the following requirements: 1. Set up port A in the handshake mode to read data from an A/D converter. 2. Set up port B as an output port to display data at seven-segment LEDs. 3. Use line PC3 from port C to initiate a conversion. 4. Use the same decode logic as in Example 14.2 (Figure 14.7) to assign I/O port addresses. 5. Use the 8155 timer to record the conversion time. PROBLEM ANALYSIS Figure 5.18 shows an interfacing circuit that uses the 8155 I/O ports as follows: 1. Port A is configured as an input port in the handshake mode for reading data from the A/D converter. 2. Port B is configured as a simple output port for seven-segment LEDs. 3. The upper half of port C is a simple output port, and bit PC3 is being used to start conversion. 4. The lower half of port C provides handshake signals for port A. Bit PC2 is being used as a strobe (STB) to inform the 8155 that the conversion is complete and that the output of the converter has been placed in port A. INPUT WITH STATUS CHECK The circuit shows that the INTR signal (bit PC0) is not being used. This suggests that port A is configured for status check and not for interrupt I/O. Therefore, the control word (see Figure 5.12) required to set up the ports as specified above and the masking byte to check the Data Ready (DR) line are as follows: Control Word D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 1 D0 0 = 06H
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Fig 5.18 Interfacing the A/D Converter AD570 in the Handshake Mode Status Word. The MPU needs to check bit D1 of the status register to verify the end of conversion and the availability of data in port A. The status word will have the following information (see Figure 14.13): D7 X D6 X D5 X D4 X D3 X D2 X D1 BFA D0 X INTRA
INTRB INTEA
When the status word is masked with byte 02H, the availability of a data byte in port A can be verified.
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8155 TIMER The timer can be used to calculate the conversion time. When a conversion begins, the timer should be started with a known count, and at the end of conversion the timer should be stopped. The difference between the two counts multiplied by the clock period of the timer should provide a fairly accurate reading of the conversion time. To start the timer, set bits D7 and D6 of the control register to 1 without affecting the other bits of the register. Therefore, to start the timer, the control word should be: = 1 1 0 0 0 1 1 0 = C6H
Start Timer
I/O Assignments
Stop Timer
I/O Assignments
PORT ADDRESSES The decode logic is the same as in Example 1; therefore, the I/O port addresses range from 20H (control register) to 25H (Timer -- MSB). PROGRAM MVI A, 06H OUT 20H MVI A, 00H OUT 24H OUT 25H MVI A, 08H OUT 23H MVI A, C6H OUT 20H MVI A, 00H Control word for I/O ports Set up ports as specified Load 0000H in the timer registers Byte to set PC3 = 1 Send START pulse Control word to start timer Start timer Byte to set PC3 = 0
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The 8355/8755 is a 2K-byte (2048 x 8) memory with two I/O ports; each I/O line of the ports can be programmed either as input or output. The 8355 is ROM and the 8755 is EPROM Figure 5.19 shows: (a) the block diagram of the 8755, and (b) the internal control registers called Data Direction Registers (DDR). Each bit in the DDR registers controls the corresponding bit in the I/O ports. The port addresses of the DDR registers and I/O ports are determined by the Chip Enable (CE) logic and address lines AD0 and AD1. The table, Figure 14.15(c) shows the logic levels required for address lines AD0 and AD1 to select a port. These logic levels are combined with CE logic to determine the port addresses, as explained below. Figure 5.20 is a schematic from the SDK-85 system. The interfacing logic shows the 3to-8 decoder; its output line 0 is connected to the CE signal of the 8755. To select the 8755, the logic on the address lines should be as follows: A15/ AD7 0 A14/ AD6 0 A13/ AD5 0 A12/ AD4 0 A11/ AD3 0 AD2 X AD1 0 0 1 1 AD0 0 1 0 1 = 00 = 01 = 02 = 03 Selected Register A B DDR A DDR B
The logic levels on the high-order address lines (A15 -- A11) are duplicated on the loworder address lines (AD7 -- AD3). Each bit of port A and port B can be programmed by writing control words in their respective DDR registers; logic 0 in a DDR register specifies input mode for the corresponding bit in the I/O port. For example, byte F0H in the DDRA specifies that lines PA0 to PA3 are inputs and lines PA4 to PA7 are outputs.
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Fig 5.19
8755 Block Diagram (a), Data Direction Register (b), and I/O Selection Table (c)
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Fig 5.20 Interfacing the 8755 I/O Ports Example 2. Write initialization instructions to configure port A and port B as output ports, and display 32H at port A. Instructions MVI A, FFH OUT 02H OUT 03H MVI A, 32H OUT 00H HLT 5.2.8 ; Control word to set up all bits as output bits ; Initialize port A as output ; Initialize port B as output ; Display 32H at port A
The 8279 is a hardware approach to interfacing a matrix keyboard and a multiplexed display. There is a software approach to interfacing a matrix keyboard and a multiplexed display of seven-segment LEDs. The disadvantage of the software approach is that the microprocessor is occupied for a considerable amount of time in checking the keyboard and refreshing the display. The 8279 relieves the processor from these two tasks. The disadvantage of using the 8279 is the cost. The trade-offs between the hardware approach and the software approach are the production cost vs. the processor time and the software development cost. The 8279 (Figure 5.21) is a 40-pin device with two major segments: keyboard and display. The keyboard segment can be connected to a 64-contact key matrix. Keyboard entries are debounced and stored in the internal FIFO (First-In-First-Out) memory, while an interrupt signal is generated with each entry. The display segment can provide a
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Fig 5.21 The 8279 Logic Pinout Block Diagram of the 8279 The block diagram (Figure 5.22) shows four major sections of the 8279: keyboard, scan, display, and MPU interface. The functions of these sections are described below.
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Fig 5.22 The 8279 Logic Block Diagram KEYBOARD SECTION This section has eight lines (RL0 -- RL7) that can be connected to eight columns of a keyboard, plus two additional lines: Shift and CNTL/STB (Control/Strobe). The status of the SHIFT key and the Control key can be stored along with a key closure. The keys are automatically debounced, and the keyboard can operate in two modes: two-key lockout or N-key rollover. In the two-key lockout mode, if two keys are pressed almost simultaneously, only the first key is recognized. In the N-key rollover mode, simultaneous keys re recognized and their codes are stored in the internal buffer; it can also be set up so that no key is recognized until only one key remains pressed. The keyboard section also includes 8 x 8 FIFO (First-In-First-Out) RAM. The FIFO RAM consists of eight registers that can store eight keyboard entries; each is then read in the order of entries. The status logic keeps track of the number of entries and provides an IRQ (Interrupt Request) signal when the FIFO is not empty. SCAN SECTION The scan section has a scan counter and four scan lines (SL0 -- SL3). These four scan lines can be decoded using a 4-to-16 decoder to generate sixteen lines for scanning.
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Fig 5.23 SDK 85 Keyboard / Display Circuit CIRCUIT DESCRIPTION Figure 5.23 shows the following components: 1. The 8279 Programmable Keyboard/Display Interface. 2. A matrix keyboard with 22 keys. 3. Six seven-segment LEDs: DS1 - DS6. (Only one is shown; other five are identical). 4. The 74LS156 decoder with open collector outputs. 5. Transistors as current drivers. 6. The 8205 decoder for the decoding logic.
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Decoder Enable
Decoder Input
1900H 1800H
INITIALIZATION INSTRUCTIONS In the SDK-85 system, the 8279 is initialized for the keyboard/display mode: Two-key Lockout; Left Entry; and 8-bit, 8-Character Display. The RESET signal sets the clock Page 204
Data Format D6 D5 D4
D3
D2
D1
D0 COL
To display characters, the routine determines whether it is displaying a 4-digit memory address or a 2-digit data value. Then it sends the control word to read the display RAM. For example, to display a 4-digit memory address, the control word instructions are as follows: MVI A, 90H Control word to write starting at first RAM Write Display RAM Control Word location STA 1900H 1 0 0 A1 A A A A MVI A, CODE Load seven-segment code
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To display a 2-digit data value, the control instructions are as follows: MVI A, 94H : Control word to display data STA 1900H In this example, the control word 94H points to the fifth memory location in the display RAM; the first four locations are reserved for memory addresses. 5.2.9 Applications Of Microprocessors
INTRODUCTION Since the advent of the P in 1971, its application domain has been expanding rapidly. This trend will definitely continue especially in the wake of the fact that new Ps and Cs with superior performance are now available to the system designer, e.g. Intels 80386,80196, Motorolas MC68030, M68CH11A8, NECs 7800 series of microcontrollers. The purpose of this chapter is to familiarize the reader with a variety of application areas of Ps. Obviously, it is not possible to present each application in detail. We have therefore presented a brief description of several application areas and one application in detail. The application presented in detail is that of a temperature monitoring system for which the detailed software and hardware design is also presented. 5.2.10 A Temperature Monitoring System
One of the application areas of Ps is process control. In a typical process control application, the P continuously monitors one or more process variables and generates outputs to the electro-mechanical elements which in turn control the process variables. This kind of control is known as closed loop control. If the P outputs the control variables to human operators, via displays or line printers, who in turn apply the necessary control inputs, then the control strategy is known as open loop control. In this section we shall present an example to illustrate the use of a P in open loop process control. To illustrate, we shall use the 8085 as the control P. For simplicity, only one process variable, namely the temperature at a point, will be monitored and displayed. We shall present the detailed software and hardware design. SYSTEM REQUIREMENTS It is required to design a P-based open loop control system that monitors a process temperature and displays it on a four-digit seven-segment display. The system should have the facility to input, from a human operator, the lower and upper limits of the temperature being monitored. If at any moment these limits are violated, one of the two Page 206
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Figure 5.24: Operator panel for temperature monitoring system. with a minimum of 50 ms inter-reading gap. A transducer that can be used if the temperature being measured is within the range of 55C to +150C, is the Analog Devices AD590. It has a wide power supply range of +4 V to +30 V. It generates a current output of 1 A/Kelvin. For example, at 25C, the output current is 298 A. There are several ways in which the low and high limits may be set and read by the P. We shall use a very simple scheme described below. Assume that a switch is provided which may be closed by the operator to indicate to the P whether limit setting is desired or not. Call this as the SET LIMIT switch. Another switch, called the LO/HI switch, can be used to indicated whether lower or upper limit is
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Fig 5.25: Block diagram of a microprocessor-based temperature monitoring system it is assumed that timers will be used for interrupting the P to indicate the two conditions time to input limits and time to turn off the LIMIT-SET lamp. HARDWARE DESIGN Let us begin the detailed hardware design of the system. To begin with, we assume that we shall not require more than 2K bytes of EPROM and 2 K bytes of RAM. This decision is difficult to make so early in the design when the software has not been designed. However, we postpone a discussion on this aspect to the end of this section. Thus, we require one 2716A and one 6116A. We can now assign addresses to these chips. As the 8085 jumps to location 0 when it is reset, we must have at least one instruction stored at this location. Generally, this instruction is a jump to an initialization routing for the application. This implies that location 0 must be in EPROM. Thus, we may assign addresses 0-2047 to the bytes in the 2716A and addresses 2048-4095 to the bytes in the 6116A static RAM. To design the address decoding circuitry, we have selected the 11 least significant bits of the 16-bit address for each memory chip. Bit A11 selects one of the two memory chips. Fig. 5.28 shows this assignment.
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Fig 5.28 Address assignment for EPROM and RAM MODES OF OPERATION Though the 8254 provides five different modes of operation for the counters, we shall describe only mode 0. We shall use mode 0 in our design. When programmed to operate in mode 0, a counter generates an interrupt on terminal count. The entire operation, from loading the counter to the generation of the interrupt, proceeds as follows: 1. 2. The control word is written into the control register. This should specify that a counter, say counter 0, is to operate in mode 0. Writing the control word forces OUT 0 to go low. The initial count is written to the counter. This count can be programmed to be a 16-bit or an 8-bit value.
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PA0 PA3 Input Digit 1 limit PA4 PA7 Input Digit 2 of limit PA0 PA3 Input Digit 3 of limit PA4 PA7 Input Digit 4 of limit PC1 Input LO/HI switch input PC0 Input SET LIMIT switch input Output Output Output Output Output Output One digit, in BCD, to be displayed HIGH alarm display LOW alarm display Cathode of seven-segment display LIMIT SET Blanking input Of 7448 seven-segment driver
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Fig 5.30 (a) Address assignment and (b) chip select signals for I/O ports and counters.
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Count-down begins one clock pulse after the count has been written into the counter. If GATE 0 is high, then counter 0 counts down. For each CLK 0 pulse, counter 0 decrements by 1. If GATE 0 is low, countdown is inhibited. Countdown resumes when GATE 0 goes high. When the counter reaches 0, which is the terminal count, OUT 0 goes high. OUT 0 remains high until a new count is written or the counter is reprogrammed with the control word.
The above operation sequence is identical for all the three counters. Note that the counter does not stop after the count has reached 0. It wraps around to 0FFFFH and continues the countdown. In some other modes, the counter gets reloaded to the count that was loaded initially. Thus mode 0 can be used to interrupt a P. The time delay before an interrupt is generated after the counter has been loaded, can be controlled by the value loaded into the counter. Note that a count of 0 leads to the maximum delay. It corresponds to a total count of 216 CLK pulses. Thus, if the clock period is 320 ns and the counter is loaded with a count of 0, then OUT will go high 216 x 320 ns = 20.972 ms after the counter was loaded. PROGRAMMING THE 8254 The control word format for the 8254 appears in Fig. 5.32. As an example of how to set the control word, assume that we desire to use counter 0 (a) in mode 0, (b) as a binary counter, and (c) as a 16-bit counter. The control word can be set to: 00 11 00 0. Setting the RW0 and RW1 bits to 11 implies that counter 0 must be loaded with a 16-bit count. The count itself is sent to the counter in two steps. First, the least significant byte is sent followed by the most significant byte.
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Fig 5.31 Signals in the 8254 Writing data to the 8254 can be accomplished using the OUT instruction of the 8085. Bits A0 and A1 of the port address specified in this instruction will determine the destination of the data as shown in Table 5.2. USING THE 8254 IN OUR DESIGN We shall use counter 0 of the 8254 for read limit and counter 1 for turning off LIMIT SET display timing. The OUT 0 output can be connected to the RST 7.5 input of the 8085. Thus, when OUT 0 goes high, implying that counter 0 has reached the terminal count, the 8085 will be interrupted. Later, we describe how this interrupt is processed.
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Fig 5.32 Control word format for the 8254 timer. Table 5.3: Memory, Port, and Timer Addresses Chip No. 2716A 6116A 8255A #1 Type EPROM Static RAM Port A Port B Port C Control word register Port A Port B Port C Control word register Counter 0 Counter 1 Control word register Address 0000-07FFH 08FFH-0FFFH 0 1 2 3 4 5 6 7 12 13 15
8255A #2
8254
The OUT 1 output is connected to the RST 5.5 input of the 8085. Thus when counter 1 reaches the terminal count, the 8085 will be interrupted. Recall that RST 7.5 input is rising edge sensitive and the RST 5.5 input is high level sensitive. Thus, after OUT 1 goes high, and the RST 5.5 interrupt has been processed, the 8085 will be interrupted Page 219
Fig 5.33 Port A (input) limit digits (note that all other input ports are to be connected as in this figure and therefore are not shown here.). An N7448 BCD-seven segment Decoder/Driver drives the 7-segment display. The 7448 is used in multiplexed mode. Its outputs a g are always connected to the anodes of all the digit segments. The common cathode of each digit is driven separately through port C pins. Thus, for example, if digit 1 is to be displayed, its cathode should be driven low. Making transistor T1 conduct by driving its base low can do this. Thus PC0 should be set to 1 if digit 1 is to be displayed.
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Fig 5.35 Alarm and LIMIT SET display hardware ANALOG INPUT To input the analog signal corresponding to the temperature, we shall use the AD 7820 ADC. The complete interface including the A/D converter and the temperature transducer is shown in Fig. 5.36. Page 221
Fig 5.36
The AD7820 has been interfaced using I/O mapped I/O. The 74LS138 decoder generates the chip select signal. The O4 output of the 74LS138 selects the AD7820. See Fig. 5.11 for the decoder circuit. Evidently, there are several addresses that will select the ADC. The reader can find out all the other addresses and ensure that they do not overlap with the memory and I/O ports. The RDY output of the ADC drives the READY input of the 8085. As the conversion time in the RD-mode is about 1.6 s, it is essential for the RDY signal to be connected to the 8085. With the circuit shown in Fig. 5.36, any 8085 instruction that can read a byte from an I/O port can be used to read the digital data from the ADC. The temperature transducer interface is quite simple. We know that the AD590 generates 1A current per Kelvin. Over the temperature range of this transducer, the generated current will vary from 218 A to 423A. These numbers can be obtained easily be noticing that 55C to +150C corresponds to 218 Kelvin to 423 Kelvin. A 10 K resistance shown in Fig. 5.36 will force the VIN of the ADC to vary between approximately 2.18 V to 4.23 V. This corresponds to approximately half the full scale range of the ADC which is 5 V. If we set the VREF (-) input of the ADC to 2.18 V, then the ADC will output all zeroes when the input temperature is approximately 55C. However, for economy of components, we shall not do so. The least significant bit of the ADC output corresponds to approximately 19 mV. Thus, an input of 2.18 V will result in approximately. (2.18/19 mV ~ 01101110B)
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(4.23/19 mV ~ 11100000B) The BINBCD routine can use this data to transform the digital output of the ADC to the corresponding temperature reading to be displayed. Note that as we are using an 8-bit ADC, we need only three digits to display the temperature. However, as we have used for 7-segment displays, the BINBCD routine must always generate the fourth, or the highest order digit, to be 0. That completes the hardware design of the temperature monitoring system. Figure 5.42 gives the complete design for an overview by the reader. We shall now design the software without which all the hardware designed so far would not work as desired. SOFTWARE DESIGN As is evident from the flow charts presented earlier, the complete software may be partitioned into the following subroutines. 1. INIT for initializing program variables immediately after system RESET. 2. DISPLAY for displaying the next digit of the current average value of temperature. It is called once each time the main loop shown in Fig 8.3 is executed. 3. UPDATE for computing the average value of the temperature. It is invoked after sixteen readings have been accumulated. 4. RLIMITS for reading new limit values, if desired by the operator. Called when an interrupt occurs. It reads only one limit at a time, high or low, at 15s intervals. 5. LAMPOFF for putting off the lamp that was turned on to indicate that a limit has been read from the input switches. It is called when an interrupt occurs or after the lamp has been turned ON. The lamp is turned off 5 s after it was turned ON. 6. DELAY for creating a 50 ms delay before the next temperature reading. 7. ATOD for getting one temperature reading and assigning it to variable RDNG. In addition to these subroutines, several other subroutines are required one for converting an input BCD number to equivalent binary and another for converting a binary number (average temperature) to BCD. We shall refer to these as BCDBIN and BINBCD subroutines, respectively. The other subroutine requirements will arise as we develop the software. We shall now design each of the above subroutines and the main program. In order that these subroutines are readable; we shall use symbolic addresses for various I/O ports and
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; Address of the list of cathode addresses. DADDR LSADDR DATAL EQU DIGITS ;First cathode address. EQU DDIGITS ;LSD address. EQU RDNG ;Address of the temperature reading.
INITIALIZATION: THE INIT ROUTINE Several variables and I/O ports are to be initialized before the infinite loop in the main program begins. We shall first initialize various ports and timers by a subroutine named INIT. The variables shall be initialized in the main program using DB and DW statements. All ports must be initialized to be in modes specified in Table 5.1. The command words for 8255A #1 and 8255A #2 are given in Fig. 5.37(a) and (b). The control word for the two counters inside the 8254 appears in Fig. 5.37(c). Note that in Fig. 5.37(c), altering the leftmost two bits from 00 to 01 changes the control word for counter 0 to that for counter 1.
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Fig 5.37 Command word for (a) 8255A#1 (b) 8255A#2 (c) Control word for the 8254 The command words may be assigned the symbols CWR1 and CWR2 for the two 8255A chips and CCWR0 an CCWR1 for the two counters, respectively. These symbols can be defined as shown below. ; *Command words for I/O ports and timer* CWR1 CWR2 EQU 1 00 11011B ;8255A # command word EQU 1 00 00000B ;8255A # 2 command word
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; Next two bytes are to turn the LIMIT set lamp on or off. BLMSET LLMSET BHALRM LHALRM BLALRM LLALRM EQU 00000 0 0B EQU 00000 1 0B EQU EQU EQU EQU 000000 0B 000000 1B 000000 0B 000001 0B ;Bit 6 is 0 to blank the LIMIT SET lamp. ;Bit 6 is 1 to light the LIMIT SET lamp. ;Bit 0 is 0 to turn off the H1 alarm ;Bit 0 is 1 to turn on the H1 alarm ;Bit 1 is 0 to turn off the LO alarm ;Bit 1 is 1 to turn on the H1 alarm
INITIALIZING THE TIMERS The mode bits for both the counters in the 8254 are set to 00 which implies that each counter will generate a pulse on reaching the terminal count. The counter will continue counting after reaching the terminal count. In our case, as the initial count is 0, each counter will begin counting from 0FFFFH after it has reached the terminal count for the first time. Recall that counter 0 is used for getting the 15s delay between two successive limit settings. Counter 1 is used for deriving the 5s delay after which the LIMIT SET lamp is turned off. Counter 1 should be stopped after resetting the lamp. Counter 0 must be started immediately after all variables have been initialized. Counter 1 should be started immediately after the LIMIT SET lamp is turned ON. Note that the counters should be programmed first and only then any command issued to them. STARTING AND STOPPING THE COUNTERS Immediately after the control word has been writing into the control register, the corresponding OUT line goes low. This does not affect any 8085 interrupt input. When the initial count has been written into the counter, the counter starts counting. For counter 0, this approach is acceptable. It keeps counting down and generates an interrupt on the RST 7.5 input. After reaching the terminal count, it begins counting again. However, we would like to start counter 1 only when the 5s delay is desired. This implies that once the counter has interrupted the 8085, it should be stopped and started again only when the LIMIT SET lamp is to be reset. How can we stop the counter and synchronize it with the software? This can be done by sending only the low byte of the count to counter 1. When this low byte is received by counter 1, it stops and waits for the high byte to arrive. The high byte can be sent when the counter needs to be started. This is the procedure used in the INIT routine described below. We can now write the INIT subroutine as given below.
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;*Subroutine to program the 8254 and initialize counters.* ; STCNTR0: MVI A, CCWR0 OUT CWR ;Get counter 0 command word.
; Send count (=0) to counter 0. This will start the counter. MVI A, O OUT CNTR0 OUT CNTR0 RET ; Get low byte of initial count. ; Send low byte to counter 0. ; Send high byte to counter 0.
; Program counter 1 by sending only the ; control word and the low byte of the count for counter 1. PRCNTR1: MVI A, CCWR1 OUT CWR ; Get counter 1 command word.
; Send only the low byte to counter 1. This will force ; the counter to stop counting and OUT 1 will be ; set to low by the 8254. The counting can be started, ; when necessary, by sending the high byte. MVI A, 0 OUT CNTR1 ; This is the low byte of the count. ; Send low byte to counter 1.
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*Subroutine to blank 7-segment display.* BDSPLY: MVI A, 01H OUT PORTB2 RET ; Set LSB to 1 ; Send to blanking input, BI, of 7448. ; End of subroutine.
*Subroutine to unblank the 7-segment display.* LDSPLY: MVI A, 00H OUT PORTB2 RET ; Set LSB to 0. ; Send to blanking input, BI, of 7448. ; End of subroutine.
DISPLAYING THE TEMPERATURE: THE DISPLAY ROUTINE As we have already seen, the temperature is displayed digit by digit, using a multiplexing scheme. Thus, when DISPLAY is called, it should first ascertain the digit that is being displayed currently and then display the next digit after blanking out the previous one. The DISPLAY subroutine given below, performs this task by first blanking the currently ON display by applying a 1 at the BI input of 7448. It then selects the cathode of the next
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STA NXTDG LHLD DADDR SHLD CADDR LHLD LSDADDR SHLD TEMPD JMP FINIS ADDR1:LHLD CADDR INX H SHLD CADDR LHLD TEMPD
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; End of display
CADDR is the address of the next displayable element of DIGITS. It is initialized to point to the first byte of DIGITS. After each digit is displayed, it is incremented to point to the next one. After all the four digits have been displayed, it is reset to point to the first byte of DIGITS. NXTDG indicates the digit number to be displayed next. It assumes values from 0 to 3 in a round-robin fashion. When NXTDG reaches 4, it is reset to 0. At this time, CADDR is also reset to point to the first byte of DIGITS. DADDR denotes the address of the first byte of the DIGITS array. TEMPD holds the address of the next BCD digit to be displayed. LSDADDR is a constant that point to the least significant BCD digit. All the variables mentioned above are initialized in the main program. UPDATING THE DISPLAY DATA: THE UPDATE ROUTINE This routine is invoked after 16 temperature readings have been accumulated. It computes the average of all these readings, checks these against lower and upper limits and accordingly sets or resets the alarms. It also calls BINBCD to convert the average reading to 4 BCD digits for display. ;*Subroutine to update display data and reset alarms* UPDATE: MVI STA CALL CALL CALL RET A, 0FH UPCNT AVRG BINBCD CHECK ; Get 15 in ACC ; Reset update count ; Compute average temperature ; Convert to 4 BCD digits. ; Set/reset alarms if required. ; End of UPDATE.
;*Subroutine to compute the average of 16 readings. ;*ACCUML and ACCUMH contain, respectively, the low and ;*high byte of this value. The low and high bytes ;*of the average value are stored in AVRGL and AVRGH, ;*respectively.* AVRG: LDA ACCUML ; Get low byte
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;* Subroutine to shift the ACC right by 4 bits.* SHR4: RRC RRC RRC RRC ANI RET
OFH
;* Subroutine to shift the ACC left by 4 bits.* SHL4: RLC RLC RLC RLC ANI RET
The CHECK subroutine finds out whether the averaged reading, stored as BCD digits in a 4-byte array DDIGITS, has crossed the limits. The LOLMT and HILMT arrays contain the BCD codes of low and high limits respectively. If any limit is crossed, the corresponding alarm is set, otherwise only the alarm, that is currently set, is reset. Fig. 5.38 shows the logic used by CHECK in flow chart form. The program appears below. The reader is invited to design a more structured flow chart and readable program. ;* Subroutine to check whether averaged reading is in or ;* out of range and accordingly reset alarms.* CHECK: MVI A, 04H; Initialize counter
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; Initialize H-L, D-E and B-C to addresses of MSK of LOLMT, ; HILMT and DDIGITS, respectively. These are symbolically ; denoted by MSDL, MSDH, and MSDT, respectively.
Fig 5.38 Flow chart for comparing the averaged temperature reading with low and high limits and accordingly resetting alarms. LXI LXI LXI H, LOLMT + 3 B, DDIGITS + 3 D, HILMT + 3 ; Get temp digit. ; Compare with LOLMT Page 232
; Reset LO alarm and set HI alarm RLSH: IN ANI ORI PORTC2 0FCH 01H ; Get port C of 8255 #w status. ; Mask off the alarm bits. ; Set H1 alarm bit to 0(PC0) and LO ; alarm bit to 1(PC1).
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READING LIMITS FROM THE OPERATOR PANEL: THE RLIMITS ROUTINE As required, the limits are to be read every 15 s. We are using counter 0 to interrupt the 8085 on RST 7.5 every, approximately, 20.972 ms by setting the corresponding count to 0. Thus, to get an interval of 15 s we need to count this interrupt 15/20.972 ~ 715 times. A 2-byte software counter may be initialized to 715 and decremented by 1 each time the interrupt occurs. When this counter reaches 0, the limit value could be read. The program appears below. The software counter SCNTR0 in initialized to 715 before any interrupt occurs. VALCT0 holds the value to which SCNTR1 should be initialized each time it reaches 0. ;*Subroutine to read lower/upper limits. Reads once every ;*15 seconds. Locations 3C-2E should contain a JMP RLIMITS ;*instruction to force the 8085 to enter RLIMITS on RST 7.5 ;*interrupt.* RLIMITS: CALL LHLD DCD SHLD MOV ORA CPI JNZ LHLK SHLD IN RRC JC RRC JC SAVE SCNTR0 H SCNTR0 A, H L 0 ROVER VALCT0 SCNTR0 PORTC0 ROVER HIADDR ; Save 8085 status. ; Get current counter value ; Decrement it. ; Save it ; Check if 0.
; Reset SCNTR0 to ; 715 ; Get operators request. ; Check if resetting ; desired. ; Check if LOW/HIGH ; limit should to be reset. ; Go get high limit.
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;Point to digit 3, strip next digit and store it in LO/HI limit area. DCX IN MOV CALL MOV H PORTB0 B, A SHR4 M, A ; Get 2 least significant digits of the limit. ; Strip digit 3. ; and store it.
.;Point to digit 4, strip next digit and store it in LO/HI limit area. DCX H MOV A, B CALL SHL4 CALL SHR4 MOV M, A IN PORTC2 ANI 8FH ORI 40H OUT PORTC2 CALL STCNTR1 ROVER: CALL EI RET ; Point to digit 4 ; get digit 4 and ; store it in ; LO/HI limit area ; ; Get status of port C of 8255 #2 ; Mask out LIMIT SET display bit (PC6) ; set LIMIT SET bit to 1. ; Send to LIMIT SET display. ; Start counter 1 to get 5s delay RESTORE ; Restore 8085 status. ; Enable interrupts. ; End of RLIMITS
; *Subroutine to save and restore 8085 status.* SAVE: XTHL PUSH PSW PUSH B PUSH D RET ; Get return address, that is currently ; on stack top, into H-L and save H-L on stack. ; Save PSW. ; Save B-C pair. ; Save D-E pair ; End of SAVE
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H D B PSW
; Pop return address into H-L. ; Restore D-E pair. ; Restore B-C pair. ; Restore PSW. ; Get return address on ; stack top and restore H-L pair. ; End of RESTORE
TURNING OFF THE LIMIT SET LAMP: THE LAMPOFF ROUTINE Immediately after the LIMIT SET indicator is turned ON, counter 1 is also started. This would generate an interrupt after 20.972 ms on RST 5.5. The lamp should be reset after 5 s which implies that approximately 239 such interrupts should be counted before resetting the lamp. We get this number as: 5 s/20.972 ms ~ 239 This can be done using the method already described above with the RLIMITS routine. For this purpose, we use a software counter named SCNTR1. The value to which SCNTR1 should always be reset is held in VALCT1. The desired routine appears below. ;*Subroutine to turn off limit-set lamp 5 s after it ;* is turned on to indicate that the limits have been set.* LAMPOFF: CALL LHLD DCX SHLD MOV ORA CPI JNZ LHLD SHLD SAVE SCNTR1 H SCNTR2 A, H L 0 LMOVER VALCT1 SCNTR1 ; Save 8085 status. ; Get current value of the software counter. ; Decrement it. ; Save it ; If zero then ; turn off ; the lamp, else return. ; Reinitialize software counter. ; Get status of port C of 8255 #2 ; Mask out LIMIT SET display bit (PC6). ; Send to port C of 8255 #2 ; and turn off the lamp ; This will stop counter 1. ; Restore 8085 status. ; Enable interrupts.
IN PORTC2 ANI 8FH OUT PORTC2 CALL PRCNTR1 LMOVER: CALL RESTORE EI
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ANALOG TO DIGITAL CONVERSION: THE ATOD ROUTINE Obtaining a temperature sample from the ADC is simple. The ATOD routine given below does it by merely reading the ADC output. Reading from the ADC will force its RDY output to go low and will remain so until the conversion is over. The RDY output forces the 8085 to wail until the conversion is over. Thus, the IN instruction in ATOD initiates the A-to-D conversion and also reads the digital output. The data obtained is stored at location RDNG from where the BINBCD routine can pick it up for conversion to BCD. ;* Subroutine to get an 8-bit temperature reading from the AD7820 ;* Hardware handshaking is used.* ATOD: STA RET THE DELAY ROUTINE The DELAY subroutine uses a nested loop to decrement the L and H registers until both reach zero. Before DELAY is called, both the H and L registers should be initialized to proper values in order to get a (approximately) 8 ms delay. ;* Subroutine to get desired delay. Registers H and L ;* should be initialized before calling this routine.* LOOP: DCR JNZ DCR JNZ RET L LOOP H LOOP IN RDNG LCRS ; This command starts conversion, ; forces the 8085 to wait until conversion ; is over, and gets the data into ACC. ; Save reading in memory. ; End of ATOD subroutine
It can be proved that the delay D caused by this subroutine is given as (approximately) D = 24 + (L 1) x 14 + (H 1) x [(255 x 14) + 21] (states) Where H and L denote the initial values of the H and L registers, respectively, when DELAY is entered. Assuming a 320 ns clock cycle, the approximately values of H and L for a 50 ms delay are H = 12, L = 3 (other values are also possible).
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TEMPD:
;* Begin main program execution.* ;* The program instructions are in the EPROM.* ORG MAIN: START: MLOOP: LXI SPHL CALL LDA ANI JNZ CALL JMP SUI STA CALL MVI MVI CALL CALL LDA MOV LDA ADD STA MOV LDA ADC H, 0FFFH INIT UPCNT OFFH MODFY UPDATE DISP 01H UPCNT DISPLAY H, 0CH L, 03H DELAY ATOD RDNG B, A ACUML B ACUML B, A ACUMH B ; Initialize stack pointer to ; 0FFFH. This is the highest RAM address. ; Initialize other variables. ; Get update counter. ; Check if zero. ; Do not update display ; Update display ; Go display next digit ; Decrement UPCNT by 1. ; Save it ; Display next digit. ; Prepare for 8 ms delay. ; Generate the delay. ; Get next reading. ; Get temperature reading into the ACC. ; Save it in register B. ; Get low byte of sum. ; Add low byte. ; Save it in memory. ; Also get it in register B. ; Get the high byte of sum in ACC. ; Add with carry. 40H ; Set the address of the next byte to be 40H.
MODFY: DISP:
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;Place jumps to interrupt processing routines. ORG address JMP ORG JMP END 4.2.11 LAMPOFF 3CH RLIMITS START ; This the RST 7.5 interrupt branch address ; Begin execution from start 2C ; This is the RST 5.5 interrupt branch
In the previous section we developed a system illustrating how Ps can be effectively used in open loop process control. In this section we shall briefly describe one of the many P applications in closed loop process control. The specific example chosen is the control of the growth of synthetic quartz. The control system was developed by Robert Pettirossi (1977). THE PROCESS OF GROWING SYNTHETIC QUARTZ The growth of synthetic quartz takes place inside a long, vertically placed, growing chamber (autoclave) made of steel. Before the process starts, sodium hydroxide solution is used to fill the bottom of the autoclave. Small pieces of natural quartz (known as the nutrient) are mixed with this solution to be dissolved at a later stage. Thin wafers of quartz (known as seeds) are sliced along the desired crystallographic structure and suspended at the top of the autoclave. The growth process begins by turning on two heaters-one at the bottom and the other at the top. Thus, a two zone temperature system is maintained. The bottom is maintained at a higher temperature than the top. The nutrient dissolves in the solution and is carried to the top by convection currents. The growth of desired crystals begins on seeds after the growth zone (top) becomes supersaturated. The growth is a pressure, temperature and time dependent process. The growth period is about 30 days and can be subdivided into three stages-the startup, intermediate, and the growth cycle. Fig. 5.39 shows the relationship between the top zone temperature (T t) and the bottom zone temperature (Tb). This relationship must be maintained for proper growth. During the startup period, the rate of temperature rise is critical and must be maintained taking into account Tb, Tt, and t1. The intermediate period is the one during which the temperatures move towards stabilization with a difference of t2. During the final growth
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Fig 5.39
In order to meet the demand, a group of 30 independent such chambers need to be operated. As the control is critical, independent microprocessor based control is employed for each autoclave.
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Fig 5.40 Control system for growth of synthetic quartz. MICROPROCESSOR BASED CONTROL SYSTEM HARDWARE The hardware is centered around an 8080 P. For each autoclave to be controlled, the following are the inputs from the process, which are converted to digital form using transducers and ADCs. 1. Top zone temperature (16 bits). 2. Bottom zone temperature (16 bits) 3. Autoclave pressure (8 bits) The growth is controlled by controlling the power supplied to various heater. When any of the three values corresponding to temperatures and pressure exceed limits, an alarm is set. Thus, the P outputs digital data to DACs for controlling the two heaters and setting/resetting the alarm. An overall block diagram of the complete control system appears in Fig. 5.40. The 8080 require an external clock generator to supply a two phase overlapping clock. This is unlike the 8085, which generates an internal clock using an externally supplied crystal. This function is performed by the 8224. Another chip, known as the system controller, is required to latch the 8-bit status code sent out by the 8080 at the beginning of every machine cycle. The controller, 8228 chips, latches the code and decodes it to produce control signals for memory and I/O devices. Recall that all control signals; IO/M, RD, WR, etc. are generated on chip in 8085.
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Fig 5.41 Overall logic of the control algorithm During the intermediate phase, only Tb is read and adjusted until it reaches the desired final value Tbf. The successive values are read at 3-minute intervals. Apart from these three main modules, there are a few other routines for manipulating 16bit data approximating Tb and Tt. The complete software requires about 1.2 K bytes of memory. This is partitioned into 1 K bytes of ROM and 256 bytes of RAM. One prototype system costs (in 1977) about $400. Thus, to control 30 autoclaves the total cost would be about $12000. However, the designers also experimented with a centralized
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Fi g 5. 42
8080A interrupt The 8080A interrupt process is controlled by the Interrupt Enable flip-flop, which is internal to the processor and can be set or reset by using software instructions. If the flipflop is enabled and the input to the interrupt signal INT (pin 14) goes high, the microprocessor is interrupted. This is a maskable interrupt and can be disabled. The 8080A has only one interrupt signal; it does not have a nonmaskable interrupt. The 8085 has an interrupt signal called INTR (pin 10), functionally identical with the 8080A interrupt. However, the 8085 has additional interrupt signals as well. Alphanumeric Codes A computer is a binary machine; in order to communicate with the computer in alphabetic letters and decimal numbers, translation codes are necessary. The commonly used code known as ASCII, the American Standard Code for Information Interchange. Another code, called EBCDIC (Extended Binary Coded Decimal Interchange Code), is widely used in IBM computer. This is an 8-bit code representing 256 combinations; however, several combinations are not being used. Transmission Format A transmission format is concerned with issues such as synchronization, direction of data flow, speed, errors, and medium of transmission (telephone lines for example). Serial communication occurs either in synchronous or asynchronous format. In the asynchronous format, a receiver and a transmitter are synchronized; a block of characters is transmitted along with the synchronization information. Simplex and Duplex Transmission In simplex transmission, data are transmitted in only one direction. A typical example is the transmission from a microcomputer to a printer. In duplex transmission, data flow in both directions. However, if the transmission goes one way at a time, it is called half duplex; if it goes both ways simultaneously, it is called full duplex. Generally, transmission between two computers or between a computer and a terminal is full duplex. BAUD The rate at which the bits are transmitted bits/second is called a baud in serial I/O. MODEM A modem (Modulator / Demodulator) is a circuit that translates digital data into audio tone frequencies for transmission over telephone lines and converts audio frequencies into digital data for reception.
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5.5
Summary
These input and output devices are called peripherals or I / Os; memory can be viewed as a special type of I / O. The microprocessor (MPU) communicates with the peripherals in either of two formats: asynchronous or synchronous. Similarly, it transfers data in either of two modes: parallel I / O or serial I / O. The 8085 has five interrupt inputs. These interrupts are sensitive to different types of triggering. Serial communication also can be classified according the direction and simultaneity of data flow. A tri-state buffer is used as an input port to read data from devices such as a keyboard or data converters. The timer can be used to calculate the conversion time.
5.6
Terminal Exercises
1. What is a RST instruction? 2. What is a Control word? 3. What are the functions performed by a interfacing I/O device? 4. What is TRAP? 5. What is Parity Check?
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5.8
Assignments
1. Write a brief note on Serial I/O concepts 2. Discuss the applications of microprocessor in detail.
5.9
5.11 Keywords
Modem Extended Binary Coded Decimal Interchange Code (EBCDIC) American Standard Code for Information Interchange (ASCII) Simplex Half duplex Full duplex Baud rate.
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