Microprocessor Slides-2

Dr. Ritika
Department of Computer Application

 MPU is device or group of device(as a unit) that

communicate with peripherals provide timing signals, direct data flow, and perform computing task as specified by the instructions in memory. 8085 is MPU but with 2 limitations:

8085 MPU

Low order address bus is multiplexed (time-shared) with

Appropriate control signals need to be generated to
interface memory and I/O with the 8085. data bus. The buses need to be demultiplexed.

 Interfacing Device necessary to interconnect the components of busoriented system.

Tri-State Devices

Devices essential for proper functioning of bus-oriented system.

have 3 states : logic 1, logic 0, and high impedance.

Trademark of National Semiconductor.

It is a useful device that allows us to control when current passes through

the device, and when it doesn't.

Third line is called Enable is activated, tri-state device function same as

ordinary logic device.

Tri-State Devices
When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters into a high impedance state.

 8085 is 8-bit general purpose microprocessor. Capable of addressing 64K (2 = 65,536 registers ) of
16

8085 MPU

40 pin DIP(Dual in line package). +5V 3 - 5MHz

o ADDRESS BUS

memory.

o DATA BUS
o CONTROL STATUS o POWER SUPPLY AND FREQUENCY o EXTERNALLY INITIATED SIGNALS o SERIAL I/O PORTS

8085 Microprocessor Pinout and Signals

330_01

8085 Microprocessor Pinout and Signals

8085 Microprocessor Pinout and Signals

Address Bus:

A8 - A15 (output; 3-state) It carries the most significant 8 bits of the memory address or the 8 bits of the
I/O address;

Multiplexed Address / Data Bus:

AD0 - AD7 (input/output; 3-state) These multiplexed set of lines used to carry the lower order 8 bit address as

During the opcode fetch operation, in the first clock cycle, the lines deliver the
In the subsequent IO / memory, read / write clock cycle the lines are used as
lower order address A0 - A7. data bus.

well as data bus.

The CPU may read or write out data through these lines.

8085 Microprocessor Pinout and Signals

Control and Status signals:

ALE

RD (active low) - Read memory or IO device. This indicates that the selected WR (active low) - Write memory or IO device. This indicates that the data on (output) - Select memory or an IO device. T his status signal indicates that
the data bus is to be written into the selected memory location or I/O device. the read / write operation relates to whether the memory or I/O device. It goes high to indicate an I/O operation. It goes low for memory operations. but they are rarely used in small systems. memory location or I/O device is to be read and that the data bus is ready for accepting data from the memory or I/O device.

(output) - Address Latch Enable. This signal helps to capture the lower order address presented on the multiplexed address / data bus.

S1 and S0: These status signals, similar to , can identify various operations,

8085 Microprocessor Pinout and Signals All the operations and their associated status signals are listed in Table for reference :

Generating Control Signals

Four Control Signals are generated by
combining the signals RD, WR and IO/M

This signal is ANDed with RD and WR

signals by using 74LS32 quadruple two input OR gates.

OR gates are functionally connected as

negative NAND gates.

When both inputs are low output are low

generate MEMR and MEMW control signal.

IO/M goes high, indicates peripheral I/O

operation.

Fig shows signal is complemented with

hex inverter 74LS04 and ADDed with RD

 The power supply and frequency signals as follows:

Vcc: +5V power supply.

8085 Microprocessor Pinout and Signals: Power Supply And Clock Frequency

Vss: Ground Reference.

X1, X2: A crystal (or RC, LC network) is connected at these two
pins. The frequency is internally divided by two; therefore, to operate a system at 3 MHz, the crystal should have a frequency of 6 MHz.

CLK (OUT) Clock Output: This signal can be used as the system
clock for other devices.

8085 Microprocessor Pinout and Signals Externally Initiated Signals, Including Interrupts
The 8085 have five interrupt signals that can be used to interrupt a program
execution. One of the signals, INTR (Interrupt Request), is identical to the 8080A microprocessor or interrupt signal (INT); the others are enhancement to the 8080A. The microprocessor acknowledges an interrupt request by the INTA (Interrupt Acknowledge) signal.

In addition to the interrupts, three pinsRESET, HOLD and READY

accept the externally initiated signals as inputs. To respond to the HOLD request, it has one signal called HLDA (Hold Acknowledge).

RESET IN: When the signal on this pin goes low, the program counter is set
to zero, the buses are tri-stated, and the MPU is reset.

RESET OUT: This signal indicates that the MPU is being reset. This signal

8085 Microprocessor Pinout and Signals Serial I/O Ports

Input Data) and SOD (Serial Output Data).

The 8085 have two signals to implement the serial transmission: SID (Serial

FUNCTIONAL BLOCK DIAGRAM OF 8085

Example of 8085Microcomputer
8085 Microcomputer includes:

8085 Microprocessor. An octal latch(de-multiplexes the buses AD7-AD0 using signal ALE). Logic gates (to generate control signals). Interfacing devices buffers, decoders and latches. Unidirectional Bus Driver for address bus (to increase the driving
Bidirectional Bus Driver for data bus (to increase the driving capacity
of bus)
capacity of bus)

TIMING DIAGRAM
Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states. Instruction Cycle:

The time required to execute an instruction is called instruction cycle. 8085

instruction cycle consist of 1 to 6 machine cycle ( or operations).

Machine Cycle:

The time required to complete one operation of accessing memory,

input/output devices or acknowledging an external request is called machine cycle. It consist of 3 to 6 T-states.

T-State ( or Clock Period):

The machine cycle and instruction cycle takes multiple clock periods. A portion of an operation carried out in one system clock period is called as

MACHINE CYCLES OF 8085:

The 8085 microprocessor has 5 basic machine cycles. They are:

Opcode fetch cycle (4T) Memory read cycle (3T) Memory write cycle (3T) I/O read cycle (3T)

Microprocessor Communication and Bus Timings

Microprocessor Communication and Bus Timings

Opcode fetch machine cycle of 8085 :

Each instruction of the processor has one byte opcode. The opcodes are stored in memory. So, the processor executes the
opcode fetch machine cycle to fetch the opcode from memory.

Hence, every instruction starts with opcode fetch machine cycle.

The time taken by the processor to execute the opcode fetch cycle
is 4T.

In this time, the first, 3 T-states are used for fetching the opcode
from memory and the remaining T-states are used for internal operations by the processor.

Microprocessor Communication and Bus Timings

To understand the functions of various signals of the 8085, we should examine the process of communication (reading from and writing into the memory) between the microprocessor and memory and the timings of these signals in relation to the system clock. The first step in the communication process is reading from memory or fetching an instruction.

Step 1: The microprocessor places the 16-bit memory address from the

program counter (PC) on the address bus. At T1 20H is placed on A15-A8 and 05H is placed on AD7-AD0. ALE goes high, goes low.

Step 2: The control unit sends the control signal RD to enable the memory
chip. It is active during 2 clock periods.

Step 3: The byte (4FH)from the memory location is placed on the data bus
(AD7-AD0) when memory is enabled and when RD goes high it causes buses to go into high impedance.

Microprocessor Communication and Bus Timings

Demultiplexing the Bus AD7-AD0

Need for Demultiplexing the Bus AD7-AD0

Address on high-order bus (20H) remains on bus for three clock periods.

Loworder address 05H is lost after the first clock period.

Address need to be latched and used for identifying memory location
(2005H), the address will change to 204FH after first clock periods.

When ALE goes high (during T1), the latch is transparent (output changes
according to input). During T1 output of latch is 05H.

When ALE goes Low, the data byte 05H is latched until next ALE, and
output of latch represents the low-order address bus AD7-AD0 after latching operation.

Read Machine Cycle of 8085:

ALE is asserted at the beginning of T1 of each bus cycle and is

negated towards the end of T1. ALE is active during T1 only and is used as the clock pulse to latch the address (AD7 AD0) during T1.

The RD is asserted near the beginning of T2. It ends at the end of

T3. As soon as the RD becomes active, it forces the memory or I/O port to assert data. RD becomes inactive towards the end of T3, causing the port or memory to terminate the data.

The memory read machine cycle is executed by the processor to

read a data byte from memory.

The processor takes 3T states to execute this cycle. The instructions which have more than one byte word size (like

Timing Diagram of 8085 Memory Read Machine Cycle

Timing Diagram of 8085 I/O Read Machine Cycle

Memory Write Machine Cycle of 8085

Immediately after the termination of the low order address, at the beginning of
the T2, data is asserted on the address/data bus by the processor.

WR control is activated near the start of T2 and becomes inactive at the end of
T3. The processor maintains valid data until after WR is terminated. This ensures that the memory or port has valid data while WR is active.

I/O Write Cycle of 8085

The I/O write machine cycle is executed by the processor to write a

data byte in the I/O port or to a peripheral, which is I/O, mapped in the system.

The processor takes, 3T states to execute this machine cycle.

The 8085 instructions consist of one to five machine cycles.

Actually the execution of an instruction is the execution of the machine

cycles of that instruction in the predefined order. The timing diagram is obtained by drawing the timing diagrams of the machine cycles of that instruction, one by one in the order of execution.

I/O Write Cycle of 8085

Examining 2-byte instruction for memory Read

To examine Memory Read operation we always examine 2-byte or 3-byte instruction because in 1-byte instruction machine code is an opcode therefore operation is always an Opcode Fetch.

To understand the memory read machine cycle, lets study the execution of the following instruction MVI A, 32
In memory, this instruction looks like: -The first byte 3EH represents the opcode for loading a byte into the accumulator (MVI A),
the second byte is the data to be loaded.

The 8085 needs to read these two bytes from memory before it can execute the instruction. Therefore, it will need at least two machine cycles.
-The first machine cycle is the opcode fetch. -The second machine cycle is the Memory Read Cycle.

MVI A,32H Instruction

2000H 3EH ;MVI A, 32H

2001H 32H
M1 (Opcodefetch) T
2

T
1

T
3

T
4

M2 (Memory Read) T T T
1 2 3

A15-A8 AD7-AD0 ALE

20H; high-order address

00H; loworder Add
3E; opcode

Unspecified

20H; High-order address

01H; loworder Add

32H; Data

Status IO/M=0,S1=1,S0=1; opcode fetch

Status IO/M=0,S1=1,S0=0; data read

RD

Execution Times of Memory Read Cycle and Instruction cycle are calculated as:
Time required to execute 1 T-state = 1/ operating frequency of 8085 Microprocessor
For example operating frequency = 2MHz then time required to execute 1 T-state = 0.5 Sec Execution Time for Opcode Fetch: (4T)x.5=2 Sec Execution Time for Memory Read: (3T)x.5= 1.5 Sec Execution Time for Instruction: (7T)x.5= 3.5 Sec

Examining 3-byte instruction for memory Read

STA 2065H: This instruction store the content of Accumulator in Memory
Location 2065H. Opcode
STA

Operand
2065

Bytes
3

Machine Cycles 4

T-states
13

Machine Codes are stored in 2010H, 2011H and 2012H in reverse order Memory Address 2010 2011 2012 Machine Code 0011 0010->32H Opcode 0110 0101->65H Low Order Address 0010 0000-> 20H High-order Address

Examining 3-byte instruction for memory Read

In the first machine cycle, the 8085 places address 2010H on the address bus
and fetch the opcode 32H.

The second machine cycle is Memory Read. The processor places the address
2011H and get the low-order byte 65H.

The third machine cycle is also Memory Read, the 8085 get the high order byte
20H from memory location 2012H.

The last machine cycle is memory write. The 8085 places the address 2065H
on the address bus, identifies the operation as Memory Write (IO/M=0 S1=0 and S0=1). It places contents of data bus AD7-AD0 and asserts the WR signal. During the last T-state the contents of data bus are placed in memory location 2065H.

Assume the memory address for the instruction and let the content of
accumulator is C7H. So, C7H from accumulator is now stored in 2065H.

Timing Diagram of 3-byte instruction

Timing diagram for IN C0H.

Fetching the Opcode DBH from the memory 4125H.

Read the port address C0H from 4126H.

Read the content of port C0H and send it to the accumulator.

Let the content of port is 5EH.

Timing diagram for IN C0H.