COMPUTER organization & architecture

Lecture-1 UNIT-II
Topics to be covered
 CPU Organization
 Data Representation
 Instruction Set
 CPU Organization
 What is CPU?
 Fundamentals

 Additional Features
 What is CPU? How it Organized?
 CPU:
 CPU (pronounced as separate letters) is the abbreviation for
Central Processing Unit. Sometimes referred to simply as
the Central Processor, but more commonly called Processor,
the CPU is the brains of the computer where most
calculations take place. In terms of computing power, the
CPU is the most important element of a computer system.
 The Components of a CPU are:
• The Arithmetic Logic Unit (ALU), which performs
arithmetic and logical operations.
• The Control Unit (CU), which extracts instructions
from memory and decodes and executes them, calling
on the ALU when necessary.
• The Registers, which holds the data temporarily before
and after processing.
Fundamentals:
 The Primary function of the CPU is to execute sequence of
instructions, that is, programs, which are stored in an external main
memory.
1. The CPU transfers the instructions, and when necessary, their input
data (operands) from main memory to registers in CPU.
2. The CPU executes the instructions in their stored sequence except
when the execution sequence is explicitly altered by a branch
instruction.
3. If necessary, the CPU transfers output data (results) from the CPU
registers to main memory.
Central Processing Unit
 Manages the Instruction-Execution Cycle
 FETCH – DECODE – EXECUTE
 Coordinates the activities of other devices
Connections between the Processor and Memory

Memory
Processor

MAR MDR
Control
R0
PC
R1
.
IR
.
ALU
Rn-1
n general purpose
registers
Instruction Register (IR)
 The instruction register holds the instruction that is
currently being executed.

 Its
output is available to the control circuits, which generate
the timing signals that control the various processing
elements involved in executing the instruction
Program Counter (PC)
 The program counter is another specialized register.
 It keeps track of the execution of a program.
 It contains the memory address of the next instruction to be
fetched and executed.
 During the execution of an instruction, the contents of the PC
are updated to correspond to the address of the next
instruction to be executed.
 It is customary to say that PC points to the next instruction
that is to be fetched from the memory.
Memory address register (MAR) & Memory
data register (MDR)
 Thesetwo registers facilitate communication with the
memory.

 The MAR holds the address of the location to be accessed.

 The MDR contains the data to be written into or read out of

the addressed location.
Operating steps for Program execution
 Programs are stored in the memory through the input unit.

 Execution of the program starts when the PC is set to point to the first
instruction of the program.

 The contents of the PC are transferred to the MAR and a Read control signal
is sent to the memory.

 After the time required to access the memory elapses, the addressed word (in
this case, the first instruction of the program) is read out of the memory and
loaded into the MDR.
Operating steps for Program execution (Contd.,)
 Next, the contents of the MDR are transferred to the IR .

 At this point, the instruction is ready to be decoded and executed.

 If the instruction involves an operation to be performed by the ALU, it

is necessary to obtain the required operands.

 Ifan operand resides in memory ( it could also be in a general-purpose

register in the processor), it has to be fetched by sending its address to
the MAR and initiating a Read cycle.
Operating steps for Program execution (Contd.,)
 When the operand has been read from the memory into the MDR, it
transferred from the MDR to the ALU.

 After one or more operands are fetched in this way, the ALU can perform the
desired operation.

 If the result of the operation is to be stored in the memory, then the result is
sent to the MDR.

 The address of the location where the result is to be stored is sent to the
MAR, and a write cycle is initiated.
Operating steps for Program execution (Contd.,)
 At some point during the execution of the current instruction, the contents of
the PC are incremented so that the PC points to the next instruction to be
executed.

 Thus, as soon as the execution of the current instruction is completed, a new

instruction fetch may be started.

 In addition to transferring data between the memory and the processor, the
computer accepts data from input devices and sends data to output devices.
Thus, some machine instructions with the ability to handle I/O transfers are
provided.
Example: High-Level/Low-Level Languages, Machine Code
 High-Level Language (e.g. Java, C++)

A=B+C Assignment Statement

 Low-Level Language -> Assembly Language (e.g. Pentium, PowerPC,

ARM etc,)
LOAD R2, B Assembly Language
ADD R2, C Instructions
STORE R2, A

 (Binary) Machine Code

0001101000000001 Machine Code
0011101000000010 Instructions
0010101000000000
Let us Consider a simple Architecture
 Maximum of 1024 x 16-bit memory words
Memory is Word Addressed

 Two’s Complement Integer Representation

 4 General Purpose Registers (16-bit) : R0, R1, R2, R3

 Upto 16 “Instructions”, e.g. LOAD, ADD, STORE


 LOAD Register , [MemoryAddress]
Register = Memory [MemoryAddress]

 STORE Register , [MemoryAddress]

Memory [MemoryAddress] = Register

 ADD Register , [MemoryAddress]

Register = Register + Memory [MemoryAddress]

 SUB Register , [MemoryAddress]

Register = Register - Memory [MemoryAddress]
Instruction Format
Assembly Instruction e.g. ADD R2, C

Machine Code OPCODE REG ADDRESS

4-bit 2-bit 10-bit

Instruction Fields
 OPeration CODE (Selects CPU Instruction)
 REGister (Specifies 1st Operand for Instruction)
 ADDRESS (Specifies 2nd Operand for Instruction)
Instruction Field Encoding
OPCODE REG ADDRESS

4-bit 2-bit 10-bit 16-bit Instruction

 OPCODE LOAD 0001

(4-bit) STORE 0010
ADD 0011
SUB 0100
 REG Register 0 00
(2-bit) Register 1 01
Register 2 10
Register 3 11
 ADDRESS 10-bit Memory Word Address
Memory Placement (Program)
Assembly Machine Instruction Memory
Instruction OP REG ADDRESS Address

LOAD R2, [201H] 000 10 10 0000 00 1000

1 0001 0000
A 0 1 0 8 0
1 H
ADD R2, 001 10 10 0000 00 1000
[202H] 1 0010 0001
A 0 2 0 8 1
3 H
STORE R2, 001 10 10 0000 00 1000
[200H] 0 0000 0010
2 A 0 0 0 8 2
H

MEMORY
Memory Placement (Data)
Assembly Data Memory
Instruction Address

A=0 0000 0000 0000 10 0000

0000 0000
0 0 0 0 2 0 0
H
B=9 0000 0000 0000 10 0000
1001 0001
0 0 0 9 2 0 1
H
C=6 0000 0000 0000 10 0000
0110 0010
0 0 0 6 2 0 2
H

MEMORY
 CPU Organisation
CPU R0 000
Address 001
R1 002
R2 Bus
I 003
R3 n
t
ALU e
Input Reg1 Data
r Bus
Output Reg RAM
n
Input Reg2 a
l
Control
Program Counter MAR B Bus
u
Instr. Decoder Instr. Register MDR s
3FD
3FE
Control Unit 3FF
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H 002
R2 003

ALU

080H
RAM

080H
PC 080H 0
Instr. Decoder
3FD

0
0 3FE
Control Unit 3FF
1
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H 002
R2 003

ALU

RAM

PC 080H + 1 0
Instr. Decoder
3FD
3FE
Control Unit 3FF
2
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H 002
R2 003

ALU

RAM

0
PC 081H
Instr. Decoder
3FD
3FE
Control Unit 3FF
3
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H
R2
080 1A01H
1A01
081 3A02H
ALU 082 2A00H

RAM

200 0000
0 201 0009
PC 081H 202 0006

Instr. Decoder
3FD
3FE
Control Unit 3FF
4
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
201H
R2
080 1A01H
081 3A02H

201H
ALU 082 2A00H
1A01H 1A01
RAM

1A01H
200 0000
201 0009
PC 081H 0 202 0006
1A01H
1A01H 1A01H
3FD

0
1, 2, 201H 201H 3FE
1, 2, 201H 0 3FF
5
LOAD R2, [201H] R2=Memory[201H]
CPU 000
201H 001
0009 201H
R2 0009
080 1A01H
081 3A02H

0009
ALU 082 2A00H
0009 0009
RAM

200 0000
0 201 0009
0009
PC 081H 0 202 0006

1A01H
3FD
3FE
1, 2, 201H 3FF
6
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
081H
R2 0009
080 1A01H
081 3A02H

081H
ALU 082 2A00H

RAM

200 0000
081H 201 0009
PC 081H 0 202 0006

3FD

0
0 3FE
3FF
7
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
081H
R2 0009
080 1A01H
081 3A02H
ALU 082 2A00H

RAM

200 0000
201 0009
PC 081H+ 1 0 202 0006

3FD
3FE
3FF
8
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
081H
0009 202H
R2 0009
0009

3A02H 202H 0009

080 1A01H
081 3A02H
3A02
ALU 0009 082 2A00H
0009 3A02H 3A02H
RAM

200 0000
201 0009
PC 082H 0 0 202 0006
3A02H
3A02H 3A02H
3FD

0
3, 2, 202H 202H 3FE
3, 2, 202H 0 3FF
9
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
000FH 202H 202H
R2 000FH
0009

000FH 000FH
080 1A01
081 3A02
082 2A00
ALU
0009 0006 0006
000FH ADD RAM
0006
000FH 0006
200 0000
201 0009
PC 082H 0 0 202 0006
0006

3A02H
3FD
3FE
3, 2, 202H 10
3FF
STORE R2, [200H] Memory[200H]=R2
CPU 000
001
082H
R2 000FH
080 1A01H

082H
081 3A02H
ALU 082 2A00H

RAM

200 0000
082H 201 0009
PC 082H 0 202 0006

3FD

0
0 3FE
3FF
11
STORE R2, [200H] Memory[200H]=R2
CPU 000
001
082H
R2 000FH
080 1A01H
081 3A02H
ALU 082 2A00H

RAM

200 0000
201 0009
PC 082H + 1 0 202 0006

3FD
3FE
3FF
12
STORE R2, [200H] Memory[200H]=R2
CPU 000
001
200H 082H
000FH

2A00H 200H 000FH

R2 000FH
000F
080 1A01H
081 3A02H
ALU 082 2A00H
2A00
000FH 2A00H
RAM

200 0000
201 0009
PC 1 1
083H 202 0006
2A00H
2A00H 2A00H
3FD

1
2, 2, 200H 200H 3FE
2, 2, 200H 1 3FF
13
STORE R2, [200H] Memory[200H]=R2
CPU 000
200H 200H 001

R2 000FH
080 1A01H
081 3A02H
ALU 082 2A00H
00FH 00FH
RAM

200 000FH
0000
1 1 201 0009
PC 083H 202 0006

3FD
3FE
3FF
14
Summery:
 Fetch the Instruction

 Increment the Program Counter

 Decode the Instruction

 Fetch the Operands

 Perform the Operation

 Store the Results

 Repeat Forever
Any Questions?
 COMPUTER organization & architecture

Lecture-2 UNIT-II
 CPU Organization
 What is CPU?
 Fundamentals

 Additional Features
Re-Cap
 What is CPU?
 Fundamentals
 Fetch the Instruction

 Increment the Program Counter

 Decode the Instruction

 Fetch the Operands

 Perform the Operation

 Store the Results

 Repeat Forever
Additional Features:
Architecture extensions:
The basic design of CPU is improved to increase performance and ease of
programming.
 Multipurpose registers for storing data and address:
 Thesereplace the accumulator AC and auxiliary registers DR and AR of basic
CPU  general register organization, 32 such registers, usually referred as
Register file.
 Additional data, Instruction, and address types:
 Most CPUs have instructions to handle data and address with various
different word sizes and formats. Some CPUs have only ADD/SUB
instructions in their arithmetic.

 Little extra circuitry required for fixed point arithmetic of MUL/DIV

 to simplify the programming tasks.

 CALL and RET instructions also simplify program design.

 Registers to indicate computation status:

A Status Register also called as Flag register indicates the exceptional

conditions resulting from the instruction execution. Ex. Zero result
obtained, Invalid instruction like divide by zero etc.

 It also indicates the user and supervisor states.

 Conditionalbranch instruction check the status register , which simplifies

the programming of conditional actions.
 Program control stack:
 Various
special registers and instructions facilitate the transfer of control
among the programs due to procedure calling or external interrupts.

 Many CPUs use flexible scheme for program control transfer, which
employs the part of the external memory M as a push down stack.

 The stack memory is intended for saving the key information about an
interrupted program via PUSH operations so that the saved information can
be retrieved later via POP operations.
Pipelining:

A substantial improvement in performance can be achieved by overlapping

the execution of successive instructions, using a technique called
Pipelining.

 Overlapping of instruction fetching and execution is an example of

Instruction Pipeline, which is an important speed up feature in RISC
Processors.
 Pipelining: Overlapping Instruction in 2 Stage
Fetch + Execute

Hence Two instructions can be processed simultaneously in every CPU clock cycle, with
one completing its fetch phase and the other completing its execute phase.
So this will double the CPU performance.
 Co-Processors (P):
 It
is a specialized instruction execution unit that can be coupled
to a microprocessor so that instructions to be executed by P can
be included in programs fetched by the microprocessor.
Fig. 68020-Based Micro-Computer with Floating Point Co-Processor
 CISC and RISC
 CISC – complex instruction set
 Large Instruction Set
 High-Level Operations (simpler for compiler?)
 Requires Microcode Interpreter (could take a long time)
 Examples: Intel 80x86 family
 RISC – reduced instruction set
 Small Instruction Set
 Simple, Atomic Instructions
 Directly Executed by Hardware very Quickly
 Easier to Incorporate Advanced Architecture Design
 Examples: ARM (Advanced RISC Machines) and DEC Alpha (now Compaq),
PowerPC, MIPS
 CISC Machine:
 Instruction pipeline
 Superscalar processing
 Floating point execution unit etc.
 Ex. Motorola 68060
Multiprocessors
 Large computer systems may contain a number of processor units, in which
case they are called Multiprocessor systems.
 These systems either execute a number of different application tasks in
parallel, or they execute subtasks of a single large task in parallel.

 Ex: Dual Core, Quad Core, Octa Core etc

Summery:
 Architecture extensions
 Pipelining
 Co-Processors (P)