ARM7TDMI Architecture

ARM Programming model
• ARM core are functional units connected by data buses, where

the arrows represent the flow of data, the lines represent the
buses, and the boxes represent either an operation unit or a
storage area.
• Data enters the processor core through the Data bus. The data
may be an instruction to execute or a data item.
• The instruction decoder translates instructions before they are
executed.
• The ARM processor uses a load-store architecture.
– Load instructions copy data from memory to registers in
the core,
– store instructions copy data from registers to memory.
• There are no data processing instructions that directly
manipulate data in memory. Thus, data processing is carried out
solely in registers.
• Data items are placed in the register file—a storage bank made up of 32-bit registers.
• Since the ARM core is a 32-bit processor, most instructions treat the registers as holding signed or unsigned 32-bit
values.
• The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-bit values as they are read from memory
and placed in a register.
• ARM instructions typically have two source registers, Rn and Rm, and a single result or destination register, Rd.
• Source operands are read from the register file using the internal buses A and B, respectively.
• The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the register values Rn and Rm from the A
and B buses and computes a result.
• Data processing instructions write the result in Rd directly to the register file.
• Load and store instructions use the ALU to generate an address to be held in the address register and broadcast on the
Address bus.
• register Rm alternatively can be preprocessed in the barrel shifter before it enters the ALU. Together the barrel
shifter and ALU can calculate a wide range of expressions and addresses.
• For load and store instructions the incrementer updates the address register before the core reads or writes the
next register value from or to the next sequential memory location.
• The processor continues executing instructions until an exception or interrupt changes the normal execution flow.
REGISTERS
• General-purpose registers hold either data or an address.
• They are identified with the letter r prefixed to the register number
• There are up to 18 active registers: 16 data registers and 2 processor
status registers.
• The data registers are visible to the programmer as r0 to r15.
• It has three registers assigned as special function registers:
– r13 is used as the stack pointer (sp) and stores the head of the
stack in the current processor mode.
– r14 is called the link register (lr) where the core puts the return
address whenever it calls a subroutine.
– r15 is the program counter (pc) and contains the address of the
next instruction to be fetched by the processor.
PROGRAM STATUS REGISTER
1. Current Program Status Register

– The ARM core uses the cpsr to monitor and control internal operations.
– The cpsr is a dedicated 32-bit register and resides in the register file.
– The cpsr is divided into four fields, each 8 bits wide: flags, status, extension, and control.
– In current designs the extension and status fields are reserved for future use.
– The control field contains the processor mode, state, and interrupt mask bits.
– The flags field contains the condition flags.
– the J bit, which can be found in the flags field, is only available on Jazelle-enabled processors, which
execute 8 bit instructions
• Saved program status register (spsr), which stores the previous mode’s cpsr.
Processor Modes
• The processor mode determines which registers are active and has the access rights to the cpsr register itself.
• Each processor mode is either privileged or nonprivileged:
• A privileged mode allows full read-write access to the cpsr.
• A nonprivileged mode only allows read access to the control field in the cpsr but still allows read-write access to
the condition flags.
• There are seven processor modes in total:
• six privileged modes

 The processor enters abort mode when there is a failed attempt to access memory.
 Fast interrupt request and interrupt request modes correspond to the two interrupt levels available on the
ARM processor.
 Supervisor mode is the mode that the processor is in after reset and is generally the mode that an operating
system kernel operates in.
 System mode is a special version of user mode that allows full read-write access to the cpsr.
 Undefined mode is used when the processor encounters an instruction that is undefined or not supported by
the implementation.
• one nonprivileged mode User mode is used for programs and applications.
Condition Flags
Banked Registers
• Of all 37 registers in the register file, 20

registers are hidden from a program at
different times - banked registers
• They are available only when the processor
is in a particular mode
• for example, abort mode has banked registers r13_abt, r14_abt and spsr_abt.
• Banked registers of a particular mode are denoted by an underline character post-fixed to the mode mnemonic or
_mode.
• Except user mode, Every processor mode can change by writing directly to the mode bits of the cpsr or by
hardware when the core responds to an exception or interrupt.
• All processor modes except system mode have a set of associated banked registers that are a subset of the main
16 registers.
• If you change processor mode, a banked register from the new mode will replace an existing register.
• For example, when the processor is in the interrupt request mode, the instructions you execute still access
registers named r13 and r14. However, these registers are the banked registers r13_irq and r14_irq.
Pipeline
Exceptions, Interrupts, and the Vector Table
• When an exception or interrupt occurs, the processor sets the pc to a specific memory address.
• The address is within a special address range called the vector table.
• The memory map address 0x00000000 is reserved for the vector table, a set of 32-bit words.
• On some processors the vector table can be optionally located at a higher address
• When an exception or interrupt occurs, the processor suspends normal execution and starts loading instructions
from the exception vector table.
• Each vector table entry contains a form of branch instruction pointing to the start of a specific routine
• Reset vector: is location of the first instruction executed by the processor when power is applied. This instruction
branches to the initialization code.
• Undefined instruction vector: is used when the processor cannot decode an instruction.
• Software interrupt vector: is called when you execute a SWI instruction. The SWI instruction is frequently used
as the mechanism to invoke an operating system routine.
• Prefetch abort vector: occurs when the processor attempts to fetch an instruction from an address without the
correct access permissions. The actual abort occurs in the decode stage.
• Data abort vector: is similar to a prefetch abort but is raised when an instruction attempts to access data memory
without the correct access permissions.
• Interrupt request vector: is used by external hardware to interrupt the normal execution flow of the processor. It
can only be raised if IRQs are not masked in the cpsr.
• Fast interrupt request vector : is similar to the interrupt request but is reserved for hardware requiring faster
response times. It can only be raised if FIQs are not masked in the cpsr.

ARM7TDMI Architecture

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ARM7TDMI Architecture

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ARM Programming model

• ARM core are functional units connected by data buses, where

1. Current Program Status Register

– The flags field contains the condition flags.

• six privileged modes

• Of all 37 registers in the register file, 20

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