Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd
Upload
2K views

Arm Program Model

The ARM processor uses a load-store architecture with 16 general purpose registers that are visible to programmers. It has a Current Program Status Register (CPSR) that contains condition codes. Memory is addressed at the byte level and data is aligned to words and half-words. Instructions only operate on registers and either load data to/from memory or control program flow. The ARM supports supervisor mode to protect system resources from user programs.

Uploaded by

vlkumashankardeekshith
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
2K views

Arm Program Model

The ARM processor uses a load-store architecture with 16 general purpose registers that are visible to programmers. It has a Current Program Status Register (CPSR) that contains condition codes. Memory is addressed at the byte level and data is aligned to words and half-words. Instructions only operate on registers and either load data to/from memory or control program flow. The ARM supports supervisor mode to protect system resources from user programs.

Uploaded by

vlkumashankardeekshith
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

unit 4

2. Describe ARM programmer's model in detail. [OR] Explain the various operating
modes programmers model in ARM processor. [Nov’16] [OR] Explain the ARM
programmer’s model in detail, with supporting diagram. [Apr’17] [OR] Draw and
explain the visible registers in an ARM processor. [Apr’18]
 A processor's instruction set defines the operations that the programmer can use to
change the state of the system incorporating the processor.
 This state usually comprises the values of the data items in the processor's visible
registers and the system's memory.
 Each instruction can be viewed as performing a defined transformation from the state
before the instruction is executed to the state after it has completed.
 The visible registers in an ARM processor are shown in Figure.
 When writing user-level programs, only the 15 general-purpose 32-bit registers (r0 to
r14), the program counter (r15) and the current program status register (CPSR) need be
considered.
 The remaining registers are used only for system-level programming and for handling
exceptions (for example, interrupts).
ARM's visible registers

The Current Program Status Register (CPSR)


 The CPSR is used in user-level programs to store the condition code bits. These bits are
used, to record the result of a comparison operation and to control whether or not a
conditional branch is taken.
 The user-level programmer need not usually be concerned with how this register is
configured, but for completeness the register is illustrated in figure below.
 The bits at the bottom of the register control the processor mode, instruction set and
interrupt enables and are protected from change by the user-level program.

ARM CPSR format

 N: Negative; the last ALU operation which changed the flags produced a negative
result (the top bit of the 32-bit result was a one).
 Z: Zero; the last ALU operation which changed the flags produced a zero result
(every bit of the 32-bit result was zero).
 C: Carry; the last ALU operation which changed the flags generated a carry-out,
either as a result of an arithmetic operation in the ALU or from the shifter.
 V: Overflow; the last arithmetic ALU operation which changed the flags generated an
overflow into the sign bit.

The memory system


 In addition to the processor register state, an ARM system has memory state.
 Memory may be viewed as a linear array of bytes numbered from zero up to 23.
 Data items may be 8-bit bytes, 16-bit half-words or 32-bit words.
 Words are always aligned on 4-byte boundaries (that is, the two least significant address
bits are zero) and half-words are aligned on even byte boundaries.
 The memory organization is illustrated in figure below. This shows a small area of
memory where each byte location has a unique number.
 A byte may occupy any of these locations.
 A word-sized data item must occupy a group of four byte locations starting at a byte
address which is a multiple of four.
 Half-words occupy two byte locations starting at an even byte address.

ARM memory organization.

Load-store architecture
 In common with most RISC processors, ARM employs a load-store architecture.
 This means that the instruction set will only process (add, subtract, and so on) values
which are in registers (or specified directly within the instruction itself), and will always
place the results of such processing into a register.
 The only operations which apply to memory state are ones which copy memory values
into registers(load instructions) or copy register values into memory (store instructions).
 CISC processors typically allow a value from memory to be added to a value in a
register, and sometimes allow a value in a register to be added to a value in memory.
 ARM does not support such 'memory-to-memory' operations.

 Therefore all ARM instructions fall into one of the following three categories:
 Data processing instructions.
 These use and change only register values.
 For example, an instruction can add two registers and place the result in a
register.

 Data transfer instructions.


 These copy memory values into registers (load instructions) or copy register
values into memory (store instructions).
 An additional form, useful only in systems code, exchanges a memory value
with a register value.
 Control flow instructions.
 Control flow instructions cause execution to switch to a different address,
either permanently (branch instructions) or saving a return address to resume
the original sequence (branch and link instructions) or trapping into system
code (supervisor calls).
Supervisor mode
 The ARM processor supports a protected supervisor mode.
 The protection mechanism ensures that user code cannot gain supervisor privileges
without appropriate checks being carried
 Out to ensure that the code is not attempting illegal operations.
 The upshot of this for the user-level programmer is that system-level functions can only
be accessed through specified supervisor calls.
 These functions generally include any accesses to hardware peripheral registers, and to
widely used operations such as character input and output.
 User-level programmers are concerned with devising algorithms to operate on the data
'owned' by their programs, and rely on the operating system to handle all transactions
with the world outside their programs.
 The instructions which request operating system functions are covered in 'Supervisor
calls'

ARM instruction set


 All ARM instructions are 32 bits wide and are aligned on 4-byte boundaries in memory.
 The features of the ARM instruction sets are:
 The load-store architecture;
 3-address data processing instructions (the two source operand registers and the
result register are all independently specified);
 Conditional execution of every instruction;
 The inclusion of very powerful load and store multiple register instructions;
 The ability to perform a general shift operation and a general ALU operation in a
single instruction that executes in a single clock cycle;
 Open instruction set extension through the coprocessor instruction set, including
adding new registers and data types to the programmer's model;
 A very dense 16-bit compressed representation of the instruction set in the
Thumb architecture.
 For the small embedded systems that most ARM processors are used in, this code
density advantage outweighs the small performance penalty incurred by the decode
complexity.
 Thumb code extends this advantage to give ARM better code density than most CISC
processors.

The I/O system


 The ARM handles I/O (input/output) peripherals (such as disk controllers, network
interfaces, and so on) as memory-mapped devices with interrupt support.
 The internal registers in these devices appear as addressable locations within the ARM's
memory map and may be read and written using the same (load-store) instructions as
any other memory locations.
 Peripherals may attract the processor's attention by making an interrupt request using
either the normal interrupt (IRQ) or the fast interrupt (FIQ) input.
 Both interrupt inputs are level-sensitive and mask able.
 Normally most interrupt sources share the IRQ input, with just one or two time-critical
sources connected to the higher-priority FIQ input.
 Some systems may include direct memory access (DMA) hardware external to the
processor to handle high-bandwidth I/O traffic.

You might also like