ARM Processor :

ARM is a a 32-bit RISC processor architecture currently being developed by the ARM corporation. ARM processors possess a unique combination of features that makes ARM the most popular embedded architecture today. 1. First, ARM cores are very simple compared to most other general-purpose processors, which means that they can be manufactured using a comparatively small number of transistors, leaving plenty of space on the chip for application-specific macrocells. A typical ARM chip can contain several peripheral controllers, a digital signal processor, and some amount of on-chip memory, along with an ARM core. 2. Second, both ARM ISA and pipeline design are aimed at minimising energy consumption a critical requirement in mobile embedded systems. 3. Third, the ARM architecture is highly modular: the only mandatory component of an ARM processor is the integer pipeline; all other components, including caches, MMU, floating point and other co-processors are optional, which gives a lot of flexibility in building application-specific ARM-based processors. Finally, while being small and low-power, ARM processors provide high performance for embedded applications. For example, the PXA255 XScale processor running at 400MHz provides performance comparable to Pentium 2 at 300MHz, while using fifty times less energy. The business model behind ARM is based on licensing the ARM architecture to companies that want to manufacture ARM-based CPUs or system-on-a-chip products. The two main types of licenses are : 1. Implementation license 2. Architecture license.

The Implementation license provides complete information required to design and manufacture integrated circuits containing an ARM processor core. ARM licenses two types of cores: soft cores and hard cores. A hard core is optimised for a specific manufacturing process, while a soft core can be used in any process but is less optimised. The architecture license enables the licensee to develop their own processors compliant with the ARM ISA.

ARM designs various 16/32-bit architecture for microprocessors and controllers. Those designs are then licensed to electronic companies to be used as embedded solutions. For example, Intel licensed Arm technology to create the StrongArm and the Xscale processor, both used in modern PDA and network equipment

ARM Architecture :
ARM has 37 registers in total, all of which are 32-bits long. 1 dedicated (program counter) 1 dedicated (current program status register)

5 dedicated (saved program status registers) 30 (general purpose registers) And Each mode can access a particular set of r0-r12 registers a particular r13 (the stack pointer) and r14 (link register) r15 (the program counter) cpsr (the current program status register) and privileged modes can also access a particular spsr (saved program status register)

The ARM ISA provides 16 general-purpose registers in the user mode. i.e ARM architecture has 16 registers. R0-R12 : 13 general purpose registers R13: Stack Pointer R14: Link Register R15: Program Counter Bit 2-25 : Next Instruction ( only 24 bits because instructions are word aligned ) Bit 0-1 and 26-31 : Status Register

In addition to user-visible registers, ARM provides several registers available in privileged modes only. SPSR registers are used to store a copy of the value of the CPSR register before an exception was raised.Those privileged modes that are activated in response to exceptions have their own R13 and R14 registers, which allows to avoid saving the corresponding user registers on every exception. In order to further reduce the amount of state that has to be saved during handling of fast interrupts, ARM provides 5 additional registers available in the fast interrupt processing mode only.

Processor Modes : The ARM has six operating modes:

1. 2. 3. 4. 5. 6. User (unprivileged mode under which most tasks run) FIQ (entered when a high priority (fast) interrupt is raised) IRQ (entered when a low priority (normal) interrupt is raised) Supervisor (entered on reset and when a Software Interrupt instruction is executed) Abort (used to handle memory access violations) Undef (used to handle undefined instructions)

ARM Architecture Version 4 adds a seventh mode: 7. System (privileged mode using the same registers as user mode)

All other execution modes are privileged and are therefore only used to run system software. Fast interrupt processing mode is entered whenever the processor receives an interrupt signal from the designated fast interrupt source. Normal interrupt processing mode is entered whenever the processor receives an interrupt signal from any other interrupt source. Software interrupt mode is entered when the processor encounters a s/w interrupt instruction. Software interrupts are a standard way to invoke OS services on ARM. Undefined instruction mode is entered when the processor attempts to execute an instruction that is supported neither by the main integer core nor by one of the coprocessors. This mode can be used to implement coprocessor emulation. System mode is used for running privileged operating system tasks. Abort mode is entered in response to memory faults.

Instructions : The ARM processor supports 25 different instruction.

1. 2. 3. 4. These instructions can be grouped into 4 categories: Data processing instructions ( 18 instructions ) Memory instructions ( 4 instructions ) Branch instructions ( 2 instructions ) Software interrupts ( 1 instruction )

Data processing instructions :

These basic data manipulation instructions can be found in all architectures. Notice that division operations are not included in the basic instruction set. MVN Move Not MUL Multiplication ORR Bitwise logical OR RSB Reverse Subtract RSC Reverse Subtract with Carry SBC Subtract with Carry SUB Subtract TEQ Test Equivalence TST Test and Mask ADC Add with Carry ADD Add AND Bitwise logical AND BIC Bit Clear CMN Compare Negated CMP Compare EOR Exclusive OR MLA Multiplication with accumulate MOV Move

Memory Instruction
As mentioned previously, ARM is a load and store architecture. As such, load (LDR) and store (STR) instruction are provided. Load byte (LDRB) and store byte (STRB) instruction are also provided. ARM also provides instructions to load (LDM) and store (STM) a large number of register. This is very useful when entering or exiting a subroutine. With STM and LDM, the programmer must define if the registers should be stored in an ascending or descending order. The programmer must also define if the memory address supplied can be used ( or it should take the next block).

Branch Instructions :
ARM provides a simple branch instruction. Since every instruction is conditional, there is no need for explicit conditional branching instructions. ARM also provides a branch with link instruction. This instruction branches and updates the link register with the return address. ARM provides no explicit return instruction.

Software Interrupts instructions (SWI) :

IS the only way an ARM processor can access resources controlled by the operating system.

Conditional Instructions :
All ARM instructions are conditional. The four most significant bits of the instruction word are used to indicate one of the following 16 conditions: HI (Higher) 1000 LS (Lower or Same) 1001 GE (Greater or Equal) 1010 LT (Less Than) 1011 GT (Greater Than) 1100 LE (Less than or Equal) 1101 AL (Always) 1110 NV (NeVer) 1111 EQ (EQual) 0000 NE (Not Equal) 0001 CS (Carry Set) 0010 CC (Carry Clear) 0011 MI (MInus) 0100 PL (PLus) 0101 VS (oVerflow Set) 0110 VC (oVerflow Clear) 0111

If no condition is appended to the opcode menmonic, the condition AL (always) is assumed. Appending the condition NV (never) to any instruction effectively turns it into a no operation instruction. The Stack The ARM architecture offers extensive support for memory stack by allowing programmers to chose one of four stack format/orientation. 1. Empty or Full: Empty: Stack Pointer points to the next free space on stack Full: Stack 2. Ascending or Descending:Pointer points to the last item on the stack Ascending: Grows from low memory to high memory Descending: Grows from high memory to low memory Instruction

Shift and Rotate Operations :

Shift and rotate operations are performed by the barrel shifter, and can be appended to any of the data processing operations in the previous section. They are applied to operand2 of the data processing instruction before execution of its function. 1. LSL: Logical shift left 2. LSR: Logical shift right 3. ASL: Arithmetic shift left 4. ASR: Arithmetic shift right 5. ROR: Rotate right 6. RRX: Rotate right with extend

Addressing Modes :
The ARM architecture has a large variety of addressing modes: 1. Register Indirect Addressing : Simplest way to address memory, storing the source/destination address in a register. Ex: ldr r0, r1 2. Pre-Indexed Addressing : Similar to register indirect addressing, the source/destination address stored in a register is offset by another value. Simple register : ldr r0, [r1, r2] Shifted register : ldr r0,[r1,r2,LSL#2] Immediate offset : ldr r0,[r1,#-4] Write back When working with pre-index addressing, it is sometimes practical to save the modified address ( like load and update on PowerPC ). ldr r0,[r1,r8,LSL#2]! 3. Post-Indexed Addressing : Post-Indexed Addressing is similar to Pre-Indexed Addressing with Write back. However, the address is modified and saved only after the load/store operation. 4. Program Counter Relative Addressing : The ARM architecture allows developers to address memory relative to the Program Counter (r15).

Features of ARM Architecture :

1. 2. 3. 4. 5. 6. RISC Architecture. 32 bit microprocessor. Reduced instruction set - only 25 basic instruction types. Most operations are executed over registers. All instructions can be conditional. Multiple addressing modes are provided (including modes that allow direct bit shifting) 7. Manual stack manipulation 8. Stack addressing must be explicitly programmed 9. Subroutines (including return) must be explicitly programmed 10. Big-endian and little-endian MEMORY 11. access to memory and data manipulation made in blocks of 32 bits. 12. Address range 26 bit wide Registers