Vlsi Mitra Definitions

Power Calculations
1. Number Of The Core Power Pad Required For Each Side Of Chip=(Total Core
Power)/{(Number Of Side)*(Core Voltage)*Maximum Allowable Current For A I/O Pad)}
2. Core Current(mA)=(CORE Power)/(Core Voltage )
3. Core P/G Ring Width=(Total Core Current)/{(N0.Of.Sides)*(Maximum Current Density Of The

Metal Layer Used For Pg Ring)}
4. Total Current =Total Power Consumption Of Chip(P)/Voltage(V)
5. No.Of Power Pads(Npads) = Itotal/Ip
6. No.Of Power Pins=Itotal/Ip
Where,
Itotal =TOTAL Current
Ip Obtained From Io Library Specification.
7. Total Power=Static Power+Dynamic Power

=Leakage Power+[Internal Power+Ext Switching Power]
=Leakage Power+[{Shortckt+Int Power}]+Ext Switching Power]
=Leakage Power+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]
Clock skews (timing skew)
Clock signal in synchronous circuits arrives at different components at different times.

Clock skew = clock insertion delay of FF1 - clock insertion delay of FF2
Reasons for the Skew:

Wire-interconnect length
Temperature variations
Variation in intermediate devices
Capacitive coupling
Material imperfections
Two Types of Clock Skew:

Negative skew
Positive skew
Positive skew:
Occurs when the clock reaches the receiving register later than it reaches the register sending data to
the receiving register.
Negative skew:
Is the opposite:- the receiving register gets the clock earlier than the sending register.
Local skew
Local skew is the difference in the arrival of clock signal at the clock pin of related flops.
Global skew
Global skew is the difference in the arrival of clock signal at the clock pin of non related flops. This
also defined as the difference between shortest clock path delay and longest clock path delay
reaching two sequential elements.
Physical design questions : Placement
1. How do you remove hot spots (more congestion?)

Ans: By spreading the cells, Macro placement refinements, pin placement
modifications
2. WHAT DO WE DO IF WE GET CONGESTION?

Ans: By spreading the cells, Macro placement refinements, pin placement
modifications
3. What is cell delay?

Ans: Propagation delay from input terminal to output of the cell
4. What is congestion?
Ans: Congestion occurs when there are more wires to be routed than the available
tracks
5. What are spare cells? In which stage u uses to place spare cells?
Ans: Dummy cells which are inserted in the netlist to accommodate future ECOs.
Whenever it is required to perform some functional ECO, spare cells would be used..
these are extra cells, floating in an ASIC .. and if you want to include some more
functionality, after chips is taped-out, you can use these cells to get avail of required
functionality.
6. What is aspect ratio of block? Can we change aspect ratio of block? If so in what
situation u change?
Ans: Aspect Ratio= height/width
Click for Detail
If congestion is happening because of less horizontal/vertical routing
resources,we try to change the aspect ratio.
We can change the aspect ratio of block if it not going affect the top level.
7. What cross talk noise? How to avoid?

Ans: A disturbance, caused by coupling capacitance. It may lead to functional failure
Fixes: Buffer the victim net, Upsize the victim net cell, Double space the net
and Shielding
8. What cross talk delay? How to avoid?

Ans: A delay, caused by coupling capacitance. It may lead to timing violations
Fixes: Buffer the victim net, Upsize the victim net cell, Double space the net
and Shielding
9. What is multi voltage technique? What are its advantages and disadvatages?
Ans: Use low vt cells on timing critical path and high vt cells on non-critical paths.
Advantages: Power consumption Reduction
Disadvantages: Increases fabrication complexity and lengthens design cycle time
and improper optimization may lead to increase in power.
10. What is temperature inversion?

Ans: As temperature decreases...delay increases
Because threshold voltage can increase with decreasing temperature, the
worst delay corner for circuit may be actually at low temperature corner rather than
high temperature
11. What is Net delay and Transition delay?

Ans: Net delay/wire delay: difference between the time a signal first applied to the
net and the time it reaches other devices connected to that. It is due to finite
resistance and capacitance of the net.
Net Delay = f(Rnet, Cnet + Cpin)
Transition delay/slew: Time taken by the signal to reach from 10% to the 90% of its
maximum value
18) How does u avoid congestion among standard cells? Can you use cell padding
in this situation?
Spreading cells, Remove power straps in the affected area
21) What is aspect ratio of block? Can we change aspect ratio of block? If so in what
Situation u change?
21. WHAT IS INSTANCE CLONING AND LOGIC RESTRUCTURING?
Cloning is the duplication of a cell which is having huge fan-out to avoid load violation. Logic
restructuring is to reduce the number of logic levels while maintaining the functionality
Congestion Removal Techniques:
1) If congestion is on/over macro:
1. Check whether the macros are blocking any high density IO pins. If so try to
move those macros from that IO pins area. Otherwise, leave enough routing
tracks/space for those IO pins and place soft placement blockage over there.
2. See if the macros belong to same hierarchy stacked or not. If they are placed
apart, then it may create congestion over the macros, which are sitting in
between them.
3. Orientation of macros must be same in order to minimize the net length if they
have communication between them.

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Power Calculations

2. Core Current(mA)=(CORE Power)/(Core Voltage )

3. Core P/G Ring Width=(Total Core Current)/{(N0.Of.Sides)*(Maximum Current Density Of The

4. Total Current =Total Power Consumption Of Chip(P)/Voltage(V)

5. No.Of Power Pads(Npads) = Itotal/Ip

6. No.Of Power Pins=Itotal/Ip

7. Total Power=Static Power+Dynamic Power

Clock skews (timing skew)

Clock signal in synchronous circuits arrives at different components at different times.

Reasons for the Skew:

Two Types of Clock Skew:

1. How do you remove hot spots (more congestion?)

2. WHAT DO WE DO IF WE GET CONGESTION?

3. What is cell delay?

7. What cross talk noise? How to avoid?

8. What cross talk delay? How to avoid?

10. What is temperature inversion?

11. What is Net delay and Transition delay?

Spreading cells, Remove power straps in the affected area

21. WHAT IS INSTANCE CLONING AND LOGIC RESTRUCTURING?

1) If congestion is on/over macro:

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