SHIVARAM PORIKA 9703114680

1. What we need to start Floor plan?

Ans: To start a floor plan first we need inputs like .v, .lib, .lef, .SDC

This is the first major step in getting your layout done. Your floor plan determines your chip quality. At this
step, you define the size of your chip/block, allocates power routing resources, place the hard macros, and reserve
space for standard cells

2.Tell about input files?

 Ans:NETLIST(.v) (logical connectivity)
 : It contains the logical connectivity information of all sequential and combinational circuits . It contains the Module
Information, Input & Output information of the design, wire information, Cell & Instance information, Port information,
Hierarchy information.
 Logic Libraries(.lib) : (timing, functionality, power)
It has time, power and functionality of a cell
Time- input delays, output delays, setup and hold
Power- leakage power and internal power
Cell functionality ## For eg:- (A+B)*(B+C)
PVT(process voltage and temperature) conditions
 PHYSICAL LIBRARIES (.lef library exchange format) : (physical info)
It contains physical information like height, width, number of input/output pins their location and their metal
layers used and their directions etc..
Technology Lef : It contains physical info of metal layers and vias.
Standard Cell Lef : It contains physical info of all standard cells.
Macro Cell Lef : It contains physical info of all Macros.
IO Cell Lef : It contains physical info of all Input Output cells
 SDC (Synopsys design constraint .sdc): (clock definitions)
It contains clock related information, timing exceptions information, External delays information.
Clock definition External delays DRV’S Timing path exceptions 
Create clock Input delays Max tran False path
Create virtual clock Output delays max cap Multi cycle path
Create generated clock max fanout Max delay
Create clock uncertainty max net length Min delay
 TLU+ FILE (RC TAB) : Cap table (RC values for every net)
It contains R, C parasitic information per unit length for each metal and it is used for calculation of net delay.
Design Exchange Format(.def) : Exact location information is provided. It contains the height, width, rows , tracks
etc.. Info of blocks.
 (.upf) : Cpf/upf (consists of power domain info) power related information.
(.spec) : max,min ID values , max,min skew values, name of metal layers used , cells used , NDRs .
MMMC [Multi – Mode Multi – Corner file] =It is used to generate different analysis views based on different delay
corners and constraints mode.
3. What are the guidelines to place macros?
Ans: 1.Place macros around chip periphery.
If you don’t have reasonable rationale to place the macro inside the core area, then place macros around
the chip periphery. Placing a macro inside the core can invite serious consequence during routing due to a
lot of detour routing, because macros are equal to a large obstacle for routing. Another advantage to
placing the hard macros around the core periphery is it's easier to supply power to them, and reduces the
change of IR drop problems to macros consuming high amounts of power.
2. Consider connections to fixed cells when placing macros.
When you decide macro position, you have to pay attention to connections to fixed elements such as I/O
and perplaced macros. Place macros near their associate fixed element. Check connections by displaying
flight lines inthe GUI.
3. Orient macros to minimize distance between pins. p.shivaram 9703114680
When you decide the orientation of macros, you also have to take account of pins positions and their connections.
4. Reserve enough room around macros.
For regular net routing and power grid, you have to reserve enough routing space around macros. In this
case estimating routing resources with precision is very important. Use the congestion map from
trialRoute to identify hot spots between macros and adjust their placement as needed.
5. Reduce open fields as much as possible.
Except for reserved routing resources, remove dead space to increase the area for random logic. Choosing
different aspect ratio (if that option is available) can eliminate open fields.
6. Reserve space for power grid.
The number of power routes required can change based on power consumption. You have to estimate
the power consumption and reserve enough room for the power grid. If you underestimate the space
required for power routing, you can encounter routing problems.

4. Whathappens if pins assign to left or right.(if you have IO pins at top and bottom) ?
Ans: Actually top level chip will be divided into some blocks, IO pins will be placed
according to the communication between surrounding blocks.
If we assign pins to left and right rather than top and bottom we will face routing issues in further stages.
5. How we will assign spacing between two macros?
Ans: channel spacing= 2*no of pins*pitch/ total number of metal layers
6. In placement what are the congestion types, how to resolve congestion?
Ans: we will see congestion where available tracks are less than required tracks.
We may see congestion because of
 Cell density
 Pin density
 Bad floorplan
There are two types of congestion
1. horizontal congestion and
2. vertical congestion
we will see horizontal congestion when horizontal tracks are less and similarly for vertical congestion if
vertical tracks are less
prevention techniques:
 we can avoid congestion by placing blockages.
 Cell padding
 Scan chain reordering.

7. What happens if cell density and pin density is more, how to resolve it?
Ans: if cell density and pin density is more we will see congestion and routing issues.
By placing partial blockage we can avoid cell density and by cell padding we can avoid pin density.
8. what happens if cells place closer to macros?
Ans: if cells are placed close to macros we will see routing issues near macros, to avoid
this we are placing Halo around the macro.
9. explain about power planning?
Ans: Power Planning is one of the most important stage in Physical design. Power network is being
synthesized, It is used provide power to macros and standard cells within the given IR-Drop limit. Steady
state IR Drop is caused by the resistance of the metal wires comprising the power distribution network.
By reducing the voltage difference between local power and ground, steady-state IR Drop reduces both
the speed and noise immunity of the local cells and macros.
Power planning management can be divided in two major category first one is core cell power
management and second one I/O cell power management. In core cell power planning power rings are
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 formed around the core and macro.In IO cell power planning power rings are formed for I/O cells and
trunks are created between core power ring and power pads.
In addition trunks are also created for macros as per the power requirement.
power planning is part of floor plan stage. In power plan, offset value for rings around the core and
vertical and horizontal straps is being define
I/O cell library contains I/O cell and VDD/VSS pad cell libraries. It also contain IP libraries for reusable
IP like RAM, ROM and other pre designed, standard, complex blocks.
10. What happens if IO pins placed at core boundary?
Ans: nothing happen, we can place IO pins in core boundary
11. what are the timing issues after placement?
Ans: DRV’s and setup.
12. what is path timing and data path?
Ans: Timing Path
Timing path is defined as the path between start point and end point where start point and end
point is defined as follows:

Start Point: All input ports or clock pins of a sequential element are considered as valid start point.

End Point: All output port or D pin of sequential element is considered as End point
For STA design is split into different timing path and each timing path delay is calculated based
on gate delays and net delays. In timing path data gets launched and traverses through combinational
elements and stops when it encounter a sequential element. In any timing path, in general (there are
exceptions); delay requirements should be satisfied within a clock cycle.
In a timing path wherein start point is sequential element and end point is sequential element, if
these two sequential elements are triggered by two different clocks(i.e. asynchronous) then a common
least common multiple (LCM) of these two different clock periods should be considered to find the
launch edge and capture edge for setup and hold timing analysis.
Different Timing Paths: Any synchronous design is split into various timing paths and each timing path is verified
for its timing requirements. In general four types of timing paths can be identified in a synchronous design. Theyare:
Input to Register
Input to Output
Register to Register
Register to Output
Data path: The path wherein data traverses is known as data path. Data path is a pure combinational path. It can haveany
basic combinational gates or group of gates.

13. Explain about PD flow?

Ans: INPUTS:
 NETLIST(.v) : It contains the logical connectivity information of all sequential and combinational
circuits . It contains the Module Information, Input & Output information of the design, wire information,
Cell & Instance information, Port information, Hierarchy information.
 Logic Libraries(.lib) :
It has time, power and functionality of a cell
Time- input delays, output delays, setup and hold
Power- leakage power and internal power
Cell functionality ## For eg:- (A+B)*(B+C)
PVT(process voltage and temperature) conditions
 PHYSICAL LIBRARIES (.lef library exchange format) : It contains physical information like
height, width, number of input/output pins their location and their metal layers used and their
directions etc..
Technology Lef : It contains physical info of metal layers and vias.
Standard Cell Lef : It contains physical info of all standard cells.
Macro Cell Lef : It contains physical info of all Macros.
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 IO Cell Lef : It contains physical info of all Input Output cells
 SDC (Synopsys design constraint .sdc): It contains clock related information, timing
exceptions information, External delays information.
Clock definition External delays DRV’S Timing path exceptions 
Create clock Input delays Max tran False path
Create virtual clock Output delays max cap Multi cycle path
Create generated clock max fanout Max delay
Create clock uncertainty max net length Min delay

 TLU+ FILE (RC TAB) : It contains R, C parasitic information per unit length for each metal and
it is used for calculation of net delay.
 Design Exchange Format(.def) : Exact location information is provided. It contains the height,
width, rows , tracks etc.. Info of blocks.
 (.upf) : power related information.
 (.spec) : max,min ID values , max,min skew values, name of metal layers used , cells used , NDRs
 MMMC [Multi – Mode Multi – Corner file] =It is used to generate different analysis views based
on different delay corners and constraints mode.
Constraint checks:
 All flops are clocked are not
 no unconstrained paths
 IO delays
SANITY CHECKS:
Check_ library: missing cell information, missing pin information, duplicates cells.
Check_design: Floating inputs, Tristate buffers, multiple drivers Nets, Combinational loops, Empty modules &
Assign statements.
Check_timing: All flops are clocked or not , should not be unconstrained paths, input and output no clock relative delay.
checkUnique : checks the uniqueness of netlist. ## if Netlist is unique returns 1 otherwise returns 0
Check_legality: reports overlap and cells placement related violation like orientation , overlaps etc
report_constraints: It checks (WNS) and (TNS) DRV’s like worst negative slack, total negative slack
report_Design : reports the max and/or min operating conditions and active design rules for the design
report_qor:-Displays complete QOR information. Timing numbers should be acceptable value.
report_design_mismatch –verbose :-Command that helps identify discrepancies between your design and a reference source.
By providing a detailed report.
check_design – checks pre_placement_stage #atomic checks #design mismatch, scan chain, mv design & timing.
FLOORPLAN:
1. Utilization factor decides the size of the block.
2. Aspect ratio gives shape of the block.
3. After utilization and aspect ratio we go for pin placement. In pin placement we have to place pins legally
4. Macros should be placed according to guidelines
a. Place macros around chip periphery.
If you don’t have reasonable rationale to place the macro inside the core area, then place macros around the chip periphery.
Placing a macro inside the core can invite serious consequence during routing due to a lot of detour routing, because macros are
equal to a large obstacle for routing. Another advantage to placing the hard macros around the core periphery is it's easier to
supply power to them, and reduces the change of IR drop problems to macros consuming high amounts of power.
b. Consider connections to fixed cells when placing macros.
When you decide macro position, you have to pay attention to connections to fixed elements such as I/O and perplaced macros.
Place macros near their associate fixed element. Check connections by displaying flight lines in the GUI.
c. Orient macros to minimize distance between pins.
When you decide the orientation of macros, you also have to take account of pins positions and their connections.
d. Reserve enough room around macros.
For regular net routing and power grid, you have to reserve enough routing space around macros. In this case estimating
routing resources with precision is very important. Use the congestion map from trialRoute to identify hot spots between
macros and adjust their placement as needed.
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 e. Reduce open fields as much as possible.
Except for reserved routing resources, remove dead space to increase the area for random logic. Choosing different aspect ratio
(if that option is available) can eliminate open fields.
f. Reserve space for power grid.
The number of power routes required can change based on power consumption. You have to estimate the power consumption
and reserve enough room for the power grid. If you underestimate the space required for power routing, you can encounter
routing problems
5 .After macro placement we will place physical cells like endcap and welltapcells
POWER PLANNING:
Power planning is to supply power to the standard cells and macros.
Power pads
↓
Power rings
↓
Power stripes→ Macros
↓
Follow pins
↓
Standard cells
PLACEMENT:Two stages- 1. Course placement 2. Detail placement
1. Course placement:
a. First tool will place standard cells based on hierarchy
b. It will do High fanout net synthesis :
Adding buffers to the high fanouts
c. Scan chain reordering
In a less complex design, you don’t usually do scan reordering. However,
sometimes it may become difficult to pass scan timing constraints once the
placement is done. The scan flip flop placements may create lengthier routes
if the consecutive flops in scan chain are placed far apart due to a functional
requirement. In this case, the PnR tool can reconnect the scan chains, to make
routing easier. A prerequisite for thisoption is a scan DEF for the tool to
recognize the chains.
d. Logical optimization:
Sizing , VT Swapping ,Buffering , Logic restructuring ,
Pin swapping , Cloning , Rebuff ring & Trail route

2. Detail placement
a. Area recovery
b. Congestion driven
c. Time driven
PLACEMENT OPTIMIZATION:
In optimization tool will optimize DRV’s and setup timing
Here we will not see hold because clock is ideal.
Checks in placement: Cells legalizationUtilization ,Area ,Timing & Congestion

CLOCK TREE SYNTHESIS:

Before CTS we need to check:
1. All cells should be legalized.
2. All power nets are prerouted.
3. All pins should legalized.
4. Congestion, timing should control.
GOALS OF CTS:
1. To minimize the logical DRCs.
2. Balancing the skew.
3. Minimum Insertion Delay.
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 INPUTS OF CTS:
1. SDC
2. SPEC FILE
3. PLACEMENT DATABASE
what is CTS? : To distribute a clock from Clock port to Clock pin
WHY CTS? : To minimize skew and insertion delay to build the clock tree.
createClockTreeSpec -file leon_cts.spec ## creates clock specification file, mostly given by full chip engineer
Here we are generating SPEC file using clockbuffers and clock inverters.
SPEC file consists of
1. Buffers list
2. Max skew
3. Min and Max Insertion delay
4. Max trans, Cap, Fanout
5. Inverters list
6. Clock tree leaf pin, exclude pin, stop pin
7. Clock name &Clock period

COMMANDS USED IN CTS:

clockdesign
optDesign -postCTS
clockDesign -specFile leon_cts.spec ## CTS is done
reportClockTree -postCTS ## checks ID & skew values
[ max : skew -186.8ps (required - 160ps) ; min : skew - 66.5ps (required – 320ps) ]
checkPlace ## [ placed – 41227, Unplaced – 0, placement Desnsity – 66.40% ]
timeDesign -postCTS # checks setup timing before optimization ( 42 paths are violated )
timeDesign -postCTS -hold ## checks Hold timing before optimization ( 4 paths are violated )
describeCongestion ## gives congestion related information
reportCongestion –overflow ##in detail congestion reports are given
report_power ## checking power
report_area ## checking Area

CHECKS IN CTS:
1. Timing numbers
2. Utilization numbers
3. Congestion
4. All cells should legalize
ROUTING:
INPUTS:
 CTSdatabase (.v, .lib, .sdc, )
 Physical libraries
 Technology LEF file / rule deck file
 Captables

GOAL: We need to interconnect all the nets without leaving shots and Spacing violations.
STEPS INVOLVED IN ROUTING:

1. Global Routing
2. Track Assignment
3. Detailed Routing
GLOBALROUTING: Router breaks the routing portion of the design into rectangles called Gcells and assigns signalnets to
Gcells. The global router attempts to find shortest path through gcells but does not make actual connection or assign nets to
specific nets and to specific track within Gcell.
TRACKASSIGNMENT:In this step the nets are properly assigned on tracks. p.shivaram 9703114680
DETAILED ROUTING: Nanoroute follows global routing plan and lays down actual wires that connect pins to their
corresponding nets.It creates shorts and opens or spacing violations rather than leaving unconnected nets.
We can route detailed routing on entire design, a specified area of design on selected nets.
Router runs SEARCH AND REPAIR ROUTING during detail routing.It locates shorts and opens and spacing violations so, it
reroutes the affected area to eliminate violations.
CHECKS:
1 .Verify connectivity
2. Verify geometry
3. timing numbers
4. utilization numbers
5. All cells should legalize
6. Congestion
Commands:
RouteDesign
optDesign –postRoute
routeDesign ## routing process is done
verifyGeometry ## checking shorts ( 992 violations )
verifyConnectivity ## checking opens (160 violations )
timeDesign -postRoute ## setup analysis ( 20 paths are violated)
 setAnalysisMode –analysisType onChipVariation
timeDesign -postRoute -hold ## hold analysis ( 11176 paths are violated)
checkPlace ## (placed 41258, placement Density – 66.43%, glitch violations - 0)
describeCongestion ## gives congestion related information
reportCongestion –overflow ##in detail congestion reports are given
report_power ## checking power
report_area ## checking Area

14. how will you place macros according to hierarchy?

Ans: According to hierarchy communicating macros will be in same color, based on that we can place
macros .

15. if we do macro abutment, what happens?

Ans: There are two cases
1. If two macros communicating only with each other we can abutment the macros
2. If the macros communicating with other cells(std cells and IO ports) then we must should
provide a proper channel spacing between the macros or else we can see the routing issue

16. Can we place macros 90 and 270dergees orientation?

Ans: It depends on which technology you are working on. 45nm & below there are orientation
requirements by foundry. Poly orientation should be same throughout the chip. So Macro poly orientation
should match with the poly orientation of the standard cells.

17. In power planning for rings and stripes which metal layers used and why?
Ans: For rings and stripes we use top metal layers because for top metal layers we have low resistivity.
18. Can we place cells between the space of IO and core boundary?
Ans: No, we cannot place cells between the space of IO and core boundary because in between IO and
core boundary power rings will be placed and we may see routing issues.

19. How did you placed standard cells with command and tool?
Ans: command: placeDesign
Tool: place →place standard cells
20. what type of congestion you seen after placement?
Ans: 1. Congestion near Macro corners due to insufficient placement blockage.
2. Standard cell placement in narrow channels led to congestion.
3. Macros of same partition which are placed far apart can cause timing violation.
4. Macro placement or macro channels is not proper. p.shivaram 9703114680
 5. Placement blockages not given
6. No Macro to Macro channel space given.
7. High cell density
8. High local utilization
9. High number of complex cells like AOI/OAI cells which has more pin count is placedtogether.
10. Placement of std cells near macros
11. Logic optimization is not properly done.
12. Pin density is more on edge of block
13. Buffers added too many while optimization
14. IO ports are crisscrossed; it needs to be properly aligned in order.
21. what are the physical cells?
Ans: End Cap cells:
1. These cells prevent the cell damage during fabrication.
2. Used for row connectivity and specifying row ending.
3. To avoid drain and source short.
4. These are used to address boundary N-Well issues for DRC cleanup.
Well Tap cells:
1. These are used to connect VDD and GND to substrate and N-Well respectively because it
results in lesser drift to prevent latch-up.
2. If we keep well taps according to the specified distances, N-Well potential leads to proper
electrical functioning.
3. To limit the resistance between power and ground connections to wells of the substrate.
De-cap Cells: They are temporary capacitors which are added in the design between power and ground rails
to counter the functional failure due to dynamic IR drop.
1. To avoid the flop which is far from the power source going into metastable state.
Spare cells: Spare cells will be used to implement ECO after BaseTape Out & Before Metal-Tape
Out. If any bugs are reported/found after the tape-out, we can use these spare cells to fix the bugs.
The key to having spare cells in your design is that you only need to change the metal layers to
rewire the logic and fix any bugs. This means you only need to pay for new metal masks, thus
saving money. The Spare Cell Input pins must be tied to VSS and output pins left floating. Spare
cells are nothing but standard cells and are placed randomly across the chip for later use.
IO buffers: Signal strengthening/slew rate improvement
Tie cells: Tie cells are used to protect the std cells from power and ground bounces &
Tie high cell connect gate to VDD , Tie low cell connect the gate to VSS .
Filler Cells:To fill the empty space and provide connectivity of N-wells and implant layers.
22. Tell about Non Default Rules?
Ans: Double width and double space.
After PNR stage if u will get timing /crosstalk/noise violations which are difficult to fix at ECO
stage we can try this NDR option at routing stage.
USAGE OF NDRs and Example:

When we are routing special nets like clock we would like to provide more width and
more spacing for them. Instead of default of 1unit spacing and 1unit width specified in tech
file;But NDR having double spacing and double width .When clocknet is routed using NDR it has
better Signal integrity, lesser crosstalk,lessernoise,but we cannot increase the spacing and width
because it effects the area of the chip.

Double spacing: It is used to avoid the crosstalk.

Double width: It is used to avoid the EM.

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23. What is setup and hold?
Ans: SETUP: Minimum time required for data stability before the clock edge.

HOLD: Minimum time required for data stability after the clock edge.
24. Can we do setup check at placement?
Ans: Yes, we will check setup in placement stage, where as we won’t bother about hold because clock is
ideal in placement stage.

25. what is trail route and global route?

Ans: Trail route: Trial Route performs quick global and detailed routing for estimating routing-related
congestionand capacitance values. It also incorporates any changes made during placement, such as scan reorder.
You can use Trial Route results to estimate and view routing congestion, and to estimate parasitic valuesfor
optimization and timing analysis. When used during prototyping, Trial Route creates actual wires, so you can get a
good representation of RC and coupling for timing optimization at an early stage in the flow. Trial Route also
produces a congestion map you can view to get early feedback on whether the design is routable. Trial Route results
can also be used for pin assignment when you commit partitions.
Detaile route: Detailed routing is where we specify the exact location of the wires/interconnects in the channels
specified by the global routing. Metal Layer information of the interconnects are also specified here.
26. What is the cell height?
Ans: It is the height between two rows.
27. what is max tran range?
Ans: It is the range given in SDC file, if transition delay crosses that range we will see tran violations.

28. which technology is yours?

Ans: 6&7nm.
29. What is macro count, standard cell count and how many clocks in your design?
Ans: 4 macros, 36k standard cells and 3 clocks.
30. Explain about isolation cells?
Ans: Isolation cells are used to isolate the output signals of a powered down domain. Output signals of a
powered down domain has an intermediate voltage levels because of power gating effect. When such intermediate
Voltage signals are feed as input to powered up domain, it could result in crowbar currents which affects the proper
functioning of the powered up domain. Isolation cells help to drive a valid logic value either zero or one.

31. What is functional design and logical design?

Ans: Any chip designing can be subdivided in 2 steps
1. Front end or logic design- Based on specification provided, functionalities are created at RTL
level abstraction to meet all the requirements. Generally Uses Gated logic. It is basically coding
of digital design.

2. Back end or Physical design- After logic design and front end verification, in order to tape-
out, the RTL abstraction is converted in form of transistors. They need to be optimised for low
area, power and quality. This is physical or say analog design.

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32. Setup calculation?

33. what are the inputs of all stages in PD flow?

Ans: Floorplan: .v and .lef
Placement: floorplan data base, lib.
CTS: placement database, SDC and spec.
Routing: CTS database, captables.
34. What are universal gates and why they are called as universal gates?
Ans: NOR gate and NAND gates have the particular property that any one of them can createany
logical Boolean expression if designed in a proper way.
35. ASIC flow
Ans:

36. What is LVS?

Ans: Layout verses schematic
Inputs: .LVS.V, GDS II and rule deck file.
 Source netlist(physical) and reference netlist(logical) are converted in spice netlist
 LAYOUT: it takes source netlist into spice netlist
 SCHEMATIC: It takes reference netlist into spice netlilst.
 LVS means comparison of layout and schematic spice netlist
 Spice netlist will count transistors and connectivity
 If layout and schematic netlist are equal we can proceed atherwise it will give below
violations
o Shorts
o Opens
o Floating nets
o Pin mismatches
o Component mismatch
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37. Write setup and hold equations?
Ans: setup= require time – arrival time

Where require time= clock period+capture clock path latency – library setup – setup uncertainty
Arrival time= launch clock path latency + clock to Q delay + comb delay
Hold = arrival time – required time
Where require time= capture clock path latency+library hold +hold uncertainty
Arrival time = launch clock path latency + clock to Q delay + comb delay
38. How many master and generated clocks in your design?
Ans: 2master clocks and 1 generated clock

39. whar are sequential and combinational circuits?

Combinational Logic Circuits Sequential Logic Circuits

Output is a function of clock, present inputs and

Output is a function of the present inputs(Time
the previous states of thesystem.
Independent Logic).

Have memory to store the present states that is sent as

Do not have the ability to store data (state).
control input (enable) for the next operation.

It does not require any feedback. It simply outputs the It involves feedback from output to input that is stored
input according to the logic designed. in the memory for the next operation.

Used mainly for Arithmetic and Boolean operations. Used for storing data (and hence used in RAM).

Logic gates are the elementary building blocks. Flip flops (binary storage device) are the elementary
building unit.

Independent of clock and hence does not require Clocked (Triggered for operation with electronic
triggering to operate. pulses).

Example: Counter [Previous O/P

Example: Adder [1+0=1; Dependency only on present
+1=Current O/P; Dependency on present input as well
inputs i.e., 1 and 0].
as previous state].

40. Why we should not place macros in middle?

Ans: we will see more RC net delays and congestion.

41. Why top layers for power, below layers for std. cells and middle layers for clock?
Ans: Top metals layers: The resistivity of top metal layers are less and hence less IR drop is seen in
power distribution network. If power stripes are routed in lower metal layers this will use good amount of
lower routing resources and therefore it can create routing congestion.

Middle metal layers: Middle routing layers such as 4,5 and 6 tend to have the same characteristics so the
clock can be more predictable on those layers .Also ,fewer vias are required to connect to the metal to
clock pin on the flop. It also require to metal layers but they are already reserved for power and GND.

Lower metal layers: Std cell require less power it will be available in lower metal layers. And some std
cell are made up of lower metal layers. So no need to connect vias between std cell pins and metal layers.

42. What are the targets of placement?

Ans: 1.Utilization
2. Timing
3. Congestion
4. Area

43. Is SDC mandatory in floorplan?

Ans: no, because SDC contains clock definitions, delays, DRV’s and exceptional paths so in floorplan we
don’t need all these information.
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44. What information you see in SFEC and SPEF files?
Ans: SPEC contains:

• Clock name
• Clock period
• Max and min delay
• Max skew
• Sink max tran
• Buffer max tran
• Clock buffers and clock inverters information
• Exclude pin
• Through pin
• Information about Metal layers used
• Leaf route type

SPEF contains: RC values

45. What is the difference between normal buff & inverter and clock buff & clock inverter?
Ans: compare to normal buffers & inverters clock buffers & inverters have equal rise and fall time.

46. What are the outputs of powerplan?

Ans: power rings, power stripes, follow pins

47. What is formal verification?

Ans:

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48. How did you open the prime time
pt_shell

49. what will you ask pd team in order to do STA

SPEF
DEF

50. If PD team has generated 10 spefs after routing, which spef will you ask for?
Worst RC corner spef
51. What are all the commands used in P&R flow
A.
Inputs:
 set_init_verilog
 set_init_leffile
 set_init_mmmc
 set_init_pwrnet
 set_init_gndnet
 init_design

Sanity Checks:
 checkNetlist
 checkDesign -physicalLibrary
 checkDesign –timingLibrary
Floor Planning:
 checkPinAssignment
 addEndCap –preCap FILL8 –postCap FILL8
 addWellTap –cell FILL8 –cellInterval 40
 checkDesign –floorplan
Power Planning:
 globalNetConnect
 addRing
 addStripe
 sRoute
Placement:
 placeDesign
 setPlaceMode
 optDesign –preCTS
 report_timing
CTS:
 createClockTreeSpec
 clockDesign
 optDesign –postCTS –hold

52. How do you know you have max cap violation

 report_timing –all_violators

53. What is static power

 Analyzing the power and IR drop consumed in design when there is a constant current flow
p.shivaram 9703114680
because of instances consuming average current in the design is callstatic power
54. What is dynamic power
 Analyzing the power consumed and IR drop in design when the instances draws atransient
current flow due to the instances switching

55. What is clock gating

 Clock gating is a popular technique used in many synchronous circuits for reducing dynamic
power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock
tree. Pruning the clock disables portions of the circuitry so that the flip-flops in them do not have
to switch states. Switching states consumes power. When not being switched, the switching
power consumption goes to zero, and only leakage currents are incurred.

56. What do you mean by aggressor net

 Aggressor net creates impact to the neighboring nets
57. What is cross talk noise and cross delay
 Cross talk noise: When w2 is having a constant signal, and when w1 signal is having a
transition, it produces a spike at the w2 signal. This glitch is called crosstalk noise. This is also
referred to as bump violation. This glitch if wide and large enough, can get propagated through
the logic, and can create a logical failure. The bump violations in clock network should be
totally under control. Refer to the below figure for cross talk noise.

Cross talk delay: When w2 signal is having a transition, this transition time can be
affected by the signal transition at w1. If the transition at w1 is in the same direction as
w2 signal transition, it will make w2 signal transition slower. ie,. the net delays of the
victim net will change with respect to the signal transition in the aggressor net, this
should be taken care in the timing analysis for proper timing closure. But keep in mind,
that the victim net will get affected, only if the transitions in both the nets happen in the
p.shivaram 9703114680
 same timing window. Also the delay change in the victim depends on the type of
transition (rise or fall) in the aggressor net. See the below figures for more understanding.

58. What is signal integrity

 Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital
electronics, a stream of binary values is represented by a voltage (orcurrent) waveform
59. How can you fix max cap violations
Upsizing & Adding the buffer
60. What is synthesis and what are the inputs to synthesis
 Synthesis is the process of transforming your HDL design into a gate-level netlist,given all the
specified constraints and optimization settings.
Inputs:
Lib
RTL
Sdc

61. What is STA

 STA is a method of validating the timing performance of a design by checking allpossible paths
for timing violations under worst case conditions.

62. Create a clock with 10ps period and rise edge 4ps and fall edge 8ps
 create_clock [get_ports{clk}] –name pclk –period 10 –waveform{4 8}

63. what are mandatory things for generate clock

o Source master pin
o Divided by /multiple by factor

64. Write a command for generating clock

 Create_generated_clock –name clk –source PLL –divided_by 2 [get_pins uff0/q]

p.shivaram 9703114680
65. What type of library did you use in your design
 Fast Lib & Slow Lib
66. What are asynchronous circuits
 The circuit in which the change in the input signals can affect memory
elements at any instants of the time is call asynchronous circuit
 In this circuit, clock is absent and hence the state changes can occur
according to delay time of the logic.

67. Why do you need the virtual clock

 To address the IO delays

68. What is recovery and removal

Recovery: The recovery time is the minimum time that an asynchronous input is
stableafter being de-asserted before next active clock edge.
Removal: The removal time is the minimum time after an active clock edge that
theasynchronous pin must remain active before it can be de-asserted
69. What does report_constraints –all_violators contain
 It show all the violations
 Max_transition
 Max_fanout
 Max_capacitance
 Setup
 Hold

70. In sanity checks if we have floating inputs, can we move forward?

 No, we don’t move forward because the floating inputs can take any input
value from the neighboring switching nets. Then the undesired output
will appear. so,we don’t move forward if there is any floating input.

71. While giving the inputs to the floorplan, which LEF(tech lef
or cell lef) wehave to give first?
 First, we give the tech lef. Whenever the tech lef is loaded after all other
inputs areloaded

72. Is .lib is mandatory inut for floorplan, and what information

you take fromlib?
 No , .lib is not mandatory for floorplan
73. What are the floorplan inputs
 Lef and .v

74. Guidelines of floorplan

A.
 IO ports must be placed.
 communication between macros and io ports
 macro to macro communication should be checked
 macros should be placed around the core boundary only
 macro pins should be towards the core area only
 crisscrossing should not be there between macros
 proper channel spacing should be given between the macro
 spacing between macros should be covered with the macros
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 75. what is overshoot glitch and undershoot glitch
 There is still a glitch which takes the victim net voltage above its steady
high value. Such a glitch is called an overshoot glitch. Similarly, a falling
aggressor when coupled to a steady low victim net causes an undershoot
glitch on the victim net.
76. What are the mandatory things for creating clocks
 Period & Source
77. Why do you required setup checks and hold checks
A.
 To meet the timing
 Proper functionality of the device
78. If I increases power supply, what happen to cell delay
 The cell delay will decrease

79. If I increase my metal width, what happens to it’s height

 The height remains same
80. Why we are using different metal width for different layers
 For supply the different currents inside the design. Top metal layers
have highcurrent flow and low metal layers have low current flow

81. What happens if in my design have a same metal width for all 9 layers
If the width is high the current flow is high. Due to high current flow standardcells will damage.
If the width is low then we see more IR drop
82. How cell delay depends on channel length
 If the channel length is more than the cell delay is more and vice versa

84.What is multicycle path and false path?

A.The combinational data path between two flip-flops can take more than one clock
cycle to propagate through the logic. In such cases, the combinational path is
declared as a multicycle path.

Some certain timing paths are not real (or not possible) in the actual functional operation
of the design. Such paths can be turned off during STA by setting these as false paths. A
false path is ignored by the STA for analysis.
85.At the placement stage what are all the different types of congestion you see? And
how you overcome that congestion in your design? Or Explain different techniques to
overcome the congestion?
A1. Using hard blockages in case of congestion due to notches.
2. Using partial blockage, in case of high cell density.
3. Using cell padding, in case of congestion due to pin density.
86.At placement stage, if we have the utilization of 95%, can we move forward and why?
A . No, we should not proceed with that utilization. We have to check the reason for the jump
in the utilization number.
87.What are the timing checks we do after placement?
A. DRVs and setup checks
88.If the design had violated by 500ps of setup then will you move forward and why?
A. No, we have to fix the setup violation. If we proceed at this stage by the next stage the setup
will be violated more there may not be chance to fix.
p.shivaram 9703114680
 89.What is the skew?
a. Skew is the difference in timing between two or more signals, maybe data, clock or both.
Clock skew is the difference in arrival times at the end points of the clock tree. Clock latency
is the total time it takes from the clock source to an end point.
Skew is the difference between capture flop latency and launch flop latency.
90.Explain setup and hold with equation.
b. Setup: The minimum time before the active clock when the data input must remain
stable is called the setup time.
Setup time = Required Time - Arrival Time
Required time = Clock period + capture clock latency – lib setup – setup uncertainity
Arrival time = launch clock latency + C to Q delay + combo delay
Hold: The minimum time the data input must remain stable just after the active edge of the
clock.
Hold time = Arrival Time – Required Time
Required time = Capture clock latency + lib hold time
Arrival time = launch clock latency + C to Q delay + combo delay

91.If launch clock is 20ns and capture clock is 10ns then where do we check the setup
and hold? and vice versa?
A.

92.What is the resistor, capacitor and current formulae?

c. Capacitance, C = ∈ 𝐴/𝑑,
Where, ∈ is the permittivity, A is area and d is distance.
Resistance, R = ρl/A,
Where, ρ is resistivity, l is length and A is area.
Current, I = V/R,
Where, V is voltage and R is resistance.

93.What is antenna violation? On what basis antenna violation will affect the cell.
It is also called “Plasma induced gate effect damage”. It will occur at manufacturing
stage. It is a gate damage that can occur due to charge accumulation on metals and
discharge to a gate through gate oxide. These are normally expressed as an
allowable ratio of metal area to gate area greater than allowable area.

p.shivaram 9703114680
 94.What is cloning?
A.

95.On what tool and technology, you have worked? Have you ever seen PT and calibre tools?
ICC2 and 6&7nm ------yes

96.What happens if we have setup and hold violations in our design?

setup and hold timings are to be met in order to ensure that data launched from one
flop is captured properly at another and in accordance to the state machine designed.
In other words, no timing violations means that the data launched by one flip-flop at
one clock edge is getting captured by another flip-flop at the desired clock edge. If the
setup check is violated, data will not be captured properly at the next clock edge.
Similarly, if hold check is violated, data intended to get captured at the next edge will
get captured at the same edge. Moreover, setup/hold violations can lead to data getting
captured within the setup/hold window which can lead to metastability of the
capturing flip-flop. So, it is very important to have setup and hold requirements met
for all the registers in the design and there should not be any setup/hold violations.

97.What will you do if your design has setup violation and how will you meet setup in
such cases where there are no margins available?
We can meet the setup violations by adding buffers and downsizing the buffers present in
the clock path.

98.What is time borrowing?

The time borrowing technique, which is also called cycle stealing, occurs at a latch. In
a latch, one edge of the clock makes the latch transparent, that is, it opens the latch so
that output of the latch is the same as the data input; this clock edge is called the
opening edge. The second edge of the clock closes the latch, that is, any change on the
data input is no longer available at the output of the latch; this clock edge is called the
closing edge.
99.What are the concepts involved in STA?
modeling of cells, propagation delay, slew of waveform, skew between signals,
Timing arcs, Timing paths, Clock domains,Operating conditions.

100.What is signal integrity?

The ability of the signal to with stand the interference from the nearby signal.

101.What is aggressor net? Why it’s called aggressor net?

The net in which high switching activity is performed is aggressor. It is the
affecting net so that it is called as aggressor net.

102.Both nets are having same drive strength, but voltage is different, capacitance is
occurred or not?
yes, the capacitance occurs due to different voltage levels.

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 103.Both nets are having same voltage, capacitance is occurred or not?
No, the capacitance does not occur because the voltage levels are same.
104.What is cross coupling capacitance? Why it occurs?
The capacitance formed between two different nets in which one of the net is having
high switching activity and other net is containing low level signal. The capacitance is
formed because of different voltage levels in the nets and different switching.

105.What is cross talk? Explain in detail.

A. The interference of the high switching signal on the low level signal due to the
formation of coupling capacitor between the nets. The net in which high switching
activity is there and affecting the idle net is called aggressor net. The net which is having
low switching activity and affected by aggressor is called victim net.
When aggressor net is switching and victim net is idle, we
may get cross talk noise. When aggressor net and victim net
both are switching, we may get cross talk delay.
106.How to avoid crosstalk?
B. Applying NDRs, downsizing aggressor, upsizing victim, shielding victim net.

107.What is data path?

A. The path between Q pin of the launch flop and D pin of the capture flop is called data
path.
108.What is OCV?
The process and environmental conditions may not be uniform across the different
portions of the chip. Due to process variations, identical transistors may not have similar
characteristics in different portions of the chip.
109.What is process?
Process variation is the naturally occurring variation in the attributes of transistors (length,
widths, oxide thickness)
when integrated circuits are fabricated. The amount of process variation becomes
particularly pronounced at smaller process nodes (<65 nm) as the variation becomes a
larger percentage of the full length or width of the device and as feature sizes approach
the fundamental dimensions such as the size of atoms and the wavelength of usable light
for patterning lithography masks.
110.Explain the corners.
Parasitics can be extracted at many corners. These are mostly governed by the
variations in the metal width and metal etch in the manufacturing process. Some of
these are:
• Typical: This refers to the nominal values for interconnect resistance and capacitance.
• Max C: This refers to the interconnect corner which results in maximum capacitance.
The interconnect resistance is smaller than at typical corner. This corner results in
largest delay for paths with short nets and can be used for max path analysis.
• Min C: This refers to the interconnect corner which results in minimum capacitance.
The interconnect resistance is larger than at typical corner. This corner results in
smallest delay for paths with short nets and can be used for min path analysis.
• Max RC: This refers to the interconnect corner which maximizes the interconnect RC
product. This typically corresponds to larger etch which reduces the trace width. This
results in largest resistance but corresponds to smaller than typical capacitance. Overall,
this corner has the largest delay for paths with long interconnects and can be used for
max path analysis.
• Min RC: This refers to the interconnect corner which minimizes the interconnect
RC product. This typically corresponds to smaller etch which increases the trace
width. This results in smallest resistance but corresponds to larger than typical
capacitance. Overall, this corner has the smallest path delay for paths with long
interconnects and can be used for min path analysis.
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111.Tell me about STA?
Ans: It is a method of validating the timing performance of the design by checking all
possible paths for timing violations under worstcase conditions.
Read lib
Read netlist :(Link the design and check any unresolved references and black box)
Read SDC :(check_timing(we should not get any unconstrained end points; clock
notfound; No drive Assertion))
Read spef :(report_annotated parasitics)
Report timing :(we need to generate timing reports for all variable paths in the design)
Analysis :(After generating the reports we should analyse all the slack, setup, holdvalues)
112. Tell me about PD?
Ans: A. Inputs for PD
1. lib (timing, functionality, power)
2. lef (physical info)
3. v (logical connectivity)
4. sdc (clock definitions)
5. cpf/upf (consists of power domain info)
6. cap table (RC values for every net)
B. Sanity checks
a) Library sanity checks (physical and logical library)
1. Missing cells and pins
2. Mismatched pins
3. Duplicate cell name
b) Design sanity checks (checkNetlist)
1. Floating pins
2. Combinational loops
3. Assign statements
4. Tristate buffers
5. Empty modules
6. Multi Driven nets
c) Constraint sanity checks
1. All flops are clocked or not
2. No unconstrained path
3. Input and Output delays
• Floorplan (defining core and die area based on Aspect ratio and Utilization
factor and placing macros physical cells )
• Power Plan (supplying power from Pads to the Design)
• Placement (finding the appropriate location of the std cells)
• Place opt (to meeting area congestion and timing [setup])
• CTS (Distributing clock from clock port to clock pin)
• opt CTS (balancing skew and latency also DRC's to meet the timing[setup, hold])
• Routing (Connecting components physically and finding optimized net
length with introduced net delays)
• opt Routing (Assigning the track for every net and fixing the timings )
• Signoff (meeting the all requirements timing, functionality, power, area and DRC.)
113 .Inputs of STA?
Ans: 1. Lib
2. netlist
3. sdc
4. Spef p.shivaram 9703114680
114.What is BlackBox?
Ans: It consists of input and output but we cannot see the inside functionality.

115 .What are the commands using entire pd flow?

Ans:
FloorPlan:
1. floorPlan -site CoreSite -r 1 0.698983 1.0 1.14 1.0 1.0
2. editPin -fixedPin 1 -fixOverlap 1 -unit MICRON -spreadDirection
clockwise -side Top -layer 4 -spreadType start -spacing 0.4 -start 4.337
750.8455 -pin {pin names}
3. addHaloToBlock 1 1 1 1 -allBlock
4. addEndCap -preCap FILL2 -postCap FILL2 -prefix ENDCAP
5. addWellTap -cell FILL8 -cellInterval 40 -fixedGap -prefix WELLTAP
PowerPlan:
1. for global net connection
globalNetConnect VDD -type pgpin -pin VDD -inst *
globalNetConnect VSS -type pgpin -pin VSS -inst *
globalNetConnect VDD -type tiehi -pin VDD -inst *
globalNetConnect VSS -type tielo -pin VSS -inst *
Placement:
1. placeDesign
2. for hard blockage (createPlaceBlockage -box <area> )
3. softblockage (createDensityArea <area> <percentage>)
4. placeDesign -incremental
5. optDesign -preCTS
CTS:
1. clockDesign
2. optDesign -postCTS
3. report_timing
4. report_constraints –all _violators
Routing:
1. RouteDesign
2. optDesign -postRoute

116.Tell me ten ways to fix Setup and hold?

Ans: To fix SETUP:
1. Upsizing the cell.
2.Vt Swapping.
3. Pulling the launch.
4. Pushing the capture.
5. Logical Restructuring.
6. Pin Swapping.
7.Cloning.
8. If net delay dominates the cell delay, Break the net and adding buffers.
To fix HOLD:
1. Downsize the cell
2. Vt Swapping
3. Pulling the capture
4. Pushing the launch
5. Insert the buffer in the data path
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117.What is OCV and AOCV?
Ans: : OCV:
Minor changes in delays due to the variations in PVT conditions.As cell delays
are varying we will apply a global derating factor then every cell having min and max delay.
All the cells are applying with same derating factor.
AOCV:
Here we are applying a derating factor based on logical depth and distance.OCV is more
pessimistic than AOCV so we are going for AOCV.

118.What is Dutycycle?
Ans: A duty cycle is the fraction of one period in which a signal or system is active known as
Duty cycle.

Duty cycle = (Ton/Ton+Toff)*100

119. What is PVT?

Ans: PVT- Process Voltage Temperature
 Best case: fast process, highest voltage and lowest temperature

 Worst case: slow process, lowest voltage and highest temperature

 Normal case: normal process, normal voltage, normal temperature

120.Make a waveform 30./.dutycycle?

p.shivaram 9703114680
 121.How many spef files used in your project?

Ans: 6 spef files

122.Cell Delay Vs VTH?

Ans: If temperatute increases mobility decreases and Vth decreases.

If temperature decreases mobility increases and Vth increases.
In lower technologies temperature decreases delay increases because it depends on threshold
voltage.
Because of Drain current i.e., Id is inversely proportional to Vth if vth increases Id
decreases then process is slow then delay also increases.

123. which is being used currently AOCV or POCV?

Ans: POCV [Parametric On Chip Variation]:

It uses a statistical approach, it calculates delay variation by modeling the intrinsic cell
delayand parasitic of load which determines sigma and mean of a logic stage.

124. Draw a clock waveform. What is the time period of a clock with
1GHZ frequency?
Ans:

125. Where will the data get launched and

captured?
Ans:

126 .If setup checks and hold checks not done what happened? If it necessary why?
Ans: Timing doesn’t meet if we do not do setup and hold check.

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 127.What are opens and shots? How u fix?

Ans: Opens: Different metals with same name known as Opens.

How to fix opens:
a. Stretching the metal layers.
b. Metal jogging

Shorts: Same metal with different name known as shorts.

How to fix shorts:
1. Metal shorts:
Metal Jogging (or) change the metal layers.
2. Via shorts:
Changes the vias.

128.What is FV?
Ans: FV (Or) LEC:
It checks the functionality of the netlists
LEC Flow :
Read lib
Read golden netlist
Read revised netlist
Mapping(Names are mapping here)
Comparing
129.What kind of errors u seen in
LEC?Ans: 1. Unmapped names

130.What is Congestion? If congestion is there what happened?

Ans: Available tracks are less than Required tracks known as Congestion.
a. First we need to do set uniform density then also if we observe congestion
b. If Global congestion is there:

• The congestion which is occurring at every g-cell in the design is called global
congestion
• Due to this global congestion we are facing the improper routing (it will generate
opens)
• This is mainly occurred due to improper placement of macros and bad floor plan
To reduce the global congestion change the core size(increase area) and fixing the proper
placement area for std cells.

c. If there are notches congestion there is a possibility to apply hard blockage.

d. If there is more cell density at particular stage we r applying partial blockage and also
cell padding.

131.What is CrossTalk?Explain CrossTalk?

Ans: The voltage transition from one net to another net through coupling capacitor known as
Crosstalk.
There are two types:
a. Crosstalk Noise
b. Crosstalk Delay

Crosstalk Noise:
If aggressor switches victim is constant known as Crosstalk noise.
If bump is above 50% it goes to metastable state(or) functionality failure.
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 Crosstalk Delay:
If aggressor and victim both in same direction delay decreases.
If aggressor and victim both in opposite direction delay increases.

132.What is Coupling Capacitor?

Ans:

A coupling capacitor is a capacitor which is used to couple or link together only the AC
signal from one circuit element to another. The capacitor blocks the DC signal from entering
the second element and, thus, only passes the AC signal.

133. Why metals are placed in horizontal and vertical fasion?

Ans: At routing stage if we place metals in horizontal and vertical manner it leads to
metals lays exactly on tracks.

134. What is CTS? Explain CTS?

Ans: Before CTS we need to
check:
1. All cells should be legalized.
2. All power nets are prerouted.
3. All pins should legalized.
4.Congestion, timing should control.

GOALS OF CTS :
To minimize skew and insertion delay to build the clock tree.
1. To minimize the logical DRCs.
2. Balancing the skew.
3. Minimum Insertion delay
4. To distribute a clock from Clock port to Clock pin

INPUTS OF CTS:
1. SDC
2. SPEC FILE
3.PLACEMENT DATABASE

CHECKS IN CTS:
1. Timing numbers
2. Utilization numbers
3. Congestion
4. All cells should legalize

135.What is CD in shell command?

Ans: change directory
p.shivaram 9703114680
136.how you make a directorie?
Ans: makedirectory(mkdir)

137.Tell me the command for directory with in a directory?

Ans: mkdir dir1
138.Based on what we will place the macros?
Hierarchy, macro to macro communication, macro to IO communication and guidelines.

139. If macros are placed at the center, what are the problems we get?
Congestion, net lengths will be more due to detouring, timing issues, IR drop.
140 .How will you give spacing between macros?
Spacing =2* (no. of pins * pitch of routing layer)/no. of available layers in the preferred
direction
141. To avoid congestion in between macros, what are the cares we take?
proper channel spacing should be provided between macro to macro and the halo should be
provided around the macro, there should not be crisscrossing between macro to macro.
142. What are the types of blockages?
Placement blockages:
 Hard blockage: It will not allow any cells inside the blockage.
 Soft blockage: It will not allow std cell but it will allow buffers and inverters during
optimization.
 Partial blockage: It will allow only certain specified percentage of cells. Routing blockage: It will
allow only some specified metal layers inside the blockage.

143. If we place soft blockage in between the macros it will allow the buffers and inverters,
in that, then how power will get to that cells?
Stripe should be added to get the power to those cells.

144. What are all the targets after power plan?

A. Checks after power planning:
1. Connectivity should be verified.
2. Any open, floating nets in the design.

145.Inputs of placement?
Design database upto power plan, lib, sdc, scandef

146. Create Clock Command?

Ans: create_clock -name top – period 10 -waveform (0 5) –get_ports[scan clk]
147. Types of VT Cells?
There are four types of VT flavours
 HVT Cells
 SVT/RVT Cells
 LVT Cells
 Ultra LVT cells
148. What is Inter Clock Uncertainty?
Uncertainty between two different clock domains is called Inter Clock Uncertainty.
149. Tell me Uncertainty value in your design for Setup and Hold?
 Setup: 120
 Skew – 80
 Jitter – 20
 Margin – 20
 Hold: 100
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  Skew – 80
 Margin – 20
 There is no jitter for hold because the hold is independent of frequency.
150. Are you doing insert buffer?
Yes, I have done endpoint buffering to fix the hold by checking the setup margin.
151. What is the preference for Tran, Cap, Fanout?
First preference is given to Tran and then Cap at last fanout.
152. What are Cworst and Cbest?
CWorst: In CWorst the capacitance is dominant i.e; maximum capacitance, and Interconnect
Resistance is smaller, it is also known as Cmax Corner.
CBest: In CBest the capacitance is minimum, and interconnect resistance is larger , it is also called
as Cmin Corner.
153. In all cases Crosstalk helpful to setup and hold?
No, in any case Crosstalk is not helpful to setup and hold.
154. Derates in OCV and AOCV?
OCV: In OCV flat derates are applied.
AOCV: In AOCV the derates are applied based on the cell depth and physical distance.
155. How will u apply derates for setup and hold in 10nm and 14nm?
In 14nm derates are applied from AOCV, in 10nm derates are applied from POCV.
156. What is False path, Multicycle path?
 False Path: The path which does not exist functionally is called False path.
All Asynchronous Clocks, Static Paths, and Non-functional paths are false paths.
 MultiCycle Path: The path which takes more than one clock cycle to capture the data is
called MultiCycle Path.
157. What are Exceptions?
Timing exceptions are:
 False path
 Multicycle path
 Max Delay/Min Delay
158. What are the violations you check in your design?
The violations we check in the design are:
 Design Rule Violations
 Setup
 Hold
 Minimum Pulse Width
 Recovery
 Removal
 Clock Gating Setup and
 Clock Gating Hold
159. How u will apply derates for both setup and hold?
 Setup: For setup derates are added to the launch path i.e; late path and reduced in the
capture path i.e; early path.
Command for applying derates are: By default the value will be 1 for both late path and early path,
if we apply 10% derate the values changes as below
Set_timing_derate – late 1.1 –data
Set_timing_derate – early 0.9 – clock
 Hold: For hold derates are added to the capture path i.e; late path and reduced in the launch
path i.e; early path.
Command for applying derates are: By default the value will be 1 for both late path and early path,
if we apply 10% derate the values changes as below
Set_timing_derate – late 1.1 – clock
Set_timing_derate – early 0.9 – data
160. Difference between master clock and generated clock?
 Master Clock: It is the clock defined from the clock source i.e; PLL
 Generated Clock: It is the clock generated internally in the design using master clock.
p.shivaram 9703114680
161. What is CRPR?
Clock Reconvergence Pessimism Removal: During OCV analysis, different derates are applied to
the launch path and capture path, the cells present in the common path cannot drive both max and
min delay at a time in order to reduce this pessimism the CRPR is introduced, the pessimism is
taken by subtracting the min delay from max delay.
162. How many corners you worked in Placement, CTS, Routing?
 Placement:
In Placement I worked on 2 worst setup corners.
PVT Corners RC Corners
0.720V, -30C, 1Process CWorst
0.720V, 125C, 1Process CWorst

 Clock Tree Synthesis:

In CTS I worked on 4 corners, 2 setup worst corners and 2 hold worst corners.
Setup:
PVT Corners RC Corners
0.720V, -30C, 1Process CWorst
0.720V, 125C, 1Process CWorst
Hold:
PVT Corners RC Corners
1.05V, -30C, 1Process CBest
1.05V, 125C, 1Process CBest

 Routing:
In Routing stage I worked on the 4 corners, 2 setup worst corners and 2 hold worst corners.
Setup:
PVT Corners RC Corners
0.720V, -30C, 1Process CWorst
0.720V, 125C, 1Process CWorst
Hold:
PVT Corners RC Corners
1.05V, -30C, 1Process CBest
1.05V, 125C, 1Process CBest

163. Tell me inputs and outputs of Synthesis?

Inputs:
 Lib
 RTL
 SDC
Outputs:
 Gate level Netlist
 Reports
 Updated SDC
164. Do you know synthesis flow?
The inputs of synthesis are
 Lib
 RTL
 SDC
Then we should perform the sanity checks
 Linking checks/ Elaboration
 Design checks
 Constraint checks
Then compile ultra should be done and then analyse the reports using
 Report_timing RTL
 Report_qor
 Report_constraint –all_violators p.shivaram 9703114680
 Synthesis Flow:
RREAD RTL
READ LIB
↓
READ RTL
↓
LINK/ELABORATION
↓
CHECK DESIGN
↓
READ SDC
↓
CHECK TIMINGH
↓TIMING
COMPILE ULTRA
↓
UPDATE TIMING
↓
REPORT QOR
↓
REPORT TIMING

165. Setup and hold calculations for Halfcycle paths?

Setup:
Setup Time = Required Time – Arrival Time
Arrival Time = Launch Clk + Launch Clk Latency + TCQ + Tcombo
Required Time = Capture Clk + Capture Clk Latency – Tsetup –Tuncertainty + CRPR
 Hold:
Hold Time = Arrival Time – Required Time
Arrival Time = Launch Clk + Launch Clk Latency + TCQ + Tcombo
Required Time = Capture Clk + Capture Clk Latency +Thold +Tuncertainty – CRPR
166. In MultiCycle path which constraints having START and why?
When the launch clock is fast and capture clock is slow then those constraints will have START
option, because the changes should be made in the START only.

Set_multicycle_path 2 –from [get_clocks Lclk] –to [get_clocks Cclk] –setup -start

Set_multicycle_path 1 –from [get_clocks Lclk] –to [get_clocks Cclk] –hold – start
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167. How you will see multicycle path issues in PT?
Using report_timing –exceptions_all
168. 114. What information you give to PD as well as Synthesis team?
Synthesis:
 If there are any missing constraints in SDC, we will analyse and give the constraints which are
not proper.
 If there are any LVT cells present in the design, we will give feedback to replace these cells with
HVT.
 If all the DRV’s and Setup violations are met with margins and all the cells used are of HVT
then we will give signoff.

Physical Design:
 Placement:
If some paths are not meeting the timing due to over buffering and under buffering, we will
give feedback to optimise those paths.
If all the Data DRV’s and setup is met with margins or if that violation can be met by sizing or
swapping then we will give signoff.
 Clock Tree Synthesis:
If the skew is not balanced, we will give feedback to balance the skew
If there is no minimum insertion delay, we will give feedback to reduce the insertion delay.
If the Clock DRV’s, Setup and Hold are met with margins then we will give signoff.
 Routing:
If there are any not annotated nets, we will collect those nets and give them to analyse and
provide the RC values for those nets.
If there is any crosstalk issue we will tell them to increase spacing or net deteriorate.
If all the DRV’s, Setup, Hold and Crosstalk is met then we will give signoff.
169. What is the information present in SDF and TWF?
Timing Window File: TWF contains all the margins
Standard Delay Format: It contains
 Cell Delays
 Timing Checks
 Interconnect Delays
170. PT flow?
In order to start PT we need the inputs
 Lib
 Verilog
 SDC
 SPEF

Then we should perform sanity checks

 Linking Checks
 Constraint Checks and
 Parasitic Checks

Then we should analyse the reports using

 Update_timing
 Report_Qor
 Report_timing
 Report_Constraint –all_violators

p.shivaram 9703114680
 PT FLOW:

1. READ LIB
2. READ VERILOG
3. LINK
4. READ SDC
5. CHECK TIMINGEK TIMING
6. READ PARASITICS
7. REPORT ANNOTATED PARASITICS
8. UPDATE TIMING
9. REPORT QOR
10. REPORT TIMIN
171. What are GBA and PBA?
Graph Based Analysis: In GBA the delays are calculated based on the worst slews. It is more
pessimistic analysis. It takes less run time compared to PBA.
Path Based Analysis: In PBA the delays are calculated based on the actual slews. It is less
pessimistic compared to GBA. It takes more run time.
172. What type of reasons for Max Tran violations?
The reasons for Max Tran violations
 When long nets are present
 When the driver cell load capacitance is high
 When driver cell drive strength is less
173. How to fix Crosstalk?
Fixes of crosstalk are:
 Upsize the Victim driver cell
 Downsize the aggressor driver cell
 Spacing between the two nets
 Shielding
 Inserting Buffer at the victim net
 Net deteriorate
174. What are the Reasons for 2w 2s in clock network?
The reason for double width is to avoid the EM violations and double spacing is to avoid crosstalk.
175. What is not annotated nets?
The nets which do not contain RC values are called as not annotated nets.
176. How to fix DRV’S?
Max Tran:
 Upsize the cell
 Insert a buffer when the net is dominant
 Buffer can be replaced with Inverter pair.
 Move the cells nearer
 Vt Swapping from HVT to LVT
 Metal width increases
 Metal jogging from lower to higher metals.
Max Cap/ Fanout:
 Upsize the cell
 Load splitting
 Cloning
 Swapping
177. What are the inputs for Tweaker and explain?
Inputs for Tweaker are
 PT sessions
 LEF
 DEF

p.shivaram 9703114680
PT sessions:

PT sessions contains Lib, Verilog, SDC, SPEF

 Liberty File:
It is also called as logical library, it contains the following
Cell Functionality
Delay Information
Timing Information
PVT Information
DRV’s
Power Information
 Verilog:
It contains the following
Name of the Module
Module information
Logical connectivity of cells
Pin Information
Port Information
Wire Information
Instance Information
 Synopsis Design Constraints:
It contains the following
Clock Definitions
Create_Clock
Create_Generated_Clock
Virtual clock
I/O Delays
Input Delays
Output Delays
Path Exceptions
False path
Multicycle path
Max Delay / Min Delay
Design Rule Violation’s
Max Transition
Max Capacitance
Max Fanout
 Standard Parasitic Exchange Format:
It contains the RC values of all the nets.
 Library Exchange Format:
It contains all the physical information, so it is also called as physical library. There are two LEF’s
 Tech LEF
 Cell LEF
Tech LEF:
It contains metal and via information
Metal name
Metal Direction
Pitch Information
Area
Minimum Width
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Minimum spacing
Resistivity
Max Density
Min Density
Via Name
Type of Via
Cell LEF:
It contains the cell physical Information
Cell name
Area
Site Information
Pin Information
Port Information
Obstruction
 Design Exchange Format:
It contains all the physical information if the design
 Design name
 Die Information
 Core area Information
 Pin Information
 Row Information
 Grid Information
 Components Information
 Metal Information
 Blockage Information
 Halo Information
 Via Information
 Wire Information
 Special nets Information
178. What are Tweaker Commands? How the Tweaker fix those violations?
Tweaker Commands:
 Commands to read inputs:
Libin
Lefin
Verilogin
Spefin
Defin
 Commands to fix violations
Slkfix -all_max_transition
Slkfix -setup –all
Slkfix –hold –all
Slkfix –noise -all
Slkfix –area_recovery
Slkfix –power_eco
Slkfix –dynamic_power_eco
Commands to set fixes
Set slk_fix_hold_by_sizing true
Set slk_fix_hold_by_delay_insertion true p.shivaram 9703114680
Set slk_fix_setup_by_sizing true
 Commands to extract Reports
Slk_report –summary
Slk_report –timing_summary
Slk_report –leakage_power
 Commands to dump outputs
Ecotclout –pt/icc
Verilogout
Defout
Spefout
179. What is the command for upsize and write the full command?
Size_cell instance_name cell_name
180. How Tweaker will do upsize?
By setting slk_fix_setup_by_sizing true
Slk_fix_hold_by_sizing true
181. Briefly explain logical synthesis ?
synthesis= [TOM] {T= translation,O= optimization,M= mapping}
Synthesis is process of converting the "RTL code" into optimised technology dependent "Gate level
Netlist".
Input of Logical synthesis outputs of Logical synthesis:
- RTL code (verilog, VHDL, system verilog) - Gate level Netlist (.v)
- .lib - output SDC
- .SDC -Reports
SYNTHESIS FLOW: tools used : synopsis : Design Compiler Cadence : Genus

STA Basic
#Include all libraries –technology and IP model ( libraries set link_path“.db” )
#Read all gate-level design files (read_verilogfull_chip.v)
#Read libraries and link the design (link_designFULL_CHIP)
#Read the SDF (read_sdf–analysis_typebewc–max_typesdf_max–min_typesdf_min)
#Do all sort of reporting
report_design
report_clock
report_annotated_delay
report_annotated_check
check_timing
report_timing

p.shivaram 9703114680
LINUX BASICS
 mkdir – make directories
Usage: mkdir [OPTION] DIRECTORY...
eg. mkdir prabhat
• ls – list directory contents
 ls -lrt
Usage: ls [OPTION]... [FILE]...
eg. ls, ls l,
ls prabhat
• cd – changes directories
Usage: cd [DIRECTORY]
eg. cd prabhat
 pwd print
name of current working directory
Usage: pwd
• vim /gvim – Vi Improved, a programmers text editor
Usage: vim [OPTION] [file]...
eg. vim file1.txt
 cp – copy files and directories
Usage: cp [OPTION]... SOURCE DEST
eg. cp sample.txt sample_copy.txt
cp sample_copy.txt target_dir
 mv – move (rename) files
Usage: mv [OPTION]... SOURCE DEST
eg. mv source.txt target_dir
mv old.txt new.txt
• rm remove
 rm-rf forcible removed files or directories

Usage: rm [OPTION]... FILE...

eg. rm file1.txt , rm rf
some_dir
• find – search for files in a directory hierarchy
Usage: find [OPTION] [path] [pattern]
eg. find file1.txt, find name
file1.txt p.shivaram 9703114680
• history – prints recently used commands
Usage: history
 cat – concatenate files and print on the standard output
Usage: cat [OPTION] [FILE]...
eg. cat file1.txt file2.txt
• echo – display a line of text
Usage: echo [OPTION] [string] ...
eg. echo I love India
echo $HOME
 grep print
lines matching a pattern
Usage: grep [OPTION] PATTERN [FILE]...
eg. grep –i apple sample.txt
• wc print
the number of newlines, words, and bytes in files
Usage: wc [OPTION]... [FILE]...
eg. wc file1.txt
wc -L file1.txt

sort – sort lines of text files

Usage: sort [OPTION]... [FILE]...
eg. sort file1.txt
sort –r file1.txt

chmod – change file access permissions

Usage: chmod [OPTION] [MODE] [FILE]
eg. chmod 744 calculate.sh
• chown – change file owner and group
Usage: chown [OPTION]... OWNER[:[GROUP]] FILE...
eg. chown remo myfile.txt

• su – change user ID or become superuser

Usage: su [OPTION] [LOGIN]
eg. su remo, su
• passwd – update a user’s authentication tokens(s)
Usage: passwd [OPTION]
eg. passwd
• who – show who is logged on
Usage: who [OPTION]
eg. who , who –b , who –q

 kill – to kill a process(using signal mechanism)

Usage: kill [OPTION] pid
 zip – package and compress (archive) files
Usage: zip [OPTION] DEST SOURSE
eg. zip original.zip original
• unzip – list, test and extract compressed files in a ZIP archive
Usage: unzip filename
eg. unzip original.zip

 du – estimate file space usage

Usage: du [OPTION]... [FILE]...
p.shivaram 9703114680
eg. du
• df – report filesystem disk space usage
Usage: df [OPTION]... [FILE]...
eg. df
du -df
• quota – display disk usage and limits
Usage: quota [OPTION]
eg. quota –v
 poweroff – power off the system
Usage: poweroff [OPTION]
eg. poweroff

 sed stream editor for filtering and transforming text

Usage: sed [OPTION] [inputfile]...
eg. sed 's/love/hate/g' loveletter.txt
• awk pattern scanning and processing language
eg. awk F: '{ print $1 }' sample_awk.txt

p.shivaram 9703114680