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VLSI Interview questions
CISCO:
1)
2) Some star to delta conversion networks for finding the R
3) What shud we do to reduce latch up-----
3) How to reduce short channel effects – substrate is to heavily doped
4) Some mental ability q’s
5) Convert a mux to an OR gate
6) Design a 2X1 mux using half adders
7) Some clk skew q
8) Some simple ckt which has 2 voltage sources in series to it and a
current source u had
to find the I through resistor which is a easy one to solve
9) Two latches constructed using muxes are cascaded such that it acts
like a master slave
flipflop and u shud mention wether it is +ve edge triggered or –ve edge
triggered..
10) Some stuck at fault in a ckt and u shud mention the test vector for it.
11) Some k map simplification….
12) Given a boolean eq. and u shud design the ckt using min no. of nmos
and pmos for
that go for pseudo nmos technique.
13) Given the below ckt and u shud tell wether the clk period is enough
or not and what
problems that the ckt will faces (I m not able to remember the correct q
and diagram)
1ohm
1ohm
1ohm
1ohm
1ohm
1
o
h
m
1
o
h
m
6V
V1
3V
Find V1?
Interview questions:
Some basic inverter q’s
Latch up q’s
Timing violation q’s
Freescale:
1. How to design AND Gate using one pMOS and one nMOS.
2. Design a flip flop using MUX.
3.Design a divide by 3 synchronous circuit.
4. Positive edge detector circuit.
5. A simple combinational circuit was asked to be simplified.
6. Design a two bit comparator with and without using MUX.
7. A transistor circuit is given.find out the output voltage given Vbe
and Vce. This is a
simple one.
8. Design a square wave generator which takes only one positive edge
trigger.
9. A question on maximum frequency of operation of a circuit. the setup
time, hold time
of the flip flops are given.
f/f1
tsetup=3.5ns
thold=2ns
tc-q=3ns
f/f1
tsetup=3.5ns
thold=2ns
tc-q=3ns
Buffer
tbuffer=3.3ns
D
Clk
Tclk=5ns
Tcomb=3ns
10. What is the purpose of the impedence matching between the load and
source?
ans: To avoid the reflection of the power.
ITTIAM:
Written Test (Apti) :
1. Probability of 0 1 is p1 and 1 0 is p2. If 00 is xferred what is
the prob of
receiving at least one of them is 0. Ans 1 – (p1*p1)
2. Triangle 1: width is 5, height is 2.
Triangle 2: width is 8, height is 3
Rectangle 3: width is 5, height is 3
What’s the total area?
a) 32
b) 32.5
c) 33
d) both a and b
2. Something like this:
6471p + 3245q = 263452
3245p + 6471q = 236231
a) 1.5 <= p <= 2
b) 2 <= p <= 2.5 etc.
3. Speed downstream is 72 Kmph, level is 63 Kmph, upstream is 54 Kmph. A
person
travels A to B in 4 hrs and returns in 4 hrs 40 min. Distance from A to
B is
a) 203 Km b) 273 Km c) 302 Km
d) Data insufficient
4. Something like this:
A said “B didn’t do it”
B said “I didn’t do it”
C said “A did it”
D said “B lies”
Who is true?
5. Speed uphill=53miles/hr; speed downhill=70 miles/hr; speed on flat
road=63miles/sec. It takes 4 hr to travel from town A to B and 4hrs
40min to travel from B to A. Find the distance between the towns.
3
1
2
6. A has n+1 coins and B has n coins. Both of them together toss all
their coins.
What is the probability that A gets more no of heads than B.
Interview
1. How to construct 4x1 mux using 2x1 mux only.
2. How to find out contents of PC at any point in the code. Ans Using
CALL and
reading top of stack.
3. x = (x +1) % 2 in the body of big loop. Optimize this to single
operation. Initially
x = 0. Ans x = not (x)
4. How to make a monostable (one shot) multivibrator using flipflops.
5. If the clock and D input of a D flipflop are shoted and clock
connected to this
circuit, how will it respond?
6. Some opamp circuit with several voltage and current sources connected
through
resistor dividers, find output.
7. Basic DSP theory: What is the frequency domain representation of (1)
sinewave
(2) cosine wave (3) the combination of sine and cosine waves. Given the
output of
(3)above, how will you find the input? Draw and show how it looks like.
8. If a LPF and HPF are connected in series, how will they respond under
different
cases of their cutoff frequencies (example if f1 < f2, what will happen)?
9. Interface an 8 bit µP with two 8Kx8 RAM chips. What would you do if
A0, A1 are interchanged in h/w for only one memory chip. What’d you do
in case of PROMs in case of RAMs?
DSP Paper
There are 3 sections ee, dsp and cse each with 20 q?s u have to attempt
any one section
only . Here I am sending the dsp section which I took , in other section
the first and last 4
q?s were same as dsp.
1
--------S ----R1-------
|
R2
V
|___
|
R3 |( C
|
| -----
--------------------------
instantaneous Voltage across R2 when switch S is closed :
a.V*R2/(R1+R2)
b.V*R2/(R1+R2+R3)
c.0
d.V
Ans V*R2/(R1+R2+R3)------is what I wrote
2
---------R----------
|
|
V
L
|
|
_______________
as freq increases which of the following increases
ans : Z and V(L)
3 q? on setup time and dealy
diagram below given not very clear\
clock period is 10ns ,
setuptime of each ff is 2 ns
clk2Q delay is 3ns
Slew dew to inverter is 1ns
Wht is the max allowable dealy of block D hold time=0
Ans 10-2-3-1=4ns
4 o/p of the following gate
D
Slew=1
CLK=10ns
ans : (a+b)c+de
5 SER=10^-4 the BER of a QPSK
a =SER
b <=S ER
c>=SER
d =SER/2
ans >=SER
6 for 62db of PCM System what is the no of bits =10
7 for a 4 level pipeline processor the no of machine cycles required for
executing 4
and (someno I don’t rember) with initially pipeline flushed
ans = 4+3 and …+3
u add there for initial latency
8 An ideal LPF is
a causal
bnon causal
c non stable
d none
ans: non causal ,
9 impluse func and white noise have same
a magnitude and phase response
b magnitude response
c phase response
d none
ans magnitude and phase response
or
nand
nand
and
not
A
BC
D
e
10
y(t)=y(t-1)+0.1x(n) is what typr of filter
ans : IIR LPF
11 a signal s(t)=sin(omega*t) is sampled at fs, then the resulting
signal spectrum is
periodic depends on:
aOmega/fs
b omega *fs
c omega
d fs
ans omega/fs
12 if 2 gaussian func of mean m1 and m2 are added the wht is the
resulting PDF
a guassian func with mean m1+m2
b guassian func with mean m1+m2/2
c uniform with mean m1+m2
d rayelig with mean m1+m2
13 u(t)+ sumof( deltafunc(n-k)){n=- infinitive to+ infinitive ) is
equaltent to
I hope I am made this clear it is a simple one
Ans u(-t-1) +2u(t)
14 if the probable of drawing an even no is p the wht is the probailty
of drawing odd
no in 2nd chance given 1st draw resulted in even one
a.p
b.(1-p)
c.p(1-p)
d.p/(1-p)
ans p(1-p)
15 no of multi required to mutli 2 upper triangular matrixes
a p(p+1)/2
b (p-1)(p+1)/2
c.summation (i=1 to p) i(i+1)/2
d…..
ans:c
16 a c program given something like this
unsigned short int i, j=1;
for (i=0,i<10,i++)
if(i&j)
printf(“ITTIAM”);
how many time is Ittiam printed .
ans 5 since bitwise and therefore only odd no will result in true if
condtion
17 some c program abt function concerned with pointer and local variable
easy one
ans 25
18 f=100 khz fs=125khz
o/p of filter with cutoff 150khzs
ans 25 and 100 khzs
19 stack in a processor is used for
a function call
b unlimted function call
c local variable
d something
I am not very sure if it is function call or unlimited function call ,
since function call
also be done with shadow registers but only to a certain depth but most
processor
don’t use shadow registers . at the same time depth of stack is also limited
20 x(F) is a signal whose freq response is asymmetric i.e H(F)=H(-f)
then it can be concluded that x(t) is
a real
b real or complex
c comples
d none
ans complex
here is the apti paper it also has 20 q?s and 30 min
1 some q? on some no is appended with 7(on right of units place)
multiplied by 5 then result is similar to intial no with 7 on the left
most (most significant digit)find the 3rd digit
ans =2 (?)
2 OTTSSFF?N
a.T
b.E
c.N
d…
ans: I wrote E
3 abcdefghij
a=no of zeros in the no
b= no of ones in the no
c= no of twos
so on
wht is the sum of digts
a.10
b.55
c.9
d….
ans 9(?)
4 of a no +2/3 of another no =3/8 of sum
wht is their ratio
ans: 3:7 (7:3)
5,6,7,8 9 four q? on some gre type analytical it was abt some 4 family
runs a 4
restaurant name of husband (jai, jayesh, Parikh,bipin), wife(beena,
chand, preethi,
sangeetha) and their familyname (joshi,natwar,sahni,….)give , some hint
and who runs
which hotel(Indian court, American court,….) asked
ans D D D C in that order in our paper :ANSWER THIS Q ( I think this was
an important
question)
10 If in a test 1 mark is for correct answer ,what negative mark should
be kept for
nullifying the correct answers…
a.1/4
b.1/2
c.3/4
d…
ans=1/4
11 A wins B by 28 meters or (some) seconds( time) the A is ahead of B
Ans 4 min 20 sec
12 Given 2 circles of radius R1 & R2. how many rotations will the
smaller circle
have to make a full revolution around the circle with radius R1.
ans (r1+r2)/r1
13 An equlateral triangle and its circumcircle..what is the probability
that a line
drawn inside this circle is longer than the side of the equilateral
triangle
R1
R
2
ans =1/3(?)
14 given wt 1,3,9,27 how much max can u weigh
ans 40
15 43 players play some knock out game . how many games should be
conducted to
declare a winner
ans 42
15A man traveling at a speed of….misses a train by 7 mins…if he travels
at a speed
…..how far should he travel to catch the train
ans 6 km
16
2 traingle made form circles fiven
0
0000
00
000
000
00
0000
0
how many min circles have to be removed to get some thing
ans 3
17 a boy has trasfered 100 galss from one palce to another the owner puts a
condition tht if he delivers safely he gets 3 paise for each glassand he
would
forfeit 9 paise for every broken glass. He loses some glass and gets
Rs.2.40/-
wht are the no of broken glass
ans 5
in EE paper:
some questions which I saw:
5. what is the expression for o/p?
a.AC
b.A’C+AC’
c.C
d.B’C+BC’
_
_
+
ans:A’C+AC’
6.what is the current I in the ckt assuming ideal opamp as shown:
resistance values given
current source
I
7.what does the ckt below work as:
something similar to this : I think it was Schmitt trigger ckt (check it
out)
CC’
Y
CC’
B
A
8.what is the current flowing in the ckt:
a.Is
b.0
c…
d….
9.some problem on writing laplace transform of the given ckt
a.E/s[….]
b.Es[…]
c….
d….
Hi …… These are the questions,in interview for ITTIAM. I have written
the answers I
gave. There might be better solns
Q. Give the time and frequency domain representation of a sine wave.
A. Sketch a sine wave for time domain rep. For freq domain rep, it is
1/2j [delta(f-fc)-
delta(f+fc)]. Phase of the sine wave is 90 deg. ( lag )
-
-
+
Q. Repeat the above for a cosine wave – Phase is zero deg.
Q. Repeat the above for sum of sine and cos waves.
Q. Given large amount of data of ones and zeros, how wud u compress it
using huffman
coding.
A. Use Run Length coding and code the run lengths using Huffman coding
Q. Any alternate way for the abov prob.
A. Consider three bits at a time. That can give rise to eight possible
symbols. Then code
these symbols using Huffman Coding.
Q. Will Huffman coding be always advantageous.
A. No, If the prob of occurance of symbols are equal then there is no
advantage
Q. When is Huffman coding optimum
A. When prob of symbols are powers of ½ it can be optimum
Q. why
A. Use the equation, bits reqd = – log p. If p is powers of ½ then no of
bits will be an
integer and hence it will be optimum.
Q. Is there any other method of optimal entropy coding
A. Arithmetic Coding
Q. Why is it optimal
A. Since group of symbols are coded, fractional bit rate can be used.
Q. What is a notch filter
A. Filter with response
Q. Given Low pass and High pass filters how to realise above filter
A.
I/P
+
O/P
LPF
+
Choose LPF with cut off slightly below the notch freq.
HPF with cut off slightly above the notch freq.
Q. How to design filter with gain at single freq
A. Put LPF and HPF in series. Choose Cut off of LPF slightly above the
notch freq.
Choose cut off of HPF slightly below notch freq.
Q. Given an RC-Ckt, Low pass output is obtained across which component
and why
A. Across C. Because impedance of C inc as freq reduces, so voltage
across it inc, as freq
reduces.
Q. Given two LTI systems in cascade what is the resultant gain and phase
A. Resultant Gain is product of the two gains, Resultant Phase is sum of
the two phases.
Q. what is the O/P of the following system
+
_
A. All the low freq components will be attenuated and high freq
components will be
inverted
Q. How will the phase of LPF affect the above ckt.
A. Low frequencies get cancelled only when phase shift is integer
multiples of 2pi.
Q. Two LTI sys are in cascade. Impulse response of first system is
h1(n). Second system
is described by the diff equ. Y(n)=x(n-1)+x(n), what is the overall
response of the
cascade
A. overall response is h1(n-1) + h1(n)
Q. I have a database of 5 faces. Given a test image of some face, what
is the simplest way
to recognize it.
A. Correlation
Q. If the test face is taken in totally diff lighting conditions wud
correlation work, How
wud o solve the prob
A. I gave solns like removal of DC Component, Histogram equalisation and
then
correlation etc…….he was not convinced.
HPF
LPF
Q. Is an image zero mean signal
A. No
Q. P.T. sum of 2 odd nos is even
Q. Is sum of two prime nos prime. If Yes Prove, If not Prove
A. Same proof for both of the above
Q. Give diff configurations to realise 4 - I/P AND gate using 2 – I/P
AND gates
A.
Config 1:
Config 2:
Q. Given a black box consisting of one of the above config, how wud u
detect as to which
is the config.
A. In Config 1, delay is same for all i/ps. In Config 2 delay for i/p
1110 is less than for
1011.
There were other small questions which I do not remember. All were very
very basic. Just
stay cool and u can answer everything.
ITTIAM paper 2004 (EE section only)
1) If the probability of 0 being received as 1 is p1 and that of 1 being
received as 0 is p2.
What is the prob of receiving at least one 1 if two consecutive zeroes
are sent?
1-(1-p1)2
2) For symbols a, r, and p having a prob of occurrence as 0.4, 0.2, and
0.2 and t being
another symbol, what is the length of code for ‘a’ in huffman binary
coding?
1
3) For probability of 0.25,0.25,0.5, find the entropy.
3/2
4) How many multiplications will be required for multiplying two p×p
upper triangular
matrices.
sigma p3 (I am not sure of the answer)
5) How many cycles are required for a N,M convolution given that each
addition, mult
and mac requires one cycle?
I ticked (N-M+1)M/2 (not sure of the answer)
6) For 62db of SNR, what it the channel capacity? (think they meant per
unit BW)
use C=B log2(1+SNR)
7) One question on odd-parity detector. (‘what is this’ type)
8) One question on bistable multivibrator using 741. (again ‘what it
this’ type)
9) The above is a 4 bit shift reg. The feedback path has an XOR gate.
Tell the value of
the reg after two shift right.
10) A simple C program. What will be the output of i&j where i=10, j=20.
0
11) For Vcc =20 V and beta =100 find Ie for Vbe= 0.6 V. Take Ic = Ie.
9.6 mA
XOR
Gate
1
|
0
|
1
|
1
12) The propagation delay of each AND gate is 10 ns. What could be the
max clock
frequency.
1 08 Hz
13) The current across 20 ohm res is
0.5
100 k
1 k
1 k
Vcc
D Flip-
Flop
D Flip-
Flop
D Flip-
Flop
D Flip-
Flop
AND
AND
AND
20 ohms
XOhm
s
30 ohm
+
30 V
10
Ohm
10 A
current
source
14) Block diagram (find the Transfer Function):
15) Find I for t=0 when the switch S is closed. Also dI/dt.
0A, 5A/s
16) There was a question about the causality and non-linearity of a
system given its
difference equation.
Ittiam interveiw questions
1. make a 4x1 mux using 2x1 multiplexers
2. make a 2-input Or gate using 2x1 mux
ans. make A & B as the input of Mux & B as the select signal
3. In the z-plane there is a zero at intersection of unit circle and
x-axis & there are two poles somewhere inside the unit circle Then what
can u tell about the fourier transform of the signal??
ans. the FT will definitely be zero at origin
4. A signal s1(t) is passed through a LPF to get s2(t) and the s2(t) is
G1
G2
G3
G4
+-
+-++
S
R = 5K
L=2H
C=5F
+10
Volts
-
subtracted from s1(t) to get s3(t) =s1(t)-s2(t)
How will s3(t) relate with s1(t)??
ans. It may or may not be the high pass filtered version of s1(t)
depending on the phase of LPF (he was not convinced with the answer)
5. what is difference between A-law & mu-law ??
ans. ??
Some questions of Ittiam:

ABCDEFGHIJ
is a number.
A is the number of 0s.
B is the number of 1s etc
J is the number of 9s
What is the number
Some question on logic was there. like finding whose husband is john or
whose wife is mary type.
in general other aptitude questions were peace
(interview) what is the algorithm to find if p is a prime. Why do u
need to test only upto sqrt(p) factors.
Technical test and interview):
DSP: y(n) = a y(n-1) + b x(n); what is the condition for system to be
stable ? why?
find region of convergence of 1 +2 z inverse
if y1(n)= h1(n)*x(n) and y(n)= ay1(n)+by1(n-1). Find impulse response
of over all sysemin terms of h1(n) only.
Huffman coding.(given set of symbols and probabilities construct code)
ASked the algorithm in general to generate such an optimal code.( there
is something like a tree diagram given in every digi compression book).
asked to give output of RC circuit with const voltage source. then with
const current source. Asked why in 2nd case the voltage cannot goto
infinity( could be capacitor break down or that the voltage across current
source can
t exceed a certain value)
Construct four input and gate using 3 two input and gates in two ways.
If a black box with one of them is given how will u find which
configuration it is. U have only black box and nothing to compare that
with. u
can give any input and see output.
How many min number of input combinations do u need
Pseudo code for matrix transpose. Should be optimal and swapping alos
should be optimal. I gave sswapping using arithmetic operators. But they
wanted that using logical operators. jus replace the arithmetic
operations with xor. how many computations do u need for the getting the
transpose of n*n matrix. Why
Whats the probability that u pick two red balls out of a bag of two red
balls and 3 black balls? they tried to confuse. But i held on . They
were seeing it in a different manner but finally landed up with the same
answer i gave. Soif ur sure don
t give up
Intel:
Paper I
1. Find Voltage across R and C in the following circuits.
a. In a given RC circuit find the voltage across C and R?
b. In a given CR circuit find the voltage across R and C ?;
2. For the given _expression Y=A’B’C+A’BC+AB’C+ABC+ABC’ realize using
the following
a. 2 input and 3input NAND gate
b. 2 input and 3 input NOR gate
c. AND,OR, INVERTER.
d. INVERTER;
3. What is the importance of scan in digital system.;
4.Given A XOR B =C, such that prove the following
a. B XOR C =A
b. A XOR BXOR C=0;
5. Construct an input test pattern that can detect the result E stuck at
1 in the ckt below
NAND (A,B)->E, NAND(C,D)->F
AND(E,F)->A.
6. In a given opamp ckt input offcet is 5mv,volatage gain =10,000,vsat=+-15v
such that find the output voltage .
7. Draw the p side equation of the circuit.(I am not sulre about it)
8. Make a JK FF using a D FF and 4->1 MUX.
9.Use 2->1 MUX to implement the following _expression
Y=A+BC’+BC(A+B).
10.For the following ckt what is the relation between fin and fout.?
the D FF use +ve edge triggered and have a intial value is 0
CLK->two DFFs with complementing (i.e one DFF have CLK and other one have
Complement of it),inputs of DFF is same and output of DFFs is given to NOR
Gate and output of NOR gate is feedback to the two DFFs.
11. Design a asyncronous circuit for the following clk waveforms.
CLK->thrice the CLK period->half the period of input.
12. What is the setup time and hold time parameters of the FF, what
happens if we are not
consider it in designing the digital ckt.
13. Given two DFF A,B ones output is the input of other and have the
common clock.
Fmax if A and B are +ve edge triggered, if A is+ve edge triggered ,B is
-ve edge triggered what is
the Fmax relation to previous Fmax relation…
14. What are the FIFOS .? give some use of FIFOS in design.
Paper II
1. What is FIFO ? where it is used?
2. what is set-up and hold time?
3. Two +ive triggered FFs are connected in series and if the maximum
frequency that can
operate this circuit is Fmax. Now assume other circuit that has +ive
trigger FF followed by –
ive trigger FF than what would be maximum frequency in terms of the Fmax
that the circuit
can work?
4. layout of gates were shown and u have to identify the gates (NAND &
NOR gates)
5. make a JK FF using a mux(4:1) and a FF.
6. the waveform of clk, i/p and o/p were shown and u have to make a
seqential circuit that
should satisfy the required waveform.
7. resistor is connected in series with capacitor and the input is dc
voltage. Draw the waveform
across the capacitor and resistor.
8. two FFs, one is –ive triggered and other is +ive triggered are
connected in parallel. The 2 i/p NAND gate is has the i/ps from the
q_out of both the FFs and the output of the NAND gate is connected with
the I/p of both FFs . Find the frequency of the output of the NAND gate
w.r.t clk.
Interview questions (face to face discussion)
1.Draw the circuit for inverter. How does it work?
2.If the pmos and nmos is changed in the inveretr, how does it behave?
3. Design flow for ASICs and FPGA. what are the difference between the
ASICs and
FPGA?where do u use ASIC and where u use FPGA?
4. What is floorplanning?
5.What do u mean by technology file used in the synthesis or
optimization for the circuit
(netlist)? What is the difference in the technology files used for the
ASICs and FPGAs based
designing?
6. Using a FF and gates. Make a memory (i.e include RD, WR etc.)
7. If the setup & hold time gets violated than what u ‘ll do to remove it?
8. What is clock skew? How u ‘ll minimize it?
9. What is clock tree? How it looks like? Concept behind that.
10. What about the Vdd and Gnd lines ? does one Vdd and Gnd pins will be
sufficient for the
chip. What will be the effect of using single Vdd and Gnd pins in the chip?
11.What is voltage refernce circuit? What is bandgap? How does it work?
12. what is FIFO? How does it work? Draw the circuit of FIFO of 1-bit
and 4memory location
deep? What would happen if memory is full and again u try to write in
FIFO? What u ‘ll do to
overcome this problem? Which one would be more easier to implement :-
either dropping the
packet, when the FIFO is full or pushing the data of FIFO every time.
And why ?
The following questions are used for screening the candidates during the
prescreening interview.
The questions apply mostly to fresh college grads pursuing an
engineering career at Intel.
COMPUTER ARCHITECTURE QUESTIONS
1. For a single computer processor computer system, what is the purpose
of a processor cache
and describe its operation?
2. Explain the operation considering a two processor computer system
with a cache for each
processor.
What are the main issues associated with multiprocessor caches and how
might you solve it?
3. Explain the difference between write through and write back cache.
4. Are you familiar with the term MESI?
5. Are you familiar with the term snooping?
STATE MACHINE QUESTIONS
1. Describe a finite state machine that will detect three consecutive
coin tosses (of one coin) that
results in heads.
2. In what cases do you need to double clock a signal before presenting
it to a synchronous state
machine?
3. Design a FSM that will assert output when more than one ‘1’ is
recieved in last three samples.
Do not use more then 4 states.
SIGNAL LINE QUESTIONS
1. You have a driver that drives a long signal & connects to an input
device. At the input device
there is either overshoot,
undershoot or signal threshold violations, what can be done to correct
this problem?
VALIDATION QUESTIONS:
What are the total number of lines written in C/C++? What is the most
complicated/valuable
program written in C/C++?
What compiler was used?
Have you studied busses? What types?
Have you studied pipelining? List the 5 stages of a 5 stage pipeline.
Assuming 1 clock per stage,
what is the latency of an
instruction in a 5 stage machine? What is the throughput of this machine ?
How many bit combinations are there in a byte?
What is the difference between = and == in C?
Are you familiar with VHDL and/or Verilog?
MEMORY, I/O, CLOCK AND POWER QUESTIONS
1. What types of CMOS memories have you designed? What were their size?
Speed?
Configuration Process technology?
2. What work have you done on full chip Clock and Power distribution?
What process technology
and budgets were used?
3. What types of I/O have you designed? What were their size? Speed?
Configuration? Voltage
requirements?
Process technology? What package was used and how did you model the
package/system?
What parasitic effects were considered?
4. What types of high speed CMOS circuits have you designed?
5. What transistor level design tools are you proficient with? What
types of designs were they
used on?
6. What products have you designed which have entered high volume
production?
What was your role in the silicon evaluation/product ramp? What tools
did you use?
7. If not into production, how far did you follow the design and why did
not you see it into
production?
nVIDIA:
1-6 are multiple choice questions)
1. The max. value and min. value of 16-bit 2
s complement (hex, dec,
binary)?
2. The max.,min. value of 16-bit 1
s complement (hex, dec, binary)?
3. max. no. of logic functions for n-variables? ans: 2^2^n
4. about physical and virtual address, which is greater?
5. TLB (Translation Lookahead Buffer) is used for ?
options:
1. L1 cache misses
2. L2 cache miss
3. some thing page miss (not remembered exactly)
6. Minimum no. of P and N Mos transistors required to implement The
logic
Function Y= !(A | B & C) using CMOS
1. 1 p & 3 n
2. 3 p & 1 n
3. 3 p & 3 n
7.One shot digital circuit
8.Noise eliminator (both -ve and +ve pulses of one clock cycle duration)
__
__
__
__
__
__
__
__
__
__| |__| |__| |__| |__| |__| |__| |__| |__| | --> Clock
__ __
__ __ __ __
_________--> Input
________|
|___________|
|_____|
__ __ __ ____________--> Output
________________________________|
Observe the one clock delay in output.
Design a state machine for this operation.
9. Implement the following 2 functions using only 2x1 MUX without gates.
U can use 1 or 0 for inputs.
a) Y = AB+not(C)
b) Y = A xor B
10. Write a program in C or C++ to implement Stack and its functions
such as
isEmpty, isFull, Push, Pop, Init etc. (I think based on the question
given,
array implementation is sufficient)
11. Question on clock frequency required for given Sequential ckt.
Given 2 F/Fs, 3 delays ( 2 delays for clock dly1, dly2 and 1 delay
dly3 ofcombinational circuit ) given setup, hold and propagation times
Ans: T+(dly2-dly1) >= Tpd + dly3 + Tsetup
Tpd + dly3 > Thold + (dly2-dly1)
Others:
1. A Positive logic NAND gate will be equuivalent to a

-
ive logic---------- gate.
a)NAND
b)EX-NOR
c)NOR
d)OR
SANDISK:
SANDISK IIT BOMBAY PAPER, 26th DECEMBER, 2005
Written Test 45 mins
1) No. of universal logic gates reqd to implement EXOR
a) 4 NAND
b) 4 NOR
c) 5 NAND
d) 5 NOR
2) Using (A AND Bbar), we can implement
a) only AND
b) only OR
c) any logic function
d) none
3) A –V to +V pulse voltage source is connected to a RC series ckt. Draw
the
waveforms of voltage across R, voltage across C, and current in the
circuit.
4) Draw the capacitance vs voltage characteristics of MOSFET and MOS
cap, and
point their differences in the HF region
5) Arrange an underdamped, critically damped, and overdamped system in
order of
phase margins
6) Find the voltage gain of a transconductance amplifier of
transconducatnce gm, with Vi at +ve terminal, C btwn –ve term and gnd,
and R between –ve term and output
7) Considering MOS caps Cgs and Cgd,
a) Cgs>Cgd in cut-off region
b) Cgd>Cgs in saturation region
c) Cgd=Cgs in triode region
d) None
8) Draw the waveform of “A” from the verilog code
Always(@clk)
Begin
A=0;
#5 A=1;
end;
9) Draw a NORbased latch, calculate its setup time if delay of each gate
is td
10) A 1V dc source is connected to the source of an NMOS, a 0.1 nf cap
is connected to the drain, and a 5V single pulse of duration 1 us is
applied to the gate. To act as an integrator,
a) W/L >>1
b) W/L<<1
c) W/L=1
d) Cant be said from the given data
Interview 1st round :
Questions from the written test which I could not answer correctly, transfer
characteristics of a CMOS inverter, implementation of an FSM given a
state diagram,
and a riddle :-given only a 3 l and a 5 l bottle, and nothing else, how
would u measure
4 l water?
Interview 2nd round :
What are the issues if the duty cycle of the clock in a digital ckt is
changed from
50%?
What are the different tests you would do to verify your verilog code?
How would your friends describe you?
What is the greatest risk you have taken so far in life?
What are the differences between academics and industry?
Paper II
1 simple current mirror question.
2 to generate non-overlapping clock.(see Rabaey page 339)
3 question on Verilog synthesis
4 always@( posedge clk)
begin
a=0;
#5 a=1;
end
what is the output waveform of a?
5 question on differential amplifier gain with (w/l)1=2*(w/l)2
6 V=vin1 – vin2 ( vin1 and vin2 are two input voltages of 1 stage diff.
amplifier).Now V is varied from -5 to +5 then draw the output voltage vs
V.(Vdd=+5
Vss= -5).
7 two simple question on charging of capacitor with constant current source.
8 draw the VTC of buffer ( PMOS and NMOS are interchanged in inverter)
9 what should be the ratio of (W/L)PM OS / (W/L)N MOS for switching
threshold of
Vdd/2.Given Kn/Kp=2.8.
10 there is 2 input CMOS NAND gate .inputs A and B changes from 0 to
Vdd. but A
goes to Vdd after B( after some delay ). which input should be closer to
Vout.
11 what are the benefits of finger layout----less junction capacitance etc
Others couldn’t recall ..
Two rounds of interview-- HR and technical.
Nearly 45 mins for technical ( Device, digital and mostly analog).
HR also of 45 mins.
Paper III
Q1) why noise margin in invertor calculated when slope becomes -1
Q2) one question on OTA acting as HPF (resistance with -ve f/b) and a
capacitance at
vin-
ans: gm(1+rsc)/gm+sc
Q3) question on verilog synthesis
Q4) draw c-v w/f for mos capacitance and mosfet
Q5) an ideal current pulse source charging a capacitance what wud be
voltage across it
Q6) 3 step response given wat wud be the relative phase margin
ST Micro:
There were two papers
1. separate for the hardware (electonics people(VLSI))
2. and other for the embedded software design(both for electronics and
comp).
1. which conversion is not possible
a. float to int
b. int to float
c. char to float
d. all are possible
2. threads have which thing in common
a. register set
b. data section
c. thread id
d. ...
3. one que like
main()
{int x=5, y;
y= x*x++ * ++x ;
// print x and y
}
4. A CPU has four group of instruction set A, B, C, D
CPI of A = 1
CPI of B=3
Cpi of c =2
cpi of d= 4
the cpu access 20% of A, 30% of b, 30% of C and 20 % of D
what will be the average CPI.
( this que was repeated in section 2 & 3)
5 . a question on hit ratio n effective memory access time.
6.
main()
{int a=10,b=5
while ( --b>=0 && ++a)
{--b;
++a;
}print (a);
print (b);
}
7.
main()
{char i;
for (i=0; i<=255; i++)
{printf("%c", i);
}}
8. One question on controls systems
to find the transfer function.
poles n zeroes were given in a graph
9. One question on sampling theorem,
highest frequency of a signal is f, and it is sampled at fs( >= 2f).
what is the
frequency range of a bandpass signal whose spectrum looks exactly like the
original signal.
10.One on the signal to noise ratio
There are N bits to represent each sample and total number of levels is
M. If
the amplitude range is reduced by half then SNR will be reduced by:
11. A cellular network operator is operating at 9.6Kbps. If he want to
transmitt the
audio quality of 44.1KHz with 16 bits for each sample how much bandwidth
should be increased.
12. calculating the checksum for the bits to be transmitted given the
frame-
11000101 and generator is1100.
13. calculating the no of bits required for the error detection & the
error correction
for the given codeword set.
codeword a:
0000
0001
0011
1111
codeword b:
101111
....110101
14. options were given to choose as which was an example of multitasking.
a:multiple remote users accessing a server
b:user working on spreadsheet, downloading some matter from
internet
c:multiple programs resident in memory
15. CA in CSMA/ CA stands for
a. collision approval
b. collision avoidance
c. critical access
16. in a triangle, without changing the angle, if we double the
sides,then new
area will be
17. there is a pipe having dia 6mm, then how many pipes having 1mm dia
wiill be
needed to provide same amount of water.
18. in which of the folwng schemes after page replacement the entered
page will
enter in the same memory location as of the replaced one
a. direct mapping
b. n-set associative
c. associative
d. none of them
19. belady anamoly is related to.
ans. page replacement algos
20.which one uses cache mechanism
ans TLB
21.what will happen in following code..
signal(mutex)
critical section
wait(mutex)
ans. violation of mutual exclusion
22.an RLC ckt was given, fuctioning of ckt to be determined.
a: will act like FM
b: PM
c:AM
d: none of the above
23.
int i=0;
switch(i)
{case 1: printf("hi");
case 0: printf("zero");
case 2: printf("world");
}24.which one is the declaration of static string
a: static string
b:
static string
c: "static string" d:char sting[30]
25.a que on file handling in c
a: file cant be opened
b:msg.txt is copied to msg
c:only first string be copied
d:
26. which of the fuction will store a 100 char string in X
a: fread(x,100,....)
b. fread(100,x,.......)
c.gets(x)
d.read(x)
27. which of the following data type will occupy the same memory
irrespective of
the compiler.
a.int
b.double
c.char
d.float
TI:
TEXAS INSTRUMENTS: TECHNICAL TEST
Date: 20th December 2003
1. For a CMOS inverter, the transition slope of Vout vs Vin DC
characteristics can be
increased (steeper transition) by:
a. Increasing W/L of PMOS transistor
b. Increasing W/L of NMOS transistor
c. Increasing W/L of both transistors by the same factor
d. Decreasing W/L of both transistor by the same factor
Ans: c
2. Minimum number of 2-input NAND gates that will be required to
implement the
function: Y = AB + CD + EF is
a. 4 b. 5 c. 6 d. 7
ans: c
3. Consider a two-level memory hierarchy system M1 & M2. M1 is accessed
first and on
miss M2 is accessed. The access of M1 is 2 nanoseconds and the miss
penalty (the time
to get the data from M2 in case of a miss) is 100 nanoseconds. The
probability that a
valid data is found in M1 is 0.97. The average memory access time is:
a. 4.94 nanoseconds
b. 3.06 nanoseconds
c. 5.00 nanoseconds
d. 5.06 nanoseconds
ans: a
4. Interrupt latency is the time elapsed between:
a. Occurrence of an interrupt and its detection by the CPU
b. Assertion of an interrupt and the start of the associated ISR
c. Assertion of an interrupt and the completion of the associated ISR
d. Start and completion of associated ISR
Ans: d (not confirmed)
5. Which of the following is true for the function (A.B + A’.C + B.C)
a. This function can glitch and can be further reduced
b. This function can neither glitch nor can be further reduced
c. This function can glitch and cannot be further reduced
d. This function cannot glitch but can be further reduced
Ans: c This can be reduced further using K-map, don’t know abt glich,
but it should
not glitch
6. For the two flip-flop configuration below, what is the relationship
of the output at B to
the clock frequency?
a. Output frequency is 1/4th the clock frequency, with 50% duty cycle
b. Output frequency is 1/3rd the clock frequency, with 50% duty cycle
c. Output frequency is 1/4th the clock frequency, with 25% duty cycle
d. Output frequency is equal to the clock frequency
A
B
Ans: a
7. The voltage on Node B is:
a. 0
b. 10
c. –10
Q
DCLK
Q’
D
Q
CLK
Q’
XOR
d. –5
+
+
10V
20V
_
_
GND
B
Ans: d
8. A CPU supports 250 instructions. Each instruction op-code has these
fields:
•The instruction type (one among 250)
•A conditional register specification
•3 register operands
•Addressing mode specification for both source operands
The CPU has 16 registers and supports 5 addressing modes. What is the
instruction op-
code length in bits?
a. 32 b. 24 c. 30 d. 36
ans: don’t know
9. In the iterative network shown, the output Yn of any stage N is 1 if
the total number of
1s at the inputs starting from the first stage to the Nth stage is odd.
(Each identical box in
the iterative network has two inputs and two outputs). The optimal logic
structure for the
box consists of:
a. One AND gate and one NOR gate
b. One NOR gate and one NAND gate
c. Two XNOR gates
d. One XOR gate
I1
I2
In
I n +1
I n +2
10Ω
10Ω
10Ω
10Ω
10Ω
0
Y1
Y2
Yn
Yn+1
Yn+2
Ans: d
10. Consider a circuit with N logic nets. If each net can be stuck-at
either values 0 and 1,
in how many ways can the circuit be faulty such that only one net in it
can be faulty, and
such that up-to all nets in it can be faulty?
a. 2 and 2N
b. N and 2^N
c. 2N and 3^N-1
d. 2N and 3N
ans: 2N and 2^N ( no match ) see it .
sorry , no idea abt this
11. In the circuit shown, all the flip-flops are identical. If the
set-up time is 2 ns, clock->Q
delay is 3 ns and hold time is 1 ns, what is the maximum frequency of
operation for the
circuit?
D1
Q1 D2
Q2 D3
Q3
CLOCK SIGNAL
a. 200 MHz b. 333 MHz c. 250 MHz
d. None of the above
Ans: a
12. Which of the following statements is/are true?
I.
Combinational circuits may have feedback, sequential circuits do not.
II.
Combinational circuits have a ‘memory-less’ property, sequential
circuits do not.
III.
Both combinational and sequential circuits must be controlled by an
external clock.
a. I only
b. II and III only
c. I and II only
d. II only
Ans: d
13. Consider an alternate binary number representation scheme, wherein
the number of
ones M, in a word of N bits, is always the same. This scheme is called
the M-out-of-N
coding scheme. If M=N/2, and N=8, what is the efficiency of this coding
scheme as
against the regular binary number representation scheme? (As a hint,
consider that the
number of unique words represent able in the latter representation with
N bits is 2^N.
Hence the efficiency is 100%)
a. Close to 30% b. Close to 50% c. Close to 70%
d. Close to 100%
Ans: a
14. A CPU supports 4 interrupts- I1, I2, I3 and I4. It supports priority
of interrupts.
Nested interrupts are allowed if later interrupt is higher priority than
previous one. During
a certain period of time, we observe the following sequence of entry
into and exit from
the interrupt service routine:
I1-start---I2-start---I2-end---I4-start---I3-start---I3-end---I4-end---I1-end
From this sequence, what can we infer about the interrupt routines?
a. I3 > I4 > I2 > I1
b. I4 > I3 > I2 > I1
c. I2 > I1; I3 > I4 > I1
d. I2 > I1, I3 > I4 > I2 > I1
Ans: c
15. I decide to build myself a small electric kettle to boil my cup of
tea. I need 200 ml of
water for my cup of tea. Assuming that typical tap water temperature is
25 C and I want
the water boiling in exactly one minute, then what is the wattage
required for the heating
element?
[Assume: Boiling point of water is 100 C, 1 Calorie (heat required to
change 1 gm of
water by 1 C)= 4 joules, 1 ml of water weighs 1 gm.]
a. Data given is insufficient
b. 800 W
c. 300 W
d. 1000 W
e. 250 W
ans: d
16. The athletics team from REC Trichy is traveling by train. The train
slows down, (but
does not halt) at a small wayside station that has a 100 mts long
platform. The sprinter
(who can run 100 mts in 10 sec) decides to jump down and get a newspaper
and some
idlis. He jumps out just as his compartment enters the platform and
spends 5 secs buying
his newspaper that is at the point where he jumped out. He then sprints
along the platform
to buy idlis that is another 50 mts. He spends another 5 secs buying the
idlis. He is now
just 50 mts from the other end of the platform where the train is moving
out. He begins
running in the direction of the train and the only other open door in
his train is located 50
mts behind the door from where he jumped. At what(uniform) speed should
the train be
traveled if he just misses jumping into the open door at the very edge
of the platform?
Make the following assumptions
•He always runs at his peak speed uniformly
•The train travels at uniform speed
•He does not wait (other than for the idlis & newspaper) or run baclwards
a. Data given is insufficient
b. 4 m/s
c. 5 m/s
d. 7.5 m/s
e. 10 m/s
ans: c
17. State which of the following gate combinations does not form a
universal logic set:
a. 2-input AND + 2-input OR
b. 2-to-1 multiplexer
c. 2-input XOR + inverter
d. 3-input NAND
ans: a
18. For the circuit shown below, what should the function F be, so that
it produces an
output of the same frequency (function F1), and an output of double the
frequency
(function F2).
IN
OUT
F
INVERTER
a. F1= NOR gate and F2= OR gate
b. F1=NAND gate and F2= AND gate
c. F1=AND gate and F2=XOR gate
d. None of the above
Ans: c
19. The FSM (finite state machine) below starts in state Sa, which is
the reset state, and
detects a particular sequence of inputs leading it to state Sc. FSMs
have a few
characteristics. An autonomous FSM has no inputs. For a Moore FSM, the
output
depends on the present state alone. For a Mealy FSM, the output depends
on the present
state as well as the inputs. Which of the statements best describes the
FSM below?
a. It has two states and is autonomous
b. The information available is insufficient
c. It is a Mealy machine with three states
d. It is a Moor machine with three states
0
1
0
1
SA
SB
SC
0
Ans :d
20. In the circuit given below, the switch is opened at time t=0.
Voltage across the
capacitor at t=infinity is:
a. 2V b. 3V c. 5V d. 7V
+
+
_
_Ans: c
R= 10KΩ
5V
2V
C=2F
t =0
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