1.

Design Setup
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load logic libraries(search path,link library,target)
load physical library(milkyway reference lib or give milky way ref file)
load tech file
check_library
-checks logic versus physical library consistency
-number of cells missing in logic library,cells missing in pjysical library
-list of physical only cells
-missing or mismatched pins in logic and physical libraries
2.read verilog netlist
uniquify
read_def scan chain,check_scan_chain
load UPF
3.check_design(validate floorplan)
-unloaded input ports
-undriven output ports
-nets with out loads or multiple drivers
-cells with out inputs or outputs
-mismatched pin counts between an instance and its reference
3.a)check_database(validate database)
--The power and ground network is consistent
There are no logical connections to physical-only cells
The UPF data is consistent, if it exists
The design has been uniquified and contains hierarchy preservation data
create power net connections for for single and multi vltage domains(derive _pg_
nets)
4. load TDF(ports.tcl)
scenarios[[tlu+,sdc,operating conditions,power optimizations),
5.check_timing(use vitual routing)
-zero interconnect timing check
-clock crossing ,if false paths(*),some false paths(#)
-warns if no clock period
-if multiple clock reach same register(timing_enable_multiple_clock_per_reg)
-if no clock is reaching resigter
-ideal clocks(shd be propagated)
-generated clocks(source port is not clock source,clock source has no path to so
urce point
-generic cells in the desing(has no delay)
-warns of feedback loops (will be automatically broken)
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======================
6.floorplan
-using hierarchy,

-flylines(macro to macro ,macro to standard cells)

-ports conected macros)
-placement blockages
orientation of macros
macro macro distance
7.Floorplan Checks
legalisation - macros(no overlap)
check-utilization - around 60-65
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------8.powerplan
UPF file already loaded
low power techniques
voltage regions
power domians
low vt
substrate biasing
clock gating
frequency scaling
voltage regions:variable voltage(level shifter ,isolation cells)
power domains:(isolation cells,retention registers) power up and down
(level shifter ,isolation cells,retention registers already inlcuded in design)
got tcl for ir engineer or offset valure and strap width and length
static ir drop dynamic ir drop
During power analysis, if you are facing IR drop problem, then how did you avoid
?
Increase power metal layer width.
Go for higher metal layer.
Spread macros or standard cells.
Provide more straps.
reduce dynamic power
-Reduce switching activity by designing good RTL
o -Clock gating
o -Architectural improvements
o -Reduce supply voltage
o -Use multiple voltage domains-Multi vdd
2) Reduce voltage swing in all nodes
3) Reduce the switching probability (transition factor)
4) Reduce load capacitance
verify pg nets(power plans)
9.place physical(pre placed) cells
end cap cells-has dummy poly to protech cells during etching stage,use at end of
rows
decap- to control dynamic ir drop
well tap-substate plus connection to vdd vss

filler cells-just substrate continuity

spare cells already inlcuded in netlist
10. save design after floor plan(def out)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------11.placement
check macros are fixed before placement
HFN,Scan chain Reordering,
magnet placement-cells connected to pin placed near the pin
relative placement- same type of cells(logic) near
checks
-congestion
1.Reason:.near corner of macros(no over the macro routing)
solution:hard placement blockage near edges in form of jogs
2.channel between macros:(wrong channel space calculation)
solution: placement blockage and correct channel lenght calclulation
3.pins beneath power straps:
solution:placement blockage
4.near edges of power domain(voltage areas)(high utilization inside power d
omain)
-solution:maintain optimum utilization in power domain and cell paddinf
for cells near edges
5.pin density very high(too many high pins cells like andorinvert,orandinv
ert(AOI,OAI- 4pins+(2 and one nor gate--AOI,2 or oen nand gate-OAI)
solution:cell padding or try to use less number of high cell count gates
6.localized congetion at timing critical area( too many cells)
solution:use density screens(limit standard cell density)(may cause timi
ng issues) then use module paddingor cell padding
-utilization
-timing
-power drc(verify_pg_nets -tie)(add tie cells where ever needed)
fix drv
congestion fix (iteration back to floor plan)
no setup or hold fix
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------12.cts
inputs
target skew,(100ps)
propagate clock
ndr rules clock nets
clock slew no
clock references
load cts scenario
exceptions:false path ,multicycle path,min delay,max delay
constraints:input delay ,output delay,drive at input port,load at output port,ca
se analysis

cts
-synthesize clock tree to balance skew and reduce insertion delay
checks after cts
pulse width check
drv ,hold fix ,see setup
if congetion in cts:not much added to give congetion
change uncertainity (250 300)
target skew 10 percent of clock period
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------13.routing
inputs
stages-global route,track assignment,detail route,search and repair
congetion
clock nets,signal nets
after detail route
verify_zrc_route to find drc
checks after routing
-DFM -antenna
-timing
-power anaysis
-SI
route_opt -xtalk_reduction
set_si_options -delta_delat true -static_noise true
How can you avoid cross talk?
Double spacing=>more spacing=>less capacitance=>less cross talk
-Multiple vias=>less resistance=>less RC delay
Shielding=> constant cross coupling capacitance =>known value of crossta
lk
Buffer insertion=>boost the victim strength
-EM Check
report_signal_em
fix_signal_em
-DRC,LVS
--DRC
inputs-gds,rules file
--LVS
inputs-gds,routed netlist,rules file
-spef (use starRC)
inputs-tech file,tlu+,gds
-prime time
inputs-lib,spef,routed netlist,SDC
-double pattern checks(if possible)
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--------------14.eco flow:
pre mask:
run eco_netlist
place_eco_cells
legalize cells
post mask(freeze silicon)
use spare cells for eco
route the spare cells
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------15.signoff
-TIMING
-MVRC/CLP
inputs-UPF database,design database
-Formal verification
inputs:synthesis netlist,routed netlist
-SI
-DRC/LVS
-Power analysis
-EM analysis(prime rail,apache redhawk)
FIX-increase width of wire
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Issues with pd
1.why is less latency better?
sol:: 1. less latency means less no of clock buffers,leading to less congestio
n,area,power
2. less ocv effects
2.why should clock buffer transition(80ps)be better than normal buffer(150=160ps
)?
sol:
because during cross talk analysis,net witg better transition acts as ag
gressor ,so we dont want clock as victim so better clock transition
3.EM violations how to fix?
sol:
1.increase width of effected wire
2.decrese drive strength of wire(if timing not violating)
4.Do you know about input vector controlled method of leakage reduction?
sol:
Leakage current of a gate is dependant on its inputs also. Hence find th
e set of inputs which gives least leakage. By applyig this minimum leakage vecto
r to a circuit it is possible to
decrease the leakage current of the circ
uit when it is in the standby mode. This method is known as input vector control
led method of leakage reduction.
5. In a reg to reg path if you have setup problem where will you insert buffer-n
ear to launching flop or capture flop? Why?

(buffers are inserted for fixing fanout voilations and hence they reduce setup v
oilation; otherwise we try to fix setup voilation with the sizing of cells; now
just assume that you must insert buffer !)
sol:
Near to capture path.
Because there may be other paths passing through or originating from the
flop nearer to lauch flop. Hence buffer insertion may affect other paths also.
It may improve all those paths or
degarde. If all those paths have voilati
on then you may insert buffer nearer to launch flop provided it improves slack.
6.What parameters (or aspects) differentiate Chip Design and Block level design?
sol:
Chip design has I/O pads; block design has pins.
Chip design uses all metal layes available; block design may not use all
metal layers.
Chip is generally rectangular in shape; blocks can be rectangular, recti
linear.
Chip design requires several packaging; block design ends in a macro.
7.What is NDR (Non-Default rule) ? How DRC will be affected due to NDR? Can you
relax NDR to resolve DRC's?
8.What is double switching?
9.How to debug Shorts due to Ground connection.?
10.If design is in final tapout stage how will you resolve violation if they are
due SI effects.?
11.If there is cloning of flop what can be issue in LEC and how to resolve it.?
12.What is ESD violation. What is used for ESD violation.?
13.What is Latchup DRC and how is it resolved.?
14.What is ERC and which violation is considered in ERC.?
15.Effect of SI on setup and hold and how.?
16.What is timing window and how is it prepared.?
17.Is it possible to get good results due to SI?
18.data pulse violation, difference in glitch and data pulse,min pulse width.?
19.What is max cap and max fan out? what is it is relaxed?
20.if two reg physically very near each other and setup is violating,we cant ups
ize reg how to fix setup?
21.wat is inside each physical cell(,tap,endcap,decap,filler)
22.what is grid violations?n column as well as row wise if so why please explain
this
23.should we avoid macro stacking in coulmn as well as row wise if so why pleas
e explain this?
24.can we flip or rotate the macros ?explain this?
25.should we give priority to macro stacking ot contiguos are to standard cell
?explain this?

26.why congetion allowed over standard cells but not on macros?

27.is it permissilbbe to have any number of horicaontal straps with minimum widt
h?(effects on EM and routing?
28.on what parameters does routing congestion is determined?
29.why are metal layers placed in VHV or HVH?
30.we found some blank space between standard cells at he same time we are getti
ng the conestion in contiguos area?so why cant tool places the standard cells in
these blank spaces?
31.why we use metal2 in standard cells?
32.what are the considerations to decide which stripe should be added to the pow
er plan first?
33.is it always necessary to give uniform step size to horizontal stripes?can we
use non unifor step size for different horizontal stripes if necessary?
34.intra clock skew(differet clock) ,inter clock skew(same clock)?how are they c
alculated?are they different formlocal skew and global skew and whether they are
calculated between asynchronous clocks?
35.looking at timing reports after cts ,we oberved that there are paths with clo
ck_gates at the end points.is it a valid path for timing analysis?if so what cou
ld be the input to data pin for clock gate(latch)?
36.in common_cts_setting there is "avoid setting the rule on metal1 to avoid pi
n access issues on buffers and gates in the tree".what is the reason for this?
37.what and how negative clock uncertainity ?
38.local skew take less time compared to global skew run time why?
39.why arent we declaring max fanout ,max load cap ?(in common_cts_settings)?
40.default max buffer level is 20,what factors we need to consider if we want to
change it?
41.after cts and getting good clock tree,if there is still congestion,then can w
e go for manual moment of std cells to clear cogestion?is it good practise to us
e manual moent for congestion?
42.how to calculate clock latency of a generated clock?
43what is ideal clock latency of a generated clock?
44.how to reduce ceongstion after cts?
45.once placement is done ,how do we fix the transition violations and cap viola
tions?
46.from which library are antenna diodes being fetched?
47.for delay cells ,the input capacitance is more in fast process compared to sl
ow process,how is it related with pvt?

48.scan clk and sys clk are sharing same clock path ,what is the need for buildi
ng clock trees for both the clocks?
49.after clock opt clock psyn
clock opt - warning clock network may not be up to date since only 95.38
percentage clock
nets re routed
clock opt - warning clock network may not be up to date since only 98.33
percentage clock
nets re routed
what is the meaning of this %routing differences?what factors effect the clk ne
t routing to particular percentage only?
50.in clock_opt_psyn we are inseting port protection diodes?what is the reason f
or adding them here?
51.is skew_opt used intiming closure or after cts?
52.why are filler cells in size 1,2,4,6 not odd multiples 3,5,7?
53.hwo to fix errors which come during sanity checks ?explain each?
54.how to reduce congestion when in floor plan stage?
55.which and how did errors u fixed in drc,lvs?extra drc,lvs errors u get in 28
nm?
56.diference in placement,placement optimization?
57.will multi cycle path caus echange in frequncy of design ?explain?
58.expalin how u do timing between asynchronous clocks?
59.after routing how will u fix setup (use focal opt):
60.useful skew?what checks u do?
61.if two nets change in same direction?what happes in with voltage level?
62.which is better for clocks?shielding or spacing?
63.what are isolation cells?
64.what cheks after placement?

inputs to
grep
sed -i "s/oldname/newname/g"*