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STA Basic Commands and Timing Report Analysis

Static timing analysis (STA) is used to validate the timing performance of a design by checking all possible signal paths for timing violations. STA breaks the design down into timing paths consisting of startpoints, combinational logic, and endpoints. It then calculates the delay along each path and checks if the delays meet timing constraints. STA has advantages of speed and handling full chips compared to dynamic timing analysis, but it can be more pessimistic and report false paths. STA tools take as inputs the gate-level Verilog, constraints, extracted parasitic information, and library models.

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366 views

STA Basic Commands and Timing Report Analysis

Static timing analysis (STA) is used to validate the timing performance of a design by checking all possible signal paths for timing violations. STA breaks the design down into timing paths consisting of startpoints, combinational logic, and endpoints. It then calculates the delay along each path and checks if the delays meet timing constraints. STA has advantages of speed and handling full chips compared to dynamic timing analysis, but it can be more pessimistic and report false paths. STA tools take as inputs the gate-level Verilog, constraints, extracted parasitic information, and library models.

Uploaded by

santhosh216eee
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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STA Basic Commands and Timing Report

Analysis

-Govind B
Agenda:
• What is STA
• Difference between DTA & STA
• STA Commands & Flow Chart
• How Does STA Work
• STA Timing Report Structure & Analysis
• Setup and Hold Violations Analysis
What is STA
Static timing analysis (STA) is a method of validating the timing
performance of a design by checking all possible paths for timing
violations.

The static timing analyzer will report the following delays (or it can do
following analysis):

➢ Register to Register delays


➢ Setup times of all external synchronous inputs
➢ Clock to Output delays
➢ Pin to Pin combinational delays
➢ Different Analysis Modes-Best, Worst, Typical, On Chip Variation (OCV)
➢ Data to Data Checks

➢ and many more......!!


DTA and STA

Dynamic Timing Analysis Static Timing Analysis


Checks the functionality of the design Checks the static delay requirements of the design

SPICE Simulation based Formula based


Highly Accurate More pessimistic, Critical path analysis
Very Slow Runtime Fast Runtime
Applicable at IP-Block Level Applicable at Full-Chip/SOC Level
Tools: HSPICE, Eldo Tools: Prime Time(PT), PT- SI, Tempus, ETS
Inputs Files: Spice models, Circuit file, SPF/DSPF Input Files: Verilog, SPEF, SDF, Liberty file(timing (.lib))
STA I/O:
STA
Commands
and Flow:
STA Commands Example

#Include all libraries – technology and IP model libraries


set link_path “.db”
#Read all gate-level design files
read_verilog full_chip.v
#Read libraries and link the design
link_design FULL_CHIP
#Read the SDF
read_sdf –analysis_type bewc –max_type sdf_max –min_type sdf_min
#Do all sort of reporting
report_design
report_clock
report_annotated_delay
report_annotated_check
check_timing
etc….
Command ARGs Purpose
report_timing -num_paths <integer> the number of paths to report
-min the min path
-max the max path
-rise the rising endpoint
-fall the falling endpoint

report_tns report the total negative slack


report_wns report the worst negative slack

report_slew -pin name the name of a pin


-min the min transition time
-max the max transition time
-rise the transition time at the rising edge
-fall the transition time at the falling edge
Command ARGs Purpose
report_slack -pin name the name of a pin
-min the min slack time
-max the max slack time
-rise the slack time at the rising edge
-fall the slack time at the falling edge

set_at -pin name the name of the input port pin


set_rat
-delay the arrival time value
-min the min arrival time
-max the max arrival time
-rise the arrival time at the rising edge
-fall the arrival time at the falling edge
How Does STA Work?
When performing timing analysis, STA first
breaks down the design into timing paths. Each
timing path consists of the following elements:

Startpoint. The start of a timing path where


data is launched by a clock edge or where the
data must be available at a specific time. Every
startpoint must be either an input port or a
register clock pin.

Combinational logic network. Elements that


have no memory or internal state.
Combinational logic can contain AND, OR, XOR,
and inverter elements, but cannot contain flip-
flops, latches, registers, or RAM.

Endpoint. The end of a timing path where data


is captured by a clock edge or where the data
must be available at a specific time. Every
endpoint must be either a register data input
pin or an output port.
The following figure shows the timing paths in
a simple design example:
MULTIPLE PATHS THROUGH COMBINATIONAL LOGIC
What Effects the Circuit Timing?

➢Length of Wire
➢R and C of wire
➢Logic depth of the path
➢Size of the Transistor
➢Process – P
➢Voltage – V
➢Temperature - T
Timing report :: report_timing
The Header

➢ Start point:- The start of a timing path where data is launched by a clock edge. Every startpoint must be either an input port or a register
clock pin.
➢ End point:- The end of a timing path where data is captured by a clock edge. Every endpoint must be either a register data input pin or an
output port
➢ Path group:- which tells for which timing path it belongs to.
➢ Path Type:- here it is Max which states Setup and If it was min then it is Hold
Data Arrival Section

The time it takes for the data to arrive at the destination register input The time it takes for the
data to arrive at the destination register input
Data Required Section

The time it takes for the clock to arrive at the destination register.
Slack

Time Difference between the RT- AT


Setup Violation (Max Analysis)
Hold Violations (Min Analysis)
Summary:

STA consists of three major steps:


• Break down the design into timing paths (R-R, I-R,I-O & R-O).
• Delay of each path is calculated.
• All path delays are checked against timing constraints to see if it is met.
STA advantage
• Speed
• Capacity to handling full chip
• Exhaustive timing coverage
• Vectors are not required
STA disadvantage
• It is pessimistic
• Reports false paths
Flow Inputs:
• Gate-level Verilog.
• Constraints (SDC)
• Extracted nets (SPEF)
• Libraries (liberty format - .lib)
Thank You

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