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    Cortex-M3/M4 Architecture

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    suhaskakade0075745
    The document summarizes the Cortex-M3/M4 architecture by describing its operation modes and states, registers, and special registers. It discusses the thread and handler modes as well as privileged and unprivileged states in thread mode. It also covers the debug state. The document then describes the general purpose registers, stack pointers, link register, and program counter. It discusses the special registers including the program status registers, interrupt mask registers, and control register for setting privilege levels and stack pointers. Finally, it briefly mentions the floating point registers and status/control register.

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    Cortex-M3/M4 Architecture

    Uploaded by

    suhaskakade0075745
    42 views37 pages
    The document summarizes the Cortex-M3/M4 architecture by describing its operation modes and states, registers, and special registers. It discusses the thread and handler modes as well as privileged and unprivileged states in thread mode. It also covers the debug state. The document then describes the general purpose registers, stack pointers, link register, and program counter. It discusses the special registers including the program status registers, interrupt mask registers, and control register for setting privilege levels and stack pointers. Finally, it briefly mentions the floating point registers and status/control register.

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    The document summarizes the Cortex-M3/M4 architecture by describing its operation modes and states, registers, and special registers. It discusses the thread and handler modes as well as privileged and unprivileged states in thread mode. It also covers the debug state. The document then describes the general purpose registers, stack pointers, link register, and program counter. It discusses the special registers including the program status registers, interrupt mask registers, and control register for setting privilege levels and stack pointers. Finally, it briefly mentions the floating point registers and status/control register.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    42 views37 pages

    Cortex-M3/M4 Architecture

    Uploaded by

    suhaskakade0075745
    The document summarizes the Cortex-M3/M4 architecture by describing its operation modes and states, registers, and special registers. It discusses the thread and handler modes as well as privileged and unprivileged states in thread mode. It also covers the debug state. The document then describes the general purpose registers, stack pointers, link register, and program counter. It discusses the special registers including the program status registers, interrupt mask registers, and control register for setting privilege levels and stack pointers. Finally, it briefly mentions the floating point registers and status/control register.

    Copyright:

    © All Rights Reserved
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    of 37

    Cortex-M3/M4 Architecture

    Programmer’s Model
    • Operation Modes and States
    • Registers
    • Special Registers
    • Floating Point Registers
    Operation Modes and States
    • Two Modes
    – Thread and Handler

    • Two States (Thread Mode only)


    • Privileged and Unprivileged

    • Debug State
    – Processor stops executing instructions
    – Triggered by debug event of request
    Operation Mode/State Transition
    Simple Applications
    Registers
    • R0 through R15 and a number of special registers.
    • Some of the 16-bit Thumb instructions can only
    access R0 through R7 (low registers), whereas 32-
    bit Thumb-2 instructions can access all these
    registers.
    • Special registers have predefined functions and
    can only be accessed by special register access
    instructions.
    • The reset value of R0 to r12 is unpredictable
    Stack Pointer R13
    • Two SPs – MSP and PSP (SP_main and SP_process
    as specified in ARM documentation)
    • Referring to R13 gives access to current SP.
    • The other SP can be accessed by using special
    instructions – MSR, MRS
    • MSP: This is the default SP; it is used by the OS
    kernel, exception handlers, and all application
    codes that require privileged access.
    • PSP: This is used by the base-level application
    code (when not running an exception handler).
    Link Register R14
    • LR is used to store the return program counter (PC) when a subroutine or
    function is called—for example, when you’re using the branch and link (BL)
    instruction:

    main ; Main program


    ...
    BL function1 ; Call function1 using Branch with Link
    instruction.
    ; PC = function1 and
    ; LR = the next instruction in main
    ...
    function1
    ... ; Program code for function 1
    BX LR ; Return

    • Despite the fact that bit 0 of the PC is always 0, the LR bit 0 is readable and
    writable.
    – This is because in the Thumb instruction set, bit 0 is often used to indicate ARM/Thumb
    states.
    – To allow the Thumb-2 program for the Cortex-M3/M4 to work with other ARM
    processors that support the Thumb-2 technology, this least significant bit (LSB) is
    writable and readable.
    Program Counter R15
    • Because of the pipelined nature of the Cortex-M3 processor, when
    you read this register, you will find that the value is different than
    the location of the executing instruction, normally by 4. For
    example:
    0x1000 : MOV R0, PC ; R0 = 0x1004
    • In other instructions like literal load the effective value of PC might
    not be instruction address plus 4 due to alignment in address
    calculation.
    • But the PC value is still at least 2 bytes ahead of the instruction
    address during execution.
    • Writing to the PC will cause a branch.
    – Because an instruction address must be half word aligned, the LSB (bit
    0) of the PC read value is always 0.
    – However, in branching, either by writing to PC or using branch
    instructions, the LSB of the target address should be set to 1 because
    it is used to indicate the Thumb state operations.
    – If it is 0, it can imply trying to switch to the ARM state and will result in
    a fault exception in the Cortex-M3.
    Register Naming Conventions
    Special Registers
    • Program Status registers (PSRs)
    • Interrupt Mask registers (PRIMASK,
    FAULTMASK, and BASEPRI)
    • Control register (CONTROL)
    • Accessing special registers:
    – MRS <reg>, <special_reg> ; Read special register
    – MSR <special_reg>, <reg> ; write to special register
    Program Status Registers
    • Divided in three status registers
    – Application Program Status register (APSR) – RW
    – Interrupt Program Status register (IPSR) – RO
    – Execution Program Status register (EPSR) – RO
    • Can be accessed together (xPSR) or separately
    • Examples
    – MRS r0, APSR ; Read Flag state into R0
    – MRS r0, IPSR ; Read Exception/Interrupt state
    – MRS r0, EPSR ; Read Execution state
    – MSR APSR, r0 ; Write Flag state
    APSR, IPSR and EPSR

    xPSR
    Bit Fields in PSR
    Accessing xPSR
    • In ARM assembler, when accessing xPSR (all
    three PSRs as one), the symbol PSR is used:
    – MRS r0, PSR ; Read the combined program status word
    – MSR PSR, r0 ; Write combined program state word

    • xPSR is significantly different as compared to


    CSPR in ARM7 ( Find out the differences?)
    APSR
    • Status flags for integer operations (N-Z-C-V
    bits)
    • Status flag for saturated arithmetic (Q bit)
    • Status flag for SIMD operations (GE bits)
    N-Z-C-V Bits
    • Affected by
    – Most 16 bit instructions
    – 32 bit instructions with ‘S’ qualifier
    – Some instructions affect only N and Z flag e.g. MULS
    N-Z-C-V Bits Examples
    Q Bit
    • Set in case of overflow or underflow due to finite word
    size of destination register/s
    • Instructions for saturation arithmetic
    – Usually start with Q e.g. QADD16
    GE Bits
    • 4 bit field
    • Updated by number of SIMD instructions
    • Each bit represents positive or overflow for
    each byte
    • Used by SEL instructions which multiplexes
    the byte values from two source registers
    GE Bits (contd..)
    GE Bits (contd..)
    PRIMASK, FAULTMASK, and BASEPRI
    Registers
    • Used to disable exceptions
    • The PRIMASK and BASEPRI registers are useful
    for temporarily disabling interrupts in timing-
    critical tasks.
    • An OS could use FAULTMASK to temporarily
    disable fault handling when a task has
    crashed.
    PRIMASK, FAULTMASK, and
    BASEPRI Registers (contd..)
    PRIMASK, FAULTMASK, BASEPRI
    Functionality
    • PRIMASK
    – Blocks all exceptions except NMI and HardFault
    – Disables all interrupts for a time critical process
    • FAULTMASK
    – Additionally it also blocks HardFault
    – Used by fault handler to suppress triggering of further faults
    • BASEPRI
    – Blocks exceptions that have same of lower priority level
    – Width is implementation dependent
    – When 0, it is disabled
    Accessing Interrupt Mask Registers
    using Device Driver Libraries
    • Cortex Microcontroller Software Interface Standard
    (CMSIS)
    • x = __get_BASEPRI() ; // Read BASEPRI register
    • x = __get_PRIMARK() ; // Read PRIMASK register
    • x = __get_FAULTMASK(); // Read FAULTMASK register
    • __set_BASEPRI(x) ; // Set new value for BASEPRI
    • __set_PRIMASK(x) ; // Set new value for PRIMASK
    • __set_FAULTMASK(x) ; // Set new value for
    FAULTMASK
    • __disable_irq() ; // Clear PRIMASK, enable IRQ
    • __enable_irq() ; // Set PRIMASK, disable IRQ
    Accessing Interrupt Mask Registers in
    Assembly Language
    • The PRIMASK, FAULTMASK, and BASEPRI registers
    cannot be set in the user access level.

    • MRS r0, BASEPRI ; Read BASEPRI register into R0


    • MRS r0, PRIMASK ; Read PRIMASK register into R0
    • MRS r0, FAULTMASK ; Read FAULTMASK register into R0
    • MSR BASEPRI, r0 ; Write R0 into BASEPRI register
    • MSR PRIMASK, r0 ; Write R0 into PRIMASK register
    • MSR FAULTMASK, r0 ; Write R0 into FAULTMASK register
    CPS Instructions
    • CPSIE i ; Enable interrupt (clear PRIMASK)
    • CPSID i ; Disable interrupt (set PRIMASK)
    • CPSIE f ; Enable interrupt (clear FAULTMASK)
    • CPSID f ; Disable interrupt (set FAULTMASK)
    The Control Register
    • Used to define the privilege level and the SP
    selection
    Bit Fields in Control Register
    Stack Pointer Selection
    Accessing the Control Register
    • In ‘C’ language:
    – x = __get_CONTROL() ; // Read the current value of CONTROL
    – __set_CONTROL(x) ; // Set the CONTROL value to x

    • In assembly language:
    – MRS r0, CONTROL ; Read CONTROL register into R0
    – MSR CONTROL, r0 ; Write R0 into CONTROL register
    Switching Between Privileged and
    UnPrivileged Thread Modes
    Simple Applications
    Determining Execution Level
    int in_privileged(void)
    {
    if (__get_IPSR() != 0) return 1; // True
    else
    if ((__get_CONTROL() & 0x1)==0) return 1; // True
    else return 0; // False
    }
    Floating Point Registers
    • Data Processing:
    – S0 to S31 or D0 to D15
    • Floating Point Status and Control Register (FPSCR),
    used to
    – Define some of the floating point operation behaviors
    – Provide status information about the floating point
    operation results
    • Additional memory mapped registers such as
    Coprocessor Access Control Register to enable or
    disable floating point unit.
    Floating Point Registers (contd..)

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