UNIT-V

ARM Microcontroller

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 INTRODUCTION:
The ARM was originally developed at Acorn Computers Limited
of Cambridge, England, between 1983 and 1985.
It was the first RISC microprocessor developed for commercial
use and has some significant differences from subsequent RISC
architectures.
The ARM is supported by a toolkit which includes an instruction
set emulator for hardware modelling and software testing and
benchmarking, an assembler, C and C++ compilers, a linker and
a symbolic debugger.

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FEATURES OF ARM PROCESSORS
The ARM processors are based on RISC architectures are very low
power consumption, Implementation size, performance remain
the key features in the development of the ARM devices.
A large uniform register file.
A load/store architecture, where data-processing operations only
operate on register contents, not directly on memory contents.
Control over both the Arithmetic Logic Unit (ALU) and shifter in
most data-processing instructions to maximize the use of an ALU
and a shifter.
Auto-increment and auto-decrement addressing modes to
optimize program loops.
Load and Store Multiple instructions to maximize data
throughput.
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ARCHITECTURE OF ARM PROCESSORS:
The ARM processor consists of
Arithmetic Logic Unit (32-bit)
One Booth multiplier(32-bit)
One Barrel shifter
One Control unit

In addition to this the ARM also consists of a Program status

register of 32 bits.
Some special registers like the instruction register, memory
data read and write register and memory address register ,one
Priority encoder which is used in the multiple load and store
instruction.

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ARM Registers:
ARM has a total of 37 registers.
In which - 31 are general-purpose registers of 32-bits, and six
status registers .
Among the 31 general purpose registers only 16 registers are
available to the user.
The remaining 15 registers are used to speed up exception
processing. there are two program status registers: CPSR and SPSR
(the current and saved program status registers, respectively.

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 R13 acts as a stack pointer register
R14 acts as a link register and
R15 acts as a program counter register.

Register r13 is the sp register ,and it is used to store the address

of the stack top. R13 is used by the PUSH and POP instructions

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 Register 14 is the Link Register (LR). This register holds the
address of the next instruction after a Branch and Link (BL or
BLX) instruction, which is the instruction used to make a
subroutine call. It is also used for return address information on
entry to exception modes.
Register 15 is the Program Counter (PC). It can be used in most
instructions as a pointer to the instruction which is two
instructions after the instruction being executed.
The remaining 13 registers have no special hardware purpose.

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 CPSR : The ARM core uses the CPSR register to monitor and
control internal operations. The CPSR is a dedicated 32-bit
register and resides in the register file.

The ARM7 processor has a three stage pipelining architecture

namely Fetch , Decode and Execute. And the ARM 9 has five stage
Pipe line architecture.
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 Exceptions, Interrupts, and the Vector Table :
Exceptions are generated by internal and external sources to cause
the ARM processor to handle an event, such as an externally
generated interrupt or an attempt to execute an Undefined
instruction.
More than one exception can arise at the same time.
The ARM architecture supports seven types of exceptions.
i. Reset
ii. Undefined Instruction
iii. Software Interrupt(SWI)
iv. Pre-fetch abort(Instruction Fetch memory fault)
v. Data abort (Data access memory fault)
vi. IRQ(normal Interrupt)
vii. FIQ (Fast Interrupt request).
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 ARM Year of Architecture Pipeline Operational Multiplier MIPS
Family Release Frequency

ARM7 1995 Von Neumann 3 stage 80 M.Hz 8x32 0.97

ARM9 1997 Harvard 5 stage 150M.Hz 8x32 1.1

ARM10 1999 Harvard 6 stage 260M.Hz 16x32 1.3

ARM11 2003 Harvard 8 stage 335M.Hz 16x32 1.2

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 ARM INSTRUCTION SET
ARM instructions process data held in registers and only access
memory with load and store instructions. ARM instructions
commonly take two or three operands.
For example ,the ADD instruction adds the two values stored in
registers r1 and r2 (the source registers). It stores the result to
register r3 (the destination register). ADD r3, r1, r2
ARM instructions are classified into
data processing instructions
branch instructions
load-store instructions
software interrupt instruction
program status register instructions.

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Data Processing Instructions :
The data processing instructions manipulate data within
registers. They are move instructions, Arithmetic instructions,
logical instructions, comparison instructions, and multiply
instructions.
Arithmetic Instructions :
SUB r0, r1, r2 ; This subtract instruction subtracts a value stored in
register r2 from a value stored in register r1. The result is stored in
register r0.
RSB r0, r1, #0 ; This reverse subtract instruction (RSB) subtracts
r1 from the constant value #0, writing. the result to r0.You can
use this instruction to negate numbers.

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 Logical Instructions :
These Logical instructions perform bitwise logical operations on the
two source registers.

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Branch Instructions:
A branch instruction changes the normal flow of execution of a
main program or is used to call a subroutine routine.
This type of instruction allows programs to have subroutines, if-
then-else structures, and loops.
The change of execution flow forces the program counter pc to
point to a new address.

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 Load-Store Instructions :
Load-store instructions transfer data between memory and processor
registers.
There are three types of load-store instructions:
Single-register transfer
Multiple-register transfer, and
Swap.

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 Single-Register Transfer :
These instructions are used for moving a single data item in and
out of a register.
Ex1: STR r0, [r1] ; = STR r0, [r1, #0] ; store the contents of register
r0 to the memory address pointed to by register r1.
Ex2 : LDR r0, [r1] ; = LDR r0, [r1, #0] ; load register r0 with the
contents of the memory address pointed to by register r1.
Multiple-Register Transfer :
Load-store multiple instructions can transfer multiple registers
between memory and the processor in a single instruction.
Swap Instruction :
The Swap instruction is a special case of a load-store instruction.
It swaps (Similar to exchange) the contents of memory with the
contents of a register.

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 Software Interrupt Instruction :
A software interrupt instruction (SWI) is used to generate a
software interrupt exception, which can be used to call operating system
routines. When the processor executes an SWI instruction, it sets the
program counter pc to the offset 0x8 in the vector table.
Program Status Register Instructions :
There are two instructions available to directly control a program
status register (PSR). The MRS instruction transfers the contents of
either the CPSR or SPSR into a register. Similarly the MSR instruction
transfers the contents of a register into the CPSR or SPSR .These
instructions together are used to read and write the CPSR and SPSR.
MRS : copy program status register to a general-purpose register , Rd=
PSR
MSR : move a general-purpose register to a program status register,
PSR[field]=Rm
MSR : move an immediate value to a program status register,
PSR[field]=immediate
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 Introduction to Thumb instruction set :
Thumb encodes a subset of the 32-bit ARM instructions into
a 16-bit instruction set space. Since Thumb has higher
performance than ARM on a processor with a 16-bit data bus, but
lower performance than ARM on a 32-bit data bus, use Thumb for
memory-constrained systems.
Thumb has higher code density the space taken up in
memory by an executable program than ARM. For memory-
constrained embedded systems, for example, mobile phones and
PDAs, code density is very important. Cost pressures also limit
memory size, width, and speed.
A Thumb implementation of the same code takes up around
30% less memory than the equivalent ARM implementation.

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