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Module 2 Chapter 3

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7 views

Module 2 Chapter 3

Uploaded by

Harsha
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter-3

INTRODUCTION TO THE ARM INSTRUCTION SET


The Instruction Set Architecture is fundamental for building fast, efficient computers that optimize
memory and processing resources. It specifies the following supported capabilities:

 instructions
 data types
 processor registers
 main memory hardware
 input/output model
 addressing modes

Programmers and system engineers rely on the ISA for guidance on how to program various
activities.

Instruction sets work with other important parts of a computer, such as compilers and interpreters.
Those components translate high-level programming code into machine code that the processor
can understand.

Think of the ISA as a programmer's gateway into the inner workings of a computer.

Opcode and Operand


Each assembly language statement is split into an opcode and an operand. The opcode is
the instruction that is executed by the CPU and the operand is the data or memory location used to
execute that instruction.
ARMv7 Instruction set Architecture.
 Different ARM architecture revisions support different instructions. However, new
revisions are backwardly compatible.
 The ARMv7 architecture is a 32-bit processor architecture.
 It is also a load/store architecture, meaning that data-processing instructions operate only
on values in general purpose registers.
 Only load and store instructions access memory.
 General purpose registers are also 32 bits.
 A word, we mean 32 bits. A double-word is therefore 64 bits and a half-word is 16 bits
wide.
Classes of Instructions
1. Data Processing Ins
2. Branch Ins
3. Load – Store Ins
4. Software Interrupt Ins
5. Program Status Register Ins

3.1 Data Processing Instructions


These are the fundamental arithmetic and logical operations of the processor and operate on values in
the general-purpose registers, or a register and an immediate value.
Multiply and divide instructions can be considered special cases of these instructions.
Data processing instructions mostly use one destination register and two source operands.
The general format can be considered to be the instruction, followed by the operands, as follows:

The data processing operations include:


 Move Instructions
 Arithmetic Instructions
 Logical Instructions
 Comparison Instructions
 Multiply Instructions

3.1.1 Move Instructions


It is the simplest ARM Instructions.
It copies N into a destination register Rd, where N is a register or immediate value.
Used to initialize a value or to transfer data between registers.
Example

3.1.2 Barrel Shifter


The barrel shifter is a functional unit which can be used in a number of different circumstances.
Barrel shifter along with ALU is shown here.

It provides five types of shifts and rotates which can be applied to Operand2. (These are not operations
themselves in ARM mode.)
Certain ARM instructions such as MUL, CLZ and QADD cannot use the barrel shifter.
Pre-processing or shift occurs within the cycle time of the instruction. This is useful for multiplying
or dividing a constant by a power of 2.
Instructions that uses Barrel shifter is illustrated with examples.
3.1.3 Arithmetic Instruction
Used to carry out addition and subtraction of 32 bit signed and unsigned values.

Simple subtract instruction

Reverse Subtract Instruction


3.1.4 Using the Barrel shifter with Arithmetic Instructions

3.1.5 Logical Instruction


Bitwise logical operations can be performed using this instructions
3.1.6 Comparison Instructions
Comparison instructions are used to compare or test a register. These instructions
compare and update the cpsr register. Hence, S suffix instructions are not there for these
instructions.
CMP is actually a subtract instruction but the results are simply discarded. However, the cpsr
flags are modified.
TST is a logical AND operation.
TEQ is logical Exclusive OR operation.
In all the cases, only the cpsr register is modified no other registers are changed. Results are
simply discarded.
3.1.7 Multiply Instructions
Multiply instructions multiply the contents of a pair of registers
The long multiply instruction results in 64 bit value. In such cases, RdLo holds the lower 32 bit
of the 64 bit result, and RdHi holds the higher 32 bit of the 64 bit result. So, we must specify two
registers as destination to hold the results.

3.2 Branch Instructions


Branch instruction changes the flow of execution or call a subroutine.
3.3 Load Store Instructions
These instructions are used to transfer data between memory and processor registers.
Three types are there.
 Single-register transfer,
 Multiple Register Transfer,
 Swap
3.3.1 Single-Register Transfer
These instructions are used to move a single data item in and out of a register.
With these, we can able to transfer signed or unsigned 32 bit / 16 bit data.
3.4 Software Interrupt Instructions (SWI)
It causes a software Interrupt exceptions. It provides a gateway to call the operating system
routines.
When the program executes the SWI ins, it sets the content of the program counter (pc) to an
offset value 0x8.
Also, it forces the proccessor mode to SVC.
Each SWI has anassociated SWI number.
3.5 Program Status Register Instructions
The ARM instruction set provides two instructions namely MRS and MSR to directly control the
psr.
3.5.1 Co-Processor Instructions
These instructions are used to extend the Instruction Set.
A co-processor can either provide additional computational capability or to control the
ma=emory management.
The Coprocessor instruction can be of
Data processing, register ttransfering, memory transfering. However,. These instructions are only
used by the cores with a coprocessor.

3.6 Loading Constants


Since ARM instructions are 32 bits in size, they obviously cannot specify a general 32 bit
constant.
So, to move a 32 bit constant, two pseudoinstructions are employed.

3.7 Programs
to find the sum of first 10 numbers
Find the factorial of a number
Result is stored in register R0.

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