Module 1 –Part 2

 Stack:
 Advantages: Simple Model of expression evaluation (reverse polish). Short
instructions.
 Disadvantages: A stack can't be randomly accessed This makes it hard to
generate efficient code. The stack itself is accessed every operation and
becomes a bottleneck.
 Accumulator:
 Advantages: Short instructions.
 Disadvantages: The accumulator is only temporary storage so memory
traffic is the highest for this approach.
 GPR:
 Advantages: Makes code generation easy. Data can be stored for long
periods in registers.
 Disadvantages: All operands must be named leading to longer
instructions.
Why GPR based CPU?

 Earlier CPUs were of the first 2 types but in the last 15

years all CPUs made are GPR processors.
 The 2 major reasons are that registers are faster than
memory, the more data that can be kept internally in the
CPU the faster the program will run.
 The other reason is that registers are easier for a
compiler to use.
 As we mentioned before most modern CPUs are of the GPR
(General Purpose Register) type. A few examples of such CPUs are
the IBM 360, DEC VAX, Intel 80x86 and Motorola 68xxx.
 But while these CPUS were clearly better than previous stack and
accumulator based CPUs they were still lacking in several areas:
 Instructions were of varying length from 1 byte to 6-8 bytes. This
causes problems with the pre-fetching and pipelining of
instructions.
 •ALU (Arithmetic Logical Unit) instructions could have operands
that were memory locations. Because the number of cycles it takes
to access memory varies so does the whole instruction. This isn't
good for compiler writers, pipelining and multiple issue.
 Most ALU instructions had only 2 operands where one of the
operands is also the destination. This means this operand is
destroyed during the operation or it must be saved before
somewhere.
 The ISA defines the functions performed by the CPU. The instruction set
is the programmer's means of controlling the CPU.
 Thus programmer requirements must be considered in designing the
instruction set.
 Most important and fundamental design issues:
 Operation repertoire : How many and which operations to provide, and
how complex operations should be.
 Data Types : The various type of data upon which operations are
performed.
 Instruction format : Instruction length (in bits), number of addresses,
size of various fields and so on.
 Registers : Number of CPU registers that can be referenced by
instructions and their use.
 Addressing : The mode or modes by which the address of an operand is
specified.
 Each instruction must contain following information required by the CPU
for execution.
 Operation Code:
 Specifies the operation to be performed (e.g., add, move etc.). The
operation is specified by a binary code, know as the operation code or
opcode.
 Source operand reference:
 The operation may involve one or more source operands; that is,
operands that are inputs for the operation.
 Result operand reference:
 The operation may produce a result.
 Next instruction reference:
 This tells the CPU where to fetch the next instruction after the execution
of this instruction is complete.
 Operation Code:
– Most basic part of instruction is its operation part aka
operation code.
– Operation code defines operations such as ADD, SHIFT etc.
– No. Of bits in Opcode depends on available operations for
that particular computer
– Opcode with n-bits can specify 2^n instructions.
 Source and result operands can be in one of the three
areas:
– main or virtual memory,
– CPU register or
– I/O device.
1. Data Processing:
 • Arithmetic and Logic instructions Arithmetic instructions provide
computational capabilities for processing numeric data. Logic (Boolean)
instructions operate on the bits of a word as bits rather than as numbers. Logic
instructions thus provide capabilities for processing any other type of data.
There operations are performed primarily on data in CPU registers.
2. Data Storage:
 • Memory instructions Memory instructions are used for moving data between
memory and CPU registers.
3. Data Movement:
 • I/O instructions I/O instructions are needed to transfer program and data into
memory from storage device or input device and the results of computation
back to the user.
4. Control:
 • Test and branch instructions: Test instructions are used to test the value of a
data word or the status of a computation. Branch instructions are then used to
branch to a different set of instructions depending on the decision made.
 Three-Address Instructions
-ADD R1, R2, R3: R1 ← R2 + R3
 Two-Address Instructions
- ADD R1, R2 :R1 ← R1 + R2
 One-Address Instructions
- ADD M :AC ← AC + M[AR]
 Zero-Address Instructions
-ADD :TOS ← TOS + (TOS – 1)
Instruction Format
 A 32-bit Instruction Example
 • Suppose we have an ISA with 32-bit instructions only.
– Fixed size instructions make the decoding easier.
 • Some instruction encoding examples are shown.
– Assume that there are 32 registers R0 to R31, all of 32-bits.
– 5-bits are required to specify a register.
 Example-Instruction format
What are Addressing Modes?
• They specify the mechanism by which the operand data can be
located.
• Some ISA’s are quite complex and supports many addressing
modes.
• ISA’s based on load-store architecture are usually simple and
support very limited number of addressing modes.
• Various addressing modes exist:
– Immediate, Direct, Indirect, Register, Register Indirect, Indexed,
Stack, Relative, Autoincrement, Autodecrement, Based, etc.
– Not all processors support all addressing modes.
 The operand is part of the instruction itself.
– No memory reference is required to access the
operand.
– Fast but limited range (because a limited number of
bits are provided to specify the immediate data).
 • Examples:
– ADD #25 // ACC = ACC + 25
– ADDI R1,R2,42 // R1 = R2 + 42
 The instruction contains a field that holds the memory
address of the operand.
 • Examples:
– ADD R1,20A6H // R1 = R1 + Mem[20A6]
 • Single memory access is required to access the
operand.
– No additional calculations required to determine the
operand address.
– Limited address space (as number of bits is limited, say,
16 bits).
Direct Addressing
 The instruction contains a field that holds the memory
address, which in turn holds the memory address of the
operand.
 • Two memory accesses are required to get the operand
value.
 • Slower but can access large address space.
 – Not limited by the number of bits in operand address
like direct addressing.
 They permit the same code to be used to operate on
different data
 • Examples:
 – ADD R1,(20A6H) // R1 = R1 + (Mem[20A6])
Indirect Addressing
 The operand is held in a register, and the instruction
specifies the register number.
 – Very few number of bits needed, as the number of
registers is limited.
 – Faster execution, since no memory access is required
for getting the operand.
 • Modern load-store architectures support large number
of registers.
 • Examples:
– ADD R1,R2,R3 // R1 = R2 + R3
– MOV R2,R5 // R2 = R5
Register Addressing
 The instruction specifies a register, and the register
holds the memory address where the operand is stored.
– Can access large address space.
– One fewer memory access as compared to
indirect addressing.
 • Example:
– ADD R1,(R5) // PC = R1 + Mem[R5]
Register indirect Addressing
 For relative addressing, the implicitly referenced register is the
program counter (PC). That is, the current instruction address
is added to the address field to produce the EA. Thus, the
effective address is a displacement relative to the address of the
instruction.
 Base-Register Addressing:
 The reference register contains a memory address, and the
address field contains a displacement from that address. The
register reference may be explicit or implicit.
 In some implementation, a single segment/base register is
employed and is used implicitly. In others, the programmer may
choose a register to hold the base address of a segment, and the
instruction must reference it explicitly.
 Relative Addressing:
 • For relative addressing, the implicitly referenced register is the program
counter (PC). That is, the current instruction address is added to the address
field to produce the EA. Thus, the effective address is a displacement relative
to the address of the instruction.
 • Base-Register Addressing:
 • The reference register contains a memory address, and the address field
contains a displacement from that address. The register reference may be
explicit or implicit.
 • In some implementation, a single segment/base register is employed and is
used implicitly. In others, the programmer may choose a register to hold the
base address of a segment, and the instruction must reference it explicitly.
 • The instruction specifies an offset of displacement,
which is added to the program counter (PC) to get the
effective address of the operand.
 – Since the number of bits to specify the offset is
limited, the range of relative addressing is also limited.
 – If a 12-bit offset is specified, it can have values
ranging from -2048 to +2047.
Relative Addressing
 Either a special-purpose register, or a general-purpose register,
is used as index register in this addressing mode.
 The instruction specifies an offset of displacement, which is
added to the index register to get the effective address of the
operand.
 Example:
– LOAD R1,1050(R3) // R1 = Mem[1050+R3]
 -Can be used to sequentially access the elements of an array.
 – Offset gives the starting address of the array, and the index
register value specifies the array element to be used.
 Either a special-purpose register, or a general-purpose register,
is used as index register in this addressing mode.
 The instruction specifies an offset of displacement, which is
added to the index register to get the effective address of the
operand.
 Example:
– LOAD R1,1050(R3) // R1 = Mem[1050+R3]
 -Can be used to sequentially access the elements of an array.
 – Offset gives the starting address of the array, and the index
register value specifies the array element to be used.
Relative index Addressing
 Example of indexed addressing

Fig: A list of students’ marks.

Fig:Indexed addressing used in accessing

test scores in the list
Offset is given as a constant
Offset is in the index register

-The Index mode facilitates access to an operand whose location is defined relative to a
reference point within the data structure in which the operand appears.
 Operand is implicitly on top of the stack.
 Used in zero-address machines earlier.
 Examples:
– ADD
– PUSH X
– POP X
 Many processors have a special register called the stack pointer
(SP) that keeps track of the stack-top in memory.
– PUSH, POP, CALL, RET instructions automatically modify SP.
Effective address(EA)
 Base addressing
 – The processor has a special register called the base register or
segment register.
 – All operand addresses generated are added to the base register
to get the final memory address.
 – Allows easy movement of code and data in memory.
 Auto-increment and Auto-decrement
 – First introduced in the PDP-11 computer system.
 – The register holding the operand address is automatically
incremented or decremented after accessing the operand (like
a++ and a-- in C).
 1. Numerical Problem
 The two-word instruction at address 200 and 201 is a "load to AC"
instruction with an address field equal to 500. The first word of
the instruction specifies the operation code and mode, and the
second word specifies the address part. PC has the value 200 for
fetching this instruction. The content of processor register R 1 is
400, and the content of an index register XR is 100. AC receives
the operand after the instruction is executed. The figure lists a
few pertinent addresses and shows the memory content at each
of these addresses.
 Evaluate the EA and operand if the addressing mode of the
instruction is:
1. Direct 2.Immediate 3. Indirect
4. Relative 5. Index mode 6.Register mode 7.Register Indirect
 2. Numerical Problem
 An instruction is stored at location 500 with its address field at
location 501. The address field has the value 300. A processor
register R1 contains the number 100. Evaluate the effective
address if the addressing mode of the instruction is
 1. Immediate 2. Direct 3. Register Indirect
4. Relative 5. Index with R1 as the index register.
What is the Performance?

Plane DC to Paris Speed Passengers passengers X mph

Boeing 747 6.5 hours 610 mph 470 286,700

Concorde 3 hours 1350 mph 132 178,200

Which of the planes has better performance

 The plane with the highest speed is Concorde
 The plane with the largest capacity is Boeing 747
Performance Example

Time of Concorde vs. Boeing 747?

Concord is 1350 mph / 610 mph = 2.2 times faster

Throughput of Concorde vs. Boeing 747 ?

Boeing is 286,700 pmph / 178,200 pmph = 1.6 times faster

Boeing is 1.6 times faster in terms of throughput

Concord is 2.2 times faster in terms of flying time

When discussing processor performance, we will focus primarily on

execution time for a single job - why?
Basic Measurement Metrics
 Comparing Machines
 Metrics
 Execution time
 Throughput
 CPU time
 MIPS – millions of instructions per second
 MFLOPS – millions of floating point operations per second

 Comparing Machines Using Sets of Programs

 Benchmarks
Performance
Most processors execute instructions in a synchronous
manner using a clock that runs at a constant clock rate or
frequency f.
• Clock cycle time C is the reciprocal of the clock rate f:
C=1/f
• The clock rate f depends on two factors:
a) The implementation technology used.
b) The CPU organization used.
• A machine instruction typically consists of a number of
elementary micro-operations that vary in number and
complexity depending on the instruction and the CPU
organization used.
Computer Clock
 A computer clock runs at a constant rate and determines
when events take placed in hardware.
Clk

clock period

 The clock cycle time is the amount of time for one

clock period to elapse (e.g. 5 ns).
 The clock rate is the inverse of the clock cycle time.
 For example, if a computer has a clock cycle time of 5
ns, the clock rate is:
1
---------------------- = 200 MHz
5 x 10-9 sec
A micro-operation is an elementary hardware operation that
can be carried out in one clock cycle.
– Register transfer operations, arithmetic and logic
operations, etc.
• Thus a single machine instruction may take one or more
CPU cycles to complete.
– We can characterize an instruction by Cycles Per Instruction
(CPI).
• Average CPI of a program:
– Average CPI of all instructions executed in the program on a
given processor.
– Different instructions can have different CPIs.
 How Many Cycles are Required for a Program?

 Could assume that # of cycles = # of instructions

2nd instruction
3rd instruction
1st instruction

4th
5th
6th

...
time

 This assumption is incorrect, different instructions

take different amounts of time on different
machines.
Different Numbers of Cycles for Different Instructions

time

 Division takes more time than addition

 Floating point operations take longer than integer ones
 Accessing memory takes more time than accessing
registers
Now That We Understand Cycles

 A given program will require

 some number of instructions (machine instructions)
 some number of clock cycles
 some number of seconds

 We have a vocabulary that relates these quantities:

 clock cycle time (seconds per cycle)
 clock rate (cycles per second)
 CPI (cycles per instruction)
 a floating point intensive application might have a higher CPI
Computing CPU Time
 The time to execute a given program can be computed as
CPU time = CPU clock cycles x clock cycle time
 Since clock cycle time and clock rate are reciprocals
CPU time = CPU clock cycles / clock rate
 The number of CPU clock cycles can be determined by
CPU clock cycles = (instructions/program) x (clock cycles/instruction)
= Instruction count x CPI
which gives
CPU time = Instruction count x CPI x clock cycle time
CPU time = Instruction count x CPI / clock rate

 The units for CPU time are

instructions clock cycles seconds
CPU time = x x
program instruction clock cycle
Performance comparison

By Measuring the Execution Times

• One of the easiest methods to make the comparison.
• We measure the execution times of a program on two
machines (A and B), as XTA and XTB.
• Performance can be defined as the reciprocal of
execution time:
PerfA = 1 / XTA
PerfB = 1 / XTB
• We can estimate the speedup of machine A over
machine B as:
Speedup = PerfA / PerfB = XTB / XTA
A tradeoff:
– RISC: increases number of
instructions/program, but decreases CPI and
clock cycle time because the instructions and
hence the implementations are simple.
– CISC: decreases number of
instructions/program, but increases CPI and
clock cycle time because many instructions are
more complex.
An example:
A program is run on three different machines A, B and C
and execution times of 10, 25 and 75 are noted.
– A is 2.5 times faster than B
– A is 7.5 times faster than C
– B is 3.0 times faster than C
Example
A program is running on a machine with the following
parameters:
– Total number of instructions executed = 50,000,000
– Average CPI for the program = 2.7
– CPU clock rate = 2.0 GHz (i.e. C = 0.5 x 10-9 sec)
Example
A program is running on a machine with the following
parameters:
– Total number of instructions executed = 50,000,000
– Average CPI for the program = 2.7
– CPU clock rate = 2.0 GHz (i.e. C = 0.5 x 10-9 sec)

Execution time of the program:

XT = 50,000,000 x 2.7 x 0.5 x 10-9 = 0.0675
sec
CPU Time Example
 Example 1:
 CPU clock rate is 1 MHz
 Program takes 45 million cycles to execute
 What’s the CPU time?

 Example 2:
 CPU clock rate is 500 MHz
 Program takes 45 million cycles to execute
 What’s the CPU time
CPU Time Example
 Example 1:
 CPU clock rate is 1 MHz
 Program takes 45 million cycles to execute
 What’s the CPU time?

45,000,000 * (1 / 1,000,000) = 45 seconds

 Example 2:
 CPU clock rate is 500 MHz
 Program takes 45 million cycles to execute
 What’s the CPU time

45,000,000 * (1 / 500,000,000) = 0.09 seconds

CPI Example
 Suppose we have two implementations of the same
instruction set architecture (ISA).
For some program,
Machine A has a clock cycle time of 10 ns. and a CPI of 2.0
Machine B has a clock cycle time of 20 ns. and a CPI of 1.2

 Which machine is faster for this program, and by how much?

Assume that # of instructions in the program is 1,000,000,000.

CPI Example
 Suppose we have two implementations of the same
instruction set architecture (ISA).
For some program,
Machine A has a clock cycle time of 10 ns. and a CPI of 2.0
Machine B has a clock cycle time of 20 ns. and a CPI of 1.2

 Which machine is faster for this program, and by how much?

Assume that # of instructions in the program is 1,000,000,000.

CPU TimeA = 109 * 2.0 * 10 * 10-9 = 20 seconds
Machine A is faster
CPU TimeB = 109 * 1.2 * 20 * 10-9 = 24 seconds

24
= 1.2 times
20
Instruction Types and CPI
• Consider a program executing on a processor, with n types or
classes of instructions (like, load, store, ALU, branch, etc.).
ICi = number of instructions of type i executed
CPIi = cycles per instruction for type i
• The following expressions follow.
CPI Example

 Example: Let assume that a benchmark has 100

instructions:
25 instructions are loads/stores (each take 2 cycles)
50 instructions are adds (each takes 1 cycle)
25 instructions are square root (each takes 50 cycles)
What is the CPI for this benchmark?
CPI Example

 Example: Let assume that a benchmark has 100

instructions:
25 instructions are loads/stores (each take 2 cycles)
50 instructions are adds (each takes 1 cycle)
25 instructions are square root (each takes 50 cycles)
What is the CPI for this benchmark?

CPI = ((0.25 * 2) + (0.50 * 1) + (0.25 * 50)) = 13.5

Number of Instruction Example
 A compiler designer is trying to decide between two code sequences
for a particular machine. Based on the hardware implementation,
there are three different classes of instructions: Class A, Class B,
and Class C, and they require one, two, and three cycles
(respectively).
The first code sequence has 5 instructions: 2 of A, 1 of B, and 2 of C
The second sequence has 6 instructions: 4 of A, 1 of B, and 1 of C.

 Which sequence will be faster? How much?

 What is the CPI for each sequence?
# of cycles for first code = (2 * 1) + (1 * 2) + (2 * 3) = 10 cycles
# of cycles for second code = (4 * 1) + (1 * 2) + (1 * 3) = 9 cycles
CPI for first code = 10 / 5 = 2
10 / 9 = 1.11 times
CPI for second code = 9 / 6 = 1.5
CPI Example
 Suppose we have two implementations of the same
instruction set architecture (ISA).
For some program,
Machine A has a clock cycle time of 10 ns. and a CPI of 2.0
Machine B has a clock cycle time of 20 ns. and a CPI of 1.2

 Which machine is faster for this program, and by how much?

Assume that # of instructions in the program is 1,000,000,000.

CPU TimeA = 109 * 2.0 * 10 * 10-9 = 20 seconds
Machine A is faster
CPU TimeB = 109 * 1.2 * 20 * 10-9 = 24 seconds

24
= 1.2 times
20
Practice Example
1.Suppose that Machine A execute a program with average CPI of
2.3.Consider another machine B (with same instruction set & complier)
that execute a same program with 20% less instruction and with CPI of
1.7 at 1.2GHz.What should be clock rate of Machine A so that 2
machines have same performance.
MIPS (Million Instructions Per Second)

– Computed as (IC / XT) x 10^-6

– Dependent on instruction set, making it difficult to compare
MIPS of computers with different instruction sets.
– MIPS varies between programs running on the same processor.
– Higher MIPS rating may not mean better performance.
-The MIPS rating is only valid to compare the performance of
two or more processors provided that the following conditions
are satisfied:
a) The same program is used
b) The same ISA is used
c) The same compiler is used
-Set of standard programs used to comparison is called
benchmark.
Other Performance Metrics
 Marketing metrics for computer performance included
MIPS and MFLOPS
 MIPS : millions of instructions per second
 MIPS = instruction count / (execution time x 106)
 For example, a program that executes 3 million instructions in 2
seconds has a MIPS rating of 1.5
 Advantage : Easy to understand and measure
 Disadvantages : May not reflect actual performance, since simple
instructions do better.
 MFLOPS : millions of floating point operations per second
 MFLOPS = floating point operations / (execution time x 106)
 For example, a program that executes 4 million fp. instructions in
5 seconds has a MFLOPS rating of 0.8
 Advantage : Easy to understand and measure
 Disadvantages : Same as MIPS, only measures floating point
MIPS Example 1
 Consider processor with 3 instruction classes with 3
instruction classes with corresponding CPI values of
1,2,&3 respectively. The processor run at 1GHz.
ICA(in ICB(m) ICC(m)
millions)
Compiler 1 7 2 1
Compiler 2 12 1 1

 Compute MIPS and CPU time for 2 programs?

MIPS Example 2
 Two different compilers are being tested for a 500 MHz.
machine with three different classes of instructions:
Class A, Class B, and Class C, which require one, two,
and three cycles (respectively). Both compilers are used
to produce code for a large piece of software.
The first compiler's code uses 5 billions Class A
instructions, 1 billion Class B instructions, and 1 billion
Class C instructions.
The second compiler's code uses 10 billions Class A
instructions, 1 billion Class B instructions, and 1 billion
Class C instructions.
 Which sequence will be faster according to MIPS?
 Which sequence will be faster according to execution
time?
Performance Summary
 The two main measure of performance are
 execution time : time to do the task
 throughput : number of tasks completed per unit time
 Performance and execution time are reciprocals.
Increasing performance, decreases execution time.
 The time to execute a given program can be computed
as:
CPU time = Instruction count x CPI x clock cycle time
CPU time = Instruction count x CPI / clock rate
 These factors are affected by compiler technology, the
instruction set architecture, the machine organization,
and the underlying technology.
 When trying to improve performance, look at what
occurs frequently => make the common case fast.
 Decimal: number between 0 to 9:
 Number 724.5 is interpreted to represent the quantity:
7 X 10^2 + 2 X 10^1 + 4 X 10° + 5 X 10^-1
 Binary: String 101101 can be written as:
1 X 2^5 + 1 X 2^3 + 1 X 2^2+ 1 X 2^0=45
 Octal:

 Hexadecimal
Conversion of binary to decimal
Q. 1.Convert Integer 101011 to decimal

Q. 2. Convert .0101 to decimal

?
Conversion of binary to decimal
Q. 1.Convert Integer 101011 to decimal

1 X 2^5 + 1 X 2^3 + 1 X 2^1+ 1 X 2^0=43

Q. 2. Convert .0101 to decimal

0 X 2^-1 + 1 X 2^-2 + 0 X 2^-3+ 1 X 2^-4= (0.3125)
Conversion of decimal to binary
Q. Convert Integer 41.6875 to binary
Conversion of decimal to binary
Q. Convert Integer 41.6875 to binary
Conversion of binary to hexadecimal
Q.1. Convert Integer 1011 0100 0011 to Hexadecimal

Q. 2.Convert Integer 101010 0001 to Hexadecimal

Q.3.Convert Integer 12.3D to binary

Q.4.Convert Integer 3A5 to binary

Conversion of binary to hexadecimal
Q. 1.Convert Integer 1011 0100 0011 to Hexadecimal
B43

Q.2 Convert Integer 101010 0001 to Hexadecimal

2A1

Q.3.Convert Integer 12.3D to binary

0001 0010.0011 1101

Q.4.Convert Integer 3A5 to binary

0011 1010 0101

BCD Numbers
Sign-magnitude representation
0000 +0 1000 -0
0001 +1 1001 -1
0010 +2 1010 -2
0011 +3 1011 -3
0100 +4 1100 -4
0101 +5 1101 -5
0110 +6 1110 -6
0111 +7 1111 -7
One’s complement representation

0000 +0 1111 -0
0001 +1 1110 -1
0010 +2 1100 -2
0011 +3 1100 -3
0100 +4 1011 -4
0101 +5 1010 -5
0110 +6 1001 -6
0111 +7 1000 -7
Two’s complement representation
2’s complement
For n=4
0000 +0 1000 -8
0001 +1 1111 -1
0010 +2 1110 -2
0011 +3 1101 -3
0100 +4 1100 -4
0101 +5 1011 -5
0110 +6 1010 -6
0111 +7 1001 -7
Q.1Convert Decimal to binary:41.6875
 Ans:14 1 . 6875) = ( 1 0 1 00 1 . 1 0 1 1 )
Q.2.Convert 1938 to hexadecimal.
 Q.3. Obtain the l's and 2's complements of the following eight-digit
binary numbers: 10101 1 10; 10000001; 10000000; 00000001; and
00000000.