Lcdf3 Chap 07 p1
Lcdf3 Chap 07 p1
Lcdf3 Chap 07 p1
Overview
Part 1 - Registers, Microoperations and Implementations
Registers and load enable Register transfer operations Microoperations - arithmetic, logic, and shift Microoperations on a single register
Multiplexer-based transfers Shift registers
Register cell design Multiplexer and bus-based transfers for multiple registers Serial transfers and microoperations
Chapter 7 - Part 1
Registers
Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state table More often think of a register as storing a vector of binary values Frequently used to perform simple data storage and data movement and processing operations
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Design individual cells using the state diagram/state table model and combine them into a register
A 1-bit cell has just two states Output is usually the state variable
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Register Storage
Expectations:
A register can store information for multiple clock cycles To store or load information should be controlled by a signal
Reality:
A D flip-flop register loads information on every clock cycle
Realizing expectations:
Use a signal to block the clock to the register, Use a signal to control feedback of the output of the register back to its inputs, or Use other SR or JK flip-flops which for (0,0) applied store their state
Load is a frequent name for the signal that controls register storage and loading
Load = 1: Load the values on the data inputs Load = 0: Store the values in the register
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2-to-1 Multiplexers
A1 D Q
C A0 D Q C
Y1
Y0
Chapter 7 - Part 1
Register Notation
R 15 8 7 0 PC(H) PC(L) 76543210 15 R2 0
Letters and numbers denotes a register (ex. R2, PC, IR) Parentheses ( ) denotes a range of register bits (ex. R1(1), PC(7:0), AR(L)) Arrow () denotes data transfer (ex. R1 R2, PC(L) R0) Comma separates parallel operations Brackets [ ] Specifies a memory address (ex. R0 M[AR], R3 M[PC] )
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Conditional Transfer
If (K1 =1) then (R2 R1) K1 is shortened to K1: (R2 R1) where K1 is a control variable specifying a Clock conditional execution of the microoperation.
Clock
K1
R1
Load R2
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Microoperations
Logical Groupings:
Transfer - move data from one set of registers to another Arithmetic - perform arithmetic on data in registers Logic - manipulate data or use bitwise logical operations Shift - shift data in registers
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Example Microoperations
Add the content of R1 to the content of R2 and place the result in R1. R1 R1 + R2 Multiply the content of R1 by the content of R6 and place the result in PC. PC R1 * R6 Exclusive OR the content of R1 with the content of R2 and place the result in R1. R1 R1 R2
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Example Microoperations (Continued) Take the 1's Complement of the contents of R2 and place it in the PC. PC R2 On condition K1 OR K2, the content of R1 is Logic bitwise Ored with the content of R3 and the result placed in R1. (K1 + K2): R1 R1 R3 NOTE: "+" (as in K1 + K2) and means OR. In R1 R1 + R3, + means plus.
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Control Expressions
The control expression for Example: an operation appears to the X K1 : R1 R1 + R2 left of the operation and is X K1 : R1 R1 + R2 + 1 separated from it by a colon Control expressions specify Variable K1 enables the add or subtract operation. the logical condition for the If X =0, then X =1 so operation to occur X K1 = 1, activating the Control expression values addition of R1 and R2. of: If X = 1, then X K1 = 1, Logic "1" -- the operation occurs. activating the addition of Logic "0" -- the operation is R1 and the two's does not occur. complement of R2 (subtract).
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Arithmetic Microoperations
From Symbolic Designation Description Table R0 R1 + R2 Addition Ones Complement 7-3: R0 R1
R0 R1 + 1 R0 R2 + R1 + 1 R1 R1 + 1 R1 R1 1
Two's Complement R2 minus R1 (2's Comp) Increment (count up) Decrement (count down)
Note that any register may be specified for source 1, source 2, or destination. These simple microoperations operate on the whole word
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Logical Microoperations
From Table 7-4:
Symbolic Designation R0 R1 R0 R1 R2 R0 R1 R2 R0 R1 R2 Description Bitwise NOT Bitwise OR (sets bits)
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Shift Microoperations
From Table 7-5: Let R2 = 11001001 Then after the operation, R1
becomes:
Symbolic Designation R1 sl R2 R1 sr R2
R1 10010010 01100100
Note: These shifts "zero fill". Sometimes a separate flip-flop is used to provide the data shifted in, or to catch the data shifted out. Other shifts are possible (rotates, arithmetic) (see Chapter 11).
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Multiplexer-Based Transfers
Multiplexers connected to register inputs produce flexible transfer structures (Note: Clocks are omitted for clarity)
The transfers are:
Load R2
K1: R0 R1
K2 K1
n S 0 MUX 1
K2 K1: R0 R2
Load n R0
Load
R1
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Shift Registers
Shift Registers move data laterally within the register toward its MSB or LSB position In the simplest case, the shift register is simply a set of D flip-flops connected in a row like this:
In DQ A DQ B DQ C DQ Out
Data input, In, is called a serial input or the shift right input. Data output, Out, is often called the serial output. The vector (A, B, C, Out) is called the parallel output.
CP
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In 0 1 1 0 1 1
1
A ? 0 1 1
B ? ? 0 1
C ? ? ? 0
Out ? ? ? ?
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