UNIVERSITI MALAYSIA PERLIS

SCHOOL OF COMPUTER &

COMMUNICATIONS ENGINEERING

EKT 221 DIGITAL ELECTRONICS II

LABORATORY MODULE

LAB 3

REGISTER TRANSFER LEVEL

UniMAP DIGITAL ELECTRONICS II

LABORATORY OUTCOME

1. Ability to describe the functions of Register Transfer Level inside a digital

system design.
2. Ability to discuss the types of micro-operations inside the Register Transfer
Level.
3. Ability to transfer Algorithmic State Machines system flow onto registers or
register cell operations.
4. Ability to construct a simple digital system that includes a Control Unit and
Datapath Unit.

EQUIPMENTS/COMPONENTS

• Altera MaxPlus II software

• Altera UP2 Training Board
• Test pen screwdriver

INTRODUCTION

Register Transfer Level (RTL)

A digital system is a sequential logic system constructed using flip-flops and gates.
Sequential circuits can be specified by means of state tables and finite state diagrams
as done in the previous lab module. To specify larger digital systems using state tables
may be more difficult albeit possible because the number of states may be very large.
To overcome this difficulty, digital systems are usually designed in a modular
approach and partitioned into smaller subsystems that perform fundamental tasks.
These modules are constructed from simple digital devices such as registers,
decoders, multiplexers, arithmetic elements and control logics. Combining some or
more of these devices and interconnected with common control paths and data paths
will lead to the development of microprocessors and microcontrollers and other
complex digital system controllers.

Digital systems are best defined by a set of registers and its operations like shift,
count, clear and load. The information flow and operations on the data stored inside
the registers are often referred to as Register Transfer Level or RTL in short. Three
main components are specified when dealing with digital systems at the register
transfer level:

• The set of registers in the system

- The hardware that will have the ability to perform the elementary
operations from the stored data such as shift, count, clear and load.

• The operations that are performed on the data stored in the registers
- Elementary operations or better known as micro-operations such as
R1Å R1+R2

• The control that supervises the sequence of operations in the systems

- The control that initiates the sequence of events to perform the micro-
operations in a prescribed manner

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Types of micro-operations

Micro-operation Example
Transfer R0 Å R1
Arithmetic R0 Å R1 + 1
Logic R0 Å R1 ^ R2
Shift R0 Å sl R0

Multiplications and divisions are not listed as basic sets of micro-operations even
though they are represented by the symbols ‘*’ for multiplications and ‘/’ for
divisions. They are assumed to be implemented by the shift and add micro-operations.

The register is usually represented by the variable ‘R’ and may include multiple ‘R’s
which signifies the usage of more than one sets of registers to meet the desired
specifications of a digital system. The controller section of a digital system is usually
represented by the variable ‘K’ to show the conditional statements of the system
(control signals). A system may have more than one ‘K’ controller to meet the
purpose of multiple transfer operations.

An important note is that all registers have a load enable controller (LE) to allow data
to be stored into the destination register. Example 3.01 shows a particular RTL micro-
operation and implementing the rules above.

Example 3.01

An RTL for an n-bit adder/subtractor system can be represented as the following RTL
micro-operations :
;

The block diagram for the two statements above can be built as shown below :

R2

Adder - Subtractor
K2

R1 K1

Figure 3.1 : Block Diagram of an n-bit Adder/Subtractor

The diagram shows that K2 is the selector for the add/subtract operation and K1 is the
load enable for register R1. When K2=0 and K1 = 1, then R2 will be added to the
contents of R1 and stored back into R1. When K2=1 and K1=1, then the R2 will be
subtracted from the contents of R1 and stored back into R1.

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UniMAP DIGITAL ELECTRONICS II

For this example, the carry bit and overflow operations are not represented and left
out, but can still be constructed if desired.
Note that RTL operations are always based on the edge transitions of clock pulses as
registers are orignated from flip-flops.

PRE-LAB ASSIGNMENT

You are advised to do read this chapter on RTL to fully understand the RTL micro-
operations before coming in for this lab. A set of exercise will be given in this module
for you to prepare before coming in for the lab.

These questions will be selected during your lab sessions as part of your Altera
MaxPlus II download project for verification and the final marks to complete this lab
module.

You are permitted to bring along with you any printed copies of your homework
design done at home to help you out and allow quicker circuit development and
references throughout your lab session.

HOMEWORK EXERCISE

1. Using the n-bit Adder/Subtractor module in Example 4.01, suppose there exist
an extra output Cout for the most significant bit to complement the whole
digital system which will enter another bit-register. Assume that registers R1
and R2 hold unsigned numbers. When K2 selector is set to always HIGH, the
module operates as a subtractor. The sum will be used to enter registers R1
and Cout.
a. Show the block diagram for this module with the position of the Cout
register.
b. How is it that if Cout=1, then the operation will is R1-R2, but when
Cout=0, then the operation is actually R2-R1.
c. Indicate how the Cout value can be used to detect a borrow after the
subtraction process happens.

2. Show the diagram of the hardware that implements the register transfer
statements below :
a. A digital system with a controller function of
C3 : R2 Å R1, R1 Å R2
b. A digital system that implements a 4:1 MUX and with the RTL
function of
C0 : R4 Å R0,
C1 : R4 Å R1,
C2 : R4 Å R2,
C3 : R4 Å R3

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UniMAP DIGITAL ELECTRONICS II

3. A digital system has an n-bit register with S1 and S0 controls. Draw the RTL
block for a cell register with S1 and S0 input controllers that implement the
follwing function table :

S1 S0 Register Operation
0 0 No change
0 1 Clears register to 0
1 0 Complement output
1 1 Load parallel data

4. Using two 4-bit registers R1 and R2, draw a bit slice of the logic diagram that
implements the following statements :
C0 : R2 Å 0;
C1 : R2 Å ;
C2 : R2 Å R1;

5. Using D flip-flops to implement this design, a register cell is to be used for an

n-bit register R0 that implements the register transfer functions of :
: R0 Å 0;
: R0 Å R0 ∨ R1;
: R0 Å R0 ⊕ R1;
: R0 Å R0 ∧ R1;

6. An n-bit system is to have the following set of register transfers :

Ca : R0 Å R1;
Cb : R3 Å R1, R1 Å R4, R4 Å R0;
Cc : R2 Å R3, R0 Å R2;
Cd : R2 Å R4, R4 Å R2;
a. For each destination register, list the source registers
b. For each source register, list the destination registers
c. Draw the block diagram for this system and its interconnetctions.

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UniMAP DIGITAL ELECTRONICS II

Name
Degree Program
Matric No. MyKAD

LAB 3 VERIFICATION SHEET

VERIFICATION CHOP & SIGN
PROBLEM 1

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VERIFICATION CHOP & SIGN

PROBLEM 2

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VERIFICATION CHOP & SIGN

PROBLEM 3

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VERIFICATION CHOP & SIGN

PROBLEM 4

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VERIFICATION CHOP & SIGN

PROBLEM 5

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VERIFICATION CHOP & SIGN

PROBLEM 6

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HARDWARE VERIFICATION CHOP & SIGN

DEMO

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LAB 3 1