EDC Lab Manual

ELECTRONIC DEVICES AND CIRCUITS LAB MANUAL Experiment no 1: DIODE CLIPPING CIRCUITS
Aim : To study and test the application of diode in clipper circuits a. b. c. d. Simple positive and negative shunt clipper Simple positive and negative series clipper Biased positive and negative shunt clipper Combination shunt clipper
Components and Equipments required: Sr. No. 1. 2. 3. 4. 5. 6. 7. Bread Board/Connection Board Diodes Capacitors Signal Generator CRO Resistors Probes, wires, patch cords 1N4002/1N4148 1uF 10Hz to 1MHz Two channel with X-Y feature 100K 01 02 02 01 01 01 Components/Instruments Range Quantity
Theory: Clipping circuits are used to select and transmit a part of the given waveform. The other parts of the waveform are clipped or removed by the diode clipper circuit. These circuits are also known as voltage or current limiters, amplitude selectors or slicers. The piecewise linear model of diode characteristic exhibits a discontinuity in slope at the cut off voltage Vk. and this point of slope discontinuity is called a break point. For silicon diode the break point occurs at VK ~ 0.7V. This concept can be used to explain the transfer characteristics of a clipper circuit, which is a plot of output voltage against the input voltage.
Design: The limiting resistor R in the circuit can be designed in the following manner. From the diode forward and reverse characteristics, the resistance in either direction can be determined, respectively, as Rf and Rr. It can be shown that limiting resistor R =
RfRr . The ratio Rr/Rf can
be called the figure of merit of the diode. From V-I characteristics of diode, we have Rf= 20
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ELECTRONIC DEVICES AND CIRCUITS LAB MANUAL

and Rr = 1 M. From these values, limiting resistor required is R = 3.3 K (std), watt and we can use 1K to 5K . Procedure: 1. Study the circuit, expected waveform and transfer characteristic. 2. Place the components on bread board or connection board and connect them as per given circuit diagram. Use wires for connection as required. 3. Switch on the signal generator and set voltage to 10V P-P and frequency to 1kHz , 4. Set DC voltage to 2 V in case of biased circuits 5. Connect the input and output of the circuit to the two channels of the CRO. Observe the input and output ( in DC mode only) waveforms. 6. Measure the voltage amplitude, clipping voltage using CRO. Keep CRO setting in XY mode and observe the transfer characteristic. 7. Note down the waveforms on work sheet. (If required use additional sheet) 8. Repeat this for all clipping circuits. Result: Clipper circuits have been tested and output wave forms match with the expected waveforms. Work Sheet:Component Values:Vin
Vo Vo
t Vin
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Component Values:Vin
Vo Vo
Vin
Vo
Vo
t Vin
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Vo
Vo
Vin
Biased Clipping circuits Component Values:Vin
Vo
Vo
t Vin
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Vo Vo
t Vin
Vo Vo
t Vin
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Vo Vo
t Vin
Component Values:-
Vin
Vo Vo
t Vin
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ELECTRONIC DEVICES AND CIRCUITS LAB MANUAL Experiment no 2: DIODE CLAMPING CIRCUITS
Aim: To study and test the application of diode in clamper circuits. a. b. c. d. Positive clamper Negative clamper Biased positive clampers Biased negative clampers
Components and Equipments required: Sr. No. 1. 2. 3. 4. 5. 6. 7. Bread Board/Connection Board Diodes Capacitors Signal Generator CRO Resistors Probes, wires, patch cords 1N4002/1N4148 1uF 10Hz to 1MHz Two channel with X-Y feature 100K 01 02 02 01 01 01 Components/Instruments Range Quantity
Theory: Clamper is a circuit that "clamps" a signal to a different DC level without changing the shape of the applied signal Clamping circuit introduces a DC level into an ac signal. The different types of clampers are positive, negative and biased clampers. A clamping network must have a capacitor, a diode and a load resistor. The magnitude R and C must be chosen such that the time constant RC is large enough to ensure that the voltage across the capacitor does not discharge significantly during the interval when the diode is non- conducting. By connecting suitable DC voltage in series with the diode, clamping level can be varied.
Design: Assume C, and for clamping to occur select R such that RC >> T, (Assume RC = 100 T) where T is the period of the input signal. If C = 1uF, then from above equation R= 100K.

Procedure: 1. Study the circuit, expected waveform and transfer characteristic. 2. Place the components on bread board /connection board and connect them as given in circuit diagram fig 1a. Use the wires for connection as required. 3. Switch on the signal generator and set voltage to 10V P-P and frequency to 1kHz 4. Set DC voltage to 0 V DC (Positive clamping). 5. Connect the input and output of the circuit to the two channels of the CRO. Observe the input and output waveforms( in DC mode only) and ensures that it matches with expected wave form. 6. Vary the DC voltage and observe the level of clamping. 7. Set VDC to 2V and note down input & output waveform and draw it on work sheet (Positive Biased Clamping) .If required use additional graph sheet. 8. Reverse the polarity of the Vdc and repeat the steps 6& 7.(fig 1b) 9. Repeat the procedure for fig 2a & 2b and note down the waveforms. Result: Positive and Negative clamping circuits and biased clamping circuits are tested and output waveforms observed. Work sheet
Vin
Vo When Vdc = 0V t
Vo
Fig 1a:- Positive Clamper Circuit Component Values

t When Vdc = 2V
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Vin
t Vo When Vdc = 0V t
Fig 1b:- Positive Clamper Circuit

Vo When Vdc = 2V t
Vin
t Vo
When Vdc = 0V
Fig 2a:- Negative Clamper Circuit

Vo When Vdc = 2V t
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Vin
t Vo
When Vdc = 0V
Fig 2b:- Negative Clamper Circuit
Vo
When Vdc = 2V
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ELECTRONIC DEVICES AND CIRCUITS LAB MANUAL Experiment no 3: Testing of Diode Voltage Multiplier circuits
Aim: To study and test diode voltage multiplier circuits a. Half wave diode voltage multiplier b. Full wave diode voltage multiplier
Components and Equipments required: Sr. No. 1. 2. 3. 4. 5. 6. 7. Bread Board/Connection Board Diodes Capacitors Step down transformer CRO (for test & measurement) Multimeter (for test & measurement) Probes, Wires, Patch cords BY 127/equ 10uf, 100V -Electrolytic 230/6-0-6V Two channel 01 04 04 01 01 01 AR Components/Instruments Range Quantity
Theory: A voltage multiplier consists of two or more peak-rectifiers that produce a DC voltage equal to a multiple of peak input voltage (2VP, 3 VP, 4VP.). At the peak of negative half cycle of input, D1 is forward biased. This charges C1 to VP with the polarity as shown. At the peak of the positive halfcycle, D2 is forward biased. Since source and capacitor are in series, C2 charges to 2 VP. At the next negative half-cycle, D3 is forward biased and C3 is charged to 2VP.The voltage across C1 and C3 is charged to 3VP. Likewise, at the next half cycle, C4 is charged to 2VP and the voltage across C1 and C4 is charged 4VP.
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Circuit Diagrams:
Fig.1.A Half wave voltage multiplier circuit
Fig.1.B Full wave voltage multiplier circuit
Expected Output voltages VAP = Vp Voltage Doubler :- VBS = 2Vp Voltage Tripler :- VAQ = 3VP Voltage Quadrapuler :- VBT = 4VP
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Procedure: 1. Study the circuit. 2. Place the components on bread board/connection Board and connect them as per given circuit diagram Use the patch cords/ wires for connection as required. 3. Set secondary output voltage to around 6V rms 4. Measure the voltage across all four capacitors( multimeter in DC range) and ensure they are equal to the expected values. 5. Measure the voltage across the voltage doubler, tripler and quadrapuler and ensure that it matches with expected values. And note down the readings in the table. 6. Repeat this by changing secondary voltage of the transformer. Table Trail No. Input rms voltage (Vi) 6V 12V Peak input voltage Vp(V) Theoretical Practica 2 x Vi l Doubler output 2Vp(V Theoretical ) 2 2 x Vi VBS Tripler output Quadrupler output 3Vp(V Theoretical 4Vp(V) Theoretical ) 3 2 x Vi VBT 4 2 x Vi VAQ
Result: Voltage multiplier has been constructed and the peak input voltage, doubler output, tripler output and quadrupler output has been measured and verified with expected result.
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Experiment 4: Determination of h- parameters using static characteristic of a transistor in CE mode

Aim: To determine the h- parameters of a transistor in CE mode Components & Equipments required: Sl.No. 1. 2. 3. 4. Components/Instruments Bread Board/Connection Board Transistor Potentiometer Microammeter (Multimeter in mA range) Voltmeter (Multimeter in DC Volts range Regulated DC supply Probes, Wires, Patch cords Range SL 100 0-100K 0-500uA 0-25mA 0-5V 0-30V DC Quantity 01 01 01 01 01 01 02 AR
5. 6. Theory:
Hybrid equivalent model is one of the small signal ac analysis of transistor networks. For this model, the parameters are defined at an operating point of the transistor. The four h parameters are 1. The input impedance of the transistor is denoted by hybrid input impedance parameter hie =VBE / IB with VCE held constant. Unit is ohm. 2. Voltage feedback ratio or reverse transfer voltage ratio denoted by h re == VBE / VCE with IB held constant. It represents the dependence of the transistor's IBVBE curve on the value of VCE. It is usually very small and is often neglected (assumed to be zero). It has no unit. 3. Small signal current gain or forward transfer current ratio and is denoted by h fe = IC / IB with VCE held constant- This parameter is often specified as hFE or the DC current-gain (DC) in datasheets. It has no unit. 4. Output admittance or output conductance and is denoted by h oe = IC / VCE with IB held constant. Unit is S. The measurement of these h parameters can be done by using the input and output characteristic of transistor.To determine input characteristic, output VCE is held constant , VBE is varied in steps of 0.1V and corresponding IB value is noted. From this graph, we can find hie and hre. To determine output characteristic, input current IB is held constant, VCE is varied insteps of

1V up to 5Vand corresponding value of IC is noted. From the output characteristic we can find h fe and hoe values. Circuit diagrams:
Input Characteristic Table: VCE =0V VBE (V) IB (uA) VCE =1V VBE (V) IB (uA) VCE =2V VBE (V) IB (uA)
Output Characteristic Table IB =80uA VCE (V) IC (mA) IB =100uA VCE (V) IC (mA) IB =150uA VCE (V) IC (mA)
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Procedure: 1. Study the circuit and expected waveforms 2. Place the components on bread board /connection Board and connect them as per given circuit diagram. Use patch cords/ wires for connection as required. 3. Input characteristic: - Set V2 i.e VCE = 0V and vary the V1 in steps of 0.2V up to 1V and measure VBE and IB. Take more readings near the knee point. Repeat this for VCE =1V and VCE=2 V. Note down the readings and enter in the corresponding table. Draw the input characteristic curve on the graph. 4. Output characteristic: - Set V1 so that IB= 80uA and vary VCE in steps of 1V up to 5V and note down VCE and IC. Repeat this for IB =100uA and IB=150uA Note down the readings and enter in the corresponding table. Draw the output characteristic curve on the graph for various IBs. 5. Set Q point on output characteristics at VCEQ = 2V and suitable value of ICQ 6. In the active region of any one curve. hfe and hoe are determined as shown 7. in graph around the Q point. 8. On the input characteristic curve, Q point is fixed as intersection of IBQ and VCEQ = 2V graph. Calculate hie and hre around the Q point. Result: The h-parameters are calculated using input and output characteristics of transistor in CE mode. Results are tabulated as below.
Parameters hie hre hfe hoe
Calculated values
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Experiment no 5: To determine the characteristics of BJT Amplifier
Aim :- To design an RC coupled single stage BJT amplifier and to determine i)Input impedance, ii)Output impedance Components and Equipments required: Sl. No. 1. 2. 3. 4. 5. 6. 7. Components/Instruments Bread Board/Connection Board NPN Transistor Capacitors,Resistors Signal Generator CRO Regulated DC Power Supply Decade Resistance Box 1no SL100 As per design 10Hz to 1MHz Two channel with X-Y feature (0-30V dc) (0 t0 1 Meg OHM) 01 01 01 Range Quantity 01 01
Theory :- :- In RC coupled amplifier the input capacitor is used to couple the input signal to the base of first transistor. Since the coupling from one stage to next stage can be achieved by a coupling capacitor followed by a connection to a shunt resistor such amplifiers are called resistance capacitance (RC) coupled amplifiers. When an ac signal is applied to the input of the first stage it is amplified with a phase reversal by the transistor. Procedure:1. Draw and study the circuit, 2. Place the components on bread board and connect them as per given fig a. Note: Measure the DC values of VCE, VBE and ensure that they are close to the designed values, before connecting the function generator, coupling capacitors and bypass capacitors. Observation:I. Biasing values VCE= VBE = II. Set Vin = Undistorted
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VRC= So Ic = VRC / Rc = Max Vout ( from the CRO) =

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3. To find input impedance 1. Connect as given in fig b with DRB resistance zero. Adjust the input Vin to 50 mV. (Let the frequency of the input be around 5kHZ ) 2. Note down the peak to peak amplitude of the corresponding output Vo . Let Vo=Va 3. Increase the resistance included in DRB and observe the magnitude of the output Vo simultaneously on the Oscilloscope. 4. When the magnitude of the output Vo is reduced to half of its original value, stop varying the resistance further and remove the potentiometer from the circuit. Vo=Va/2 5. Measure the value of the DRB and this measured value will be the input impedance ( Ri) of the circuit.

5. To find output impedance: 1. Adjust the input sinusoidal peak to peak in such a way that the output sine wave is not clipped. 2. Note down this value of the input Vin. (Let the frequency of the input be around 2kHZ) 3. Note down the peak to peak amplitude of the corresponding output Vo . Let Vo=Va 4. Connect a DRB ( with maximum resistance included)at the output as shown in fig c. 5. Decrease the DRB / potentiometer and observe the magnitude of the output Vo simultaneously on the Oscilloscope. 6. When the magnitude of the output Vo is reduced to half of its original value, stop varying the potentiometer further and remove the potentiometer from the circuit. Vo=Va/2 7. Measure the value of the DRB/ potentiometer and this measured value will be the output impedance ( Ro) of the circuit.
Result:- The single stage CE amplifier was designed and its performance verified. The output waveform is in 180 phase shifted with input signal. Input Resistance = Output Resistance =

Experiment no 6: To plot the Frequency Response of the BJT Amplifier
Aim :- To design an RC coupled single stage BJT amplifier and to determine i)Input impedance, ii)Output impedance Components and Equipments required: Sl. No. 1. 2. 3. 4. 5. 6. 7. Components/Instruments Bread Board/Connection Board NPN Transistor Capacitors,Resistors Signal Generator CRO Regulated DC Power Supply Decade Resistance Box 1no SL100 As per design 10Hz to 1MHz Two channel with X-Y feature (0-30V dc) (0 t0 1 Meg OHM) 01 01 01 Range Quantity 01 01
Theory :- :- In RC coupled amplifier the input capacitor is used to couple the input signal to the base of first transistor. Since the coupling from one stage to next stage can be achieved by a coupling capacitor followed by a connection to a shunt resistor such amplifiers are called resistance capacitance (RC) coupled amplifiers. When an ac signal is applied to the input of the first stage it is amplified with a phase reversal by the transistor. The frequency response is a graph of the gain (in decibels) versus the frequency (in logarithmic scale). This characteristic can be subdivided into low, medium and high frequency regions. In the low frequency range, the gain drops due to increasing reactance of coupling capacitor, source capacitance and emitter capacitor. As the frequency increases, the capacitive reactance reduces and the gain increases. After this if the frequency is increased further, i.e. in the high frequency range, the gain drops due to the increased flow of the a.c signal through CE. To fix the boundaries of frequency where the gain is relatively high and constant, 0.707Amid is chosen to be the voltage gain at the cut-off levels. The corresponding frequencies f1 and f2 are generally called the corner, cut-off, band, break or half power frequencies. The multiplier 0.707 is chosen because at this level the output power is half the mid-band power output. This is illustrated in the model graph.
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Procedure:1. Draw and study the circuit, 2. Place the components on bread board and connect them as per given fig a. Note: Measure the DC values of VCE, VBE and ensure that they are close to the designed values, before connecting the function generator, coupling capacitors and bypass capacitors. 3. To find gain frequency response: 1. Connect the signal generator and apply a sine wave of peak-to-peak amplitude 50mV, 1 kHz. Connect input and output (Vo) of the circuit to the two channels of CRO. And observe the waveforms. The input and output waveforms should be undistorted. Note down the peak to peak amplitude of Vin and Vout. Calculate Voltage gain for maximum undistorted output , Avm = Vo/Vi 2. Vary the FREQUENCY of the input sine wave (keeping the amplitude constant) stepwise from 100HZ to 1MHZ.. 3. Note down the output peak to peak amplitude Vo for every frequency of the input. 4. Calculate the gain = output to input ratio (Vo / Vin ) for every value of the input frequency. 5. Calculate the gain in dB for each of the above readings: Gain in dB = 20 log (Vo / Vin) 6. Tabulate the readings as per frequency response Table 7. Plot the Gain in db versus frequency plot on the sem log graph. 8. Draw a horizontal line 3 db below the Avmid and note down the lower & upper cutoff frequency
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Observation:I. Biasing values VCE= II. Set Vin = Undistorted
VBE =
VRC=
So Ic = VRC / Rc =
Max Vout ( from the CRO) =
Avm = Vout/Vin = From the graph, f1 = f2 = Bandwidth (BW) = f2 - f1 = Gain bandwidth(GBW) = Avm * BW =
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X axis is in log scale; Y axis is in normal scale f1 Lower cut-off frequency f2 Higher cut-off frequency f2-f1 Band width of the amplifier 3dB - 20log10(0.707)
Result:The single stage CE amplifier was designed and its performance verified. The output waveform is in 180 phase shifted with input signal. The readings obtained are given below:Voltage Gain = Bandwidth = Gain-Bandwidth product =
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Experiment 7 :- Design of Two Stage RC coupled Amplifier
Aim :- To design a two stage RC coupled BJT amplifier and to determine frequency response.
Components & Equipments required :Sl.No. Components/Instruments 1. 2. 3. Bread Board Resistor Capacitors Range Quantity 01 AR AR
4. NPN Transistors 5. 6. 7. 8. 9. Regulated DC supply Signal /Function generator SL 100 0-30V DC 10Hz to 1 Mhz 02 01 01 01 01 AR 0 to 1 Meg ohm 01
CRO (for test & measurement) Two channel Multimeter (for testing) Probes, Wires, Patch cords
10. DRB
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Circuit diagram:-
Design:Bias circuit design: Given: VCC = 10V, VCE = 5V, IC = 2m = 100 (assumed) Assume VBE = 0.7V for silicon diodes VE = 10% of Vcc = 1V Assume IE ~ IC RE = VE /IE = 1V/ 2mA = 500 (use R8 = 470 , R4= 100 R9 = 330 ) Rc =(Vcc- VCE -VE) / IC=( 10-5-1 ) / 2mA =2 k.(Use 2.2k for R3 &R7) V 2 =V B = VE + VBE = 1+0.7 = 1.7V R E 10 R 2 R 2 = (R E)/10 = 5k (use 4.7 k for R 2 and R6) V1 = Vcc V2 = 10-1.7= 8.3V V1/ V2 = R1 / R2 R1 = (V1/ V2) * R2 = 22.9k (use 22 k R1 and R5) DEPT OF ECE, PESIT Cc = 10F, CE = 22F Page 26

Theory: -In a capacitor coupled two stage amplifier circuit, each stage is similar to the single stage circuit. Stage-1 is connected to stage-2 via the coupling capacitor. The signal is applied at stage-1 and the load is coupled to the output of stage-2. The signal is amplified by stage-1, and the output of stage-1 is amplified again by stage-2, so that overall voltage gain is much greater than the gain of a single stage. The other advantage of two stage amplifier is no phase shift in the output voltage. As the signal voltage is phase shifted by through 180 degree by stage-1 and through a further 180 degree by stage-2, the overall phase shift from input to output is 360 degree or zero degree. Design of all the components except emitter bypass capacitors is similar to the single stage amplifier. Negative feedback is introduced by the unbypassed first stage emitter bypass capacitor to reduce the gain of the first stage. Procedure:- (To find, maximum undistorted gain, frequency response, refer the procedure given in single stage amplifier.) 10. Draw and study the circuit, 11. Place the components on bread board and connect them as per given fig a. Use the wires for connection as required. Note: Measure the DC values of VCE, VBE and ensure that they are close to the designed values, before connecting the function generator, coupling capacitors and bypass capacitor. 3. To find gain frequency response: 1. 2. Gain for stage 1(Av1):- Measure the max undistorted voltage gain for stage 1 ( For this remove the connection between CC2 and base of Q2.). Gain for stage 2(Av2):- Measure the max undistorted voltage gain for stage 1 ( For this remove the connection between CC2 and collector of Q1 and connect the input signal to disconnected CC2 end. Gain for two stage (Avt):- Connect the CC2 connection and measure the max undistorted voltage gain for complete circuit. ( For this, connect signal generator at CC1 and measure Vo at CC3.) Overall frequency response:- Find the overall frequency response of the system. And find the bandwidth.
3.
4.
Input frequency = 2kHz, Sl.No Vi in mV Vo in V Gain Avm =Vo/Vi Gain in dB = 20 log (Vo / Vin) 1 2 3 Stage 1 only Stage 2 only Two stage
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Frequency Response Table ( for Two Stage Amplifier) Vin = ------- Volts ( Peak to Peak) SL. No Input frequency Output Peak Peak ( Volts) Gain = Vo / Vin Gain in dB = 20 log (Vo / Vin)
Model Frequency response Curve :-
Gain in dB Avmid 3dB
Frequency f1 Bandwidth f2
X axis is in log scale; Y axis is in normal scale f1 Lower cut-off frequency f2 Higher cut-off frequency f2-f1 Band width of the amplifier 3dB - 20log10(0.707) DEPT OF ECE, PESIT Page 28

Result:- The performance of two the RC Coupled Amplifier was designed and verified that the output waveform is in phase with input signal. Also find the gain of individual stages and verified that overall gain is the sum of dBAv1 and dBAv2.
Parameters Gain Bandwidth Gain-Bandwidth product
Stage1
Stage2
Overall
NA
NA
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Experiment 9 :- Design of Emitter follower with and without bootstrap circuit.
Aim: Design of a BJT Darlington emitter follower and to determine the gain, input and output impedances. Components & Equipments required:-
Sl.No. 01 02 03 04 05 06 07 08 09 10
Components/Instruments Bread Board NPN transistor Resistors Capacitors RPS Signal generator CRO for testing Probes, wires DRB Multimeter for testing & measurements
Range
Quantity 01
SL100
02 AR AR
0-30V DC 3A 10Hz to 1Mhz 2 channel 0 to1 Meg ohm
01 01 01 AR 01 1
Theory: In emitter follower, an input signal is applied to the base and the output is taken across emitter. The emitter follower has reasonably high input impedance and may be used wherever input impedance up to about 500 K Ohms is needed. For higher input impedance, we may use 2 transistors to form what is called a Darlington pair.. The output voltage is always less than the input voltage due to the drop between the base and emitter. However, the voltage gain is usually approximately equal to one. In addition, the output voltage is in phase with the input voltage. Hence it is said to follow the input voltage with an in-phase relationship. This accounts for the terminology Emitter follower. The collector is at ac ground; therefore the circuit is actually a Common-Collector Amplifier. This circuit presents high impedance at the input and low impedance at the output. It is therefore frequently used for impedance matching purposes, where a load is matched to the source impedance for maximum signal transfer through the system.
The Darlington connection shown is a connection of two transistors which results in a current gain that is the product of the current gains of the individual transistors. Hence the Darlington pair operates as one Super beta transistor offering a very high current gain. The Darlington Emitter follower is a CC configuration that has the following characteristics:
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Voltage gain almost unity Current gain very high, a few thousands Input impedance high, hundreds of Kilo ohms Output impedance low, tens of ohms Darlington Emitter follower with Bootstrap The biasing network reduces the input impedance of the amplifier. By h-parameter model input impedance is the parallel combination of input resistance of the transistor and of the biasing network. The biasing network resistance is always less than the input resistance of the Darlington transistor. To improve the resistance of the circuit, a series circuit consisting of a resistor and a capacitor is connected between the emitter and the base. This process of connecting output to input through a resistor under ac conditions is called Bootstrapping.
Circuit Diagram
RE = 560 ; R1 = 480 k , R2 = 800 k , Vcc = 12 V, Cc = 0.47 uf
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Design of Bias circuit Let VCE = 6V, IEQ=10mA (Q point of transistor Q2) Then Vcc = 2VCE =2 x 6 =12 V
IE = IC = 10 mA
VRE = Vcc - VCE= 12 6 = 6V RE= VR3 / IE = 6V / (10 mA) = 0.6K =560 (Choose) VR2 -VBE1 - VBE2 VRE = 0 and VR2 = VBE1 + VBE2 + VRE = 0.6 + 0.6 + (IE.RE) = 1.2 + (10x0.6) = 7.2V
VCC = VR1 + VR2

VR1= Vcc VR2 = 12 7.2 = 4.8 V IE1= IB2 = Ic / hfe = 10 mA / 100 = 0.1mA IB1=IE1 / hfe = 0.1mA / 100 = 1 A
R1 = VR1/ (10 (Ib1)) = 4.8 / (10 x 1 A) = 480 K R2= VR2 / (9 Ib) = 7.2 / (9 x 1 A = 800k
To find Cc XcC 0.2 Ri (Ri = R1|| R2 || hie = hie) Choose Ri = 1.5 K and f = 1KHz. 1 2 f CE x 0.1 R i Cc 1 / 2 f x 0.1 Ri = 1 / (2 x 3.14 x 1000 x 0.2 x 1500) = 0.53 F Therefore , Cc < 0.47 F is selected.
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Choose Rb= 100K and Cb = 47uF Procedure:1. Study the circuit and draw the required tables. 2. Place the components on bread board and connect them as per given fig. 3. DC Conditions: - Connect the circuit without ac supply. Set Vcc=12V. Measure the DC voltage (using CRO/multimeter) at the (VB2), Collector (VC2) emitter (VE2) w.r.t ground. Then determine VCE2= VC2 VE2 and IC2=IE2=VE2 / RE. Then Q point is (VCE2, IC2 ). 4. Connect the signal generator and apply a sine wave of peak-to-peak amplitude 1V, 1kHz. Connect input and output (Vo) of the circuit to the two channels of CRO. And observe the waveforms 5. Gradually increase the input signal until the output signal gets distorted. When this happens slightly reduce the input signal amplitude such that output is maximum undistorted signal. Then measure the magnitude of the input and output waveform. Calculate Voltage gain. 6. Connect input and output (Vo) of the circuit to the two channels of CRO. And observe the waveforms. Note down the waveform on the graph. 7. Find input and output impedance per given procedure. 8. Connect the bootstrap circuit Rb & Cb and make the necessary changes as per fig b. 9. Find the gain, input and output impedance with this circuit. 10. Voltage gain for maximum undistorted output, Avm = Vo/Vi
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To measure Zi DRB Vo Darlington Emitter Follower Circuit Fig c Adjust the input sinusoidal peak to peak in such a way that the output sine wave is not clipped. 2. Note down this value of the input Vin. (Let the frequency of the input be around 2kHZ) 3. Note down the peak to peak amplitude of the corresponding output Vo. Let Vo=Va 4. Connect a DRB (with zero resistance included)in series with the Function generator. 5. Increase the resistance in DRB and observe the magnitude of the output Vo simultaneously on the Oscilloscope. 6. When the magnitude of the output Vo is reduced to half of its original value, stop varying the potentiometer further and remove the DRB from the circuit. Vo=Va/2 7. Measure the value of the resistance in DRB and this measured value will be the input impedance ( Ri) of the circuit. To measure Zo (Output Impedance) 1.
Vin
Vin Darlington Emitter Follower Circuit Fig d 1. 2. 3. 4. 5. 6. 7.
DRB
Vo
Adjust the input sinusoidal peak to peak in such a way that the output sine wave is not clipped. Note down this value of the input Vin. (Let the frequency of the input be around 2kHZ) Note down the peak to peak amplitude of the corresponding output Vo . Let Vo=Va Connect a DRB ( with maximum resistance included) in parallel with the load as shown in fig c. Decrease the DRB and observe the magnitude of the output Vo simultaneously on the Oscilloscope. When the magnitude of the output Vo is reduced to half of its original value, stop varying the resistance further and remove the DRB from the circuit. Vo=Va/2 Measure the value of the DRB and this measured value will be the output impedance ( Ro) of the circuit.
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Result:- Thus the Darlingtons Emitter follower was designed and studied. It is proved that, by connecting bootstrap circuit, input impedance increases.
Parameters Without Bootstrap With bootstrap
Avm =Vo/Vi
Zi
Zo
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EXPERIMENT 9:- FET CHARACTERISTICS
Aim: To plot the characteristic of FET and to find i)Drain dynamic resistance ii) Mutual conductance iii)Amplification factor. Components & Equipments required: Bread Board, FET (1 no- BFW10 /equt), Multimeter, DC Milliammeter -1no Regulated DC power supply (2no- 0 to 30V dc), Probes, Wires (As required). Theory: FET, the field Effect transistor is a 3 terminal, voltage controlled device with three terminals drain, source and gate. The current flows between drain and source and this current is controlled by the voltage between gate & source. Mainly there are two types of FET , they are i)JFET (Junction Field Effect Transistor) ii)MOSFET (Metal Oxide Semiconductor Field Effect Transistor).. The FET has several advantages over conventional Bipolar junction transistor. 1. In a conventional transistor, the operation depends upon the flow of majority and minority carriers. That is why it is called bipolar transistor. In FET the operation depends upon the flow of majority carriers only. It is called unipolar device. 2. The input to conventional transistor amplifier involves a forward biased PN junction with its inherently low dynamic impedance. The input to FET involves a reverse biased PN junction hence the high input impedance of the order of M-ohm. 3. It is less noisy than a bipolar transistor. 4. It exhibits no offset voltage at zero drain current. 5. It has thermal stability. 6. It is relatively immune to radiation. The main disadvantage is its relatively small gain bandwidth product in comparison with conventional transistor. In FET the current is flowing through either P or N semiconductor and called as N channel or P channel . JFET. Ohmic contacts are then added on each side of the channel to bring the external connection. Thus if a voltage is applied across the bar, the current flows through the channel. The terminal from where the majority carriers (electrons) enter the channel is called source designated by S. The terminal through which majority carriers leaves the channel is called drain and designated by D. For an N-channel device, electrons are the majority carriers. Hence the circuit behaves like a dc voltage VDS applied across a resistance RDS. The resulting current is the drain current ID. If VDS increases, ID increases proportionally. Now on both sides of the n-type bar heavily doped regions of p-type impurity have been formed by any method for creating pn junction. These impurity regions are called gates (gate1 and gate2) as shown in the fig below.
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Both the gates are internally connected and they are grounded yielding zero gate source voltage (VGS =0). The word gate is used because the potential applied between gate and source controls the channel width and hence the current. As with all PN junctions, a depletion region is formed on the two sides of the reverse biased PN junction. The current carriers have diffused across the junction, leaving only uncovered positive ions on the n side and negative ions on the p side. The depletion region width increases with the magnitude of reverse bias. The conductivity of this channel is normally zero because of the unavailability of current carriers. The potential at any point along the channel depends on the distance of that point from the drain, points close to the drain are at a higher positive potential, relative to ground, then points close to the source. Both depletion regions are therefore subject to greater reverse voltage near the drain. Therefore the depletion region width increases as we move towards drain. The flow of electrons from source to drain is now restricted to the narrow channel between the no conducting depletion regions. The width of this channel determines the resistance between drain and source. Procedure: 1. Study the circuit and expected outputs. 2. Place the components on bread board and connect them as per given test set up. Use wires for connection as required. 3. Output characteristic: - Set VGS to 0V and vary VDS and measure the corresponding ID . Upto pinch off voltage Vds in steps of 0.5 and then after in steps of 1V. Repeat this experiment when Vgs = -2V . 4. Transfer characteristic: - Set VDS to 10V i.e well above the pinch off voltage. And vary the VGS from 0V till ID becomes 0 in steps of -1V and note down the output current ID . Repeat this experiment for VDS =20V 5. Plot the graph of a. VDS Vs ID for various VGS b. VGS vs ID. 6. From the output characteristic, note down the pinching voltage Vp, max drain current IDSS and output resistance, rd ( VDS / ID ). 7. From the transfer characteristic measure the mutual conductance or transconductance gm ( ID/ VDS) at a given Q point.
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Circuit Diagram: Test Set up:Calculations:- From the output characteristic graph, at Q point ----------
ID =
VDS =
So rd =
From the transfer characteristic graph, at Q point ----------
ID =
VGS =
So gm =
Amplification factor Av = gm*rd Output Characteristic Table Transfer Characteristic Table
VGS =0V VDS (V)
VGS = -2V ID (mA)
VDS =10V VGS (V)
VDS =20V ID (mA)
ID (mA) VDS (V)
ID (mA) VGS (V)
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Result:-
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ELECTRONIC DEVICES AND CIRCUITS LAB MANUAL Experiment no: 10 FET Voltage Divider Biasing circuit
Aim :-
Apply the voltage divider biasing method to set the DC operating point (VGSq , IDq) Verify the estimated DC operating point with the measured using N-channel JFET device in a common source configuration.
Components and Equipments required:Sr.No. Components/Instruments 1. 2. 3. 4. 5. Bread Board/Connection Board FET Resistors Regulated DC Power Supply Potentiometer BFW10 or equivalent As per design (0-30V dc) 50k Range Quantity 01 02 04 01 01
Circuit Diagram:.
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Theory: For the field-effect transistor, the relationship between input and output quantities is nonlinear due to the squared term in Shockleys equation. Linear relationships result in straight lines when plotted on a graph of one variable versus the other, while nonlinear functions result in curves as obtained for the transfer characteristics of a JFET. Due to the nonlinear relationship between ID and VGS dc analysis can be done using c the mathematical approach or simplified graphical approach which limit solutions to tenths-place accuracy. Another distinct difference between the analysis of BJT and FET transistors is that the input controlling variable for a BJT transistor is a current level, while for the FET a voltage is the controlling variable. In both cases, however, the controlled variable on the output side is a current level that also defines the important voltage levels of the output circuit. The general relationships that can be applied to the dc analysis of all FET amplifiers Are IG 0 A and ID = IS Shockleys equation is applied to relate the input and output quantities: Three types of FET biasing generally used are :- a) fixed bias, which needs a separate dc source b) Self bias , by grounding gate through a resistor c) Voltage divider bias . When IDQ is given, the corresponding input parameter VGS can be get using transfer characteristic curve or using the Scholkey s equation . Values IDSS and VP are taken from the data sheet.
Procedure: 1. Study the circuit, Get IDSS & VP (VGS OFF) from the data sheet of BFW 10. Design the biasing resistors. 2. Take 2FETs and measure the IDSS and VP for the same from its transfer characteristics. 3. Place the components on bread board and connect them as given in circuit diagram. Use the wires for connection as required. 4. Set VDD to 12V DC. And Measure DC voltage a) between Drain and Source (VDS) b) between Gate and Source (VGS) c) Across the resistor RD (VRD ) d) Across the resistor R2 (VG or VR2) e) Across the resistor RS (VS) d)Across the resistor R1 (VR1) 5. Calculate the value of ,Is / Id using ; ID= VRD / RD and Is= VS / Rs, 6. Compare the measured ID , IS , VGS and VD S with the design value. 7. Repeat this experiment by changing the FET 8. Draw load line and locate Q point for the FETs. DEPT OF ECE, PESIT Page 41

Design:From the data sheet of BFW 10 :VGSoff = 8V So VP = 8V IDSS = 8 to 20mA, We will take IDSS =( 8+20)/2 = 14mA Given VDD = 12V IDmaxQ = IDSS/4 = 3.5mA VDSmin = 3V Then VGSQ = VP/2 = - 4V (Note :- If IDQ is other than IDSS/4, find VGSQ using Shockleys equation or from the transfer characteristic curve ) Take VG=1V Then Vs= VG- (VGS) = 1- (-4V) = 5V Rs = 5V/3.5mA = 1.42k Take Rs =1.5 k RD = (VDD-VDS-Vs ) / ID = 12 - 3 - 5 / 3.5 mA = 1.14k Take RD = 1.2k To get VG=1 V use suitable potential divider say R2 =100K and R1 =1.1 M take R1 =1 M
Result: It is observed that for variation of IDSS from ------------ value --------------, variation in VDSQ & IDQ changes from --------------- --- to ------------------------------
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ELECTRONIC DEVICES AND CIRCUITS LAB MANUAL Experiment no 11: Common source FET Amplifier
Aim :- To design single stage FET amplifier and to determine
i)Frequency response, ii)Input impedance, iii)Output impedance
Components and Equipments required: Sr. No. 1. 2. 3. 4. 5. 6. 7. Bread Board/Connection Board FET Capacitors,Resistors Signal Generator CRO Regulated DC Power Supply Decade Resistance Box As per design 10Hz to 1MHz Two channel with X-Y feature (0-30V dc) (0 t0 1 Meg OHM) 01 01 01 01 01 Components/Instruments Range Quantity
Circuit Diagram:-
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Theory: Small signal amplifiers can also be made using Field Effect Transistors or FET's. These devices have the advantage over bipolar transistors of having extremely high input impedance along with a low noise output making them ideal for use in amplifier circuits that have very small input signals. The design of an amplifier circuit based around a junction field effect transistor or "JFET", is exactly the same principle as that for the bipolar transistor circuit. A suitable quiescent point or "Q-point" needs to be found for the correct biasing of the JFET amplifier circuit with Common-source (CS) configuration. The JFET gate voltage Vg is biased through the potential divider network set up by resistors R1 and R2 and is biased to operate within its saturation region which is equivalent to the active region of the bipolar junction transistor. Unlike a bipolar transistor circuit, the junction FET takes virtually no input gate current allowing the gate to be treated as an open circuit. We can compare the JFET to the bipolar junction transistor (BJT) in the following table. JFET to BJT Comparison JFET Gate, (G) Drain, (D) Source, (S) Gate Supply, (VG) Drain Supply, (VDD) Drain Current, (iD) BJT Base, (B) Collector, (C) Emitter, (E) Base Supply, (VB) Collector Supply, (VCC) Collector Current, (iC)
The input signal, (Vin) of the common source JFET amplifier is applied between the Gate terminal and ground. With a constant value of gate voltage Vg applied the JFET operates within its "Ohmic region" acting like a linear resistive device. The drain circuit contains the load resistor, Rd. The output voltage, Vout is developed across this load resistance. The efficiency of the common source JFET amplifier can be improved by the addition of a resistor, Rs included in the source lead with the same drain current flowing through this resistor. Resistor, Rs is also used to set the JFET amplifiers "Q-point". When the JFET is switched fully "ON" a voltage drop equal to (Rs x Id) is developed across this resistor raising the potential of the source. Since the N-Channel JFET is a depletion mode device and is normally "ON", a negative gate voltage with respect to the source is required to modulate or control the drain current. This negative voltage can be provided by biasing from a separate power supply voltage or by a self biasing arrangement as long as a steady current flows through the JFET even when there is no input signal present and Vg maintains a reverse bias of the gate-source pn junction. In this example the biasing is provided from a potential divider network allowing the input signal to produce a voltage fall at the gate as well as voltage rise at the gate with a sinusoidal signal. Any suitable pair of resistor values in the correct proportions would produce the correct biasing voltage so the DC gate biasing voltage Vg is given as:
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Note that this equation only determines the ratio of the resistors R1 and R2, but in order to take advantage of the very high input impedance of the JFET as well as reducing the power dissipation within the circuit, we need to make these resistor values as high as possible, with values in the order of 1 to terminal above 0v or ground level. This voltage drop across Rs due to the drain current provides the necessary reverse biasing condition across the gate resistor, R2 effectively generating negative feedback. In order to keep the gate-source junction reverse biased, the source voltage, Vs needs to be higher than the gate voltage, Vg. This source voltage is therefore given as:
Then the Drain current, Id is also equal to the Source current, Is as "No Current" enters the Gate terminal and this can be given as:
This potential divider biasing circuit improves the stability of the common source JFET amplifier circuit when being fed from a single DC supply compared to that of a fixed voltage biasing circuit. Both resistor, Rs and the source by-pass capacitor, Cs serve basically the same function as the emitter resistor and capacitor in the common emitter bipolar transistor amplifier circuit, namely to provide good stability and prevent a reduction in the loss of the voltage gain. However, the price paid for a stabilized quiescent gate voltage is that more of the supply voltage is dropped across Rs.The the value in farads of the source bypass capacitor is generally fairly high above 100uF and will be polarized. This gives the capacitor an impedance value much smaller, less than 10% of the transconductance, gm (the transfer coefficient representing gain) value of the device. At high frequencies the by-pass capacitor acts essentially as a shortcircuit and the source will be effectively connected directly to ground. Procedure:1. Study the circuit and Place the components on bread board and connect them as per given fig. 2. Connect the circuit without ac supply and check for the DC Conditions. 3. Connect the signal generator and apply a sine wave of peak-to-peak amplitude 20mV, 1kHz. Connect input and output (Vo) of the circuit to the two channels of CRO. 4. Find the gain, input and output impedance with this circuit. 5. Voltage gain for maximum undistorted output, Avm = Vo/Vi 6. Plot the frequency response curve by noting down Vo for different frequencies.
Observation:I. Set Vin =
II. Undistorted Max Vout ( from the CRO) =
Avm = Vout/Vin = From the graph, f1 = ________ Hz; f2 = ________kHz Bandwidth (BW) = f2 - f1 = ______; Gain bandwidth(GBW) = Avm * BW = _________
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To measure Zi DRB FET amplifier circuit Vin Vo
1. Adjust the input sinusoidal peak to peak in such a way that the output sine wave is not clipped. 2. Note down this value of the input Vin. 3. Note down the peak to peak amplitude of the corresponding output Vo. Let Vo=Va 4. Connect a DRB (with zero resistance included)in series with the Function generator. 5. Increase the resistance in DRB and observe the magnitude of the output Vo simultaneously on the Oscilloscope. 6. When the magnitude of the output Vo is reduced to half of its original value, stop varying the potentiometer further and remove the DRB from the circuit. Vo=Va/2 7. Measure the value of the resistance in DRB and this measured value will be the input impedance ( Ri) of the circuit. To measure Zo (Output Impedance)
FET amplifier circuit Vin
DRB
Vo
1. Adjust the input sinusoidal peak to peak in such a way that the output sine wave is not clipped. 2. Note down this value of the input Vin. 3. Note down the peak to peak amplitude of the corresponding output Vo . Let Vo=Va 4. Connect a DRB ( with maximum resistance included) in parallel with the load as shown in fig c. 5. Decrease the DRB and observe the magnitude of the output Vo simultaneously on the Oscilloscope. 6. When the magnitude of the output Vo is reduced to half of its original value, stop varying the resistance further and remove the DRB from the circuit. Vo=Va/2 7. Measure the value of the DRB and this measured value will be the output impedance ( Ro) of the circuit.
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Result:Parameters Avm =Vo/Vi Zi Zo
Also compare BJT and FET amplifier in terms of above parameters.
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ELECTRONIC DEVICES AND CIRCUITS LAB MANUAL Experiment no 1: DIODE CLIPPING CIRCUITS

RfRr . The ratio Rr/Rf can

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Biased Clipping circuits Component Values:Vin

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Fig 1a:- Positive Clamper Circuit Component Values

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Fig 1b:- Positive Clamper Circuit

Fig 2a:- Negative Clamper Circuit

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Fig 2b:- Negative Clamper Circuit

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Fig.1.A Half wave voltage multiplier circuit

Fig.1.B Full wave voltage multiplier circuit

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Experiment 4: Determination of h- parameters using static characteristic of a transistor in CE mode

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Parameters hie hre hfe hoe

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VRC= So Ic = VRC / Rc = Max Vout ( from the CRO) =

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ELECTRONIC DEVICES AND CIRCUITS LAB MANUAL

Observation:I. Biasing values VCE= II. Set Vin = Undistorted

Max Vout ( from the CRO) =

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ELECTRONIC DEVICES AND CIRCUITS LAB MANUAL

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ELECTRONIC DEVICES AND CIRCUITS LAB MANUAL

Model Frequency response Curve :-