MODULE I

ANALOG MOS CIRCUIT DESIGN

Dept. of AE&I, GEC Kozhikode

Analog vs. Digital

Advances in digital computing and IC technologies d iven !ocus o!

design into digital domain

Digital domain" ease o! handling#

elia$ilit% and implementation possi$ilities p omoted eplacement o! t aditional analog !unctions o! natu al signals# t ansmission# senso s# (i eless communication etc)

Digital !unctions can&t still eplace analog counte pa t li'e p ocessing Digital ci cuits t ade*o!! $+( speed and po(e ) Analog ci cuit design

depends on multi*dimensional !acto s speed# po(e # voltage# ! e,uenc%# gain# p ecision etc)
Analog designe s a e in demand - ,uic' unde standing o! ci cuit# good

mathematical s'ills# c eative !o ci cuit topologies i)e) good anal%tical and design s'ills e,ui ed
Dept. of AE&I, GEC Kozhikode

CMOS vs. Bipolar

CMOS technolog% is dominant ove $ipola technolog%

due" lo( po(e dissipation# $ette integ ation densit% and less !a$ ication cost
Int insic speed o! MOS devices has $een imp oved ove

past decades and p ime candidate !o analog designs compa ed to $ipola devices
CMOS has $een the choice to meet the scaling as pe

Moo e&s la( o! integ ation i)e) num$e o! t ansisto s integ ated dou$les eve % .)/ %ea s 0/1m in .234 4).51m in 0444)

Dept. of AE&I, GEC Kozhikode

MOS device physics

Good unde standing o! MOS device models e,ui ed !o

analog designs than digital 6t ansisto is acting as s(itch7

Second o de e!!ects and scaling in MOS impacts analog

design pe !o mance
Simplest $ehavio al model o! MOS t ansisto 8hen 9g : 9th O;; and 9g < 9th ON

Dept. of AE&I, GEC Kozhikode

MOSFET structure

n*t%pe MOS device st uctu e !a$ icated on p*su$st ate D ain and sou ce" heav% di!!usion egions Gate" =ol%silicon o metal (ith SiO0 isolation Channel Length Le!! > Ld a(n - 0Ld 6side di!!usion7 O?ide thic'ness To? and Le!! a e impo tant design pa amete s
Dept. of AE&I, GEC Kozhikode

CMOS (nMOS+pMOS

nMOS device

pMOS device

CMOS device Dept. of AE&I, GEC Kozhikode

MOS sy!"ols

;ou Te minal

Analog model

Digital model Dept. of AE&I, GEC Kozhikode

MOS #$% Characteristics

Gene ation and t anspo t o! cha ge ca ie s as a !unction o! MOS;ET

inte nal voltages at device level

Dept. of AE&I, GEC Kozhikode

Threshold %oltage (%th

Minimum gate*to*sou ce voltage to tu n on the MOS

device !o conduction

Co? > @o?+to? Dept. of AE&I, GEC Kozhikode

Derivation o& #$% characteristics

D ain cu ent Id as !unction o! MOS te minal voltages 9gs# 9ds Cu ent !lo( th ough uni!o m c oss section o! semiconducto

Uni!o m cha ge densit% pe unit channel length o! MOS;ET 6condition

9gA9th and 9ds>Be o7

8hen 9dsA4 channel cha ge densit% va ies as !unction o! length 4:?:L

Integ ating ove ange

Dept. of AE&I, GEC Kozhikode

 Setting the $ounda % conditions and evaluate and Id is constant along

the channel

L is the e!!ective channel length) Cu ent as a pa a$olic !unction o!

voltage and pea' value at and 8+L is called as aspect atio

called as ove *d ive voltage

Dept. of AE&I, GEC Kozhikode

MOSFET operation !odes

Linea esisto model" Deep t iode egion app o?imation

Dept. of AE&I, GEC Kozhikode

Saturation !ode
8hen

MOS;ET ope ates in satu ation egion) Cu ent cu ve doesn&t !ollo( pa a$olic !unction i)e) cu ent elativel% constant

Dept. of AE&I, GEC Kozhikode

Channel pinch'o&&
As Cd is p opotional to 9gs*96?7*9th hence 9ds>9gs*9th

i)e) Cd>Be o 8hen 9ds is slightl% g eate than 9gs*9th inve sion la%e stops at ?DL te med as channel pinch*o!!

Dept. of AE&I, GEC Kozhikode

 ;o =MOS;ET" D ain cu ent e,uation (hen device ope ating in

linea and satu ation egions

T ansconductance pa amete " ho( (ell device conve ts voltage into

cu ent i)e) !igu e me it) gm in satu ation egion is ecip ocal o! Ron in t iode egion

Second order e&&ects

Most assumptions and app o?imations in anal%sis and de ivation is not

valid in analog li'e digital ci cuits

Body effect" Eul' is at lo(e potential than sou ce te minal 9s$FBe o i)e

9E : 4

Dept. of AE&I, GEC Kozhikode

Channel length !odulation

Channel length is educed as 9ds inc eases i)e) L&>L*GL

$% linea app?) GL+L H I9ds) Device cu ent in satu ation

T ansconductance o! device $ecome

Dept. of AE&I, GEC Kozhikode

Su" threshold conduction

Ideal $ehavio " (hen 9gs : 9th device tu ns o!! Su$*th eshold cu ent !lo(s even (hen 9gs:9th (ith

e?ponential dependence on 9gs simila to diode e,n)

8he e

Dept. of AE&I, GEC Kozhikode

MOS device capacitance

Device capacitance must $e conside ed !o JacK modeling

o! Analog MOS ci cuits

Eve % t(o te minals o! MOS device has capacitance

depends on $ias conditions

Dept. of AE&I, GEC Kozhikode

Device capacitances divided into

C." O?ide capacitance $+( gate and channel 8LCo? C0" Depletion capacitance $+( channel and su$st ate

CL#CM" Ove lap capacitance $+( S*D and gate i)e) Cov C/#C3" Nunction capacitance $+( S*D and su$st ate can $e

decomposed into CO 6$ottom*plate7 and COs( 6side*(all7 components

Dept. of AE&I, GEC Kozhikode

MOS s!all signal !odel

La ge signal model" ,uad atic $ehavio o! cu ent (ith device voltage (ith

capacitance model i)e) help!ul in anal%Bing ci cuits (ith non*linea $ehavio

Small signal model" App o?imation o! la ge signal model to simpli!% the

anal%sis i)e) linea $ehavio )

MOS device ope ating in satu ation egion in most analog ci cuits) Modeling components"
Cu ent sou ce gmVgs" device cu ent dependenc% on 9gs Linea

esisto r0" Channel length modulation pa amete i)e) device cu ent dependenc% on 9ds on $ul' potential

Cu ent sou ce gmbVbs" Eod% e!!ect pa amete i)e device cu ent dependenc% Device capacitances

Dept. of AE&I, GEC Kozhikode

Dept. of AE&I, GEC Kozhikode

MOS AMPLIFIERS

Dept. of AE&I, GEC Kozhikode

Single'stage A!pli&iers
Impo tant analog !unction to st engthen signals !o

d iving the loads

App o?imate and simple ci cuit models 6small signal# lo(

! e,uenc%7 used !o ampli!ie ci cuit anal%sis

Ampli!ie design is a multi dimensional optimiBation

p o$lem li'e speed# suppl% voltage# po(e # linea it%# gain# input*output impedance# voltage s(ing etc)
Input*output cha acte istics o! ampli!ie

is non*linea !unction ep esented as pol%nomial ove ange

Dept. of AE&I, GEC Kozhikode

Co!!on Source (CS A!pli&ier

Gate te minal 69gs7 sensitive to input changes and conve ts in to

d ain cu ent in load esisto i)e t ansconductance $ehavio o! MOS;ET

8hen 9in aises esults in d ain cu ent !lo( in load esisto Rd

causes 9out d op
8hen 4:9in:9outP9th 69in.7 ope ates in satu ation

Small signal gain o! the CS ampli!ie

Dept. of AE&I, GEC Kozhikode

Dept. of AE&I, GEC Kozhikode

La ge signal model !o CS stage i)e) conside channel

length modulation 6non*linea model7

Qence simpl% $% inspection o! la ge signal CS stage

ci cuit model (e get"

Dept. of AE&I, GEC Kozhikode

Source Follo(er (Co!!on Drain Used as a voltage $u!!e placed in $et(een CS ampli!ie (ith la ge gain 6Rd7 d iving a lo( impedance load i)e) to avoid loading e!!ect

Dept. of AE&I, GEC Kozhikode

Ope ation" 8hen 9in : 9th *A 9out>4) 8hen 9in A 9th#

Output !ollo(s input voltage change shi!ted $% 9gs and assume device ope ating in satu ation) Input*output cha acte istics ep esented $%

Di!!e entiating $oth sides $% 9in to o$tain Av

As

Dept. of AE&I, GEC Kozhikode

Also note that"

Qence 9oltage gain e?p ession $ecomes"

Small signal e,uivalent ci cuit (ith gain cha acte istic

Dept. of AE&I, GEC Kozhikode

Co!!on )ate (C) A!pli&ier

Unli'e CS and CD stages# ci cuit senses input at sou ce

and p oduce output at d ain te minal) Gate connected to DC $ias !o p ope ope ation) T(o con!igu ations possi$le" di ect coupling 6dc7 and capacitive coupling 6ac7

Dept. of AE&I, GEC Kozhikode

Ope ation" As 9in dec eases ! om la ge positive value !o

9inA9$*9th M. is o!! hence 9out>9dd) Once 9in:9$*9th device tu ns on in satu ation

Small signal gain"

E,uivalent ci cuit"

Dept. of AE&I, GEC Kozhikode

Cascode A!pli&ier
Cascode 6Jcascaded t iodesK7 com$ination o! CS and CG

stages !o inc eased int insic gain and output impedance values in compa ison (ith othe con!igu ation

Dept. of AE&I, GEC Kozhikode

Output voltage s(ing limited to sum o! ove d ive voltages

o! M. and M0 i)e) 9dd *A 69gs.*9th.7P69gs0*9th07 compa ed to CS stage 69dd *A 9gs*9th7

Ope ation" 8hen 9in:9th.R device M.#M0 cuto!! no cu entR

9out>9dd As 9inA9th. M. sta ts conducting and 9out d ops)

Dept. of AE&I, GEC Kozhikode

Using small signal model $elo( assuming Be o channel length

modulation voltage gain o! cascode stage is that o! CS stage as cu ent is independent o! M0 pa amete s 6gm and $od% e!!ects7

Conside ing la ge signal model (ith const cu ent sou ceR Av>gm.Rout

(he e Rout is the e!!ective output esistance 6gm$0Pgm07 o0 o. i)e) int insic gain inc eased $% M0 te m
Dept. of AE&I, GEC Kozhikode

Frequency Response

Dept. of AE&I, GEC Kozhikode

Co!!on Source (CS stage

Qigh ! e,uenc% model o! CS ampli!ie " Gain is a !unction

o! ! e,uenc% G6s7 *A G6O(7

Conside

!inite impedance due to device and node capacitance and esistance *A identi!% poles in t ans!e !unction G6s7

High frequency model and equivalent ckt of CS stage

Neglect channel length modulation and device ope ating

in satu ation) Total capacitance at input node S is"

Input pole ! e,uenc% at S is"

Total capacitance at output" Output pole ! e,uenc% is"

Qence t ans!e !unction is"

Dept. of AE&I, GEC Kozhikode

Source &ollo(er (CD stage

Used e?tensivel% as level shi!te s and $u!!e s impo tant to

'no( the impact on ! e,uenc% esponse

Not possi$le to associate poles (ith nodes S and T due to

st ong inte action th ough Cgs) Intuitive method cant $e applied he e li'e CS stage) CL is the total output load capacitance including Cs$

Dept. of AE&I, GEC Kozhikode

E% UCL at output node in e,uivalent c't"

E% U9L# summing all voltages ! om 9in"

Su$stitute value o! 9. in 9in e,uation"

Dept. of AE&I, GEC Kozhikode

Conside ing pa tial ! action o! second o de denominato

(ith distinct poles (p. :: (p0

Signi!icant pole ! e,uenc% is given $%

Dept. of AE&I, GEC Kozhikode

Co!!on )ate (C) stage

To simpli!% the anal%sis channel length modulation is

neglected)
=e !ect isolation $et(een input and output nodes i)e) no

mille coe!!icient to multiplied in t ans!e !unction esults in (ide $and esponse

Dept. of AE&I, GEC Kozhikode

Cascode stage
Cha acte iBed $% high input impedance o! CS stage and high

speed and $and(idth cha acte istic o! CG stage

E% intuitive app oach# simpli!ied t ans!e !unction can $e

de ived $% associating node $ased poles $elo("

Dept. of AE&I, GEC Kozhikode

Differential Amplifier

Dept. of AE&I, GEC Kozhikode

Di&&erential A!pli&iers
Choice o! ampli!ie in high pe !o mance analog and mi?ed signal

design due to $ette noise immunit%

Di!!e ential vs) single ended ope ation

Di!!e ential ope ation can inhe entl% eliminate suppl% voltage#

c oss tal' noise va iations int oduced in ampli!ie stages

Dept. of AE&I, GEC Kozhikode

Easic di!!e ential ampli!ie composed o! t(o identical CS

stages ope ate on t(o phases o! signal a ound a common mode level 6dc o!!set at input to ensu e devices do not tu n o!! and al(a%s in satu ation7

Dept. of AE&I, GEC Kozhikode

To ma'e device least dependent on input common mode

level connect sou ce te minals th ough a cu ent sou ce !o ma?imum voltage s(ing

Qence (hen 9in.>9in0 output common mode level

Dept. of AE&I, GEC Kozhikode

Input*output cha acte istic o! di!!e ential ampli!ie

Ma?imum and minimum output voltage levels"

As input voltage s(ing inc eases $oth sides gain 6slope o!

cu ve7 dec eases and ma?imum at 9in.>9in0

Small signal gain o! di!!e ential ampli!ie " gmRd
Dept. of AE&I, GEC Kozhikode

Di&&erential A!pli&ier ($ MOS load Linea esisto load can $e $ette

eplaced $% MOS devices !o optimum a ea and po(e dissipation

Dept. of AE&I, GEC Kozhikode

Current Mirror

Dept. of AE&I, GEC Kozhikode

Cu ent mi o is also called as Jcu ent cop%ing ci cuitK

i)e) p ovide a sta$le cu ent against p ocess# suppl% and tempe atu e va iations
E?tensivel% used as $iasing and signal p ocessing

applications

Dept. of AE&I, GEC Kozhikode

Cascode current !irror

Modi!ied cu ent mi o to compensate the cu ent va iations

due to channel length modulation dependencies) Ratio o! cu ents $ecome"

8he e 9ds.69?7>9gs. 6diode connected7>9gs0 i)e) does not

impl% 9ds069%7>9gs0 $ecause 9ds0 depends on $ias ci cuit o! M0 69p7

Dept. of AE&I, GEC Kozhikode

Modi!% the $asic cu ent mi o ci cuit to p ovide a

cascode $ias voltage !o ML 69$7 to ma'e 9ds069%7 independent on 9p esults in a cascode cu ent mi o ci cuit $elo("
Select device dimensions to satis!% the condition

Dept. of AE&I, GEC Kozhikode