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Tutorial 04s

This document contains several problems related to calculating the fraction of processor time consumed by I/O devices using different interrupt and transfer methods. The first problem calculates the processor time consumed by a device that interrupts for every byte transferred at 8 KB/s, first when interrupting for every byte, then when using two 16-byte buffers, and finally using a block transfer instruction. The second problem calculates the processor slowdown from a DMA module transferring characters at 9600 bps. The third problem calculates the bus occupancy time for a device transferring 128 bytes using DMA burst and cycle-stealing modes. The last problem estimates the maximum aggregate I/O transfer rate for a system with two selector

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Karen Conrad
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3K views

Tutorial 04s

This document contains several problems related to calculating the fraction of processor time consumed by I/O devices using different interrupt and transfer methods. The first problem calculates the processor time consumed by a device that interrupts for every byte transferred at 8 KB/s, first when interrupting for every byte, then when using two 16-byte buffers, and finally using a block transfer instruction. The second problem calculates the processor slowdown from a DMA module transferring characters at 9600 bps. The third problem calculates the bus occupancy time for a device transferring 128 bytes using DMA burst and cycle-stealing modes. The last problem estimates the maximum aggregate I/O transfer rate for a system with two selector

Uploaded by

Karen Conrad
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Tutorial #4

Problems:
7.10 Consider a system employing interrupt-driven I/O for a particular device that
transfers data at an average of 8 KB/s on a continuous basis.
a. Assume that interrupt processing takes about 100 s (i.e., the time to jump
to the interrupt service routine (ISR), execute it, and return to the main program).
Determine what fraction of processor time is consumed by this I/O device if it
interrupts for every byte.
b. Now assume that the device has two 16-byte buffers and interrupts the
processor when one of the buffers is full. Naturally, interrupt processing takes
longer, because the ISR must transfer 16 bytes. While executing the ISR, the
processor takes about 8 s for the transfer of each byte. Determine what fraction
of processor time is consumed by this I/O device in this case.
c. Now assume that the processor is equipped with a block transfer I/O
instruction such as that found on the Z8000.This permits the associated ISR to
transfer each byte of a block in only 2 s. Determine what fraction of processor
time is consumed by this I/O device in this case.
a. The device generates 8 1024 = 8192 bytes per second or a rate of one
every 122 s. If each interrupt consumes 100 s, then the fraction of
processor time consumed is 100/122 = 0.82
b. In this case, the time interval between interrupts is 16 122 = 1952 s.
Each interrupt now requires 100 s for the first byte plus the time for
transferring each remaining byte, which adds up to 8 15 = 120 s, for a total
of 220 s. The fraction of processor time consumed is 220/1952 = 0.11
c. Each interrupt requires 100 s for the first byte plus 2 15 = 30 s for the
remaining bytes, for a total of 130 s. The fraction of processor time
consumed is 130/1952 = 0.06

7.12 A DMA module is transferring characters to memory using cycle stealing,


from a device transmitting at 9600 bps. The processor is fetching instructions at
the rate of 1 million instructions per second (1 MIPS). By how much will the
processor be slowed down due to the DMA activity?
Let us ignore data read/write operations and assume the processor only fetches
instructions. Then the processor needs access to main memory once every
microsecond. The DMA module is transferring characters at a rate of 1200
characters per second, or one every 833 s.
The DMA therefore "steals" every 833rd cycle.
This slows down the processor approximately = 1/833100% = 0.12%
(Backup problems)
7.13 Consider a system in which bus cycles takes 500 ns. Transfer of bus control
in either direction, from processor to I/O device or vice versa, takes 250 ns. One
of the I/O devices has a data transfer rate of 50 KB/s and employs DMA. Data are
transferred one byte at a time.
a. Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus
mastership prior to the start of a block transfer and maintains control of the bus
until the whole block is transferred. For how long would the device tie up the bus
when transferring a block of 128 bytes?
b. Repeat the calculation for cycle-stealing mode.
a. For the actual transfer, the time needed is (128 bytes)/(50 KBps) = 2.56 ms.
Added to this is the time to transfer bus control at the beginning and end of the
transfer, which is 250 + 250 = 500 ns.
This additional time is negligible, so that the transfer time can be considered as
2.56 ms.
b. The time to transfer one byte in cycle stealing mode is 250 + 500 + 250 = 1000
ns = 1 s. Total amount of time the bus is occupied for the transfer is 128 s.
This is less than the result from part (a) by a factor of 20.

7.17 A 32-bit computer has two selector channels and one multiplexor channel.
Each selector channel supports two magnetic disk and two magnetic tape units.
The multiplexor channel has two line printers, two card readers, and 10 VDT
terminals connected to it. Assume the following transfer rates:
Disk drive = 800 KBytes/s , Magnetic tape drive = 200 KBytes/s, Line printer = 6.6
KBytes/s, Card reader = 1.2 KBytes/s and VDT = 1 KBytes/s
Estimate the maximum aggregate I/O transfer rate in this system.
Only one device at a time can be serviced on a selector channel. Thus,
Maximum rate = 800 + 800 + 2 6.6 + 2 1.2 + 10 1 = 1625.6 k Bytes/sec

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