Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd
Upload
89 views

Library IEEE

This document contains VHDL code for four different digital logic designs: 1. A 4-bit adder that uses half adders (HA) and full adders (FA) in a ripple carry configuration to add two 4-bit inputs and output the sum and carry. 2. A Mealy finite state machine with 4 states that changes its output based on the current state and input. 3. A BCD to excess-3 converter that uses a parallel-in parallel-out shift register to shift in a BCD input and adds it to a fixed value to convert it to excess-3. 4. Basic D flip-flop component used in the other designs.

Uploaded by

Adeel Hanif
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
89 views

Library IEEE

This document contains VHDL code for four different digital logic designs: 1. A 4-bit adder that uses half adders (HA) and full adders (FA) in a ripple carry configuration to add two 4-bit inputs and output the sum and carry. 2. A Mealy finite state machine with 4 states that changes its output based on the current state and input. 3. A BCD to excess-3 converter that uses a parallel-in parallel-out shift register to shift in a BCD input and adds it to a fixed value to convert it to excess-3. 4. Basic D flip-flop component used in the other designs.

Uploaded by

Adeel Hanif
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 4

4-bit Adder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.all;
entity adder is
generic (width : natural := 4);
Port ( a : in STD_LOGIC_VECTOR
(width-1 downto 0);
b : in STD_LOGIC_VECTOR
(width-1 downto 0);
sum : out
STD_LOGIC_VECTOR (width-1 downto
0);
carry : out STD_LOGIC);
end adder;
architecture Behavioral of adder is
signal c : std_logic_vector(width-1
downto 0);
component ha is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic;
s : out std_logic);
end component;
component fa is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
cout : out std_logic);
end component;
begin
L1: for i in 0 to width-1 generate
first: if i=0 generate
M1: Ha port map (
a=> a(i),
b=> b(i),
s=> sum(i),
c=> c(1));
end generate first;
mid: if (i > 0 and i < width-1)
generate
M2: fa port map (
a=> a(i),
b=> b(i),
s=> sum(i),
c=> c(i),
cout => c(i+1));
end generate mid;
last: if i =width-1 generate
M3: fa port map (

a=> a(i),
b=> b(i),
s=> sum(i),
c=> c(i),
cout => carry);
end generate last;
end generate L1;
end Behavioral;

Mealy FSM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mealy is
Port ( rst : in STD_LOGIC;
in1 : in STD_LOGIC;
clk : in STD_LOGIC;
out1 : out STD_LOGIC);
end Mealy;
architecture Behavioral of Mealy is
type state_type is (s0,s1,s2,s3);
signal p_s,n_s :state_type;
begin
--Combinational Process
comP: process(p_s,in1)
begin
case p_s is
when s0 =>
if in1 = '1' then
n_s<=s1;
out1<='0';
else
n_s<=s0;
out1<='0';
end if;
when s1 =>
if in1 = '1' then
n_s<=s2;
out1<='0';
else
n_s<=s1;
out1<='0';
end if;
when s2 =>
if in1 = '1' then
n_s<=s3;
out1<='1';
else
n_s<=s2;

out1<='0';
end if;
when s3 =>
if in1 = '1' then
n_s<=s0;
out1<='0';
else
n_s<=s3;
out1<='1';
end if;
end case;
end process;
--Sequential Process
seqP: process(clk,rst,in1)
begin
if rst ='1' then
p_s <= s0;
elsif(clk' event and clk ='1') then
p_s <= n_s;
end if;
end process;
end Behavioral;

BCD to EXCESS 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Excess3 is
Port ( qin : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
qout : out
STD_LOGIC_VECTOR (3 downto 0));
end Excess3;
architecture Behavioral of Excess3 is
signal s : STD_LOGIC_VECTOR (3
downto 0);
component Adder is
Port ( A : in STD_LOGIC_VECTOR (3
downto 0);
B : in STD_LOGIC_VECTOR (3
downto 0);
cin : in STD_LOGIC;
Sum : out
STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end component;
component ParallelOut is
Port ( q : in STD_LOGIC;

yout : inout
STD_LOGIC_VECTOR (3 downto 0);
clock : in STD_LOGIC);
end component;
begin
m1: ParallelOut port map
(
q=>qin,
yout=>s,
clock=>clk
);
m2: Adder port map
(
A=>s,
B=>"0011",
cin=>'0',
Sum=>qout);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ParallelOut is
Port ( q : in STD_LOGIC;
yout : inout
STD_LOGIC_VECTOR (3 downto 0);
clock : in STD_LOGIC);
end ParallelOut;
architecture Behavioral of ParallelOut
is
component DFF is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC);
end component;
begin
Map0: DFF port map
(d=>q,
clk=>clock,
y=>yout(3));
Map1: DFF port map
(d=>yout(3),
clk=>clock,
y=>yout(2));
Map2: DFF port map
(d=>yout(2),
clk=>clock,
y=>yout(1));
Map3: DFF port map
(d=>yout(1),
clk=>clock,
y=>yout(0));
end Behavioral;
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity DFF is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
--rst : in STD_LOGIC;
y : out STD_LOGIC);
end DFF;
architecture Behavioral of DFF is
begin

process(d,clk)
begin
if (clk' event and clk = '1') then
y<=d;
end if;
end process;
end Behavioral;

You might also like