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Dcs File With Output (BPIT)

This document contains the code and output for 10 programs written in VHDL to simulate and design various digital logic circuits. The programs implement logic gates, half adders, full adders, subtractors, multiplexers, demultiplexers, seven segment displays, Gray code converters, excess-3 code converters, and 4-bit magnitude comparators. For each program, the VHDL code, RTL schematic, technology schematic, and output waveforms are shown.

Uploaded by

Abhinav Raj
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
58 views

Dcs File With Output (BPIT)

This document contains the code and output for 10 programs written in VHDL to simulate and design various digital logic circuits. The programs implement logic gates, half adders, full adders, subtractors, multiplexers, demultiplexers, seven segment displays, Gray code converters, excess-3 code converters, and 4-bit magnitude comparators. For each program, the VHDL code, RTL schematic, technology schematic, and output waveforms are shown.

Uploaded by

Abhinav Raj
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 35

Digital Circuits & Systems II

Lab
Faculty Name:

Student Name: Parwir Kumar


Roll No.:00920807311
Semester: Vth
Branch :ECE
Section: B

Bhagwan Parshuram Institute of technology, PSP Area-4,


Sector 17, Rohini, New Delhi 110085

Students Name : Parwir Kumar


Roll No. : 00920807311
INDEX

PROGRAM NO. 1
Write a program to implement the basic logic gates using
VHDL & simulate it using Xilinx.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity basic_gate is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
or_out : out STD_LOGIC;
and_out : out STD_LOGIC;
xor_out : out STD_LOGIC;
nand_out : out STD_LOGIC;
nor_out : out STD_LOGIC;
xnor_out : out STD_LOGIC;
not_out : out STD_LOGIC);
end basic_gate;
architecture data_flow of basic_gate is
begin
or_out <= x or y;
and_out <= x and y;
xor_out <= x xor y;
xnor_out <= x xnor y;
nor_out <= x nor y;
nand_out <= x nand y;
not_out <= not x;
end data_flow;

OUTPUT:-

PROGRAM NO. 2
Write a program to implement half adder using VHDL &
simulate it using Xilinx.
a) USING DATAFLOW MODELLING STYLE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity half_adder is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end half_adder;
architecture dataflow of half_adder is
begin
sum <= x xor y;
carry <= x and y;
end dataflow;

OUTPUT:-

b) USING BEHAVIORAL MODELLING STYLE


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity half_adder is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end half_adder;
architecture Behavioral of half_adder is
begin
process(x,y)
begin
sum <= x xor y;
carry <= x and y;
end process;
end Behavioral;

PROGRAM NO. 3
Write a program to implement full adder using VHDL &
simulate it using Xilinx.
a) USING DATAFLOW MODELLING STYLE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end full_adder;
architecture dataflow of full_adder is
begin
sum <= ((x xor y) xor z);
carry <= (( x and y ) or (y and z) or (z and x));
end dataflow;

OUTPUT:-

b) USING BEHAVIORAL MODELLING STYLE


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end full_adder;
architecture Behavioral of full_adder is
begin
process(x,y,z)
begin
sum <= ((x xor y) xor z);
carry <= (( x and y ) or (y and z) or (z and x));
end process;
end Behavioral;

PROGRAM NO-4
TO DESIGN AND SIMULATE HALF SUBTRACTER AND
FULL SUBTRACTOR CIRCUIT USING XILINX
VHDL CODE:library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Subtractor is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
diff_halfsubtractor : out STD_LOGIC;
diff_fullsubtractor : out STD_LOGIC;
borr_halfsubtractor : out STD_LOGIC;
borr_fullsubtractor : out STD_LOGIC);
end Subtractor;
architecture Behavioral of Subtractor is
begin
diff_halfsubtractor <= a xor b;
borr_halfsubtractor <= (not a) and b;
diff_fullsubtractor <= a xor b xor c;
borr_fullsubtractor <= ((not a) and b) or ((not a) and c) or (b and c);
end Behavioral;

RTL Schematic

Waveform

PROGRAM NO-5
TO DESIGN AND SIMULATE 4X1 MULTIPLEXER USING XILINX
VHDL CODE:library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_4_1 is
port(s: in bit_vector(0 to 1); d: in bit_vector(0 to 3);
y: out bit);
end mux_4_1;
architecture mux_4_1 of mux_4_1 is
begin
process(s,d)
begin
if s="00" then
y<=d(0);
elsif s="01" then
y<=d(1);
elsif s="10" then
y<=d(2);
else
y<=d(3);
end if;
end process;
end mux_4_1;
RTL Schematic

Technology Schematic

Waveform

PROGRAM NO-6
TO DESIGN AND SIMULATE 1X4 DEMULTIPLEXER
USING XILINX
VHDL CODE:library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1_4 is
port (
out0 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
out3 : out std_logic;
sel : in std_logic_vector(1 downto 0);
bitin : in std_logic
);
end demux1_4;
architecture Behavioral of demux1_4 is
begin
process(bitin,sel)
begin
case sel is
when "00" => out0 <= bitin; out1 <= '0'; out2 <= '0'; out3 <='0';
when "01" => out1 <= bitin; out0 <= '0'; out2 <= '0'; out3 <='0';
when "10" => out2 <= bitin; out0 <= '0'; out1 <= '0'; out3 <='0';
when others => out3 <= bitin; out0 <= '0'; out1 <= '0'; out2 <='0';
end case;
end process;
end Behavioral;

RTL Schematic

Technology Schematic

Waveform

PROGRAM NO-8

TO DESIGN AND SIMULATE BCD TO SEVEN SEGMENT


DECODER USING XILINX
VHDL CODE:LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BCD2LED IS
PORT (D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
O:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END BCD2LED;
ARCHITECTURE RTL OF BCD2LED IS
BEGIN
PROCESS (D)
BEGIN
CASE D IS
WHEN "0000"=>O<="1111110";
WHEN "0001"=>O<="1100000";
WHEN "0010"=>O<="1011010";
WHEN "0011"=>O<="1110011";
WHEN "0100"=>O<="1100101";
WHEN "0101"=>O<="0110111";
WHEN "0110"=>O<="0111111";
WHEN "0111"=>O<="1100010";
WHEN "1000"=>O<="1111111";
WHEN "1001"=>O<="1110111";
WHEN OTHERS=>O<="0000000";
END CASE;
END PROCESS;
END RTL;

RTL(register-transfer level) Schematic

Technology Schematic

Waveform

PROGRAM NO-9
TO DESIGN AND SIMILATE BCD TO GRAY CODE
CONVERTER
VHDL CODE :library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gray is
Port ( i : in STD_LOGIC_VECTOR(3 downto 0);
o : out STD_LOGIC_VECTOR(3 downto 0));
end gray;

architecture Behavioral of gray is


begin
o(3) <= i(3);
o(2) <= i(3) xor i(2);
o(1) <= i(2) xor i(1);
o(0) <= i(1) xor i(0);
end Behavioral;

RTL Schematic

Technology Schematic

Waveform

PROGRAM NO-9
TO DESIGN AND SIMULATE BCD TO EXCESS 3 CODE
CINVERTER USING XILINX
VHDL CODE:library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity saurabh is
Port ( b : in STD_LOGIC_VECTOR(3 downto 0);
e : out STD_LOGIC_VECTOR( 3 downto 0));
end saurabh;

architecture Behavioral of saurabh is


begin
process(b)
begin
e<=b + 3;
end process;
end Behavioral;

RTL Schematic

Technology Schematic

Waveform

PROGRAM NO-10
TO DESIGN AND SIMULATE 4 BIT MAGNITUDE COMPARATOR
VHDL CODE:library ieee;
USE ieee.Std_logic_1164.ALL;
ENTITY mag4comp IS
PORT(a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
greater,less,equal : OUT STD_LOGIC);
END mag4comp;
ARCHITECTURE behaviour OF mag4comp IS
BEGIN
PROCESS(a,b)
BEGIN
IF (a > b) THEN
greater <= '1';
equal <= '0' ;
less <= '0' ;
ELSIF (a < b) THEN
less <= '1' ;
equal <= '0' ;
greater <= '0';
ELSIF (a = b) THEN
equal <= '1';
greater <= '0';
less <= '0';
END IF;
END PROCESS;
END behaviour;

RTL Schematic

Technology Schematic

Waveform

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