DIGITAL CIRCUITS & SYSTEMS II LAB ETEC 351

Faculty: Mr. Amit Saxena

Student Name: Sandeep rawat Roll No. : 01796402811 Semester : V (B.Tech ECE) Group : 5E789

Maharaja Agrasen Institute Of Technology

INDEX PAPER CODE Name of the student University Roll No. Branch Section/ Group PRACTICAL DETAILS : : : : : ETEC 351 Sandeep rawat 01796402811 B.Tech ECE (IInd Shift) 5E789

S.No.

Experiment

Submission Date

Sign.

Remarks

EXPERIMENT NO.1 AIM: To simulate the Logic Gates using data flow modeling.

AND GATE VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity AND_2 is port(a,b:in std_logic; y:out std_logic); end AND_2; architecture AND_A of AND_2 is begin y <= a AND b; end AND_A; OUTPUT:

OR GATE VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity OR_2 is port(a,b:in std_logic; y:out std_logic); end OR_2; architecture OR_A of OR_2 is begin y <= a OR b; end OR_A;

OUTPUT:

NOT GATE VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity NOT_2 is port(a:in std_logic; y:out std_logic); end NOT_2; architecture NOT_A of NOT_2 is begin y <= NOT a; end NOT_A; OUTPUT:

NAND GATE VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity NAND_2 is port(a,b:in std_logic; y:out std_logic); end NAND_2; architecture NAND_A of NAND_2 is begin y <= a NAND b; end NAND_A; OUTPUT:

NOR GATE VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity NOR_2 is port(a,b:in std_logic; y:out std_logic); end NOR_2; architecture NOR_A of NOR_2 is begin y <= a NOR b; end NOR_A;

OUTPUT:

XOR GATE VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity XOR_2 is port(a,b:in std_logic; y:out std_logic); end XOR_2; architecture XOR_A of XOR_2 is begin y <= a XOR b; end XOR_A; OUTPUT:

XNOR GATE VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity XNOR_2 is port(a,b:in std_logic; y:out std_logic); end XNOR_2; architecture XNOR_A of XNOR_2 is begin y <= a XNOR b; end XNOR_A; OUTPUT:

EXPERIMENT NO.2 AIM: To simulate the following using data flow modeling. Half Adder Full Adder

HALF ADDER VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity HADD is port(a,b:in std_logic; s,c:out std_logic); end HADD; architecture HADD1 of HADD is begin s <= a XOR b; c <= a AND b; end HADD1; OUTPUT:

FULL ADDER VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity FADD is port(x,y,z : in std_logic; s,c : out std_logic); end FADD; architecture FADD1 of FADD is begin s <= (x XOR y) XOR z; c <= ((x XOR y) AND z ) OR (x AND y); end FADD1; OUTPUT:

EXPERIMENT NO. 3 AIM: To simulate the following using data flow modeling: Half Subtractor Full Subtractor HALF SUBTRACTOR VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity HSUB_2 is port ( x,y: in bit; D,B: out bit); end HSUB_2; architecture HSUB_A of HSUB_2 is begin D <= ( x XOR y ); B <= ((NOT x) AND y); end HSUB_A;

OUTPUT:

FULL SUBTRACTOR VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity FSUB_2 is port ( x, y, z : in bit; D,B : out bit); end FSUB_2; architecture FSUB_A of FSUB_2 is begin D <= ( x XOR (y XOR z)); B <= (z AND(NOT( x XOR y))OR((NOT x)AND y)) ; end FSUB_A;

OUTPUT:

EXPERIMENT NO. 4 AIM: To simulate BCD to decimal decoder using data flow modeling. VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity bcdtodec is port ( a0,a1,a2,a3 : in bit; d0,d1,d2,d3,d4,d5,d6,d7,d8,d9 : out bit); end bcdtodec; architecture bcdtodec_ar of bcdtodec is begin d0 <= (not a0)and(not a1)and(not a2)and(not a3); d1 <= a0 and(not a1)and(not a2)and(not a3); d2 <= (not a0)and a1 and(not a2)and(not a3); d3 <= a0 and a1 and (not a2)and(not a3); d4 <= (not a0)and(not a1)and a2 and (not a3); d5 <= a0 and (not a1)and a2 and(not a3); d6 <= (not a0)and a1 and a2 and (not a3); d7 <= a0 and a1 and a2 and (not a3); d8 <= (not a0)and(not a1)and(not a2)and a3; d9 <= a0 and (not a1)and(not a2)and a3; end bcdtodec_ar;

OUTPUT:

EXPERIMENT NO. 5 AIM: To simulate Binary to Gray Convertor using data flow modeling. VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity b2g is port( b0,b1,b2,b3: in bit; g0,g1,g2,g3: out bit); end b2g; architecture b2g_ar of b2g is begin g3 <=b3; g2 <=b3 xor b2; g1 <=b2 xor b1; g0 <=b1 xor b0; end b2g_ar; OUTPUT:

EXPERIMENT NO. 6 AIM: To simulate Gray to Binary Convertor using data flow modeling. VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity g2b is port( g0,g1,g2,g3: in bit ; b0,b1,b2,b3: inout bit); end g2b; architecture g2b_ar of g2b is begin b3<=g3; b2<=b3 xor g2; b1<=b2 xor g1; b0<=b1 xor g0; end g2b_ar; OUTPUT:

EXPERIMENT NO. 7 AIM: To simulate 4X1 Multiplexer VHDL CODE: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mux_4x1 is port( o: in std_logic_vector(3 downto 0); u: out std_logic; b: in std_logic_vector(1 downto 0)); end mux_4x1; architecture mux_ar of mux_4x1 is begin process(o,b) begin case b is when "00" => u<= o(0); when "01" => u<= o(1); when "10" => u<= o(2); when "11" => u<= o(3); when others => null; end case; end process; end mux_ar; OUTPUT:

EXPERIMENT NO. 8 AIM: To simulate 2X4 Decoder using data flow modeling. VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity decoder2_4 is port( s0 : in std_logic; s1 : in std_logic; en : in std_logic; z : out std_logic_vector(3 downto 0) ); end decoder2_4; architecture decoder_ar of decoder2_4 is signal s0bar,s1bar:std_logic; begin s0bar<= not s0; s1bar<= not s1; z(3)<= s0bar and s1bar and en; z(2)<= s0bar and s1 and en; z(1)<= s0 and s1bar and en; z(0)<= s0 and s1 and en; end decoder_ar;

OUTPUT: