TABLE OF CONTENT

List of experiments:
Serial Experiment name Date of Faculty’
no.
completion Signatur
1 All the basic gates :- OR,AND
,NOR,XOR,XNOR,NOT,NAND
2 Half adder and full adder

3 Half subtractor and full subtractor

4 2:1 MUX ,4:1 MUX

5 1:4 DEMUX, 1:8 DEMUX

6 3:8 Decoder
7 8:3 Encoder
8 4 – bit Parallel Adder
9 4 – bit Parity Checker
10 4 – bit Parity Generator
 Write the steps followed to create a new VHDL
project in Xilinx Vivado

Steps:
1. Open the vivado software in the system.
2. For creating a project , click on ‘create project’ under ‘Quick
Start’ .
3. A window will pop up where we will define the project name
.then , click on ‘next’.
4. Now, ‘project type’ window pops up , click on RTL project
option , the click on next.
5. ‘Default part’ window appears.its for choosing default Xilinx
part or board for our project. So, in that , just click on next.
6. Then, we get ‘project summary’ window.click on ‘Finish’. In
such a way ,our new project gets formed . We reach to our
VHDL platform to write code and simulate them.
 Experiment no.-1

Write a VHDL program for all basic gates :

i) OR gate
Code:
entity or_1 is
port(x , y : in bit ; z:out bit);
end or1;
architecture or_arch of or_1 is
begin
z<= x or y;
end or_arch;
output waveform

AND gate
Code:
entity and1 is
port
(x , y : in bit ; z:out bit);
end and1;
architecture and_arch of and1 is
begin
z<= x and y;
end and_arch;
output waveform

XOR gate
Code:
entity xor1 is
port(x , y : in bit ; z:out bit);
end xor1;
architecture xor_arch of xor1 is
begin
process(x, y)
begin -- compare to truth table
if (x/=y) then
z <= '1';
else
z <= '0';
end if;
end process;
end xor_arch;

output waveform

NOT gate
Code:
entity not1 is
port
(x: in bit ; z:out bit);
end not1;
architecture not_arch of not1 is
begin
z<= not x;
end not_arch;
 output waveform

NOR gate
Code:
entity nor1 is
port(x , y : in bit ; z:out bit);
end nor1;
architecture nor_arch of nor1 is
begin
process(x, y)
begin
if (x='0' and y='0') then
z <= '1';
else
 z <= '0';
end if;
end process;
end nor_arch;

output waveform

NAND gate
Code:
entity nand1 is
port
(x , y : in bit ; z:out bit);
end nand1;
architecture nand_arch of nand1 is
begin
z<= x nand y;
end nand_arch;
 Output waveform

XNOR gate
Code:

library ieee;

use ieee.std_logic_1164.all;

entity xnor1 is

port

( x, y: in std_logic;z: out std_logic);

end xnor1;

architecture xnor_arch of xnor1 is

begin

process(x, y)

begin
if (x/=y) then

z <= '0';

else

z <= '1';

end if;

end process;

end xnor_arch;

output waveform

EXPERIMENT NO.-2
Write a VHDL code for half adder and full adder

i)Half adder
Code:
entity ha is
port( a,b : in bit ; s,c : out bit);
end ha;
architecture ha_arch of ha is
begin
s<= a xor b; c<= a and b;
end ha_arch;

output waveform

ii) Full adder

Code:
entity fa is
port( x,y,cin :in bit; s, cout :out bit);
end fa;
architecture fa_arch of fa is
begin
s<= x xor y xor cin;
cout<= ( x and y )or ( x and cin) or (y and cin);
end fa_arch;
output waveform

EXPERIMENT NO.-3
Write a VHDL program for half subtractor and full
subtractor

i) Half subtractor
Code:
entity hs is
port( a,b :in bit; d,bor :out bit);
end hs;
architecture hs_arch of hs is
 begin
d<= a xor b;
bor<= (not a) and b;
end hs_arch;

output waveform

ii) Full subtractor

Code:
entity fs is
port( x,y,bin :in bit; d, bout :out bit);
end fs;
architecture fs_arch of fs is
begin
d<= x xor y xor bin;
bout<= ((not x) and y )or ((not x) and bin) or (y and bin);
end fs_arch;
output waveform

EXPERIMENT NO.-4
Write a VHDL code for 2:1 and 8:1 MUX

i)2:1 MUX
Code:
entity mux21 is
port (a0,a1,s:in bit; z:out bit);
end mux21;
architecture mux21_arch of mux21 is
begin
process(s, a0, a1)
begin
if s = '0' then
z<=a0;
else
z<= a1;
end if;
end process;
end mux21_arch;

Output waveform of MUX 2:1

ii)8:1 MUX
Code:
USE IEEE.STD_LOGIC_1164.ALL;
entity mux81 is
port (DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SEL:IN
STD_LOGIC_VECTOR(2 DOWNTO 0);DOUT:OUT STD_LOGIC);
end mux81;
architecture arch of mux81 is
begin
process(DIN,SEL)
begin
CASE SEL is
when "000"=>DOUT<=DIN(0);
when "001"=>DOUT<=DIN(1);
when "010"=>DOUT<=DIN(2);
when "011"=>DOUT<=DIN(3);
when "100"=>DOUT<=DIN(4);
when "101"=>DOUT<=DIN(5);
when "110"=>DOUT<=DIN(6);
when "111"=>DOUT<=DIN(7);
when OTHERS=> DOUT<='Z';
end CASE;
end PROCESS;
end arch;
output waveform

EXPERIMENT NO.-5
Write a VHDL code for 1:4 DEMUX and 1:8 DEMUX
i)1:4 DEMUX
Code:
entity demux14 is
port( d: in bit_vector(3 downto 0);
s: in bit_vector(1 downto 0);
f:out bit);
end demux14;
architecture demux_arch of demux14 is
begin
f<=d(0) when s="00" else
d(1) when s="01" else
d(2) when s="10"
else d(3) when s="11" ;
end demux_arch;

output waveform

ii)1:8 DEMUX
Code:
entity demux18 is
port( d: in bit_vector(7 downto 0); s: in bit_vector(2 downto 0); f:out bit);
end demux18;
architecture demux_arch of demux18 is
begin
f<=d(0) when s="000" else
d(1) when s="001" else
d(2) when s="010" else
d(3) when s="011" else
d(4) when s="100" else
d(5) when s="101" else
d(6) when s="110" else
d(7) when s="111";
end demux_arch;

output waveform

EXPERIMENT NO.-6
Write a VHDL code for 3:8 DECODER

3:8 Decoder
Code:
entity dec38 is
port( inp : in bit_vector(2 downto 0); outp : out bit_vector(7 downto 0));
end dec38;
architecture arch of dec38 is
begin
outp(0) <= (not inp(2)) and (not inp(1)) and (not inp(0));
outp(1) <= (not inp(2)) and (not inp(1)) and inp(0);
outp(2) <= (not inp(2)) and inp(1) and (not inp(0));
outp(3) <= (not inp(2)) and inp(1) and inp(0);
outp(4) <= inp(2) and (not inp(1)) and (not inp(0));
outp(5) <= inp(2) and (not inp(1)) and inp(0);
outp(6) <= inp(2) and inp(1) and (not inp(0));
outp(7) <= inp(2) and inp(1) and inp(0);
end arch;

Output waveforms of 3:8 DECODER

 EXPERIMENT NO.-7
Write a VHDL code for 8:3 ENCODER

8:3 Encoder
Code:
library ieee;
use ieee.std_logic_1164.all;
entity priority is
port ( sel : in std_logic_vector (7 downto 0);
code :out std_logic_vector (2 downto 0));
end priority;
architecture archi of priority is
begin
code <= "000" when sel(0) = '1' else
"001" when sel(1) = '1' else
"010" when sel(2) = '1' else
"011" when sel(3) = '1' else
"100" when sel(4) = '1' else
"101" when sel(5) = '1' else
"110" when sel(6) = '1' else
"111" when sel(7) = '1' else
"---"; end arch;
Output waveforms of 8:3 ENCODER
 EXPERIMENT NO.-8
Write a VHDL code for 4 – BIT PARALLEL ADDER

CODE:

entity binadd is
port(
A:IN STD_LOGIC_VECTOR(3 downto 0);
B:IN STD_LOGIC_VECTOR(3 downto 0);
Cin:IN STD_LOGIC;
S:out STD_LOGIC_VECTOR(3 downto 0);
Carryout:out std_logic
);
end binadd;

architecture str of binadd is

component fa is
port(
a,b,c:in std_logic;
co:out std_logic;
s:out std_logic
);
end component;
signal temp1,temp2,temp3:std_logic;
begin
fa0:fa port map(a=>A(0),b=>B(0),c=>Cin,co=>temp1,s=>S(0));
fa1:fa port map(a=>A(1),b=>B(1),c=>temp1,co=>temp2,s=>S(1));
fa2:fa port map(a=>A(2),b=>B(2),c=>temp2,co=>temp3,s=>S(2));
fa3:fa port map(a=>A(3),b=>B(3),c=>temp3,co=>Carryout,s=>S(3));
end str;
Output waveform of 4 bit parallel adder
 EXPERIMENT NO.-9
Write a VHDL code for 4 BIT PARITY CHECKER

CODE:
entity bus_parity is
generic(
WPARIN : integer := 8
);
port(
parity_in : in std_logic_vector(WPARIN-1 downto 0);
parity_out : out std_logic
);
end entity;

architecture rtl of bus_parity is

begin
process(parity_in)
variable i : integer;
variable result: std_logic;
begin
result := '0';
for i in parity_in'range loop
result := result xor parity_in(i);
end loop;
parity_out <= result;
end architecture;
 EXPERIMENT NO.-10
Write a VHDL code for 4 BIT PARITY GENERATOR
CODE:
Entity parity_sk is
Port(A,B,C,D : in std_logic ; ep , op : out std_logic);
End parity_sk
Architecture parity_sks of parity_sk is
Begin
Ep <= ((AxnorB ) xnor (CxnorD));
Op <= not ((AxnorB) xnor (CxnorD));
End parity_sks;

Output waveform of 4 bit parity generator