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Assignment 1

The document contains 4 tasks: 1. Write a VHDL description for a 74154 4-to-16 decoder using a datasheet and test in Quartus II. 2. Write a VHDL description for a 4-bit binary-to-gray code converter and test in Quartus II. 3. Write a VHDL description for a 4-bit gray-to-binary code converter and test in Quartus II. 4. Implement a truth table-based design in VHDL, test in Quartus II, and include a waveform file.

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phyrdows
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391 views

Assignment 1

The document contains 4 tasks: 1. Write a VHDL description for a 74154 4-to-16 decoder using a datasheet and test in Quartus II. 2. Write a VHDL description for a 4-bit binary-to-gray code converter and test in Quartus II. 3. Write a VHDL description for a 4-bit gray-to-binary code converter and test in Quartus II. 4. Implement a truth table-based design in VHDL, test in Quartus II, and include a waveform file.

Uploaded by

phyrdows
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1. Perform an Internet search and find the 74154 4-to-16 decoder datasheet.

From the
functional description given in the datasheet, write a VHDL description for a 74154 4-to16 decoder. Use only STD_LOGIC and STD_LOGIC_VECTOR data types in constructing
your design. Enter the design into the Quartus II software and verify the syntax
correctness by compiling the design. The design should compile without error. Use
suggested style guidelines for your VHDL source code. Turn in both the datasheet and
the VHDL source.

Answer :
library ieee ;
use ieee.std_logic_1164.all;
entity decoder2 is
port (a, b, c,d : in std_logic ;
y : out std_logic_vector (15 downto 0) ) ;
end decoder2 ;
architecture structural of decoder2 is
signal abcd : std_logic_vector (3 downto 0) ;
begin
process(a,b,c,d)
begin
abcd <= a & b & c& d ;
case abcd is
when "0000"=> y<="0000000000000001";
when "0001"=> y<="0000000000000010";
when "0010"=> y<="0000000000000100";
when "0011"=> y<="0000000000001000";
when "0100"=> y<="0000000000010000";
when "0101"=> y<="0000000000100000";
when "0110"=> y<="0000000001000000";
when "0111"=> y<="0000000010000000";
when "1000"=> y<="0000000100000000";
when "1001"=> y<="0000001000000000";
when "1010"=> y<="0000010000000000";
when "1011"=> y<="0000100000000000";
when "1100"=> y<="0001000000000000";
when "1101"=> y<="0010000000000000";
when "1110"=> y<="0100000000000000";
when others=> y<="1000000000000000";
end case;
end process;
end structural ;

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2. Write a VHDL description for a 4-bit binary-to-gray code converter. Enter the design
into the Quartus II software and verify the syntax correctness by compiling the
design. Use suggested style guidelines for your VHDL source code. The design should
compile without error.
Answer :
library ieee;
use ieee.std_logic_1164.all;
entity decoder10 IS
port(g: in std_logic_vector(3 downto 0);
b: out std_logic_vector(3 downto 0));
end decoder10 ;
architecture structural of decoder10 is
begin
b(3)<=g(3);
b(2)<=g(3)xor g(2);
b(1)<=g(2)xor g(1);
b(0)<=g(1)xor g(0);
end structural;

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3. Write a VHDL description for a 4-bit gray-to-binary code converter. Enter the design
into the Quartus II software and verify the syntax correctness by compiling the
design. Use suggested style guidelines for your VHDL source code. The design should
compile without error.
Answer :
library ieee;
use ieee.std_logic_1164.all;
entity converter is
port(g:in std_logic_vector(3 downto 0);
b:inout std_logic_vector(3 downto 0));
end converter;
architecture structural of converter is
begin
b(3)<=g(3);
b(2)<=b(3)xor g(2);
b(1)<=b(2)xor g(1);
b(0)<=b(1)xor g(0);
end structural ;

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4. Implement the following truth table-based design in VHDL code.


A B C D Y1 Y2
000010
000110
001010
001110
010010
010110
011010
011110
100010
100101
101001
101111
110010
110110
111010
111110
Verify the correctness of the entered design by simulation using the Altera Quartus II
software. Include a functional timing simulation, a Vector Waveform File (.vwf), in
your solution verifying the correctness of the design.
Answer :
library ieee;
use ieee.std_logic_1164.all;
entity decoder2to4 is
port(a,b,c,d: in std_logic;
y1, y2 : out std_logic);
end decoder2to4;
architecture structural of decoder2to4 is
begin
process(a,b,c,d)
begin
if(a='0'and b='0'and c='0'and d='0')then
y1<='1';
y2<='0';
elsif(a='0'and b='0'and c='1'and d='1')then
y1<='1';
y2<='0';
elsif(a='0'and b='0'and c='1'and d='0') then
y1<='1';
y2<='0';
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elsif(a='0'and b='0'and c='1'and d='1')then


y1<='1';
y2<='0';
elsif(a='0'and b='0'and c='1'and d='0')then
y1<='1';
y2<='0';
elsif(a='0'and b='0'and c='0'and d='1')then
y1<='1';
y2<='0';
elsif(a='0'and b='0'and c='1'and d='0')then
y1<='1';
y2<='0';
elsif(a='0'and b='0'and c='1'and d='1')then
y1<='1';
y2<='0';
elsif(a='1'and b='0'and c='0'and d='0')then
y1<='1';
y2<='0';
elsif(a='1'and b='0'and c='0'and d='1')then
y1<='1';
y2<='0';
end if;
--y:out std_logic_vector(15 downto 0);
end process;
end structural;

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