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MEE 10203 Programmable Electronics

This document is an assignment for a programmable electronics course requiring students to design, implement, and test a memory interface controller on a DE2/DE1 board. The controller interfaces a microprocessor and memory buffer. It uses a finite state machine to enable and disable the write enable and output enable signals of the memory buffer during read and write transactions based on the states of input signals from the microprocessor indicating the start of a new transaction and whether it is a read or write cycle.

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12 views

MEE 10203 Programmable Electronics

This document is an assignment for a programmable electronics course requiring students to design, implement, and test a memory interface controller on a DE2/DE1 board. The controller interfaces a microprocessor and memory buffer. It uses a finite state machine to enable and disable the write enable and output enable signals of the memory buffer during read and write transactions based on the states of input signals from the microprocessor indicating the start of a new transaction and whether it is a read or write cycle.

Uploaded by

phyrdows
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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MEE 10203 PROGRAMMABLE ELECTRONICS

ASSIGNMENT 4

1st STUDENTS NAME 1st STUDENTS MATRIC 2nd STUDENTS NAME 2nd STUDENTS MATRIC LECTURERS NAME DATE OF SUBMISSION

FIRDAUS BIN ALI GE130066 ADEB ALI AHMED MOHAMED HE DR. SHAMIAN BIN ZAINAL

1. Design, implement, and test a DE2/DE1 project that performs a simple memory interface controller (implemented using a Finite State Machine, FSM) based on the following specifications: a. The controller interfaces a microprocessor and a memory buffer. The controller is used to enable and disable the write enable (WE) and the output enable (OE) signals of a memory buffer during read and write transactions, respectively. b. The inputs to the controller are signal RDY and RW, which are outputs of a microprocessor. c. A new transaction begins with the assertion of RDY following a completed transaction (or upon a power-up reset). d. One clock cycle after the commencement of the transaction, the value of RW determines whether it is a read or write transaction. If RW is asserted, then it is a read cycle; otherwise it is a write cycle. e. A cycle is completed by the assertion of RDY, after which a new transaction can begin. WE is asserted during a write cycle, and OE is asserted during a read cycle.

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