2's Complement VHDL Code Using Structrucral Modeling

The document describes a VHDL code for implementing two's complement using a structural modeling approach. It defines the entity with input, enable, and output ports. It then defines components for XOR gates and half adders used to perform the two's complement operation. The architecture maps the components to temporarily store the one's complement result before the half adders add 1 to produce the two's complement output value.

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2's Complement VHDL Code Using Structrucral Modeling

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TWOS COMPLEMENT VHDL CODE USING STRUCTURAL MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL;

Std_logic_1164. package for std_logic (predefined data types).

-----------------------------------------------------------------entity twos_comp is Port ( i : in STD_LOGIC_VECTOR (3 downto 0); e : in STD_LOGIC; z : out STD_LOGIC_VECTOR (3 downto 0)); end twos_comp; -----------------------------------------------------------------architecture Behavioral_2scomp of twos_comp is -----------------------------------------------component xor_1 is Port ( o,p : in STD_LOGIC; q : out STD_LOGIC); end component; component half_adder is Port ( a, b: in STD_LOGIC; sum ,carry: out STD_LOGIC); end component; -------------------------------------------------------------begin x1: xor_1 port map (i(0),e,temp(0)); x2: xor_1 port map (i(1),e,temp(1)); x3: xor_1 port map (i(2),e,temp(2)); x4: xor_1 port map (i(3),e,temp(3)); x5: half_adder port map (temp(0),'1',s(0),c(0)); x6: half_adder port map (temp(1),c(0),s(1),c(1)); x7: half_adder port map (temp(2),c(1),s(2),c(2)); x8: half_adder port map (temp(3),c(2),s(3),c(3)); z<= s; ---------------------------------------------------------------end Behavioral_2scomp;

Entity declaration. i: - input port bits. e: - enable pin. If e=1 circuit will produce twos complement. z: - output port bits.(2s complement of input).

Component (Ex-or, half adder) declaration. These components are describing the structural view of twos complement circuit.

Architecture statements part (Architecture body). Components are port mapped to perform the circuit (2s complement) operation. Ex-or gate is responsible for 1s complement. Ones complement result is temporarily stored is temp signal. Then half adder will add 1 to form twos complement. Half adder sum will be assigned to output z.

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