Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • VHDL Code For 4 Bit Multiplayer and Division

    Uploaded by

    san5210
    730 views5 pages
    This document contains VHDL code for a 4-bit multiplier and its testbench, a 4-bit divider and its testbench, and a description of how to test them. The multiplier code takes in two 4-bit inputs and outputs their 8-bit product. The divider code takes in two 4-bit inputs, a start signal, and a clock, and outputs the 4-bit quotient, 4-bit remainder and a flag when division is complete. The testbenches provide inputs, outputs, and clock signals to test the multiplier and divider designs.

    Original Description:

    vhdl division

    Original Title

    Vhdl Code for 4 Bit Multiplayer and Division

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This document contains VHDL code for a 4-bit multiplier and its testbench, a 4-bit divider and its testbench, and a description of how to test them. The multiplier code takes in two 4-bit inputs and outputs their 8-bit product. The divider code takes in two 4-bit inputs, a start signal, and a clock, and outputs the 4-bit quotient, 4-bit remainder and a flag when division is complete. The testbenches provide inputs, outputs, and clock signals to test the multiplier and divider designs.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    730 views5 pages

    VHDL Code For 4 Bit Multiplayer and Division

    Uploaded by

    san5210
    This document contains VHDL code for a 4-bit multiplier and its testbench, a 4-bit divider and its testbench, and a description of how to test them. The multiplier code takes in two 4-bit inputs and outputs their 8-bit product. The divider code takes in two 4-bit inputs, a start signal, and a clock, and outputs the 4-bit quotient, 4-bit remainder and a flag when division is complete. The testbenches provide inputs, outputs, and clock signals to test the multiplier and divider designs.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    of 5

    VHDL code for 4 bit multiplayer

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;
    entity Multiplier_VHDL is
    port (
    a, b: in std_logic_vector(3 downto 0);
    y: out std_logic_vector(7 downto 0) );
    end entity Multiplier_VHDL;
    architecture Behavioral of Multiplier_VHDL is
    begin
    y <= std_logic_vector(unsigned(a) * unsigned(b));
    end Behavioral;

    Test bench for 4 bit multiplayer


    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    ENTITY multi321 IS
    END multi321;
    ARCHITECTURE behavior OF multi321 IS
    COMPONENT Multiplier_VHDL
    PORT(
    a : IN std_logic_vector(3 downto 0);
    b : IN std_logic_vector(3 downto 0);
    y : OUT std_logic_vector(7 downto 0)
    );
    END COMPONENT;
    --Inputs
    signal a : std_logic_vector(3 downto 0) := (others => '0');
    signal b : std_logic_vector(3 downto 0) := (others => '0');
    --Outputs
    signal y : std_logic_vector(7 downto 0);
    -- No clocks detected in port list. Replace <clock> below with
    -- appropriate port name

    -- constant <clock>_period : time := 10 ns;


    BEGIN
    -- Instantiate the Unit Under Test (UUT)
    uut: Multiplier_VHDL PORT MAP (
    a => a,
    b => b,
    y => y
    );

    -- Stimulus process
    stim_proc: process
    begin
    -- hold reset state for 100 ns.
    a <= "0010";
    b <= "0011";
    wait for 100 ns;
    wait;
    end process;
    END;

    VHDL code for 4 bit division:


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;

    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    entity Division is
    Port ( a : in std_logic_vector(3 downto 0);
    b : in std_logic_vector(3 downto 0);
    Start : in std_logic;
    Clk :
    in std_logic;
    quo : out std_logic_vector(3 downto 0);
    Rest : out std_logic_vector(3 downto 0);
    flag1 : out std_logic);
    end Division;
    architecture Behavioral of Division is
    signal Q:
    std_logic_vector(7 downto 0);
    signal Diff: std_logic_vector(4 downto 0);
    signal Count: std_logic_vector(2 downto 0);
    begin
    Diff <= ('0'&Q(6 downto 3)) - ('0'&b);
    process( Clk, Start)
    begin
    if Start = '0' then
    Q <= "0000" & a;
    elsif Rising_edge( Clk) then
    if Count(2)='0' then
    if Diff(4)='1' then
    Q <= Q(6 downto 0) & '0';
    else
    Q <= Diff(3 downto 0) & Q(2 downto 0) & '1';
    end if;
    end if;
    end if;
    end process;
    process(Clk)
    begin
    if Start = '0' then
    Count <= "000";
    elsif Rising_edge( Clk) then
    if Count(2)='0' then
    Count <= Count+1;
    end if;
    end if;
    end process;
    quo <= Q(3 downto 0);

    Rest <= Q(7 downto 4);


    flag1 <= Count(2);
    end Behavioral;

    Testbench for VHDL code for 4 bit division :


    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    --USE ieee.numeric_std.ALL;
    ENTITY div980 IS
    END div980;
    ARCHITECTURE behavior OF div980 IS
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT Division
    PORT(
    a : IN std_logic_vector(3 downto 0);
    b : IN std_logic_vector(3 downto 0);
    Start : IN std_logic;
    Clk : IN std_logic;
    quo : OUT std_logic_vector(3 downto 0);
    Rest : OUT std_logic_vector(3 downto 0);
    flag1 : OUT std_logic
    );
    END COMPONENT;

    --Inputs
    signal a : std_logic_vector(3 downto 0) := (others => '0');
    signal b : std_logic_vector(3 downto 0) := (others => '0');
    signal Start : std_logic := '0';
    signal Clk : std_logic := '0';
    --Outputs
    signal quo : std_logic_vector(3 downto 0);
    signal Rest : std_logic_vector(3 downto 0);

    signal flag1 : std_logic;


    -- Clock period definitions
    constant Clk_period : time := 10 ns;
    BEGIN
    -- Instantiate the Unit Under Test (UUT)
    uut: Division PORT MAP (
    a => a,
    b => b,
    Start => Start,
    Clk => Clk,
    quo => quo,
    Rest => Rest,
    flag1 => flag1
    );
    -- Clock process definitions
    Clk_process :process
    begin
    Clk <= '0';
    wait for Clk_period/2;
    Clk <= '1';
    wait for Clk_period/2;
    end process;

    -- Stimulus process
    stim_proc: process
    begin
    start <= '0';
    wait for 30 ns;
    start <= '1';
    a<= "1100";
    b <= "0010";
    -- hold reset state for 100 ns.
    wait for 300 ns;
    -- wait for Clk_period*10;
    -- insert stimulus here
    end process;
    END;

    You might also like