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Half Adder VHDL Code Using Behavioural Modeling

The document describes a VHDL code for a half adder using behavioral modeling. It defines the entity with two inputs (a and b) and two outputs (sum and carry). The architecture contains a process with if statements that implement the half adder logic according to the truth table provided, with sum and carry assigned based on the values of a and b.

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100% found this document useful (5 votes)

13K views

Half Adder VHDL Code Using Behavioural Modeling

The document describes a VHDL code for a half adder using behavioral modeling. It defines the entity with two inputs (a and b) and two outputs (sum and carry). The architecture contains a process with if statements that implement the half adder logic according to the truth table provided, with sum and carry assigned based on the values of a and b.

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Copyright

© © All Rights Reserved

We take content rights seriously. If you suspect this is your content, claim it here.

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INFOOP2R.WIX.

COM/OP2R

HALF ADDER VHDL CODE USING BEHAVIOURAL MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------

Std_logic_1164. package for std_logic (predefined data type).

entity half_adder is Port ( a, b: in STD_LOGIC; sum ,carry: out STD_LOGIC); end half_adder; --------------------------------------------architecture Behavioral_HA of half_adder is begin ------------------------------process(a,b) begin if (a='0')then sum<= b; carry<='0'; else sum <= not b; carry<='0'; A if (b='1') then 0 carry<='1'; 0 1 end if; 1 end if; end process; ---------------------------------end Behavioral_HA;

Entity declaration. a, b :- input port bits (bits to be added) Sum, carry:- output port bits.

Process statements (sensitivity list) Behavioral representation of half adder... Truth table:-

B 0 1 0 1

Sum 0 1 1 0

Carry 0 0 0 1

RTL VIEW:-

OUT PUT WAVEFORMS:-

INFOOP2R.WIX.COM/OP2R

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