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Decade Counter

This document describes a VHDL code for a 4-bit binary counter. The code defines an entity called Counter with a clock, reset, and 4-bit output port. The architecture contains a process that uses a clock edge to increment an internal variable from 0 to 9 before resetting it to 0, with the output assigned from the internal variable.

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kishore981
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© Attribution Non-Commercial (BY-NC)
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Download as DOCX, PDF, TXT or read online on Scribd
8K views

Decade Counter

This document describes a VHDL code for a 4-bit binary counter. The code defines an entity called Counter with a clock, reset, and 4-bit output port. The architecture contains a process that uses a clock edge to increment an internal variable from 0 to 9 before resetting it to 0, with the output assigned from the internal variable.

Uploaded by

kishore981
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Sample design

--Counter VHDL

library IEEE; --library definition

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity Counter is --entity definition

port (

clk:in std_logic;

reset: in std_logic;

q: out std_logic_vector(3 downto 0)

);

end Counter;

architecture Counter of Counter is -- Architecture definition

begin

process(clk,reset) -- Process definition

variable qtemp: std_logic_vector(3 downto 0); -- temporary variable for output


q[3..0]

begin

if reset='1' then

qtemp:="0000"; -- Reset asychroniously

else

if clk'event and clk='1' then -- Counting state

if qtemp<9 then
qtemp:=qtemp+1; -- Counter increase

else

qtemp:="0000"; -- Return the zero state

end if;

end if;

q<=qtemp; -- Output

end if;

end process; -- End Process

end Counter; -- End Architecture

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