Melay FSM 0110
Melay FSM 0110
Melay FSM 0110
OBJECTIVE:
To develop the source code for sequence detecter(mealy machine) by using
vhdl/verilog and obtain the simulation, synthesis, place and route and implement into fpga.
METHODOLOGY:
A sequential machine is a quintule, M=(X,Z,S,f,g), where X,Z, and S are the finate and
nonempty sets of inputs, outputs and states respectively, f is the next state function, such
that
St+1= f(St,Xt)
and g is the output function such that
Zt=g(St,Xt) for the mealy machine
BLOCK DIAGRAM:
1/0
S0
1/0
0/0
0/1
0/0
1/0
1/0
S2
SOURCE CODE:
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seqvermealy is
S1
0/0
S3
Port ( a : in STD_LOGIC;
clk : in STD_LOGIC;
z : out STD_LOGIC);
end seqvermealy;
nst<=s2;
end if;
when s2=>
if(a='0') then
z<='0';
nst<=s1;
else
z<='0';
nst<=s3;
end if;
when s3=>
if(a='0') then
z<='1';
nst<=s1;
else
z<='0';
nst<=s0;
end if;
end case;
end process p1;
end Behavioral;
VERILOG CODE:
module seqdec(a,clk,z);
input a;
input clk;
output z;
reg z;
parameter s0=0,s1=1,s2=2,s3=3;
reg[0:1] states;
initial
begin
states=s0;
end
always@(posedge clk)
case(states)
s0:
begin
if(a) begin
z=0;
states=s0;
end
else begin
z=0;
states=s1;
end
end
s1:
begin
if(a) begin
z=0;
states=s2;
end
else begin
z=0;
states=s1;
end
end
s2:
begin
if(a) begin
z=0;
states=s3;
end
else begin
z=0;
states=s1;
end
end
s3:
begin
if(a) begin
z=0;
states=s0;
end
else begin
z=1;
states=s1;
end
end
endcase
endmodule
RTL SCHEMATIC:
TECHNOLOGY SCHEMATIC:
FLOOR PLANNER:
XPOWER ANALYZER:
SUMMARY:
THERMAL INFORMATION:
SIMULATION WAVEFORMS:
SYNTHESIS REPORT:
Release 10.1 - xst K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to C:/kalyan/sequencedetector/0110mealy/xst/projnav.tmp
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=======================================================
==================
*
=======================================================
==================
---- Source Parameters
Input File Name
: "seqdetector.prj"
Input Format
: mixed
: "seqdetector"
Output Format
: NGC
Target Device
: xc3s500e-5-fg320
: seqdetector
: YES
: Auto
Safe Implementation
FSM Style
: No
: lut
RAM Extraction
RAM Style
: Yes
: Auto
ROM Extraction
Mux Style
: Yes
: Auto
Decoder Extraction
Priority Encoder Extraction
: YES
: YES
: YES
: YES
XOR Collapsing
ROM Style
: YES
: Auto
Mux Extraction
: YES
Resource Sharing
: YES
Asynchronous To Synchronous
Multiplier Style
: NO
: auto
: No
: YES
: 500
: 24
: YES
: YES
: Yes
: Yes
: Yes
: auto
: YES
: Speed
Optimization Effort
:1
: seqdetector.lso
Keep Hierarchy
: NO
Netlist Hierarchy
: as_optimized
RTL Output
Global Optimization
Read Cores
Write Timing Constraints
Cross Clock Analysis
: Yes
: AllClockNets
: YES
: NO
: NO
Hierarchy Separator
:/
Bus Delimiter
: <>
Case Specifier
: maintain
: 100
: 100
: YES
: NO
:5
=======================================================
==================
=======================================================
==================
*
HDL Compilation
=======================================================
==================
Compiling vhdl file "C:/kalyan/sequencedetector/0110mealy/seq.vhd" in Library work.
Architecture behavioral of Entity seqdetector is up to date.
=======================================================
==================
*
=======================================================
==================
Analyzing hierarchy for entity <seqdetector> in library <work> (architecture <behavioral>).
=======================================================
==================
*
HDL Analysis
=======================================================
==================
Analyzing Entity <seqdetector> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/kalyan/sequencedetector/0110mealy/seq.vhd" line 41: One or more
signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD
hardware, XST will assume that all necessary signals are present in the sensitivity list.
Please note that the result of the synthesis may differ from the initial design specification.
The missing signals are:
<nst>
Entity <seqdetector> analyzed. Unit <seqdetector> generated.
=======================================================
==================
*
HDL Synthesis
=======================================================
==================
=======================================================
==================
HDL Synthesis Report
Macro Statistics
# Latches
:1
4-bit latch
:1
=======================================================
==================
=======================================================
==================
*
=======================================================
==================
=======================================================
==================
Advanced HDL Synthesis Report
Macro Statistics
# Latches
:1
4-bit latch
:1
=======================================================
==================
=======================================================
==================
*
=======================================================
==================
=======================================================
==================
Final Register Report
Found no macro
=======================================================
==================
=======================================================
==================
*
Partition Report
=======================================================
==================
-------------------------------
=======================================================
==================
*
Final Report
=======================================================
==================
Final Results
RTL Top Level Output File Name
: seqdetector.ngr
: seqdetector
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:6
LUT2
:3
LUT2_L
LUT3
:1
LUT4
:1
:1
# FlipFlops/Latches
#
LD_1
:4
:4
# Clock Buffers
#
:1
BUFGP
:1
# IO Buffers
:2
IBUF
OBUF
:1
:1
=======================================================
==================
Number of Slices:
3 out of 4656
0%
4 out of 9312
0%
6 out of 9312
0%
Number of IOs:
3 out of
Number of GCLKs:
1 out of
232
24
1%
4%
---------------------------
=======================================================
==================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|4
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
Timing Detail:
-------------All values displayed in nanoseconds (ns)
=======================================================
==================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.715ns (frequency: 368.331MHz)
Total number of paths / destination ports: 8 / 4
------------------------------------------------------------------------Delay:
Source:
Destination:
Source Clock:
Net
---------------------------------------- -----------LD_1:G->Q
LUT2_L:I0->LO
LUT4:I3->O
LD_1:D
0.268
pst_1
---------------------------------------Total
=======================================================
==================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 4 / 4
------------------------------------------------------------------------Offset:
Source:
Destination:
Net
---------------------------------------- -----------IBUF:I->O
LUT3:I0->O
LD_1:D
----------------------------------------
pst_0
Total
=======================================================
==================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------Offset:
Source:
Destination:
Source Clock:
Net
---------------------------------------- -----------LD_1:G->Q
LUT2:I0->O
OBUF:I->O
3.169
z_OBUF (z)
---------------------------------------Total
=======================================================
==================
Timing constraint: Default path analysis
Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------Delay:
Source:
Destination:
z (PAD)
Data Path: a to z
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I1->O
OBUF:I->O
3.169
z_OBUF (z)
---------------------------------------Total
=======================================================
==================
-->
Number of errors :
Number of warnings :
Number of infos
0 ( 0 filtered)
2 ( 0 filtered)
0 ( 0 filtered)
DESIGN SUMMARY:
fsmmelay Project Status
Project File:
fsmmelay.ise
Current State:
Module Name:
melayfsm
Errors:
No Errors
Target Device:
xc3s500e-5fg320
Warnings:
6 Warnings
Routing Results:
Design Goal:
Balanced
Timing Constraints:
Design Strategy:
0 (Timing Report)
[-]
[-]
Logic Utilization
Used
Available
Utilization
9,312
1%
9,312
1%
4,656
1%
100%
Note(s)
Logic Distribution
Number of occupied Slices
0%
9,312
1%
232
1%
Number of BUFGMUXs
24
4%
Performance Summary
[-]
Pinout Data:
Pinout
Report
Routing Results:
Clock Data:
Clock Report
Timing Constraints:
[-]
Report Name
Status
Generated
Errors
Warnings
Infos
Synthesis Report
Current
5 Warnings
2 Infos
Translation Report
Current
Map Report
Current
1 Warning
2 Infos
Current
1 Info
Current
3 Infos
Bitgen Report
Date Generated: 01/02/2013 - 11:13:56
CONCLUSION:
Thus the design of sequence detector using VHDL and Verilog HDL using behavioural
programming design is implemented successfully.