//Verilog code for all (up,down and modn) counters in one.

module allcn_B (
input clk,rst,up,dn, //Using up, dn input ports to specify up or down counter.
input [3:0] n, //Using n to specify the number of states for mod-N counter.
output [3:0] cn_out
);
reg [3:0] temp;

always@(posedge clk)
begin
if (rst)
temp<=0; //Active high reset.
else
if (!n) //If n=0, works as up or down counter.
case ({up,dn})
2'd1 : temp<=temp-1; //If up=1 and dn=0, works as up counter.
2'd2 : temp<=temp+1; //If up=0 and dn=1, works as down counter.
endcase
else //These block works when 'n' as some value specified.
if (up) //If 'n' is specified and up=1 then works as up mod counter.
begin
temp<=0;
if (temp<n) //Count for n-1 states including 0 as a state.
temp<=temp+1;
end
else
begin
temp<=n; //Counts from the specified value to 0.
if (temp>0)
 temp<=temp-1;
end
end
assign cn_out=temp;
endmodule

//Linear test fixture for all in one counter block

module allcn_B_tf ();
reg clk,rst,up,dn;
reg [3:0] n;
wire [3:0] cn_out;

allcn_B x1(clk,rst,up,dn,n,cn_out);

initial
begin
clk=0;rst=0;up=0;dn=0;n=0;
#5 rst=1;
#5 rst=0;up=1; //Works as up counter.
#300 up=0;dn=1; //Works as down counter.
#300 n=5; //Works as mod_5 down counter.
#100 n=8;up=1;dn=0; //Works as mod_8 up counter.
#160 $finish; //Time dealy is selected such that it runs for 2 full cycles for every
condition.
end

always #5clk=~clk; //Time period of clock is 10ns.

Endmodule
//Verilog for 10-bit binary to BCD till decimal 999
module BintoBCD (
input [9:0] Bin, //A 10-bit binary input
output [11:0] BCD //A 12-bit BCD output displaying reg
);
reg [11:0] tBCD; //Taking a single 12-bit reg to shift the values of Bin into it
integer j;

always@(*)
begin
tBCD=12'd0; //Initializing the reg value as 0
for (j=9; j>=0; j=j-1) //For all the 10 bits according to the value of j the loop shifts the value
begin
if (tBCD[3:0]>4) //If 3 times shifted or at any point the ones value is
(101)b or greater than that add 3
tBCD[3:0]=tBCD[3:0]+2'd3;
if (tBCD[7:4]>4) //Same for tens place
tBCD[7:4]=tBCD[7:4]+2'd3;
if (tBCD[11:8]>4) //And hundreds , this is done bcoz after (1001)b for
(1010)b only we require an extra bit to display places value in Decimal
tBCD[11:8]=tBCD[11:8]+2'd3;

tBCD[11:0]=tBCD[11:0]<<1; //For every cycle the Bin values are shifted one by one
tBCD[0]=Bin[j]; //The Bin values are placed one by one to the BCD
reg
end
end
assign BCD=tBCD;
endmodule

//Verilog for 10-bit binary to BCD till decimal 999

module BintoBCD (
input [9:0] Bin, //A 10-bit binary input
output [11:0] BCD //A 12-bit BCD output displaying reg
);
reg [11:0] tBCD; //Taking a single 12-bit reg to shift the values of Bin into it
integer j;

always@(*)
begin
tBCD=12'd0; //Initializing the reg value as 0
for (j=9; j>=0; j=j-1) //For all the 10 bits according to the value of j the loop shifts the value
begin
if (tBCD[3:0]>4) //If 3 times shifted or at any point the ones value is
(101)b or greater than that add 3
tBCD[3:0]=tBCD[3:0]+2'd3;
if (tBCD[7:4]>4) //Same for tens place
tBCD[7:4]=tBCD[7:4]+2'd3;
if (tBCD[11:8]>4) //And hundreds , this is done bcoz after (1001)b for
(1010)b only we require an extra bit to display places value in Decimal
tBCD[11:8]=tBCD[11:8]+2'd3;

tBCD[11:0]=tBCD[11:0]<<1; //For every cycle the Bin values are shifted one by one
tBCD[0]=Bin[j]; //The Bin values are placed one by one to the BCD
reg
 end
end
assign BCD=tBCD;
endmodule

//Test fixture for 10-bit binary to BCD till decimal 999

module BintoBCD_tf();
reg [9:0] Bin;
wire [11:0] BCD;

BintoBCD x1(Bin,BCD); //Instantiation of the UUT

initial
begin
Bin=10'b0;
repeat (10) //Assigning 10 10-bit Binary test values
#10 Bin= $urandom%999; //in the range 0-999
#20 $finish;
end
endmodule

//Verilog code for Experimental circuit-1 for (A>B)

module Cn_CmD_G (
input clk,rst,
 input [3:0] B,
output Q
);
wire [3:0] A;
wire en;
supply0 Gnd; //Gnd can be used to ground the unconnected ports of initiated
modules

upcount_B x1(clk,rst,A); //Initiation of an Up counter

Comp_4b x2(A,B,en,Gnd,Gnd); //Initiation of a Comparator, comparing only A>B
D_ff_en x3(clk,rst,en,~Q,Q); //Initiation of a D_ff block but connecting its input to negation of its output to
act as T_ff

Endmodule

//Linear test fixture for Experimental Ckt-1 (A>B)

module Cn_Cmd_G_tf ();

reg clk,rst;
reg [3:0] B;
wire Q;

Cn_CmD_G x1(clk,rst,B,Q); //Instantiation of UUT

initial
begin
clk=1;rst=1;B=4'd7; //Reference Value B=7
 #10 rst=0;
#320 $finish; //For rst=0 output Q should start to toggle after A=7 till A=0 again
end

always #5 clk=~clk;
endmodule

//Verilog code for Experimental circuit-1 for (A<B)

module Cn_CmD_L (
input clk,rst,
input [3:0] B,
output Q
);
wire [3:0] A;
wire en;
supply0 Gnd; //Gnd can be used to ground the unconnected ports of initiated
modules

upcount_B x1(clk,rst,A); //Initiation of an Up counter

Comp_4b x2(A,B,Gnd,Gnd,en); //Initiation of a Comparator, comparing only A<B condition.
D_ff_en x3(clk,rst,en,~Q,Q); //Initiation of a D_ff block

Endmodule
//Linear test fixture for Experimental Ckt-1 (A<B)

module Cn_Cmd_L_tf ();

reg clk,rst;
reg [3:0] B;
wire Q;

Cn_CmD_L x1(clk,rst,B,Q); //Instantiation of UUT

initial
begin
clk=1;rst=1;B=4'd7; //Reference Value B=7
#10 rst=0;
#320 $finish; //For rst=0 output Q should start to toggle till A=7
end

always #5 clk=~clk;
endmodule

//Verilog code for Experimental circuit-1 for (A=B)

module CnCmD_E (
input clk,rst,
 input [3:0] B,
output Q
);
wire [3:0] A;
wire en;
supply0 Gnd; //Gnd can be used to ground the unconnected ports of initiated
modules

upcount_B x1(clk,rst,A); //Initiation of an Up counter

Comp_4b x2(A,B,Gnd,en,Gnd); //Initiation of a Comparator, comparing A and B only for their equality.
D_ff_en x3(clk,rst,en,~Q,Q); //Initiation of a D_ff block

Endmodule

//Linear test fixture for Experimental Ckt-1 (A=B)

module CnCmd_E_tf ();

reg clk,rst;
reg [3:0] B;
wire Q;

CnCmD_E x1(clk,rst,B,Q); //Instantiation of UUT

initial
begin
 clk=1;rst=1;B=4'd7; //Reference Value B=7
#10 rst=0;
#160 $finish; //After rst=0 output Q should only be high for 7
end

always #5 clk=~clk;
endmodule

//Verilog code for 4-bit comparator

module Comp_4b (
input [3:0] A,B,
output G,E,L //Comparator contains 3 separate ports for displaying 3 conditions.
);
reg tG,tE,tL;

always@(*)
begin
tG<=0;tE<=0;tL<=0;
if (A>B)
tG<=1'b1; //G=1 if A greater than B
else
if (A==B)
tE<=1'b1; //E=1 if A equal to B
else
 tL<=1'b1; //L=1 if A less than B
end
assign G=tG,E=tE,L=tL;
endmodule

//Verilog Code for D-Flip Flop with enable and reset ports

module D_ff_en (
input clk,rst,en,Din,
output Q
);
reg tQ;

always@(posedge clk)
begin
if (en)
if (rst)
tQ<=0;
else
tQ<=Din;
else
tQ<=0;
end
assign Q=tQ;
endmodule
//Verilog for 6-binary bit adder and display the resut in decimal (used in 4x4 Multiplier)

module Decadd_6b (
input [5:0] a,b,
output [5:0] out
);

assign out=a+b;

endmodule

//Verilog for D-flip flop without Qbar (used in Shift registers)

module dff (clk,rst,Din,Q);

input clk,rst,Din;
output Q;
reg tQ;

always@(posedge clk)
 begin
if (rst)
tQ<=0;
else
tQ<=Din;
end
assign Q=tQ;
endmodule

//Verilog for D-flip flop with rest and Preset (used for Jonson counter)

module dff_B (
input clk,rst,prst,Din,
output Q,Qb
);
reg tQ;

always@(posedge clk)
begin
if (rst) //If reset is high Out=0
tQ<=0;
else
if (prst) //If preset is high Out=1
tQ<=1;
 else
tQ<=Din; //Din input is got at out after one clock cycle delay
end
assign Q=tQ, Qb=~tQ;
endmodule

//Verilog code for 4-bit down counter.

module dncount_B(
input clk,rst,
output [3:0] cn_out
);
reg [3:0] temp; //Using a temporary register for using inside a procedural block

always@(posedge clk)
begin
if (rst)
temp<=0; //For an always@(posedge clk) block always use non-blocking statements
else
temp<= temp-1; //Logic for repetative down counting
end
assign cn_out=temp; //Assigning the temp reg value for our actual output port
endmodule
//Linear Test fixture for 4-bit down counter.
module dncount_tf();
reg clk,rst;
wire [3:0] cn_out;

dncount_B x1(clk,rst,cn_out);

initial
begin
clk=0;rst=0;
#5 rst=1;
#5 rst=0;
#160 $finish; // Delay_time= (Code's clock period) x (No. of cases/combinations to be executed)
end

always #5 clk=~clk;
endmodule

// Verilog code for down Mod-7 counter

module dnmod7_cn(
input clk,rst,
output [3:0] cn_out //Max. mod 15(1111) counter can be designed using 4 bit cn_out.
);
reg [3:0] temp;
 always@(posedge clk) //Counter is positive edge triggered.
begin
if (rst) //active high reset.
temp<=0;
else
if (temp==7) //7 specifies that it counts till 7. Here temp<=6 also works fine.
temp<=7;
else
temp<=temp-1;
end
assign cn_out=temp;
endmodule

module dnmod7_cn_tf();
reg clk,rst;
wire [3:0] cn_out; //For test fixture, inputs of subblock is reg for top block and output is wire.

dnmod7_cn x1(clk,rst,cn_out); //Initiating or calling my mod7 counter verilog block.

initial
begin
clk=0;rst=0;
#5 rst=1;
#25 rst=0;
#160 $finish; //Running my code for 2 complete cycles.
 end

always #5 clk=~clk; //Time period of clock is 10ns.

Endmodule

//Verilog code for even or odd number and even paritity checker for a 4-bit counter

module eg2 (
input clk,rst,
output flag1,flag2 //Flag1 shows the 4-bit is an even or odd number and Flag2 shows
if its containing even or odd number of ones
);
wire [3:0] cn_out;
reg tflag1, tflag2;
upcount_B x1(clk,rst,cn_out); //Instantiating the up counter block which is the 4-bit input to our
checking block

always@(cn_out) //Whenever the output of counter changes execute the

checking block
begin
if (cn_out % 2 ==0) //A number is even if its divisible by 2, i.e, if its modulous
is 0
tflag1<=0;
else
tflag1<=1; //If number is odd flag1=1, if even flag=0
if (^cn_out==0) //reduction xor operator on counter o/p gives us 0 if there
are odd no. of ones
tflag2<=1;
 else
tflag2<=0; //So, if there are odd no. of ones in the 4-bit o/p flag2=1, if
even flag2=0
end
assign flag1=tflag1, flag2=tflag2;
endmodule

//Linear test fixture for even or odd number and even paritity checker for a 4-bit counter

module eg2_tf ();

reg clk,rst;
wire flag1,flag2;

eg2 x1(clk,rst,flag1,flag2); //Instantiating the UUT

initial
begin
clk=1;rst=1;
#10 rst=0;
#480 $finish; //Counter is let to run for 3 cycles and parallely the output is verified
end

always #5 clk=~clk;
endmodule

//Verilog code for 3-bit Full adder using HAdder instantiation

module FAdder_inst (
input A,
input B,
input Cin,
output Sum,
output Carry
);
wire w1,w2,w3;
HAdder_G x1(A,B,w1,w2);
HAdder_G x2(w1,Cin,Sum,w3);
or x3(Carry,w2,w3);
endmodule

//Verilog code for Half Adder using Gate level modelling

module HAdder_G(
input a,
input b,
 output sum,
output carry
);
xor x1 (sum,a,b);
and x2 (carry,a,b);
endmodule

//Verilog for 4-bit Jonson counter using D-flip flops

module JCn4b_inst (
input clk,rst,prst,
output [3:0] Qb,
output [3:0] cn_out
);
wire w1;

dff_B x1(clk,rst,prst,w1,cn_out[0],Qb[0]); //Input for this ff comes from Qb of last ff

dff_B x2(clk,rst,prst,cn_out[0],cn_out[1],Qb[1]); //Input comes from Q of previous ff; output goes to next input of
ff
dff_B x3(clk,rst,prst,cn_out[1],cn_out[2],Qb[2]);
dff_B x4(clk,rst,prst,cn_out[2],cn_out[3],w1); //Output of this ff goes to inout for first ff
endmodule
module jkSyc_dncn (
input clk,rst,
output [3:0] Q,
output [3:0] Qb
);
wire w1,w2;

JKff_B a(clk,rst,1'b1,1'b1,Q[0],Qb[0]);
JKff_B b(clk,rst,Qb[0],Qb[0],Q[1],Qb[1]);
and x1(w1,Qb[0],Qb[1]);
JKff_B c(clk,rst,w1,w1,Q[2],Qb[2]);
and x2(w2,w1,Qb[2]);
JKff_B d(clk,rst,w2,w2,Q[3],Qb[3]);
endmodule

module jkSyc_upcn (
input clk,rst,
output [3:0] Q,
output [3:0] Qb
);
wire w1,w2;

JKff_B a(clk,rst,1'b1,1'b1,Q[0],Qb[0]);
JKff_B b(clk,rst,Q[0],Q[0],Q[1],Qb[1]);
and x1(w1,Q[0],Q[1]);
JKff_B c(clk,rst,w1,w1,Q[2],Qb[2]);
and x2(w2,w1,Q[2]);
JKff_B d(clk,rst,w2,w2,Q[3],Qb[3]);
endmodule

//Verilog for Left shift using logic operators

module LSh_reg (
input clk,rst,
input [3:0] In,
output [3:0] Out
);
reg [3:0] temp;

always@(posedge clk)
begin
if (rst)
temp<=In; //To take a new value to shift give the value to i/p and reset=1
else
temp<=temp<<1; //Then reset=0, and for every clock cycle this else loop gets
executed that shifts left by 1-bit
end
assign Out=temp;
endmodule
//Linear test fixture for Right shift register using logical operator
module LSh_reg_tf();
reg clk,rst;
reg [3:0] In;
wire [3:0] Out;

LSh_reg x1(clk,rst,In,Out);

initial
begin
clk=0;rst=0;In=0;
#5 rst=1;In=0001; //Giving test sequence as 0001
#5 rst=0;
#55 $finish; //The running for 5 clock; observe it gets 0000 at 4th clock.
end

always #5 clk=~clk;
endmodule

//Verilog code for 2x2 MAC unit

module MAC_2x2 (
input clk,rst,
input [1:0] a,b, //Each input bits width is 2
 output [7:0] Out //Output width is kept 8 instead of 4, so as to accomodate the extra carry
bits during repeatative addition
);
reg [7:0] Accu,Adder,tOut;
reg [3:0] Multi;

always@(posedge clk)
begin
if (rst) //Active high reset, making the Accu reg=0
begin
tOut=0;
Accu=0;
end
else
begin
Multi=a*b; //Multi reg holds the 4 bit data product of a x b
Adder=Multi+Accu; //Adder reg holds the present recursive sum of Multi and Accu reg
Accu=Adder; //Accu reg is updated with new Adder reg's sum value
tOut=Accu; //Finally for every clock updated accu reg value is taken as output
end
end
assign Out=tOut;
endmodule
//Random test fixture for 2x2 MAC unit

module MAC_2x2_tf ();

reg clk,rst;
reg [1:0] a,b;
wire [7:0] Out;

MAC_2x2 x1(clk,rst,a,b,Out); //Instantiating the UUT

initial
begin
clk=1;rst=1;a=0;b=0;
#10 rst=0;
repeat (10)
begin
#10 a=$urandom%3; b=$urandom%3; //Assigning random values for inputs a and b for 10 times
end //Here unsigned random values in the range 0-3 are
used
#10 $finish;
end

always #5 clk=~clk;
endmodule
//Verilog code for Mod-7 counter

module mod7_cn(
input clk,rst,
output [3:0] cn_out //Max. mod 15(1111) counter can be designed using 4 bit cn_out.
);
reg [3:0] temp;

always@(posedge clk) //Counter is positive edge triggered.

begin
if (rst) //active high reset.
temp<=0;
else
if (temp==7) //7 specifies that it counts till 7. Here temp<=6 also works fine.
temp<=0;
else
temp<=temp+1;
end
assign cn_out=temp;
endmodule

//Verilog code for Mod-7 counter

module mod7_cn(
input clk,rst,
 output [3:0] cn_out //Max. mod 15(1111) counter can be designed using 4 bit cn_out.
);
reg [3:0] temp;

always@(posedge clk) //Counter is positive edge triggered.

begin
if (rst) //active high reset.
temp<=0;
else
if (temp==7) //7 specifies that it counts till 7. Here temp<=6 also works fine.
temp<=0;
else
temp<=temp+1;
end
assign cn_out=temp;
endmodule

//Verilog code for 2x2 Multiplier using Half adder instantiation

module Multi2x2_Ha (
input [1:0] a,b, //Multiplier and Multiplicand size is 2 bits
output [3:0] Pout //Making the product size 2+2 4 bits size
);
wire w1,w2,w3,w4;
and x1(Pout[0],a[0],b[0]); //Multiplying individual bits of multiplicand and multiplier,
and x2(w1,a[0],b[1]);
 and x3(w2,a[1],b[0]); //And stroing all the for combination's result
and x4(w4,a[1],b[1]);
HAdder_G x5(w1,w2,Pout[1],w3); //Adding the 2 bits of individual products using Half Adder
HAdder_G x6(w3,w4,Pout[2],Pout[3]);
endmodule

//Linear test fixture for 2x2 Multiplier using Half adder instantiation

module Multi2x2_Ha_tf ();

reg [1:0] a,b;
wire [3:0] Pout;

Multi2x2_Ha x1(a,b,Pout);

initial
begin
a=0;b=0;
#10 a=2'b01; b=2'b11; //a=1, b=3, Pout=3
#10 a=2'b11; b=2'b10; //a=3, b=2, Pout=6
#10 a=2'b11; b=2'b11; //a=3, b=3, Pout=9
#10 $finish;
end
endmodule
//Verilog code for 3x3 Multiplier using FA and HA instantiation

module Multi3x3_inst (
input [2:0] a,b, //Each input bit width is 3 bits
output [5:0] Pout //Making the output bit width as 3+3 6 bits
);
wire x1,x2,y0,y1,y2,z0,z1,z2,s1,s2,c1,c2,c3,c4,c5;
and a1(Pout[0],a[0],b[0]);
and a2(x1,a[0],b[1]); //Multiplying all the combination of individual bits using
AND gates
and a4(x2,a[0],b[2]);
and a3(y0,a[1],b[0]);
and a5(y1,a[1],b[1]);
and a6(y2,b[2],a[1]);
and a7(z0,b[0],a[2]);
and a8(z1,b[1],a[2]);
and a9(z2,b[2],a[2]);
HAdder_G h1(x1,y0,Pout[1],c1); //Using half adder to add 2 1-bit product
FAdder_inst f1(c1,x2,y1,s1,c2); //The extra carry is moved to the left of the addtion block
HAdder_G h2(s1,z0,Pout[2],c3);
FAdder_inst f2(c2,c3,y2,s2,c4); //Using full adder to add 3 1-bit product
HAdder_G h3(s2,z1,Pout[3],c5); //Since the number of bits to be added decreases as we
move towards left the no. of bits to be added decreases
FAdder_inst f3(c4,c5,z2,Pout[4],Pout[5]); //Parallely moving the data to respective bits of Pout reg
endmodule
//Linear test fixture for 3x3 Multiplier using FA and HA instantiation

module Multi3x3_inst_tf();
reg [2:0] a,b;
wire [5:0] Pout;

Multi3x3_inst x1(a,b,Pout); //Instantiating the UUT

initial
begin
a=0;b=0;
#10 a=3'd2; b=3'd6; //Assigning values to a,b, for every 10 units delay
#10 a=3'd4; b=3'd3;
#10 a=3'd1; b=3'd4; //And cross checking the values
#10 a=3'd3; b=3'd5;
#10 a=3'd7; b=3'd7;
#10 a=3'd5; b=3'd2;
#10 a=3'd6; b=3'd7;
#10 $finish;
end
endmodule
//Verilog code for 4x4 Multiplier using 2x2 Multipliers and 6-bit decimal adders

module Multi4x4_in2x2 (
input [3:0] a,b, //Each input size is 4 bits
output [7:0] Pout //Making the output bit size 4+4 8 bits
);
wire [3:0] p0,p1,p2,p3;
wire [5:0] s1,s2;

Multi2x2_Ha m1(a[1:0],b[1:0],p0[3:0]); //Multiplying 2 bits of Multiplier and 2 bits of

Multiplicand using a 2x2 Multiplier block
Multi2x2_Ha m2(a[3:2],b[1:0],p1[3:0]);
Multi2x2_Ha m3(a[1:0],b[3:2],p2[3:0]);
Multi2x2_Ha m4(a[3:2],b[3:2],p3[3:0]);

Decadd_6b a1( {2'b0,p1[3:0]}, {4'b0,p0[3:2]}, s1); //Then adding the product combinations using 6 bit deciamal
adder
Decadd_6b a2( {2'b0,p2[3:0]}, {p3[3:0],2'b0}, s2); //Here concatination is used to get the right order of desired bits
addition
Decadd_6b a3(s1,s2,Pout[7:2]); //Parallely we assign the bit of final output using Bit
select

assign Pout[1:0]=p0[1:0];
endmodule
//Random test fixture for 4x4 Multiplier using 2x2 Multipliers and 6-bit decimal adders

module Multi4x4_in2x2_tf ();

reg [3:0] a,b;
wire [7:0] Pout;

Multi4x4_in2x2 x1(a,b,Pout); //Instantiating the UUT

initial
begin
a=0;b=0;
#10 a=4'd8;b=4'd2; //For a=8, b=2, Pout=16
#10 a=4'd15;b=4'd15; //For a=15, b=15, Pout=225
#10 a=4'd14;b=4'd3; //For a=14, b=3, Pout=42
#10 a=4'd8;b=4'd3; //For a=8, b=3, Pout=24
#10 a=4'd10;b=4'd10; //For a=10, b=10, Pout=100
#10 a=4'd2;b=4'd2; //For a=2, b=2, Pout=4, cross verify all the results
#10 $finish;
end
endmodule

//Verilog code for 2'bx2'b Multiplier using Gates to add

module Multiplier2x2_G (
input [1:0] a,b,
output [3:0] Pout
);
 wire x1,x2,y0,y1;

and a0b0(Pout[0],a[0],b[0]);
and a1b0(x1,a[1],b[0]);
and a0b1(y0,b[1],a[0]);
and a1b1(y1,b[1],a[1]);
xor x1y0(Pout[1],x1,y0);
and x2c(x2,x1,y0);
xor x2y1(Pout[2],x2,y1);
and y2(Pout[3],x2,y1);
endmodule

//Verilog code for 4-bit PIPO reg by instantiation.

module PIPO_4b (
input clk,rst,
input [3:0] In,
output [3:0] Out
);

dff x1(clk,rst,In[0],Out[0]);
dff x2(clk,rst,In[1],Out[1]);
dff x3(clk,rst,In[2],Out[2]);
dff x4(clk,rst,In[3],Out[3]);
endmodule
//Linear test fixture for 4-bit PIPO reg by instantiation.

module PIPO_4b_tf ();

reg clk,rst;
reg [3:0] In;
wire [3:0] Out;
PIPO_4b x1(clk,rst,In,Out);

initial
begin
clk=1;rst=1;In=0;
#20 rst=0;In=4'b1010; //Sending Input of 1010 parallely in one clock cycle.
#20 $finish; //Recieving Output parallely in one clock cycle.
end

always #5 clk=~clk; //Clock time period is 10ns.

endmodule

//Verilog for 4-bit PIPO reg (using logical operator)

module PIPO_Sft (
input clk,rst,
input [3:0] Pin,
 output [3:0] Pout
);
reg [3:0] temp;

always@(posedge clk)
begin
if (rst) //Active high reset port
temp<=0;
else
temp<=Pin; //Directly assigning input data to output
end
assign Pout=temp;
endmodule

//Linear test fixture for 4-bit PIPO reg (using logical operator)

module PIPO_Sft_tf ();

reg clk,rst;
reg [3:0] Pin;
wire [3:0] Pout;

PIPO_Sft x1(clk,rst,Pin,Pout); //Insatantiating the test module

initial
begin
clk=1;rst=0;Pin=0;
 #10 rst=1;
#10 rst=0; Pin=4'b0001; //Test sequence is 0001
#20 $finish;
end

always #5 clk=~clk; //1 clock period = 10ns

endmodule

//Verilog code for PISO register by instantiation.

module PISO_4b (
input clk,rst,Sel, //Input has Sel port extra so as to select when to load the data parallely
and retrive serially.
input [3:0] In,
output Out
);
wire w1,w2,w3,w4,w5,w6;

dff a(clk,rst,In[3],w1); //To load the data Sel=0 for one clock cycle and then Sel=1 for another 4 cycles to
retrive the parallel data.
sel_PISO4b x1(Sel,In[2],w1,w2); //A sub-module block is initiated which works as a selector(2:1 MUX) to
load the data.
dff b(clk,rst,w2,w3);
sel_PISO4b x2(Sel,In[1],w3,w4);
dff c(clk,rst,w4,w5);
sel_PISO4b x3(Sel,In[0],w5,w6);
dff d(clk,rst,w6,Out); //Output is refelected after 4cycles.
endmodule

//Linear test fixture for 4-bit PISO reg by instantiation.

module PISO_4b_tf ();

reg clk,rst,Sel;
reg [3:0] In;
wire Out;
PISO_4b x1(clk,rst,Sel,In,Out);

initial
begin
clk=0;rst=0;Sel=0;In=0;
#5 rst=1;
#10 rst=0;
#10 Sel=0; In=4'b1101; //Sel is 0 for one clock cycle to load the data 1101 parallely
#10 Sel=1; //Sel is 1 for 4 clock cycles to retrive data serially one by one.
#50 $finish;
end

always #5 clk=~clk; //Clock time period is 10ns.

endmodule
//Verilog for 4-bit PISO reg (using logical operator)

module PISO_Sft (
input clk,rst,Sel, //Sel port decides when the data is parallely loaded in and when serially
taken out
input [3:0] Pin,
output Sout
);
reg [4:0] temp;

always@(posedge clk)
begin
if (rst)
temp<=0;
else
if (Sel) //If Sel=1 then data is loaded parallely
temp[4:1]<=Pin;
else //If Sel=0 then data is taken out serially
temp<=temp>>1; //For each run of clock, keeping Sel=0 the data is right shifted to
get the other MSBs
end
assign Sout=Sel ? 1'd0 : temp[0]; //Only if Sel=0, Each shift will casuse the LSB to be the
Serial output
endmodule
//Linear test fixture for 4-bit PISO reg (using logical operator)

module PISO_Sft_tf ();

reg clk,rst,Sel;
reg [3:0] Pin;
wire Sout;

PISO_Sft x1(clk,rst,Sel,Pin,Sout); //Instantiating the UUT

initial
begin
clk=1; rst=1; Sel=0; Pin=0;
#10 rst=0;
#10 Sel=1; Pin=4'b1111; //Loading the test sequence 1111
#10 Sel=0;
#50 $finish; //Output will be got serially for every clock till 4 after Sel=0
end

always #5 clk=~clk; //1 clock period = 10ns

endmodule
//Verilog for 8-bytes Single port RAM 16 address each 4 bits

module RAM_4b ( //Single port RAM meaning it can only read or write data for a
specific clock period
input clk,rst,r,w, //r and w ports are used to read and write the data into the mem reg
input [3:0] Din,address, //Din port takes the data in hand to read it to desired address location
output [3:0] Dout
);
reg [3:0] mem [15:0]; //Declaring a 16-address location each of 4-bit memeory register
reg [3:0] tDout;

always@(posedge clk)
begin
if (rst)
tDout<=4'd0;
else
if (r==0 && w==1) //Data is written only if r=0 and w=1
mem[address]<=Din; //Data in Din is written into the address
location specifed
if (r==1 && w==0) //Data is read only if r=1 and w=0
tDout<=mem[address]; //Data is retrived from the address location
mentioned
end
assign Dout=tDout;
endmodule
//Linear test fixture for 8-bytes Single port RAM 16 address each 4 bits

module RAM_4b_tf ();

reg clk,rst,r,w;
reg [3:0] Din,address;
wire [3:0] Dout;

RAM_4b x1(clk,rst,r,w,Din,address,Dout); //Instantiating the UUT

initial
begin
clk=1;rst=1;r=0;w=0;
#10 rst=0;w=1; //Starting to write the data into the mem reg specifying the address
location
#10 address=4'd8; Din=4'd1;
#10 address=4'd15; Din=4'd8;
#10 address=4'd10; Din=4'd2;
#10 address=4'd5; Din=4'd5;
#10 w=0;r=1; //Now reading the data from previously assigned address locations
#10 address=4'd8;
#10 address=4'd15;
#10 address=4'd10;
#10 address=4'd5;
#10 $finish;
end

always #5 clk=~clk;
endmodule
//Verilog for 8-bytes Dual port RAM 16 address each 4 bits

module RAM_4b2P ( //Dual port RAM can read and write the data simultaneously for a same
clock period
input clk,rst,
input [3:0] Din,add1,add2, //add1 port specifies the address location for writing the data into and add2
specifies the data to be retrived
output [3:0] Dout
);
reg [3:0] mem [15:0]; //Declaring a 16-address location each of 4-bit memeory register
reg [3:0] tDout;

always@(posedge clk)
begin
if (rst)
tDout<=4'd0;
else
begin
mem[add1]<=Din; //Writing the value into the mem reg as per the location mentioned
in the add1
tDout<=mem[add2]; //Reading the value from the location mentioned in the add2 and
displaying that as o/p
end
end
assign Dout=tDout;
endmodule
//Linear test fixture for 8-bytes Dual port RAM 16 address each 4 bits

module RAM_4b2P_tf ();

reg clk,rst;
reg [3:0] Din,add1,add2;
wire [3:0] Dout;

RAM_4b2P x1(clk,rst,Din,add1,add2,Dout); //Instantiating the UUT

initial
begin
clk=1;rst=1;add1=0;add2=0;Din=0;
#10 rst=0; add1=4'd2;Din=4'd4; //Writing the data into the add1 location
#10 add1=4'd15;Din=4'd7;add2=4'd2; //Writing the data into add1 location and reading the already
present data from the add2 locations
#10 add1=4'd10;Din=4'd9;add2=4'd15;
#10 add1=4'd4;Din=4'd14;add2=4'd10;
#10 add1=4'd7;Din=4'd6;add2=4'd4;
#10 add1=4'd11;Din=4'd12;add2=4'd7;
#10 add2=4'd11;
#10 $finish;
end

always #5 clk=~clk;
endmodule
//Verilog code for random sequence generator using T-flip flops

module ran_sqgen (
input clk,
output [3:0] out
);
wire T0;

xor g1(T0,out[3],out[2]); //The o/p of xor of 2 and 3 flip flops is given to i/p of 1st flip flop
seq_tff x1(clk,T0,out[0]); //A T-ff block with initial Q=1
seq_tff1 x2(clk,out[0],out[1]); //A T-ff block with initial Q=0
seq_tff1 x3(clk,out[1],out[2]);
seq_tff1 x4(clk,out[2],out[3]); //o/p of each flip flop is given to 1 bit of out reg
endmodule

//Linear test fixture for random sequence generator using T-flip flops

module ran_sqgen_tf ();

reg clk;
wire [3:0] out;
 ran_sqgen x1(clk,out); //Instantiating the UUT

initial
begin
clk=0;
#200 $finish; //20 sequence is got for running the module for 200 units
end

always #5 clk=~clk;
endmodule

//Verilog code for Right Round shift

module Rnd_RSft (
input [3:0] In,
input clk,rst,
output [3:0] Out
);
reg st;
reg [3:0] tIn,tOut;

always@(posedge clk)
begin
if (rst)
begin
 tIn=In;
tOut=0;
end
else
begin
st=tIn[0];
tIn=tIn>>1;
tIn[3]=st;
tOut=tIn;
end
end
assign Out=tOut;
endmodule

//Verilog for 16 address location each 4-bit 8bytes ROM

module ROM_4b (
input clk,rst,
input [3:0] address, //address is a 4-bit reg used to specify the location of the data to be
retrived
output [3:0] Dout
);
reg [3:0] mem [15:0]; //Declaring a 16-address 4-bit memory locations where data is stored
reg [3:0] tDout;
integer j;
 always@(posedge clk)
begin
if (rst) //Active high reset, setting the output=0 and counting variable=0
begin
tDout<=4'd0;
j<=0;
end
else
begin
for (j=0; j<16; j=j+1) //For loop writes the data into the memory register
mem[j]<=j; //Data entered here is decimal 0-15 in respective address location
tDout<=#2 mem[address]; //Then after the data is read, according to the address specified the
data is written to the output port
end
end

assign Dout=tDout;
endmodule

//Linear test fixture for 16 address location each 4-bit 8bytes ROM

module ROM_4b_tf ();

reg clk,rst;
reg [3:0] address;
 wire [3:0] Dout;

ROM_4b x1(clk,rst,address,Dout); //Instantiating the UUT

initial
begin
clk=1;rst=1;address=0;
#10 rst=0;
#10 address=4'd3; //Entering the address location to retrive the data
#10 address=4'd7;
#10 address=4'd8;
#10 address=4'd15;
#10 address=4'd11;
#10 $finish;
end

always #5 clk=~clk;
endmodule
//Verilog for right shift register using logic operations

module RSh_reg (
input clk,rst,
input [3:0] In,
output [3:0] Out
);
reg [3:0] temp;

always@(posedge clk)
begin
if (rst)
begin
temp<=In; //To take a new value to shift give the value to i/p and reset=1
end
else
temp<=temp>>1; //Then reset=0, and for every clock cycle this else loop gets executed
that shifts right by 1-bit
end
assign Out=temp;
endmodule
//Linear test fixture for Right shift register using logical operator

module RSh_reg_tf();
reg clk,rst;
reg [3:0] In;
wire [3:0] Out;

RSh_reg x1(clk,rst,In,Out);

initial
begin
clk=0;rst=0;In=0;
#5 rst=1;In=1100; //Giving sequence as 1100
#5 rst=0;
#55 $finish; //The running for 5 clock; observe it gets 0000 at 4th clock.
end

always #5 clk=~clk;
endmodule

module sel_PISO4b (
input S,Pin,Q,
output out
);
wire w1,w2,w3;

not x1(w1,S);
 and x2(w2,w1,Pin);
and x3(w3,S,Q);
or x4(out,w2,w3);
endmodule

//Verilog for 4-bit sequence detector Melay model without overlapping

module seq_dect (
input clk,rst,Sin,
output flag
);

reg [1:0] cs, ns; //Variables for current state and next state
reg tflag;
parameter S0 = 2'b00, //Defining all the 4 states in the state diagram with an unique binary number for each
S1 = 2'b01,
S2 = 2'b10,
S3 = 2'b11;

always @(cs or Sin) //Execute the check for state change if current state changes or another bit of
the sequence is given
begin
case (cs) //Depending on the value of current state the sequence will reach where it left
previously
S0: if (Sin == 1'b1) //The sequence to be detected is mentioned in 'if' condition bit by bit for
each state
begin
 ns = S1; //If the sequence matches then the next state will assigned to move
on and check the other 3 bits of the sequence
tflag=1'b0; //Keeping the tflag low untill the complete sequence is detected
end
else
begin
ns = cs; //If it is not matching the first bit it self it will wait in the same
state untill the next Sin bit is given
tflag=1'b0;
end
S1: if (Sin == 1'b0)
begin
ns = S2;
tflag=1'b0;
end
else
begin //These states are written customly watching the state
diagrams
tflag=1'b0;
ns = cs;
end
S2: if (Sin == 1'b1)
begin
ns = S3;
tflag=1'b0;
end
else
begin
ns = S0;
 tflag=1'b0;
end
S3: if (Sin == 1'b0)
begin
ns = S0; //In this last state, even if the last bit matches then it hoes back to
initial state as in the state diagram
tflag=1'b1; //tflag will be high indicating that the sequence is detected
end
else
begin
ns = S1;
tflag=1'b0;
end
default: ns = S0;
endcase
end

always@(posedge clk) //This blocks is to set the reset and the current state condition to next
state as executed in the case blocks
begin
if (rst)
cs <= S0;
else
cs <= ns;
end
assign flag=tflag;
endmodule
//Verilog for 4-bit sequence detector Melay model with overlapping

module seq_dect_olp (
input clk,rst,Sin,
output flag
);
reg tflag;
reg [1:0] cs,ns;
parameter S0 = 2'b00, //Defining all the 4 states as parameter in the state diagram with an unique binary
number for each
S1 = 2'b01,
S2 = 2'b10,
S3 = 2'b11;

always @(cs or Sin)

begin
case (cs)
S0: if (Sin == 1'b1)
begin
ns = S1;
tflag=1'b0;
end
else
begin
ns = cs;
tflag=1'b0;
 end
S1: if (Sin == 1'b0)
begin
ns = S2;
tflag=1'b0;
end
else
begin
ns = cs;
tflag=1'b0;
end
S2: if (Sin == 1'b1)
begin
ns = S3;
tflag=1'b0;
end
else
begin
ns = S0;
tflag=1'b0;
end
S3: if (Sin == 1'b0)
begin
ns = S2;
tflag=1'b1;
end
else
begin
ns = S1;
 tflag=1'b0;
end
default: ns = S0;
endcase
end

always@(posedge clk)
begin
if (rst)
cs <= S0;
else
cs <= ns;
end
assign flag=tflag;
endmodule

//Linear test fixture for 4-bit sequence detector Melay model with overlapping

module seq_dect_olp_tf();
reg clk,rst,Sin;
wire flag;

seq_dect_olp x1(clk,rst,Sin,flag); //Instantiating the UUT

initial
begin
 clk=1;rst=1;Sin=0;
#10 rst=0;
Sin=0;#10 Sin=1;#10 Sin=0;#10 Sin=1; //Inputing a 16-bit test sequence of 1101_0100_1010_1101
#10 Sin=0;#10 Sin=0;#10 Sin=1;#10 Sin=0;
#10 Sin=1;#10 Sin=1;#10 Sin=0;#10 Sin=1;
#10 Sin=0;#10 Sin=1;#10 Sin=0;#10 Sin=1; //Flag should be high 2 times for 2 sequences detected here
#20 $finish;
end

always #5 clk=~clk;
endmodule

//Linear test fixture for 4-bit sequence detector Melay model without overlapping

module seq_dect_tf();
reg clk,rst,Sin;
wire flag;

seq_dect x1(clk,rst,Sin,flag); //Instantiating the UUT

initial
begin
clk=1;rst=1;Sin=0;
#10 rst=0;
Sin=0;#10 Sin=1;#10 Sin=0;#10 Sin=1; //Inputing a 16-bit test sequence of 1101_0100_1010_1101
#10 Sin=0;#10 Sin=0;#10 Sin=1;#10 Sin=0;
#10 Sin=1;#10 Sin=1;#10 Sin=0;#10 Sin=1;
#10 Sin=0;#10 Sin=1;#10 Sin=0;#10 Sin=1; //Flag should be high 2 times for 2 sequences detected here
 #20 $finish;
end

always #5 clk=~clk;
endmodule

//Verilog code for T-flip flop for a random sequence generator with initial Q=1

module seq_tff (
input clk,T,
output Q
);
reg tQ;

initial
tQ<=1;

always@(posedge clk)
begin
if (T==0)
tQ<=Q;
else
tQ<=~Q;
end
assign Q=tQ;
endmodule
//Verilog code for T-Flip flop for a random sequence generator with initial Q=0

module seq_tff1 (
input clk,T,
output Q
);
reg tQ;

initial
tQ=0;

always@(posedge clk)
begin
if (T==0)
tQ<=Q;
else
tQ<=~Q;
end
assign Q=tQ;
endmodule
//Verilog code for 4-bit sequence generator

module seq4b_gen (
input clk,rst,Din,
output Out
);
reg tOut;
integer j=0;

always@(posedge clk)
begin
if (rst)
tOut<=0;
else
case (j) //A D_ff is used here, for
sequence 1011, Din is kept high
2'd0 : begin tOut<=Din; j<=1; end //LSB comes first so Din=1 is taken as it is and
j is assigned 1
2'd1 : begin tOut<=Din; j<=2; end
2'd2 : begin tOut<=~Din; j<=3; end //When we require 0 is the sequence we change
it to ~Din
2'd3 : begin tOut<=Din; j<=0; end //Finally j is assigned 0 so that the loop of
sequence genaration continues
endcase
end
assign Out=tOut;
endmodule
//Linear test fixture for 4-bit sequence generator

module seq4b_gen_tf();
reg clk,rst,Din;
wire Out;

seq4b_gen x1(clk,rst,Din,Out); //Instantiating the UUT

initial
begin
clk=1; rst=1; Din=1; //Din is kept 1 of the test sequence 1011
#10 rst=0;
#160 $finish; //Test sequence is run for 4 cycles
end

always #5 clk=~clk;
endmodule

//Verilog code for D_ff instantiated 4-bit SIPO reg.

module SIPO_4b (
input clk,rst,Sin,
output [3:0] Pout
);
//Serial Input data is given to 1st D_ff
dff x1(clk,rst,Sin,Pout[3]); //Output of 1st D_ff is given to MSB of Pout reg.
 dff x2(clk,rst,Pout[3],Pout[2]);
dff x3(clk,rst,Pout[2],Pout[1]);
dff x4(clk,rst,Pout[1],Pout[0]); //Output is refelected in the same cycle as the last input value is declared.
endmodule

//Linear test fixture for 4-bit SIPO reg by instantiation

module SIPO_4b_tf ();

reg clk,rst,Sin;
wire [3:0] Pout;

SIPO_4b x1(clk,rst,Sin,Pout); //Instantiating the module to be tested.

initial
begin
clk=0;rst=0;Sin=0;
#5 rst=1;
#10 rst=0; Sin=0; //Serial input is given one by one after every clock cycle
#10 Sin=1;
#10 Sin=1;
#10 Sin=0;
#10 $finish; //Parallel output is got after one more clock cycle of input completion
end

always #5 clk=~clk; //1 Clock period is 10ns

endmodule
//Verilog for 4-bit SIPO reg using logical operators

module SIPO_Sft (
input clk,rst,Sin,
output [3:0] Pout
);
reg [3:0] temp;
reg [3:0] tOut;
integer j=0;

always@(posedge clk)
begin
if (rst)
begin
temp<=0; //Pout will only show the data we want after 4 Sin bits are
assigned
tOut<=0;
end
else
begin
tOut<=0; //Using tOut=0, so that after 4 cycles of Sin Pout=0, without
reseting
temp<=temp>>1; //After every clock cycle the previous Sin is taken and shifted
right making room for next Sin
temp[3]<=Sin; //First Sin is an LSB for Pout reg
 j<=j+1; //After 4 cycles of Sin and 1 cycle of shifting the last bit to
temp reg j=4
end
if (j==4) //When j=4 the complete 4 bit Sin data in temp is assigned to tOut
begin
tOut<=temp;
j<=0; //Then again j is 0 for next 4 input cycles
end
end
assign Pout=tOut;
endmodule

//Linear test fixture for 4-bit SIPO reg (using logical operator)

module SIPO_Sft_tf ();

reg clk,rst,Sin;
wire [3:0] Pout;

SIPO_Sft x1(clk,rst,Sin,Pout);

initial
begin
clk=0;rst=0;
#5 rst=1;
#10 rst=0; Sin=1; // Test sequence is 0111
 #10 Sin=1;
#10 Sin=1; //Each Sin bit is given for each clock
#10 Sin=0;
#40 $finish; //Pout is shown after an extra clock
end

always #5 clk=~clk; //1 Clock= 10ns

endmodule

//Verilog for SISO registers using logic

module SISO_Sft (
input clk,rst,Sin,
output Sout
);
reg temp;

always@(posedge clk)
begin
if (rst)
temp<=0;
else
temp<=Sin; //Similar to D-flip flop; input is seen after a clock delay at output
end
assign Sout=temp;
endmodule
//Linear test fixture for SISO shift register

module SISO_Sft_tf ();

reg clk,rst,Sin;
wire Sout;

SISO_Sft x1(clk,rst,Sin,Sout);

initial
begin
clk=1;rst=0;Sin=0;
#10 rst=1;
#10 rst=0;
#10 Sin=1; //Test sequence given is 1101
#10 Sin=0;
#10 Sin=1; //Input data is given serially one by one for every clock period
#10 Sin=1;
#20 $finish;
end

always #5 clk=~clk;
endmodule
//Verilog code for SISO reg uisng D_ff module instantiation.

module SISO4_inst (
input clk,rst,In,
output Out
);
wire w1,w2,w3;

dff x1(clk,rst,In,w1); //Synchronous Clock.

dff x2(clk,rst,w1,w2);
dff x3(clk,rst,w2,w3);
dff x4(clk,rst,w3,Out); //Input refelects after 8 clock cycles.
endmodule

//Linear test fixture for instantiated SISO reg.

module SISO4_inst_tf ();

reg clk,rst,In;
wire Out;
SISO4_inst x1(clk,rst,In,Out);

initial
begin
clk=0;rst=0;In=0;
#5 rst=1;
 #10 rst=0;In=1; //Sending data of 1011 serially in so LSB goes first
#10 In=1;
#10 In=0; //Here time delay after each Serial input should be 10 so that it matches with full one
clock period.
#10 In=1;
#40 $finish; //Complete Input data is reflected after 3 clock cycles.
end

always #5 clk=~clk; //Time period of clock is 10ns.

endmodule

//Verilog for T-flip flop with reset and preset (used in Jonson counter)

module tff_inst (
input clk,rst,prst,
output Q,Qb
);

dff_B x1(clk,rst,prst,~Q,Q,Qb); //This T-ff is run only for toggling condition

endmodule
//Verilog code for Right and left round shift in a single module

module Uni_Rnsft(
input clk,rst,R_L, //R_L input port controls the right or left round shift
operation
input [3:0] In,
output [3:0] Out
);
reg [3:0] tOut;

always@(posedge clk) //Shift takes place for every clock period

begin
if (rst)
begin
tOut<=In; //When reset is high the 4-bit to be shifted is assigned
to reg
end
else
if (R_L)
tOut<={tOut[0],tOut[3:1]}; //If R_L = 1, right round shift is carried out
else
tOut<={tOut[2:0],tOut[3]}; //If R_L = 0, left round shift is carried out
end
assign Out=tOut;
endmodule
//Linear test fixture for Right and Left round shift in a single module

module Uni_Rnsft_tf ();

reg clk,rst,R_L;
reg [3:0] In;
wire [3:0] Out;

Uni_Rnsft x1(clk,rst,R_L,In,Out); //Instantiating the UUT

initial
begin
clk=1; rst=1; R_L=0; In=0011; //Test sequence is 0011, is loaded when rst=1
#10 rst=0; R_L=1; //For R_L=1 right around shift is carried out 8 times on 0011
#80 R_L=0; //For R_L=0 right around shift is carried out 8 times on 0011
#80 $finish;
end

always #5 clk=~clk;
endmodule

//Verilog code for 4-bit Up counter.

module upcount_B(
input clk,rst,
output [3:0] cn_out
);
 reg [3:0] temp; //Using a temporary register for using inside a procedural block

always@(posedge clk)
begin
if (rst)
temp<=0; //For an always@(posedge clk) block always use non-blocking statements
else
temp<=temp+1; //Logic for repetative down counting
end
assign cn_out=temp; //Assigning the temp reg value for our actual output port
endmodule

//Linear test fixture for 4-bit upcounter

module upcount_B_tf(); //A stimulus block does not contain any i/p or o/p ports
reg clk,rst; //Inputs of the UDT are defined as reg
wire [3:0] cn_out; //Outputs of the UDT are defined as wire; port connection rule

upcount_B x1(clk,rst,cn_out); //Initiation of UDT module

initial
begin
clk=0;rst=0;
#5 rst=1;
#15 rst =0;
#160 $finish;
 end

always #5 clk=~clk; //Time period of clock is 10ns

endmodule

//Verilog code for 4-bit up-down counter

module updncount_B (
input clk,rst,up, //Additon of i/p port up; which indicates the mode of working
output [3:0] cn_out // output [n:0] for n-bit counter
);
reg [3:0] temp;

always@(posedge clk)
begin
if (rst)
temp<=0;
else
if (up) //If up=1, works as Up counter
temp<=temp+1;
else //If up=0, works as Down counter
temp<=temp-1;
end

assign cn_out=temp;
endmodule
//Linear test fixture for for 4-bit up-down counter

module updncount_B_tf ();

reg clk,rst,up;
wire [3:0] cn_out;
updncount_B x1(clk,rst,up,cn_out);

initial
begin
clk=0;rst=0;up=0;
#5 rst=1;
#15 rst=0;
#160 up=1; //Run for 16 states (1 full counting cycle) each state taking 1 clock cycle(10ns) for
downcounter first
#160 $finish; //Run the same for upcounter
end
always #5 clk=~clk; //Timne period= 1 clock cycle=10ns
endmodule
//Verilog code for 4-bit up-down Mod-N counter

module updnmod_cn (
input clk,rst,u_d, //u_d port value decides up or down Mod counter
input [3:0] n, //n value decides Mod-(1-14) counter
output [3:0] cn_out
);
reg [3:0] temp;

always@(posedge clk)
begin
if(rst)
temp<=0;
else
if (u_d)
if (temp==n-1) //If temp=7 then it resets the value back to 0 to count from
there
temp<=0;
else
temp<=temp+1; //temp value gets up counted untill it reaches its n-1 count
value
else
if (temp==(16-n)) //If temp=7 then it resets to 15 and down counts
temp<=4'b1111;
else
temp<=temp-1; //Down count logic
end
assign cn_out=temp;
endmodule

//Verilog code for 4-bit up-down Mod-N counter

module updnmod_cn (
input clk,rst,u_d, //u_d port value decides up or down Mod counter
input [3:0] n, //n value decides Mod-(1-14) counter
output [3:0] cn_out
);
reg [3:0] temp;

always@(posedge clk)
begin
if(rst)
temp<=0;
else
if (u_d)
if (temp==n-1) //If temp=7 then it resets the value back to 0 to count from
there
temp<=0;
else
temp<=temp+1; //temp value gets up counted untill it reaches its n-1 count
value
else
 if (temp==(16-n)) //If temp=7 then it resets to 15 and down counts
temp<=4'b1111;
else
temp<=temp-1; //Down count logic
end
assign cn_out=temp;
endmodule