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Module SIPO

The document contains Verilog code for various shift register designs including: - A 4-bit serial-in parallel-out shift register with clock, reset and serial data input. - Several 8-bit serial-in serial-out shift registers with different clocking schemes like positive edge, negative edge, asynchronous clear, synchronous set. - An 8-bit serial-in parallel-out shift register. - An 8-bit shift register with asynchronous/synchronous parallel load in addition to serial input. - An 8-bit shift-left/right register that can shift in either direction.

Uploaded by

VenkatGolla
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
1K views

Module SIPO

The document contains Verilog code for various shift register designs including: - A 4-bit serial-in parallel-out shift register with clock, reset and serial data input. - Several 8-bit serial-in serial-out shift registers with different clocking schemes like positive edge, negative edge, asynchronous clear, synchronous set. - An 8-bit serial-in parallel-out shift register. - An 8-bit shift register with asynchronous/synchronous parallel load in addition to serial input. - An 8-bit shift-left/right register that can shift in either direction.

Uploaded by

VenkatGolla
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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module SIPO ( din ,clk ,reset ,dout );

output [3:0] dout ;


wire [3:0] dout ;
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [3:0]s;
always @ (posedge (clk)) begin
if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end
assign dout = s;

endmodule

Verilog code for an 8-bit shift-left register with a positive-edge clock, serial in and serial out.
module shift (clk, si, so);
input
clk,si;
output
so;
reg
[7:0] tmp;
always @(posedge clk)
begin
tmp
<= tmp << 1;
tmp[0] <= si;
end
assign so = tmp[7];
endmodule

Verilog code for an 8-bit shift-left register with a negative-edge clock, a clock enable, a serial in
and a serial out.

module shift (clk, ce, si, so);


input
clk, si, ce;
output
so;
reg
[7:0] tmp;
always @(negedge clk)
begin
if (ce) begin
tmp
<= tmp << 1;
tmp[0] <= si;
end
end
assign so = tmp[7];
endmodule
Verilog code for an 8-bit shift-left register with a positive-edge clock, asynchronous clear, serial in
and serial out.
module shift (clk, clr, si, so);
input
clk, si, clr;
output
so;
reg
[7:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 8b00000000;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule
Verilog code for an 8-bit shift-left register with a positive-edge clock, a synchronous set, a serial in
and a serial out.
module shift (clk, s, si, so);
input
clk, si, s;
output
so;
reg
[7:0] tmp;
always @(posedge clk)
begin
if (s)
tmp <= 8b11111111;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule

Verilog code for an 8-bit shift-left register with a positive-edge clock, a serial in and a parallel out.

module shift (clk, si, po);


input
clk, si;
output [7:0] po;
reg
[7:0] tmp;
always @(posedge clk)
begin
tmp <= {tmp[6:0], si};
end
assign po = tmp;
endmodule

Verilog code for an 8-bit shift-left register with a positive-edge clock, an asynchronous parallel
load, a serial in and a serial out.
module shift (clk, load, si, d, so);
input
clk, si, load;
input [7:0] d;
output
so;
reg
[7:0] tmp;
always @(posedge clk or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule

Verilog code for an 8-bit shift-left register with a positive-edge clock, a synchronous parallel load,
a serial in and a serial out.
module shift (clk, sload, si, d, so);
input
clk, si, sload;
input [7:0] d;
output
so;
reg
[7:0] tmp;
always @(posedge clk)
begin
if (sload)
tmp <= d;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule

Verilog code for an 8-bit shift-left/shift-right register with a positive-edge clock, a serial in and a
serial out.
module shift (clk, si, left_right, po);
input
clk, si, left_right;
output
po;
reg
[7:0] tmp;
always @(posedge clk)
begin
if (left_right == 1b0)
tmp <= {tmp[6:0], si};
else
tmp <= {si, tmp[7:1]};
end
assign po = tmp;
endmodule

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