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Full Subtractor VHDL Code Using Structural Modeling

The document describes a VHDL code for a full subtractor using structural modeling. It includes a library declaration, entity declaration for the full subtractor with input and output ports, signal declaration, component declarations for logic gates, and architecture with components port mapped to perform full subtraction. The code structurally models the full subtractor circuit using logic gates like XOR, AND and OR.

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16K views

Full Subtractor VHDL Code Using Structural Modeling

The document describes a VHDL code for a full subtractor using structural modeling. It includes a library declaration, entity declaration for the full subtractor with input and output ports, signal declaration, component declarations for logic gates, and architecture with components port mapped to perform full subtraction. The code structurally models the full subtractor circuit using logic gates like XOR, AND and OR.

Uploaded by

OP2R
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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FULL SUBTRACTOR VHDL CODE USING STRUCTURAL MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------

Std_logic_1164; package for std_logic (predefined data type).

entity full_subtractor is Port ( a, b, c: in STD_LOGIC; difff ,borrow: out STD_LOGIC); end full_subtractor; --------------------------------------------architecture Behavioral_FS of full_subtractor is ------------------------------------------------------------signal c1, c2, c3, s1: in std_logic; component xor_2 is port (k,d,e: in std_logic; f: out std_logic); end component; component and_1 is Port ( x,y : in STD_LOGIC; z : out STD_LOGIC); end component; component or_1 is Port ( g,h,i : in STD_LOGIC; z : out STD_LOGIC); end component; component not_1 is port (u: in std_logic; v: out std_logic); end component; ----------------------------------------------------begin X0: xor_2 port map (a,b,c, diff); X2: and_1 port map (s1,b,c1); X3: and_1 port map (c,b,c2); X4: and_1 port map (s1,c,c3); x5: or_1 port map (c1, c2, c3, borrow); -------------------------------------------------end Behavioral_FS;

Entity declaration. a, b, c :- input port bits (bits to be added) diff, borrow:- output port bits

Signal declaration. Signal c1, c2, c3 will act as inout port. Component (Ex-or, and, or) declaration. Declarative part of full adders Architecture. Components represent the structure of full adder circuit.

Statements part of the architecture. Components are port mapped to perform full subtraction operation.

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