Verilog
Verilog
Verilog
yes no
1 X Z Both X and Z
5.In the following figure A is input and B is output of inverter and C is clock. Tell whether inverter is working synchronously or asynchronously?
6.In the above figure, tell whether inverter is working on positive edge or negative edge of clock?
negative edge positive edge both on positive edge and negative edge middle of positive and negative edge of clock
9.In the figure given in ques7, tell whether it is a positive edge reset or negative edge?
both positive and negative edge reset negative edge reset positive edge unpredictable
no yes using `include yes using `define yes by just writing the name of file in another file
1: Verilog was later submitted to ________ and became IEEE Standard 1364-1995, commonly referred to as Verilog-95. Institute of Electrical and Electronics Engineers EEE Computer Society IEEE Technical Activities Board IEEE Microwave Theory and Techniques Society
Question 2: The designers of Verilog wanted a language with syntax similar to the ________, which was already widely used in engineering software development. Pointer (computing) D (programming language) C (programming language) C++
Question 3: Verilog syntax A description of the syntax in ________. Parsing expression grammar Extended BackusNaur Form Programming language BackusNaur Form
Question 4: The advent of hardware verification languages such as OpenVera, and Verisity's e language encouraged the development of ________ by Co-Design Automation Inc. Logarithm Tetration Exponentiation Super-logarithm
Question 5: For information on Verilog simulators, see the ________. List of Verilog simulators Hardware description language Field-programmable gate array SystemVerilog
Question 6: These extensions became ________ Standard 1364-2001 known as Verilog-2001. IEEE Microwave Theory and Techniques Society Institute of Electrical and Electronics Engineers IEEE Technical Activities Board IEEE Computer Society
Question 7: The PLI enables Verilog to cooperate with other programs written in the C language such as test harnesses, instruction set simulators of a microcontroller, ________, and so on. Debugger IBM OLIVER (CICS interactive test/debug) Computer programming Memory debugger
Question 8: Hardware description languages, such as Verilog, differ from software ________ because they include ways of describing the propagation of time and signal dependencies (sensitivity). Functional programming Programming language Programming paradigm Computer
Question 9: In the semiconductor and electronic design industry, Verilog is a ________ (HDL) used to model electronic systems. Field-programmable gate array Programming language Hardware description language Application-specific integrated circuit
Question 10: Gateway Design Automation was purchased by ________ in 1990. Synopsys Cadence Design Systems Electronic design automation Mentor Graphics
VHDL is a Virtual Hardware Description Language. TRUE FALSE VHDL uses an ENTITY declaration to dene the interface of a component or block. TRUE FALSE
VHDL uses an ARCHITECTURE declaration to describe how a component or block should perform. TRUE FALSE
The data ow style of programming in VHDL uses assignment statements to drive one or more signals in parallel.
TRUE FALSE
The structural style of programming in VHDL allows the designer to use sequential semantics to dene the behavior of a hardware component or block TRUE FALSE
Which standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and ________ circuit design extensions. Ku band Microwave X-ray Radio waves
Question 3: VHDL is a ________, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. Visual programming language Dataflow programming Programming paradigm Concurrent computing
Question 5: Many ________ design packages offer alternative design input methods, such as blockdiagram (schematic) and state-diagram capture. Field-programmable gate array Programmable logic device
Question 6: A ________ is basically one bit of memory which is updated when an enable signal is raised: Logic gate Integrated circuit Flip-flop (electronics) Latch (electronics)
Question 7: Modern synthesis tools can extract RAM, ________, and arithmetic blocks out of the code, and implement them according to what the user specifies. Counter Digital electronics Finite-state machine Flip-flop (electronics)
Question 8: One particular pitfall is the accidental production of ________ rather than D-type flip-flops as storage elements. Integrated circuit Latch (electronics) NAND gate Logic gate
Question 9: Nearly all FPGA design and simulation flows support both VHDL and ________, another hardware description language, allowing the user to learn either or both languages. Field-programmable gate array Verilog
Question 10: The ________, or 'MUX' as it is usually called, is a simple construct very common in hardware design. Multiplexing Orthogonal frequency-division multiple access Multiplexer Media Access Control