Ca3140 A
Ca3140 A
Ca3140 A
Data Sheet
FN957.10
Features
MOSFET Input Stage
- Very High Input Impedance (ZIN) -1.5T (Typ)
- Very Low Input Current (Il) -10pA (Typ) at 15V
- Wide Common Mode Input Voltage Range (VlCR) - Can be
Swung 0.5V Below Negative Supply Voltage Rail
- Output Swing Complements Input Common Mode
Range
Directly Replaces Industry Type 741 in Most Applications
Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Ground-Referenced Single Supply Amplifiers in
Automobile and Portable Instrumentation
Sample and Hold Amplifiers
Long Duration Timers/Multivibrators
(seconds-Minutes-Hours)
Photocurrent Instrumentation
Peak Detectors
Active Filters
Comparators
Interface in 5V TTL Systems and Other Low
Supply Voltage Systems
All Standard Operational Amplifier Applications
Function Generators
Tone Controls
Power Supplies
Portable Instruments
Intrusion Alarm Systems
Pinout
CA3140 (PDIP, SOIC)
TOP VIEW
OFFSET
NULL
INV. INPUT
NON-INV.
INPUT
V-
STROBE
V+
OUTPUT
OFFSET
NULL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1998, Copyright Intersil Americas Inc. 2002, 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
CA3140, CA3140A
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE (C)
PACKAGE
PKG.
DWG. #
CA3140AE
-55 to 125
8 Ld PDIP
E8.3
CA3140AEZ*
(See Note)
-55 to 125
8 Ld PDIP
(Pb-free)
E8.3
CA3140AM
(3140A)
-55 to 125
8 Ld SOIC
M8.15
CA3140AM96
(3140A)
-55 to 125
CA3140AMZ
(3140A) (See Note)
-55 to 125
8 Ld SOIC
(Pb-free)
CA3140AMZ96
(3140A) (See Note)
-55 to 125
CA3140E
-55 to 125
8 Ld PDIP
E8.3
CA3140EZ*
(See Note)
-55 to 125
8 Ld PDIP
(Pb-free)
E8.3
CA3140M
(3140)
-55 to 125
8 Ld SOIC
M8.15
CA3140M96
(3140)
-55 to 125
CA3140MZ
(3140) (See Note)
-55 to 125
8 Ld SOIC
(Pb-free)
CA3140MZ96
(3140) (See Note)
-55 to 125
M8.15
M8.15
FN957.10
July 11, 2005
CA3140, CA3140A
Absolute Maximum Ratings
Thermal Information
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details
2. Short circuit may be applied to ground or to either supply.
VSUPPLY = 15V, TA = 25oC
Electrical Specifications
TYPICAL VALUES
PARAMETER
SYMBOL
TEST CONDITIONS
Typical Value of Resistor
Between Terminals 4 and 5 or 4 and 1 to
Adjust Max VIO
CA3140
CA3140A
UNITS
4.7
18
Input Resistance
RI
1.5
1.5
Input Capacitance
CI
pF
Output Resistance
RO
60
60
eN
BW = 140kHz, RS = 1M
48
48
eN
RS = 100
f = 1kHz
40
40
nV/Hz
f = 10kHz
12
12
nV/Hz
IOM+
Source
40
40
mA
IOM-
Sink
18
18
mA
fT
4.5
4.5
MHz
SR
V/s
220
220
Rise Time
0.08
0.08
Overshoot
10
10
To 1mV
4.5
4.5
To 10mV
1.4
1.4
tr
OS
tS
RL = 2k
CL = 100pF
RL = 2k
CL = 100pF
Voltage Follower
Electrical Specifications
CA3140
PARAMETER
CA3140A
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
|VIO|
15
mV
|IIO|
0.5
30
0.5
20
pA
II
10
50
10
40
pA
Input Current
FN957.10
July 11, 2005
CA3140, CA3140A
For Equipment Design, at VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified (Continued)
Electrical Specifications
CA3140
PARAMETER
Large Signal Voltage Gain (Note 3)
(See Figures 6, 29)
Common Mode Rejection Ratio
(See Figure 34)
CA3140A
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
AOL
20
100
20
100
kV/V
86
100
86
100
dB
32
320
32
320
V/V
70
90
70
90
dB
CMRR
VICR
-15
-15.5 to +12.5
11
-15
-15.5 to +12.5
12
PSRR
100
150
100
150
V/V
76
80
76
80
dB
VOM+
+12
13
+12
13
VOM-
-14
-14.4
-14
-14.4
I+
mA
Device Dissipation
PD
120
180
120
180
mW
VIO/T
V/oC
Electrical Specifications
TYPICAL VALUES
PARAMETER
SYMBOL
CA3140
CA3140A
UNITS
|VIO|
mV
|IIO|
0.1
0.1
pA
Input Current
II
pA
Input Resistance
RI
AOL
100
100
kV/V
100
100
dB
32
32
V/V
90
90
dB
-0.5
-0.5
2.6
2.6
PSRR
VIO/VS
100
100
V/V
80
80
dB
VOM+
CMRR
VICR
VOM-
0.13
0.13
Source
IOM+
10
10
mA
Sink
OM-
mA
SR
V/s
fT
3.7
3.7
MHz
I+
1.6
1.6
mA
Device Dissipation
PD
mW
200
200
FN957.10
July 11, 2005
CA3140, CA3140A
Block Diagram
2mA
4mA
7 V+
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
200A
1.6mA
2A
A
10,000
A 10
INPUT
200A
2mA
A1
6 OUTPUT
2
C1
12pF
5
1
OFFSET
NULL
4 VSTROBE
Schematic Diagram
BIAS CIRCUIT
INPUT STAGE
SECOND STAGE
OUTPUT STAGE
D1
D7
Q1
Q3
Q2
D8
R10
1K
Q4
Q5
Q6
Q20
R9
50
Q19 R11
20
Q7
R12
12K
R14
20K
Q21
Q17
R1
8K
R13
5K
R8
Q8
1K Q
18
6 OUTPUT
D2
D3
D4
D5
INVERTING
INPUT
NON-INVERTING
INPUT
Q9
Q10
C1
R2
500
R3
500
12pF
Q14
Q11
R4
500
Q12
R5
500
NOTE:
Q16
D6
R6
50
1
OFFSET NULL
Q15
Q13
R7
30
STROBE
V-
FN957.10
July 11, 2005
CA3140, CA3140A
Application Information
Circuit Description
As shown in the block diagram, the input terminals may be
operated down to 0.5V below the negative supply rail. Two
class A amplifier stages provide the voltage gain, and a
unique class AB amplifier stage provides the current gain
necessary to drive low-impedance loads.
A biasing circuit provides control of cascoded constant current
flow circuits in the first and second stages. The CA3140
includes an on chip phase compensating capacitor that is
sufficient for the unity gain voltage follower configuration.
Input Stage
The schematic diagram consists of a differential input stage
using PMOS field-effect transistors (Q9, Q10) working into a
mirror pair of bipolar transistors (Q11, Q12) functioning as load
resistors together with resistors R2 through R5. The mirror pair
transistors also function as a differential-to-single-ended
converter to provide base current drive to the second stage
bipolar transistor (Q13). Offset nulling, when desired, can be
effected with a 10k potentiometer connected across
Terminals 1 and 5 and with its slider arm connected to Terminal
4. Cascode-connected bipolar transistors Q2, Q5 are the
constant current source for the input stage. The base biasing
circuit for the constant current source is described
subsequently. The small diodes D3, D4, D5 provide gate oxide
protection against high voltage transients, e.g., static electricity.
Second Stage
Most of the voltage gain in the CA3140 is provided by the
second amplifier stage, consisting of bipolar transistor Q13
and its cascode connected load resistance provided by
bipolar transistors Q3, Q4. On-chip phase compensation,
sufficient for a majority of the applications is provided by C1.
Additional Miller-Effect compensation (roll off) can be
accomplished, when desired, by simply connecting a small
capacitor between Terminals 1 and 8. Terminal 8 is also
used to strobe the output stage into quiescence. When
terminal 8 is tied to the negative supply rail (Terminal 4) by
mechanical or electrical means, the output Terminal 6
swings low, i.e., approximately to Terminal 4 potential.
Output Stage
The CA3140 Series circuits employ a broad band output stage
that can sink loads to the negative supply to complement the
capability of the PMOS input stage when operating near the
negative rail. Quiescent current in the emitter-follower cascade
circuit (Q17, Q18) is established by transistors (Q14, Q15)
whose base currents are mirrored to current flowing through
diode D2 in the bias circuit section. When the CA3140 is
operating such that output Terminal 6 is sourcing current,
transistor Q18 functions as an emitter-follower to source current
from the V+ bus (Terminal 7), via D7, R9, and R11. Under these
conditions, the collector potential of Q13 is sufficiently high to
permit the necessary flow of base current to emitter follower
Q17 which, in turn, drives Q18.
6
Bias Circuit
Quiescent current in all stages (except the dynamic current
sink) of the CA3140 is dependent upon bias current flow in R1.
The function of the bias circuit is to establish and maintain
constant current flow through D1, Q6, Q8 and D2. D1 is a diode
connected transistor mirror connected in parallel with the base
emitter junctions of Q1, Q2, and Q3. D1 may be considered as a
current sampling diode that senses the emitter current of Q6
and automatically adjusts the base current of Q6 (via Q1) to
maintain a constant current through Q6, Q8, D2. The base
currents in Q2, Q3 are also determined by constant current flow
D1. Furthermore, current in diode connected transistor Q2
establishes the currents in transistors Q14 and Q15.
Typical Applications
Wide dynamic range of input and output characteristics with
the most desirable high input impedance characteristics is
achieved in the CA3140 by the use of an unique design based
upon the PMOS Bipolar process. Input common mode voltage
range and output swing capabilities are complementary,
allowing operation with the single supply down to 4V.
The wide dynamic range of these parameters also means
that this device is suitable for many single supply
applications, such as, for example, where one input is driven
below the potential of Terminal 4 and the phase sense of the
output signal must be maintained a most important
consideration in comparator applications.
FN957.10
July 11, 2005
CA3140, CA3140A
Output Circuit Considerations
V+
5V TO 36V
8
LOGIC
SUPPLY
5V
7
6.2V
6
CA3140
TYPICAL
TTL GATE
5V
100
+15V
+30V
10
1
0.01
0.1
1.0
LOAD (SINKING) CURRENT (mA)
10
The low voltage limitation occurs when the upper extreme of the
input common mode voltage range extends down to the voltage
at Terminal 4. This limit is reached at a total supply voltage just
below 4V. The output voltage range also begins to extend down
to the negative supply rail, but is slightly higher than that of the
input. Figure 8 shows these characteristics and shows that with
2V dual supplies, the lower extreme of the input common mode
voltage range is below ground potential.
V+
7
2
7
6
CA3140
CA3140
CA3140
6
3
5
R
10k
10k
4
5
1
10k
R
V-
V-
V-
FN957.10
July 11, 2005
CA3140, CA3140A
RS
V+
LOAD
30V
NO LOAD
MT2
120VAC
+HV
LOAD
6
CA3140
RL
3
CA3140
MT1
RL
3
4
FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES
FOLLOWER
+15V
7
0.1F
SIMULATED
LOAD
10k
6
CA3140
2k
100pF
4
0.1F
-15V
2k
0.05F
10
1mV
1mV
INVERTING
5k
8
INPUT VOLTAGE (V)
10mV
10mV
+15V
2
0
CA3140
200
-4
-8
-10
0.1
6
100pF
-6
1mV
10mV
2k
1mV
0.1F
4.99k
10mV
1.0
SETTLING TIME (s)
SIMULATED
LOAD
5k
INVERTING
-2
0.1F
FOLLOWER
5.11k
-15V
SETTLING POINT
10
D1
D2
1N914
1N914
FN957.10
July 11, 2005
CA3140, CA3140A
-75
OL
RL = 2k,
CL = 0pF
-90
-105
-120
-135
80
-150
60
RL = 2k,
CL = 100pF
40
10K
1K
100
10
20
0
101
102
103
104
105
106
FREQUENCY (Hz)
107
1
-60
108
RL =
0
+VICR AT TA = 125oC
+VICR AT TA = 25oC
+VICR AT TA = -55oC
-0.5
-1.0
+VOUT AT TA = 125oC
+VOUT AT TA = 25oC
+VOUT AT TA = -55oC
-1.5
-2.0
-2.5
-3.0
10
15
SUPPLY VOLTAGE (V+, V-)
20
-20
20
40
60
80
TEMPERATURE (oC)
100
120
140
-40
25
1.5
-VICR AT TA = 125oC
1.0
-VICR AT TA = 25oC
0.5
-VOUT FOR
TA = -55oC to 125oC
-VICR AT TA = -55oC
-0.5
-1.0
-1.5
10
15
SUPPLY VOLTAGE (V+, V-)
20
25
FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
FN957.10
July 11, 2005
CA3140, CA3140A
TA = 125oC
FOR METAL CAN PACKAGES
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
6
5
4
3
2
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2
1
0
0
500
10
FN957.10
July 11, 2005
CA3140, CA3140A
CENTERING
-15V 10k
7.5k
+15V
360
3
15k
4
5
2M
51
pF
7-60
pF
-15V
+15V
39k
120
-15V
+
CA3140
0.1
F
-15V
2k
FREQUENCY
ADJUSTMENT
10k
62k
10k
5.1k
EXTERNAL
OUTPUT
EXTERNAL
OUTPUT
2
11k
11k
10k
HIGH
FREQ.
SHAPE
+15V
100k
FROM BUFFER METER
DRIVER (OPTIONAL)
0.1
F
CA3080A
360
SYMMETRY
-15V
+15V
HIGH
FREQUENCY
LEVEL
910k
7-60pF
CA3080
+
4
2.7k
-15V
13k
TO OUTPUT
AMPLIFIER
TO
SINE WAVE
SHAPER
1N914
OUTPUT
AMPLIFIER
+15V
FREQUENCY
ADJUSTMENT
+15V
METER DRIVER
AND BUFFER
AMPLIFIER
POWER
SUPPLY 15V
-15V
FUNCTION
GENERATOR
WIDEBAND
LINE DRIVER
SINE WAVE
SHAPER
51
SWEEP
GENERATOR
FINE
RATE
GATE DC LEVEL
SWEEP ADJUST
OFF INT.
COARSE
RATE
1V/Div., 1s/Div.
EXT.
EXTERNAL
INPUT
SWEEP
LENGTH
Three tone test signals, highest frequency 0.5MHz. Note the slight
asymmetry at the three second/cycle signal. This asymmetry is due to
slightly different positive and negative integration from the CA3080A
and from the PC board and component leakages at the 100pA level.
FIGURE 10C. FUNCTION GENERATOR WITH FIXED
FREQUENCIES
V-
V-
11
FN957.10
July 11, 2005
CA3140, CA3140A
500k
FREQUENCY
ADJUSTMENT
10k
FREQUENCY
CALIBRATION
MAXIMUM
620k
7
51k
3
+
6
CA3140
SWEEP IN
3M
4.7k
4
+15V
2k
12k
FREQUENCY 2.4k
CALIBRATION
MINIMUM
2.5
k
0.1F
3
5.1k
510
3.6k 13
8
D6
D3
12
METER
POSITION
ADJUSTMENT
D4
9.1k
R1
10k
14
2k
10k
EXTERNAL
OUTPUT
D1
-15V
TO
WIDEBAND
OUTPUT
AMPLIFIER
1M
100
k
10
6
SUBSTRATE
OF CA3019
7
-15V
R3 10k
+15V
9
8
0.1F
1k
200A
M METER
510
620
11
5.6k
7.5k
CA3140
2
METER
SENSITIVITY
ADJUSTMENT
0.1F
-15V
+15V
TO CA3080A
OF FUNCTION CA3080A
GENERATOR
(FIGURE 10)
4
5
2
430
D2
1
R2
1k
3
4
D
CA3019 5
DIODE ARRAY
3/ OF CA3086
5
-15V
750k
LOG
SAWTOOTH 18M
1N914
100k
100k FINE
RATE
1M
22M
SAWTOOTH
SYMMETRY
1N914
0.47F
0.047F
8.2k
COARSE
RATE
4700pF
50k
75k
470pF
+15V
0.1
F
CA3140
+
4
51k
SAWTOOTH
LOG+15V
50k
LOG
RATE
ADJUST
-15V
43k
10k
10k
CA3140
+
4
100k
TO OUTPUT 2
AMPLIFIER
30k
0.1
F
+15V
36k
TRIANGLE
10k
GATE
PULSE
OUTPUT
-15V
EXTERNAL OUTPUT
-15V
3
CA3140
2
LOGVIO
+15V
51k
6.8k
91k
10k
TRIANGLE
25k
3.9
-15V
1
4
100
390
TRANSISTORS
FROM CA3086
ARRAY
SAWTOOTH
LOG
12
FN957.10
July 11, 2005
CA3140, CA3140A
This circuit can be adjusted most easily with a distortion
analyzer, but a good first approximation can be made by
comparing the output signal with that of a sine wave
generator. The initial slope is adjusted with the potentiometer
R1, followed by an adjustment of R2. The final slope is
established by adjusting R3, thereby adding additional
segments that are contributed by these diodes. Because
there is some interaction among these controls, repetition of
the adjustment procedure may be necessary.
REFERENCE
VOLTAGE
VOLTAGE
ADJUSTMENT
3
CA3140
INPUT
2
REGULATED
OUTPUT
Sweeping Generator
Figure 13 shows a sweeping generator. Three CA3140s are
used in this circuit. One CA3140 is used as an integrator, a
second device is used as a hysteresis switch that determines
the starting and stopping points of the sweep. A third
CA3140 is used as a logarithmic shaping network for the log
function. Rates and slopes, as well as sawtooth, triangle,
and logarithmic sweeps are generated by this circuit.
Wideband Output Amplifier
Figure 14 shows a high slew rate, wideband amplifier
suitable for use as a 50 transmission line driver. This
circuit, when used in conjunction with the function generator
and sine wave shaper circuits shown in Figures 10 and 12
provides 18VP-P output open circuited, or 9VP-P output
when terminated in 50. The slew rate required of this
amplifier is 28V/s (18VP-P x x 0.5MHz).
+15V
SIGNAL
LEVEL
ADJUSTMENT
2.5k
+15V
3k
-15V
200
2.4pF
2pF
1.8k
2N3053
1N914
2.7
1N914
2.7
51
OUT
2W
1
OUTPUT
DC LEVEL
ADJUSTMENT
2.2
k
CA3140
200
50F
25V
50F
25V
2.2
k
2N4037
-15V
Power Supplies
High input impedance, common mode capability down to the
negative supply and high output drive current capability are
key factors in the design of wide range output voltage
supplies that use a single input voltage to provide a
regulated output voltage that can be adjusted from
essentially 0V to 24V.
Unlike many regulator systems using comparators having a
bipolar transistor input stage, a high impedance reference
voltage divider from a single supply can be used in
connection with the CA3140 (see Figure 15).
13
FN957.10
July 11, 2005
CA3140, CA3140A
A small heat sink VERSAWATT transistor is used as the
series pass element in the fold back current system, Figure
17, since dissipation levels will only approach 10W. In this
system, the D2201 diode is used for current sampling.
Foldback is provided by the 3k and 100k divider network
connected to the base of the current sensing transistor.
Both regulators provide better than 0.02% load regulation.
Because there is constant loop gain at all voltage settings, the
+30V
2N6385
CURRENT
POWER DARLINGTON LIMITING
ADJUST
D2201
2
OUTPUT
0.1 24V
AT 1A
+30V
1k 200
75
1k
1k
1k
100
8
56pF
2.7k 10F
1k
2.2k
2.7k 10F
10 11
1 2
8 7
5F 50k
14
180k
1k
CA3140
6
82k
100k
82k
3
4
INPUT
INPUT
+
56pF
2
100k
1k
180k
2
CA3140
3k
2N2102
1k
100k
100k
2N2102
1
3k
OUTPUT 0V TO 25V
25V AT 1A
FOLDS BACK
TO 40mA
FOLDBACK CURRENT
LIMITER
2N5294
D2201
2
3
VOLTAGE
ADJUST
100k
250F
12
0.01F
2.2k
10 11
1 2
8 7
5F 50k
14
VOLTAGE
ADJUST
100k
250F
12
0.01F
13
13
CA3086
CA3086
1k
1k
62k
62k
HUM AND NOISE OUTPUT <200VRMS
(MEASUREMENT BANDWIDTH ~10MHz)
LINE REGULATION 0.1%/V
LOAD REGULATION
(NO LOAD TO FULL LOAD)
<0.02%
5V/Div., 1s/Div.
LOAD REGULATION
(NO LOAD TO FULL LOAD)
<0.02%
FIGURE 18. WAVEFORMS OF DYNAMIC CHARACTERISTICS OF POWER SUPPLY CURRENTS SHOWN IN FIGURES 16 AND 17
14
FN957.10
July 11, 2005
CA3140, CA3140A
Bass treble boost and cut are 15dB at 100Hz and 10kHz,
respectively. Full peak-to-peak output is available up to at
least 20kHz due to the high slew rate of the CA3140. The
amplifier gain is 3dB down from its flat position at 70kHz.
NOTES:
+30V
2.2M
0.005F
5.1
M
+
CA3140
0.1F
4
BOOST
2.2M
0.1
F
0.012F
TREBLE
CUT
200k
(LINEAR) 0.001F
18k
100
pF
7
+
CA3140
0.005F
100pF
5.1M
4
0.022F
2F
- +
0.0022F
0.1F
6
0.1F
-15V
10k
1M
100k
CCW (LOG)
BOOST
BASS
CUT
TONE CONTROL NETWORK
FIGURE 19. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)
FOR SINGLE SUPPLY
BOOST
0.047F
BASS
CUT
(LINEAR)
240k
240k
5M
750
pF
+32V
750
pF
+15V
7
3
2.2M
0.1
F
2.2
M 2
+
CA3140
51k
5M
51k
(LINEAR)
BOOST TREBLE
CUT
TONE CONTROL NETWORK
6
0.047F
20pF
0.1
F
TONE CONTROL
NETWORK
7
+
CA3140
:
9. 15dB Bass and Treble Boost and Cut at 100Hz and 10kHz, Respectively.
10. 25VP-P Output at 20kHz.
11. -3dB at 70kHz from 1kHz Reference.
12. 0dB Flat Position Gain.
0.1F
6
0.1F
-15V
15
FN957.10
July 11, 2005
CA3140, CA3140A
Wien Bridge Oscillator
Another application of the CA3140 that makes excellent use
of its high input impedance, high slew rate, and high voltage
qualities is the Wien Bridge sine wave oscillator. A basic Wien
Bridge oscillator is shown in Figure 21. When R1 = R2 = R
and C1 = C2 = C, the frequency equation reduces to the
familiar f = 1/(2RC) and the gain required for oscillation,
AOSC is equal to 3. Note that if C2 is increased by a factor of
four and R2 is reduced by a factor of four, the gain required
for oscillation becomes 1.5, thus permitting a potentially
higher operating frequency closer to the gain bandwidth
product of the CA3140.
C2
R2
NOTES:
+
OUTPUT
RF
C1
R1
RF
A CL = 1 + ------RS
RS
1000pF
3
C1 2
1000
pF
R1
7
+
CA3140
0.1F
CA3109
DIODE
ARRAY
6
SUBSTRATE
OF CA3019
1
2
0.1F
7
0.1F
-15V
7.5k
R 1 = R2 = R
50Hz, R =
100Hz, R =
1kHz, R =
10kHz, R =
30kHz, R =
1
f = ------------------------------------------2 R 1 C 1 R 2 C 2
C
R
A OSC = 1 + ------1- + ------2C2 R1
+15V
R2
C2
OUTPUT
19VP-P TO 22VP-P
THD <0.3%
3.3M
1.6M
160M
16M
5.1M
3.6k
500
30k
SAMPLE
STROBE
-15
1N914
HOLD
+15V
1N914
INPUT
+15V
5
2k
CA3080A
0.1F
7
6
0.1F
2k
3.5k
7
3
+
CA3140
6
0.1
F
100k
-15V
-15V
200pF
2k
C1
200pF
2k
400
0.1F
30pF
SIMULATED LOAD
NOT REQUIRED
16
FN957.10
July 11, 2005
CA3140, CA3140A
Pulse droop during the hold interval is 170pA/200pF which is
0.85V/s; (i.e., 170pA/200pF). In this case, 170pA represents
the typical leakage current of the CA3080A when strobed off. If
C1 were increased to 2000pF, the hold-droop rate will
decrease to 0.085V/s, but the slew rate would decrease to
0.25V/s. The parallel diode network connected between
Terminal 3 of the CA3080A and Terminal 6 of the CA3140
prevents large input signal feedthrough across the input
terminals of the CA3080A to the 200pF storage capacitor when
the CA3080A is strobed off. Figure 24 shows dynamic
characteristic waveforms of this sample-and-hold system.
Current Amplifier
The low input terminal current needed to drive the CA3140
makes it ideal for use in current amplifier applications such
as the one shown in Figure 25 (see Note 14). In this circuit,
low current is supplied at the input potential as the power
supply to load resistor RL. This load current is increased by
the multiplication factor R2/R1, when the load current is
monitored by the power supply meter M. Thus, if the load
current is 100nA, with values shown, the load current
presented to the supply will be 100A; a much easier current
to measure in many systems.
R1
10k
+15V
IL x
R2
R1
0.1F
7
+
CA3140
3
M
2
POWER
SUPPLY
6
0.1F
R2
10M
IL
RL
100k
4.3k
-15V
Note that the input and output voltages are transferred at the
same potential and only the output current is multiplied by
the scale factor.
SAMPLING RESPONSE
Top Trace: Output; 100mV/Div., 500ns/Div.
Bottom Trace: Input; 20V/Div., 500ns/Div.
FIGURE 24. SAMPLE AND HOLD SYSTEM DYNAMIC
CHARACTERISTICS WAVEFORMS
17
FN957.10
July 11, 2005
CA3140, CA3140A
+15V
R2
5k
+15V
0.1F
0.1F
R1
10k
+
8
6
4
1N914
10k
R3
100k
OFFSET
ADJUST
PEAK
ADJUST
10k
100pF
2k
0.1F
-15V
2k
R
R3
GAIN = ------2- = X = ---------------------------R1
R1 R2 + R3
SIMULATED
LOAD
+
CA3140
CA3140
3
INPUT
10k
BW (-3dB) = 4.5MHz
SR = 9V/s
0.05F
X+X
R 3 = ----------------- R 1
1X
R
5k
FOR X = 0.5 --------------- = ------210k
R1
0.75
R 3 = 10k ----------- = 15k
0.5
OUTPUT
0
INPUT
0
+15V
7
RS
3
1M
0.01F
+
6
CA3140
2
NOISE VOLTAGE
OUTPUT
4
0.01F
30.1k
-15V
1k
18
FN957.10
July 11, 2005
CA3140, CA3140A
Typical Performance Curves
20
GAIN BANDWIDTH PRODUCT (MHz)
RL = 2k
TA = -55oC
25oC
125
125oC
100
75
50
25
RL = 2k
CL = 100pF
10
TA = -55oC
0
0
10
15
20
25
125oC
TA = -55oC
15
10
5
0
5
10
15
SUPPLY VOLTAGE (V)
20
25
25
25
20
15
10
1M
FREQUENCY (Hz)
19
TA = -55oC
25oC
125oC
4
3
2
1
0
10
15
25
20
100K
0
10K
20
RL =
25oC
15
RL = 2k
CL = 100pF
20
10
25oC
125oC
4M
102
103
104
105
FREQUENCY (Hz)
106
107
FN957.10
July 11, 2005
CA3140, CA3140A
Typical Performance Curves
1000
(Continued)
100
10
1
1
101
102
103
FREQUENCY (Hz)
104
20
105
100
+PSRR
80
60
40
-PSRR
20
POWER SUPPLY REJECTION RATIO
(PSRR) = VIO/VS
0
101
102
103
104
105
FREQUENCY (Hz)
106
107
FN957.10
July 11, 2005
CA3140, CA3140A
Metallization Mask Layout
0
61
10
20
30
40
50
60
65
60
50
40
58-66
(1.473-1.676)
30
20
10
0
4-10
(0.102-0.254)
62-70
(1.575-1.778)
21
FN957.10
July 11, 2005
CA3140, CA3140A
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
0.210
5.33
A1
0.015
0.39
A2
0.115
0.195
2.93
4.95
0.014
0.022
0.356
0.558
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
0.008
0.014
0.204
0.355
0.400
9.01
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.005
0.13
0.300
0.325
7.62
8.25
E1
0.240
0.280
6.10
7.11
0.100 BSC
eA
0.300 BSC
eB
0.115
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
D1
0.355
10.16
2.54 BSC
7.62 BSC
0.430
0.150
2.93
10.92
3.81
8
6
7
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
22
FN957.10
July 11, 2005
CA3140, CA3140A
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
0.25(0.010) M
B M
INCHES
-B-
SYMBOL
L
SEATING PLANE
-A-
h x 45o
D
-C-
A1
B
0.25(0.010) M
C A M
B S
MILLIMETERS
MIN
MAX
NOTES
0.0532
0.0688
1.35
1.75
0.0040
0.0098
0.10
0.25
0.013
0.020
0.33
0.51
0.0075
0.0098
0.19
0.25
0.1890
0.1968
4.80
5.00
0.1497
0.1574
3.80
4.00
0.050 BSC
1.27 BSC
0.2284
0.2440
5.80
6.20
0.0099
0.0196
0.25
0.50
0.016
0.050
0.40
1.27
8o
0o
NOTES:
MAX
A1
0.10(0.004)
MIN
8
0o
7
8o
Rev. 0 12/93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
23
FN957.10
July 11, 2005