DM9368 7-Segment Decoder/Driver/Latch With Constant Current Source Outputs
DM9368 7-Segment Decoder/Driver/Latch With Constant Current Source Outputs
DM9368 7-Segment Decoder/Driver/Latch With Constant Current Source Outputs
Connection Diagram
Dual-In-Line Package
TL/F/9796 1
TL/F/9796
Description
Address (Data) Inputs
Ripple Blanking Output (Active Low)
Ripple Blanking Input (Active Low)
Segment Drivers-Outputs
Latch Enable Input (Active Low)
RRD-B30M115/Printed in U. S. A.
December 1992
7V
5.5V
0 C to a 70 C
b 65 C to a 150 C
DM9368
Parameter
VCC
Supply Voltage
VIH
VIL
Units
Min
Nom
Max
4.75
5.25
V
0.8
3.2
mA
70
b 80
IOH
IOL
TA
ts(H)
30
ns
th(H)
ns
ts(L)
20
ns
th(L)
ns
mA
tw(L)
IOH
b 16
45
b 22
mA
ns
IOL
b 250
250
mA
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
b 1.5
VI
VOH
High Level
Output Voltage
VOL
Low Level
Output Voltage
II
IIH
40
mA
IIL
b 1.6
mA
IOS
Short Circuit
Output Current
VCC e Max
(Note 2)
b 57
mA
ICC
Supply Current
67
mA
2.4
0.2
b 18
3.4
V
0.4
mA
Switching Characteristics
VCC e 5.0V, TA e 25 C (See Section 1 for Waveforms and Load Configuations)
Symbol
CL e 15 pF
RL e 100X
Parameter
Min
Units
Max
tPLH
tPHL
Propagation Delay
An to ag
50
75
ns
tPLH
tPHL
Propagation Delay
LE to ag
70
90
ns
Functional Description
HIGH. This allows 68s to be driven from an MOS device in
multiplex mode without the need for drivers on the data
lines.
The 68 also has provision for automatic blanking of the
leading and/or trailing edge zeros in a multidigit decimal
number, resulting in an easily readable decimal display conforming to normal writing practice. In an eight digit mixed
integer fraction decimal representation, using the automatic
blanking capability, 0060.0300 would be displayed as 60.03.
Leading edge zero suppression is obtained by connecting
the Ripple Blanking Output (RBO) of a decoder to the Ripple Blanking Input (RBI) of the next lower stage device. The
most significant decoder stage should have the RBI input
grounded; and since suppression of the least significant integer zero in a number is not usually desired, the RBI input
of this decoder stage should be left open. A similar procedure for the fractional part of a display will provide automatic
suppression of trailing edge zeros. The RBO terminal of the
decoder can be OR-tied with a modulating signal via an isolating buffer to achieve pulse duration intensity modulation.
A suitable signal can be generated for this purpose by forming a variable frequency multivibrator with a cross coupled
pair of TTL or DTL gates.
The 68 is a 7-segment decoder driver designed to drive 7segment common cathode LED displays. The 68 drives any
common cathode LED display rated at a nominal 20 mA at
1.7V per segment without need for current limiting resistors.
This device accepts a 4-bit binary code and produces output
drive to the appropriate segments of the 7-segment display.
It has a hexadecimal decode format which produces numeric codes 0 thru 9 and alpha codes A through F
using upper and lower case fonts.
Latches on the four data inputs are controlled by an active
LOW latch enable LE. When the LE is LOW, the state of the
outputs is determined by the input data. When the LE goes
HIGH, the last data present at the inputs is stored in the
latches and the outputs remain stable. The LE pulse width
necessary to accept and store data is typically 30 ns which
allows data to be strobed into the 68 at normal TTL speeds.
This feature means that data can be routed directly from
high speed counters and frequency dividers into the display
without slowing down the system clock or providing intermediate data storage.
Another feature of the 68 is that the unit loading on the data
inputs is very low (b100 mA Max) when the latch enable is
Logic Symbol
VCC e Pin 16
GND e PIN 8
TL/F/9796 2
Truth Table
TL/F/9796 4
TL/F/9796 8
*The RBI will blank the display only if a binary zero is stored in the latches.
**The RBO used as an input overrides all other input conditions.
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Logic Diagram
TL/F/9796 3
Numerical Designations
TL/F/9796 5
TL/F/9796 6
TL/F/9796 7
Note: Digit address data must be non-overlapping. Standard TTL decoders like the 9301, 9311, 7442 or 74155 must be strobed, since the address decoding
glitches could cause erroneous data to be strobed into the latches.
National Semiconductor
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
Italiano Tel: (a49) 0-180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.