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Assignment 1 Solution

This document contains an assignment solution for an introduction to computer architecture course. It includes solutions to multiple problems related to chip fabrication capacity and profit calculations, energy savings from reducing processor speed, parallelization speedup calculations accounting for communication overhead, and analyzing instruction sizes and addresses for different instruction set architectures. The solutions cover topics like wafer fabrication capacity, Amdahl's law, and instruction encoding sizes.

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3K views

Assignment 1 Solution

This document contains an assignment solution for an introduction to computer architecture course. It includes solutions to multiple problems related to chip fabrication capacity and profit calculations, energy savings from reducing processor speed, parallelization speedup calculations accounting for communication overhead, and analyzing instruction sizes and addresses for different instruction set architectures. The solutions cover topics like wafer fabrication capacity, Amdahl's law, and instruction encoding sizes.

Uploaded by

butterboy
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Introduction to Computer Architecture

Assignment 1 - Solution
Due March 18, 2014

1. [40 = 10 x 4] It costs $1 billion to build a new fabrication facility. You will be


selling a range of chips from that factory, and you need to decide how much capacity
to dedicate to each chip. Your Woods chip will be 150 mm2 and will make a profit of
$20 per defect-free chip. Your Markon chip will be 250 mm2 and will make a profit of
$25 per defect-free chip. Your fabrication facility will be identical to that for the
Power5. Each wafer has a 300 mm diameter.
a. How much profit do you make on each wafer of Woods chip?
b. How much profit do you make on each wafer of Markon chip?
c. Which chip should you produce in this facility?
d. What is the profit on each new Power5 chip? If your demand is 50,000 Woods
chips per month and 25,000 Markon chips per month, and your facility can fabricate
150 wafers a month, how many wafers should you make of each chip?
Solution

2. [20 = 10 x 2] You are designing a system for a real-time application in which


specific deadlines must be met. Finishing the computation faster gains nothing. You
find that your system can execute the necessary code, in the worst case, twice as fast

as necessary.
a. How much energy do you save if you execute at the current speed and turn off the
system when the computation is complete?
b. How much energy do you save if you set the voltage and frequency to be half as
much?
Solution

3. [20 = 4 x 5] When parallelizing an application, the ideal speedup is speeding up by


the number of processors. This is limited by two things: percentage of the application
that can be parallelized and the cost of communication. Amdahls law takes into
account the former but not the later.
a. What is the speedup with N processors if 80% of the application is parallelizable,
ignoring the cost of communication?
b. What is the speedup with 8 processors if, for every processor added, the
communication overhead is 0.5% of the original execution time?
c. What is the speedup with 8 processors if, for every time the number of processors is
doubled, the communication overhead is increased by 0.5% of the original execution
time?
d. What is the speedup with N processors if, for every time the number of processors
is doubled, the communication overhead is increased by 0.5% of the original
execution time?
e. Write the general equation that solves this question: What is the number of
processors with the highest speedup in an application in which P% of the original
execution time is parallelizable, and, for every time the number of processors is
doubled, the communication is increased by 0.5% of the original execution time?
Solution

4. [20 = 5 x 4] For the following assume that values A, B, and C reside in memory.

Also assume that instruction operation codes are represented in 8 bits, memory
addresses are 64 bits, and register addresses are 6 bits.
For each instruction set architecture shown in Figure A.2 (stack, accumulator,
register-memory, register-register), how many addresses, or names, appear in each
instruction for the code to compute C = A + B, and what is the total code size?
Solution

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