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    Lecture1 3 CMOS nWELL and TwinTub Process

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    Srikanth Soma
    The document describes a CMOS inverter fabrication process using an n-well technology. It details the key steps: growing oxide on a silicon wafer, patterning for n-well formation via diffusion or implantation, growing gate oxide and patterning polysilicon gates, performing self-aligned n-type and p-type diffusions for source/drain regions, depositing field oxide, and finally adding metal layers. It also introduces a twin-tub process which uses both n-wells and p-wells to provide properly doped substrates for both transistor types.

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    Lecture1 3 CMOS nWELL and TwinTub Process

    Uploaded by

    Srikanth Soma
    8K views33 pages
    The document describes a CMOS inverter fabrication process using an n-well technology. It details the key steps: growing oxide on a silicon wafer, patterning for n-well formation via diffusion or implantation, growing gate oxide and patterning polysilicon gates, performing self-aligned n-type and p-type diffusions for source/drain regions, depositing field oxide, and finally adding metal layers. It also introduces a twin-tub process which uses both n-wells and p-wells to provide properly doped substrates for both transistor types.

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    The document describes a CMOS inverter fabrication process using an n-well technology. It details the key steps: growing oxide on a silicon wafer, patterning for n-well formation via diffusion or implantation, growing gate oxide and patterning polysilicon gates, performing self-aligned n-type and p-type diffusions for source/drain regions, depositing field oxide, and finally adding metal layers. It also introduces a twin-tub process which uses both n-wells and p-wells to provide properly doped substrates for both transistor types.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    8K views33 pages

    Lecture1 3 CMOS nWELL and TwinTub Process

    Uploaded by

    Srikanth Soma
    The document describes a CMOS inverter fabrication process using an n-well technology. It details the key steps: growing oxide on a silicon wafer, patterning for n-well formation via diffusion or implantation, growing gate oxide and patterning polysilicon gates, performing self-aligned n-type and p-type diffusions for source/drain regions, depositing field oxide, and finally adding metal layers. It also introduces a twin-tub process which uses both n-wells and p-wells to provide properly doped substrates for both transistor types.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 33

    CMOS Inverter in n-well process

    UNIT I : Introduction to IC Technology

    › 
    | ||
    Out Line
    ë CMOS Inverter in n-well process
    ë CMOS Inverter in Twin-Tub Process
    CMOS Technologies
    n-well: The pMOS transistors are placed in the n-well
    and the nMOS transistors are created on the
    substrate

    P-well: The nMOS transistors are placed in the p-well


    and the pMOS transistors are created on the substrate
    ? afer

    A bare Si wafer is chosen


    The type will be n or p depending upon the technology
    | Oxidation of afer

    The wafer is oxidised at a high temperature


    This must be patterned to define the n-well
    Ñ PhotoResist deposition

    ëThe photoresist is deposited throughout the wafer


    ëThe PR has to be patterned to allow formation of
    the well
    ÿ n-well Mask

    ëThe PhotoResist is exposed through the n-well mask


    ëThe softened PhotoResist is is removed to expose
    the oxide
    - Oxide Etch

    ëThe oxide is etched with HF acid where unprotected by


    PhotoResist
    ëThe wafer is now exposed to the n-well area
    ‰ PhotoResist removal

    ëThe remaining PR is removed via piranha etch


    ëThe well is ready to be formed
    Y n-well Formation

    ·The diffusion process can make the the n-well


    ·Ion implantation can also form the same
    m Oxide Removal

    ·The remaining oxide is stripped with HF acid


    ·This leaves the exposed wafer with the n-well formed
    ] ate Formation
    ·The gates are made up of polysilicon over thinox
    ·CVD is used to grow the poly (heavily doped) layer
    ? Poly Patterning

    ·The wafer is now patterned with PhotoResist and the poly mask
    ·Finally this leaves the device gates
    ?? Diffusion Pattern

    ·Again, a protective oxide is grown and PhotoResist


    deposited
    ·PhotoResist is patterned according to the diffusion
    mask
    ?| afer Exposure for Diffusion

    ·The protective oxide is etched away


    ·The wafer is exposed for S/D formation
    ?Ñ n-Diffusion Regions

    ·The n+ diffusion regions are formed


    ·Polysilicon blocks the channel area
    ?ÿ Self-Aligned Process

    ·This is a self-aligned process


    ·S/D are automatically formed adjacent to the gate
    ?- p-Diffusion

    ·The p-diffusion mask is used next


    ·This completes creation of all active regions
    ?‰ Field Oxide
    The field oxide is grown to insulate wafer and metal
    It is patterned with the contact mask
    ?Y Metal Formation
    ëAl is sputtered over the entire area filling contact cuts too
    ëMetal is patterned with the metal mask
    Inverter Cross-section
    ëTypically use p-type substrate for nMOS transistors
    ‡ Requires n-well for body of pMOS transistors
    ell and Substrate Taps
    ·Substrate must be tied to ND, n-well to VDD
    · Use heavily doped well and substrate contacts / taps
    Six masks
    ± n-well

    ± Polysilicon

    ± n+ diffusion

    ± p+ diffusion

    ± Contact

    ± Metal
    CMOS Inverter in Twin-Tub Process
    M M


    ë M  
    
     
    
      u   
     
    p-
    type and n-type transistorsG

    ë 
      
    
    
    
     
      u    6   6 
    
    
      
        
    
    G
    Twin Tub Process: N-well / P-well

    ·First place wells to provide properly-doped


    substrate for n-type, p-type transistors:
    Twin Tub Process: Polysilicon

    Pattern polysilicon before diffusion regions:


    Twin Tub Process: N+/ P+ Diffusion

    Add diffusions, performing self-masking:


    Twin Tub Process: Contact / Via / Metal

    ·Start adding metal layers:


    Twin-well CMOS process cross section
    Twin Tub CMOS Process Cross Section
    ---Struggle gives Strength and Dignity

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