CMOS using Twin Tub Process

The Twin tub process is used for CMOS fabrication to avoid latch up problems.

-In this process the substrate can be of any type. Let’s start with n type silicon substrate.

The twin tub fabrication steps are :

1. The process is carried out on N type silicon substrate with lower doping or higher resistivity, so
that the lesser current flows through the substrate. On this, the n’ Si substrate is grown further
i.e. epitaxial layer of required thickness is grown.

2. SiO, layer is grown all over the surface, and the areas of P-well and N-well are defined. P-well is
diffused by

‘ masking N-well area and N-well is diffused by masking P-well area.

3. A thin layer of SiO, thinox is deposited all over the surface. Using masking and etching process
unrequired thinox is removed. The thinox is required only on gate areas of both the transistors.

4. The polysilicon is deposited all over the surface and using a mask it is removed from areas other
than the gate area.

Then the P-well is covered with a photoresist mask and p’ diffusion is carried out to form the source and
drain of pMOS transistor. Now the N-well is covered with a photoresist mask and un’ diffusion is carried
out to form the source and drain of nMOS transistor. . The thick layer of SiO, is grown all over the surface
for isolation. This SiO, layer is etched off to expose all the terminals. The metal is deposited and
patterned all over the wafer surface so that it makes contact with source, drain and gate terminals. We
have discussed CMOS fabrication using N-well, Pwell and twin tub processes. There is one more process
known as Silicon On Insulator (SOD) process, in which rather than using silicon as a substrate, insulating
substrate is used to improve process characteristics such as latch up and speed. Since this process is out
of the scope of our syllabus, we will not discuss it in this book. ,
Advantages Separately optimized wells are available. Balanced performance is obtained for n and p
transistor. | Threshold voltage, body effect of n and p devices is independently optimized. It avoids the
latch up problem.

Latch up in CMOS

CMOS devices, fabricated using N-well and P-well processes, have a parasitic circuit effect called ‘Latch
up’ due to formation of relatively large number of junctions in these structures resulting in formation of
‘parasitic transistors and diodes. ‘Latch up’ is 8 condition in which these parasitic components give rise to
the establishment of low resistance conducting paths between Vpp and Vg. Let us consider the cacutt
fabricated using Nwell process. There are two parasitic transistors formed. One is vertical pnp transistor
Q, and another is a lateral npn transistor, Q, as shown in Fig. 2.15.5(a). For the vertical pnp transistor Q, :
The emitter is formed by p” diffusion of pMOS transistor, the base is formed by Nwell, while the collector
is the p substrate.

- For the lateral npn transistor Q, : the emitter is formed | by the n’ diffusion of nMOS transistor,
while the base is the p substrate and the collector is the Nwell.

- Substrate resistance Rsub and well resistance Rwell are due to the resistivity of the
semiconductor involved. We get the circuit as shown in Fig. 2.15.5(b). Latch up may be
introduced by glitches on the supply rails or by incident radiation. ‘

Sometimes due to noise in the power supply, the output terminal voltage drops about 0.7 V below the
ground and the current in the channel of nMOS transistor flows such that more and more electrons flow
towards the ground.

This gives rise to the emitter current in transistor Q, and the emitter terminal of Q, becomes negative.
Vp, drop of Q, is established such that Q, turns on and the current flows through Rsub and Rwell. |

The voltage drop across Rwell gives rise to turning on of the transistor Q,. This establishes a low
resistance path between the supply rails and there is unwanted current flow between the supplies. This
is called ‘latch up’. The circuit works like a SCR.

The N Well Process

The N-well CMOS circuits are getting more popula, because of the lower substrate bias effects on
transisto, threshold voltage and lower parasitic capacitance, associated with source and drain regions.
The typica N-well fabrication steps are similar to p-wej fabrication steps.
Thick SiO, layer is grown on ptype silicon wafer

After defining the area for N-well diffusion, using , mask, the SiO, layer is etched off and n-well diffusion,

process is carried out.

Oxide in the n transistor region is removed and thip oxide layer is grown all over the surface to insulate
gate and substrate.

The polysillicon is deposited and patterned on thin oxide regions using a Mask to form gate of both the
transistors. The thin oxide on source and drain regions of both the transistors is removed by proper
masking

steps. Using n’ mask and complementary n* mask, source and drain of both nMOS and pMOS transistors
are formed one after the other using respective diffusion processes. These same masks also include the
Vpp and Vy contacts,

The contact cuts are made using proper masking procedure and metal is deposited and patterned on the
entire chip surface.

An overall passivation layer is formed and the openings for accessing bonding pads are defined.

Fig. 2.15.4 shows an inverter circuit fabricated using Nwell process.

Advantages of Nwell process

Substrate bias effects are low on transistor threshold voltage.

Parasitic capacitances are low on source and drain region. |

It reduces latch up problem.

Fig. 2.15.2 shows CMOS P-well process where pMOS is fabricated in n-type substrate by masking and
diffusion steps.

In P-well process, the diffusion must be proper otherwise it will affect the threshold voltage of nMOS.
The p-well acts as substrate for the n devices and the parent nsubstrate acts as substrate for pMOS.
These substrates are electrically isolated by connecting the p substrate to ground and n to Vpy as shown
in

Fig. 2.15.3.

The masking, patterning and diffusion processes are similar to nMOS fabrication. The entire process is
summarized below.

Initially thick SiO, layer is grown on the entire n-type silicon surface. (refer to point 2 of nMOS
Fabrication). Using photoresist layer and a mask, which defines the area of deep p well diffusion, the SiO,
layer is etched off and p-well diffusion process is carried’ out Fig. 2.15.2(a).

Oxide in the p transistor region is removed and thin oxide layer is grown all over the surface for
insulating gate and substrate.

The polysilicon is patterned on thin oxide regions using a Mask forming pMOS and nMOS gates. The thin
oxide on source and drain regions of both the transistors is removed by proper masking steps Fig.
2.15.2(b). The area of nMOS transistor is covered using Pp mask,

and p diffusion is carried out to form source and drain of pMOS transistor as shown in Fig. 2.15.2(c).

Using negative p mask the area of pMOS transistor is covered and n diffusion is carried out to form
source and drain of nMOS transistor. In these two masking steps the Vpp and Vg contacts are also
defined to bias the substrates. Fig. 2.15.2(d).
Thick oxide layer is grown on the entire chip surface and the transistor areas where contact cuts are to
be made are defined . The procedure is same as explained in point 8 of nMOS fabrication.

The metal layer is deposited on the entire chip surface and is patterned using masking and etching. | An
overall passivation layer is applied and the openings for accessing bonding pads are defined. For all these
procedures different types of Masks are used. The brief overview of the fabrication steps is shown in Fig.
2.15.3.

Advantages of P-well process aed —Area of n-channel and P-channel devices are balanced. | | . ° ~
Speed of n-channel and P-channel devices af balanced.

Basic CMOS Technology

although most of the nMOS steps are common in CMOS technology, the CMOS fabrication is Sowa
/barately as CMOS has both nMOS and pM transistors fabricated on the same substrate as a single
device. oo | . . The main CMOS technologies are : ,

1) p

2) n

3) twin tub

pMOS Transistor fabrication process

The brief introduction of pMOS transistor fabrication process is summarized below with Fig. 2.14.1(a—
h).

1. The first step is to grow thick. Silicon dioxide layer called as field oxide on n-type silicon
semiconductor. Then field oxide (SiO,) is etched using photolithography process, that exposes
silicon surface where MOS transistor will be created. Field oxide will isolate the individual
transistors.

2. On the entire surface of the water a thin layer of silicon dioxide is grown which is called thin
oxide or thinox.

After that polysilicon is deposited on top of it which is then selectively etched to form transistor gate.
Then etched away the exposed gate dioxide from the transistor region.

Then for forming source and drain region, the complete wafer is exposed to the dopant source or ion
implanted. The doping also reduces the resistivity of polysilicon. The source and drain regions are
formed only in the region where polysilicon gate is not present which 1s called as self aligned process.

Then entire wafer is covered with SiO, and contact holes are etched to form contacts with drain and
source.

To form the interconnects, the surface is covered with evaporated aluminium.

The final step is metal layer is patterned and etched. The above whole process is shown in Fig. 2.14.1 (a –
b)

nMOS Fabrication

~ a brief introduction to the nMOS fabrication process will be given in this section of the chapter. The
fabrication Processes used for nMOS are also relevant to CMOS. An nMOS process is illustrated in Fig.
2.13.1 and outlined as follows :

Processing is carried out on a thin wafer of lightly Ped P type silicon, cut from a silicon ingot of high
purity. These wafers are typically.75 to 150 mm in diameter and 0.4 mm thick, with resistivity in the
range of 25 ohm cm to 2 ohm cm. Fig. 2.13.1(a). A thick layer of silicon dioxide (SiO,), typically 1 pm
thick, is grown all over the surface of the wafer. It acts as a barrier to dopants during processing and
insulates substrate so that other layer could be deposited. Fig. 2.13.1(b).

To achieve an even distribution of required thickness the surface is covered with photoresist shown in
Fig. 2.13.1©.

Then photoresist layer is exposed to ultraviolet lhght through mask to define transistor area. The
transistor

Area ts shielded from UV light as photoresist hardens when UV heght falls on it. Fig. 2.13.1(d).
This area is etched out using chemical processes along with S1Q, layer so that the wafer surface is
exposed in

The window defined by the mask. Fig. 2.13.1€.

The remaining photoresist is removed and a thin layer of S10, (0.1 mm) is grown over the entire chip
surface. This thin oxide layer insulates gate from the substrate. Potbysilicon is then deposited on top of
this to form the gate structure. Further photoresist coating and maskmg allows the polysilicon to be
patterned. Fig. 2.13.1(H).

In Fig. 2.13.1(2), n-type impurities are diffused where thin oxide is remove to form source and drain by
heating -wafer to high temperature and passing gas containing n type impurity. The polysilicon with thin
S10, layer acts as a mask during’ diffusion. Fig. 2.13.1(2).

Thick oxide (SiO,) is grown over the entire surface again and is masked with photoresist and etched to
expose selected areas of the polysilicon gate, drain and

Source, where connections (contacts) are to be made. Fig. 2.13.3(b).

Then metal is deposited on the entire chip surface to a thickness typically of 1 ym. This metal layer is
then masked and etched to form the required interconnection pattern Fig. 2.13.1(4). The overall process
is shown is Fig. 2.13.1(a – i).

Etching

The process in which unwanted chemicals, photores: nd SiO, layers are removed at the different stapes
ip brication is called ‘Etching’. | 9.12.9 Metallization Q. Write the purpose of the

Metallization. –

After fabricating nMOS and pMOS devices using the above processes, interconnection between these
devices and ohmic contacts are required to be made. Aluminum is evaporated and patterned over the
entire wafer surface to make the contacts. This process is known as “Metallization’.
12.7 Lithography | The process in which pattern is transferred to a layer of material is called lithography.
It is used in integrated circuits to pattern the layers of doped silicon, polysilicon, metal and insulating
silicon dioxide. ; In the lithography process, a film of photoresist is first applied over the SiO, layer. This
structure with the mask on which desired pattern of the IC is imprinted, is exposed to UV light.

Q. Define the term : Epitaxy. (S-2015)

In Greek ‘epi’ means upon and ‘taxis’ means ordered. Thus epitaxial growth means an arrangement of
atoms upon a crystal substrate so that the resulting added layer structure is an exact extension of the
substrate crystal structure. Thus the Si substrate of desired thickness is obtained.

2.12.4 Deposition Q. Define the term : Deposition.

- Deposition is the process of adding layers to the wafer in CMOS fabrication process. These layers may
acts ag either buffer or as insulating or conduction layers.

~ Chemical vapor deposition (CVD) is mostly used to deposit Si,N, at temperature of 850°C or polysilicon
is deposited at 650°C.

— Implantation step after deposition reduces poly resistance.

2.12.5 Diffusion Qa. Déscribe diffusion in CMOS fabrication.

— The process in which addition of the impurities into selected regions of pure semiconductor is called
as Diffusion.

— Diffusion is achieved by heating the wafer to a high temperature and passing a gas containing the
desired impurity.

— It allows the formation of drain and source for MOSFET.

- It is useful in batch processes where many slices are ’ handled in single operation.
- A high quality junctions with minimum leakage current can be made because it does not produce
crystal damage.

2.12.6 lon implantation

Q. Define the term : lon-implantation.

Ion implantation is an alternative to diffusion process. It is a process by which energetic impurity atoms
can be introduced into a single silicon substrate. This method is used to introduce a wide range of
impurity doses into substrate.

O Dry oxidation : It is a process where the oxidizing atmosphere is pure oxygen. To achieve an acceptable
growth rate it is necessary for the temperature to be in the region of 1200°C.

2.12.2 Oxidation Q. Describe oxidation in CMOS fabrication.

— Oxidation is necessary at the various stages of fabrication for isolating different layers of conducting
materials and to prevent unwanted conducting paths between the devices. Oxidation of silicon is
achieved by heating silicon wafer in an oxidizing atmosphere such as oxygen or water vapour.

— The two common approaches are :

Wet oxidation

Dry oxidation

oO Wet oxidation : This process is carried out in the oxidizing atmosphere which contains water vapour
with the temperature ranging between 900°C and 1000°C. This is a rapid process.

o Dry oxidation : It is a process where te oxidizing atmosphere is pure oxygen. TO achieye an acceptable
growth rate it is necessary for the temperature to be in the region of 1200°C.

£.12, 1 Wafer Processing Q. Descri , O. ExOkin wee processing in CMOS fabrication. Q. Descrine
processing with C-Z method. . zochralski (C « Z processing, ( ) method of wafer
—The basic raw material is a wafer or disk of silicon, which is between 75 mm to 150 mm in diameter
and is less than 1 mm thick used in semi-conductor plants.

— Wafers are cut from ignots of silicon-crystal silicon that have been pulled from a crucible melt of pure
molten polycrystalline silicon. This method is known as ‘Czochralski’ (C-Z method) method.

For getting crystal with required electrical properties, controlled amounts of impurities are added to the
melt. Seed crystal is dipped into the melt to initiate single crystal growth which contained in quartz
crucible and surround by a graphite radiator.

The temperature of graphite is maintained a few degrees above melting point of silicon by radio
frequency induction.

The n seed is gradually withdrawn vertically with rotating from the melt. The molten polycrystalline
silicon melts the tip of seed and refreezing occurs. Internal cutting edge diamond blades are used for
slicing and wafers are between 0.25 mm to Imm thick as per their diameter.

2.12 Fabrication Process

— Silicon is a semiconductor having its’ resistance somewhere between a conductor and an insulator.
Although many elements like germanium exhibit semiconducting properties, silicon is used almost
exclusively in the fabrication of semiconductor devices and microcircuits. It is the most = important
semiconductor for electronics industry.

— Of the many reasons for the choice of silicon, the most important are the following :

ro) Silicon has a wider energy gap (1.1 eV) than germanium (0.66 eV).

ro) Silicon devices can operate up to 150°C versus 100°C for germanium.

oO Unlike germanium, silicon lends itself readily to surface passivation treatments i.e. SiO, layer could be
easily grown on the surface which provides high degree of protection to the underlying device.
_ The semiconductor in its pure form is called intrinsic semiconductor. The conductivity of sihcon can be
varied by adding impurity atoms into the silicon crystal. These impurity atoms i.e. dopants may either
supply free electrons or holes. When electrons are added to intrinsic semiconductor, it is called an n type
semiconductor and if holes are added to intrinsic semiconductor it is called a p type semiconductor. Now

we will discuss different processes that are important in CMOS fabrication.