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NR Computer Organization

This document contains instructions for an exam on computer organization with 8 questions. It provides details on topics like: 1) Designing a D type flipflop using an SR flipflop and drawing a combinational logic circuit to generate a Boolean function using only NAND gates. 2) Explaining the operation of an 8-bit serial-in parallel-out shift register and its application. Constructing a 5-32 line decoder using 3-8 and 2-4 line decoders. 3) Defining normalization of floating point numbers with an example and explaining the features of 4-bit BCD and gray codes. 4) Determining the contents of 4 registers after performing subtraction, addition,

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sarathy1231
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145 views

NR Computer Organization

This document contains instructions for an exam on computer organization with 8 questions. It provides details on topics like: 1) Designing a D type flipflop using an SR flipflop and drawing a combinational logic circuit to generate a Boolean function using only NAND gates. 2) Explaining the operation of an 8-bit serial-in parallel-out shift register and its application. Constructing a 5-32 line decoder using 3-8 and 2-4 line decoders. 3) Defining normalization of floating point numbers with an example and explaining the features of 4-bit BCD and gray codes. 4) Determining the contents of 4 registers after performing subtraction, addition,

Uploaded by

sarathy1231
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Code No: 21002

NR
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
MCA-I Semester Supplementary Examinations July 2010
COMPUTER ORGANIZATION
Time: 3hours Max.Marks:60
Answer any Five questions
All questions carry equal Marks
---
1.a) Using an SR flipflop design a D type flipflop.
b) Draw a combinational circuit using only NAND gates to generate the Boolean
function:
F(A,B,C,D) = A BC + B C + C D + A C D
Derive the relations used, if any, to draw the circuit.

2.a) With the help of a block diagram explain the operation of a 8 bit serial in-parallel
out shift registers. Suggest one application for such a register.
b) Construct a 5 to 32 line decoder with required number of 3 to 8 line decoders and
2 to 4 line decoders. Use block diagram approach and explain the function of the
5 to 32 line constructed by you.

3.a) What do you understand by normalization of a floating point number? Explain


with an example.
b) Write down a four bit BCD code and four bit gray code and explain their relevant
features.

4. The 8 bit registers AR, BR, CR and DR have the following initial values.
AR = 11011010
BR = 11100101
CR = 10101010
DR = 11111110
Determine the contents of each of the registers after execution of the following
sequence of micro operations.
AR ← AR – DR…………………...subtract DR from AR
BR ← CR + BR…………………...add BR to CR
CR ← CR + 1; CR← CR ^ BR…...increment CR, and the contents CR and BR.

5. Explain the Booth’s algorithm for signed two’s complement numbers with the
help of a block diagram. Give a numerical example of implementation of Booth’s
algorithm with 5 bit number.

6. Write a brief notes on the various addressing modes used in a computer with
simple examples.

7.a) The logical address space in a computer system consists of 128 segments. Each
segment can have upto 32 pages of 4k words in each. Physical memory consists
of 4k blocks of 4k words in each. Formulate the logical and physical address
formats.
b) List out the parameters required to be taken / considered for choosing a memory
device. Explain three such parameters in detail.

8.a) Explain in detail the necessity of an input output interface between a CPU and
peripheral device.
b) Write brief notes on input output processor.

******

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