SDH Tech

TECHNICAL MANUAL
Digital Radio-Relay System

NL290 - Family. 64/128TCM
B1086 Rev. F
des -99
Revision state for each booklet of
TECHNICAL MANUAL, NL290 - Family, 64/128TCM
B1086 REV. F
Booklet No: Revision: Booklet No: Revision:
H2014 A H2702 A
H2015 A H2726 B
H2027 B H2766 A
H2030 A H2767 B
H2066 A H2788 A
H2075 A H2789 A
H2143 I H2801 B
H2189 A H2805 B
H2455 B H2806 A
H2456 A H2823 D
H2576 A H2854 A
H2577 B H2857 B
H2580 I
H2858 A
H2591 H H2904 B
H2596 B H2969 A
H2598 D H2970 A
H2599 E
H2971 A
H2600 C H2972 A
H2605 B H2988 B
H2606 B H2989 B
H2615 B
H2990 A
H2694 A H2993 A
H2695 D H2995 A
H2696 C H3025 A
H2697 A H2996 A
H2698 A H3003 A
H2699 B H3025 A
H2700 A H3026 A
H2701 B H3028 A
Table of Contents
Code: Section:
Technical Specifications NL290 - Family H2580 1
System (Equipment) Description NL290 - Family H2591
System Block Diagrams NL290 - Family H2766
Transmitter Groups NL290 - Family H2600 2

Receiver Groups NL290 - Family H2598
Receiver Groups NL290 - Family H2599
Branching NL290 - Family H2854
Power Supply, Tx (48V) 0PR147B H2189 3

Power Supply, Tx (24V) 0PR159A H2066
Modulator, 64/128TCM 8MNF83A, 83C, 89A H2805, 2972, 2970 4

Demodulator, 64/128TCM, incl.EDNF100A* 2DNF129B, 133A, 135A* H2996, 2969, 2971
Equalizer, IF (Space Div.) 8F264A H2015
Equalizer, IF 8F267A/B H2014
IF Filter 8F312A H3028
CMI Splitter 2G264A H2789
Relay & Driver Unit OS186A H2858 5

Alarm Collection Unit (ACU) 0JG161A H2596
Alarm & Logic, Hot Standby 3KS218A H2801
Alarm Board, Radio Rack EJ163A, EJ163B H2697, H2993
Filter & Connection Panel, 48V, 24V EF280A, EF280B H2027, H2075
Distribution Board, Radio Rack EW52A H2695
Switch, XMTR 2SN218A H2788 6

RCVR Data Distribution Unit 2GN395A H2806
Adapter, 64kb/s 2N507A H2823
Adapter, RSOH 2N506A H2606
Adapter, MSOH 2N505A H2605
Adapter, PABX 2N504A H2904
Alarm Board, SVCE Rack EJ164A H2698
Alarm Adapter Unit 0JG164A H2767
Main Alarm Display EK50A H2030 7

Display Unit 0JK165A H2726
Supervisory Board 2KZ198A H2576
Supervisory Board 2KZ198B H3026
Q-Adapter (Option) 2KZ223A H2988
Radio Protection Switching Bd. 2SK220A H2577
Sync Unit, 2MHz 2SF219A, 2SF219B H2857, H2990
Optical Interface Unit 7NYD576B H3003
Service Channel, Sel. Call 2NF468A H2143 8

Service Channel Connection EK66A H2694
Distribution Board, Service Rack EW53A H2696
Connection Panel, Service UWB309 H2699
Connection Panel, Adapter UWB310 H2700
Filter & Connection Panel, SVCE EF312A H2701
Filter & Connection Panel, 24V EF313A H2702
Filter & Connection Panel, 48V EF324A H2995
Filter & Connection Panel, 48V/24V EF324C/D H3025
Power Supply, 48V 0PR171A H2455
Power Supply, 48V 0PR171B H2989
Power Supply, 24V 0PR172A H2456
Appendixes NL290 - Family H2615
WARNING!
This equipment contains components which are sensitive to "ESD"

(Electro Static Discharge).
It is therefore essential that whenever disassembling the equipment and/

or handling PC boards, special precautions to avoid ESD has to be made.
These precautions include personnel grounding, grounding of work

bench, grounding of tools and instruments as well as transport and
storage in special antistatic bags and boxes.
WARNING!
Exposure to strong high frequency electromagnetic fields may cause thermal dam-
age to personnel. The eye (Cornea and lens) is easily exposed.
Any unnecessary exposure is undesirable and should be avoided.
In Radio-Relay communication installations, orderly setup for normal operation, the

general RF radiation level will be well below the safety limit.
In the antennas and directly in front of them the RF intensity normally will exceed the
danger level, within limited portions of space.
Dangerous radiation may be found in the neighbourhood of open waveguide flanges

or horns where the power is radiated into space.
To avoid dangerous radiation the following precautions must be taken:
r During work within and close to the front of the antenna; make sure that
transmitters will remain turned off.
r Before opening coaxial - or waveguide connectors carrying RF power, turn

off transmitters.
r Consider any incidentally open RF connector as carrying power, until

otherwise proved. Do not look into coaxial connectors at closer than reading
distance (30 cm). Do not look into an open waveguide unless you are
absolutely sure that the power is turned off.
WARNING!
r DO NOT remove or insert the Transmitter / Receiver

group with DC power on.
r To avoid traffic disturbance during maintenance on

one of the RF channels in a N+1 protected system, the
traffic should be manually locked to the protection
channel before any work is started.
PLEASE OBSERVE that mechanical switches should be

activated as part of maintenance programs. Years of
inactivity could otherwise cause lubricants on contacts and
actuator mechanism to harden and thus restrict
normal operation.
CLASS 1 LASER PRODUCT
IEC825-2: 1993
CAUTION
Use of controls or adjustments or performance of procedures other than
those specified herein may result in hazardous radiation exposure.
The Optical Interface must only be serviced by qualified personnel, who are
aware of the hazards involved to repair Laser products.
When handling Laser products the following precautions must be taken:
r Never look directly into an open connector or optical cable
r Before disconnecting an optical cable from the transmitter, the power

should be shout off. If this is not possible, the cable must be
disconnected from the transmitter before it is disconnected from the
receiver.
r When the cable is reconnected it must be connected to the

receiver before it is connected to the transmitter.
TECHNICAL SPECIFICATIONS
NL290 - Family
4 - 13GHz
H2580 Rev. I
© Nera ASA
Tec. Spec. SDH - STM-1
2 H2580
Table of contents
1 - NETWORK AND SYSTEM CONSIDERATIONS ..................................................................................................... 7
2 - EQUIPMENT MAIN CHARACTERISTICS ............................................................................................................. 9

2.1 GENERAL .................................................................................................................................................................... 9
2.2 FREQUENCY BANDS AND CHANNEL ARRANGEMENT ........................................................................................................ 9
2.2.1. Frequency tolerance ....................................................................................................................................... 9
2.3 SYSTEM CONFIGURATION ............................................................................................................................................. 9
2.3.1 Radio terminal configurations ........................................................................................................................ 9
2.3.2 Radio repeater configurations...................................................................................................................... 10
2.3.2.1 Standard repeater ......................................................................................................................................................... 10
2.3.2.1 Add/drop repeater ........................................................................................................................................................ 10
2.3.3 Radio channel identification ......................................................................................................................... 10
2.4 MODES OF OPERATION ............................................................................................................................................... 10
2.5 TYPES OF INSTALLATION ............................................................................................................................................. 10
2.5.1 Safety conditions ............................................................................................................................................10
2.5.2 Environmental conditions ............................................................................................................................. 10
2.6 ELECTROMAGNETIC COMPATIBILITY CONDITIONS (EMC)........................................................................................... 11
2.7 MECHANICAL CHARACTERISTICS ................................................................................................................................. 11
2.7.1 Coaxial connectors ........................................................................................................................................ 11
2.7.2 Waveguides ..................................................................................................................................................... 11
2.8 SYSTEM SYNCHRONIZATION ........................................................................................................................................ 11
2.9 ALARM AND MONITORING FACILITIES .......................................................................................................................... 12
2.10 POWER SUPPLY ........................................................................................................................................................ 12
2.10.1 General ......................................................................................................................................................... 12
2.10.2 Power supply fuses ...................................................................................................................................... 12
2.10.3 Primary supply characteristics ................................................................................................................... 13
2.10.4 Primary supply transients ........................................................................................................................... 13
2.10.5 Power consumption ..................................................................................................................................... 13
2.11 SYSTEM PERFORMANCE ............................................................................................................................................ 14
2.11.1 Monitoring of system performance ............................................................................................................ 14
2.11.2 B1- & B2- parity-error output ....................................................................................................................14
2.11.3 B1- and B2- parity errors characteristics: ................................................................................................ 14
2.11.4 System performance calculations ............................................................................................................... 14
2.11.5 Equipment background BER (Residual BER) ............................................................................................. 14
2.11.6 System gain ................................................................................................................................................... 15
2.11.7 System signature .......................................................................................................................................... 15
2.11.8 Transmission delay ...................................................................................................................................... 15
2.12 SYSTEM RELIABILITY ................................................................................................................................................ 15
2.12.1 Mean Time Between Failure (MTBF) ......................................................................................................... 16
2.13 INTERFERENCE SENSITIVITY ...................................................................................................................................... 16
2.13.1 Co-channel interference sensitivity ........................................................................................................... 16
2.13.2 Adjacent channel interference sensitivity ................................................................................................. 17
3 - SYSTEM CHARACTERISTICS FOR SPACE DIVERSITY (SD) ......................................................................... 18
3.1 GENERAL .................................................................................................................................................................. 18
3.2 COMBINING PRINCIPLES AND PERFORMANCE ............................................................................................................... 18
3.2.1 Combiner 3DK125: ....................................................................................................................................... 18
3.2.2 Combiner 8DK138: ....................................................................................................................................... 18
3.3 ALARMS AND MONITORING FOR THE SD-EQUIPMENT .................................................................................................. 18
4 - TRANSMITTER CHARACTERISTICS ................................................................................................................... 19
4.1 TRANSMITTER OUTPUT CHARACTERISTICS .................................................................................................................. 19
4.1.1 Output power .................................................................................................................................................. 19
4.1.2 Automatic Transmitter Power Control (ATPC) ............................................................................................. 19
4.1.3 RF coaxial impedance ................................................................................................................................... 19
4.1.4 TX-oscillator frequency stability .................................................................................................................. 19
H2580 3
4.1.5 RF - filter bandwidth and losses A - B ......................................................................................................... 20
4.1.6 RF spectrum mask .......................................................................................................................................... 20
4.1.7 Spurious emission within the STM-1 system channel plan. ....................................................................... 21
4.2 IF INPUT CHARACTERISTICS (POINT E) ....................................................................................................................... 21
4.3 TRANSMITTER MONITORING FACILITIES ....................................................................................................................... 21
4.4 TRANSMITTER ALARMS .............................................................................................................................................. 21
5 - RECEIVER CHARACTERISTICS ........................................................................................................................... 22
5.1 RECEIVER INPUT CHARACTERISTICS ............................................................................................................................. 22
5.1.1 Input signal range ......................................................................................................................................... 22
5.1.2 RF - filter bandwidth and losses B - A .......................................................................................................... 22
5.1.3 RF coaxial impedance ................................................................................................................................... 23
5.1.4 RF input return loss at point C ..................................................................................................................... 23
5.1.5 Local RX-oscillator tolerance and stability ................................................................................................. 22
5.1.6 Spurious and harmonic signal emission ...................................................................................................... 23
5.1.7 Image frequency attenuation ........................................................................................................................ 23
5.1.8 Noise figure .................................................................................................................................................... 23
5.2 IF OUTPUT CHARACTERISTICS (POINT E) ..................................................................................................................... 23
5.2.1 IF-IF group delay and amplitude response ................................................................................................. 23
5.2.2 IF equalizer .................................................................................................................................................... 24
5.3 RECEIVER MONITORING FACILITIES .............................................................................................................................. 24
5.4 RECEIVER ALARMS ..................................................................................................................................................... 24
6 - MODEM CHARACTERISTICS ............................................................................................................................... 25
6.1 MODULATOR ............................................................................................................................................................. 25
6.1.1 Modulation method ........................................................................................................................................ 25
6.1.2 Input aggregate bitrate ................................................................................................................................. 25
6.1.3 IF characteristics ........................................................................................................................................... 25
6.2.1 Demodulation method ................................................................................................................................... 25
6.2.2 IF characteristics ........................................................................................................................................... 26
6.2.3 Adaptive Time Domain Equalizer (ATDE) .................................................................................................... 26
6.2.3.1 Performance and distortion sensitivity ............................................................................................................................ 26
6.2.4 Trellis decoder ............................................................................................................................................... 26
7 - BASEBAND CHARACTERISTICS .......................................................................................................................... 27
7.1 GENERAL .................................................................................................................................................................. 27
7.2 TRANSMISSION INTERFACES ........................................................................................................................................ 27
7.2.1 Transmission interface characteristics - 139.264 Mb/s: ............................................................................ 27
7.2.2 Transmission interface characteristics - STM-1 electrical: ....................................................................... 27
7.2.3 Transmission interface characteristics - STM-1 optical:............................................................................ 27
7.3 SCRAMBLING / DESCRAMBLING FUNCTIONS ................................................................................................................. 28
7.4 SECTION OVERHEAD (SOH) ..................................................................................................................................... 28
7.4.1 Frameword and parity bytes ......................................................................................................................... 28
7.4.2 Media specific bytes ....................................................................................................................................... 28
7.4.3 Other SOH-bytes ............................................................................................................................................29
7.4.4 2.048 Mb/s wayside traffic bytes .................................................................................................................. 29
7.5 SPECIFICATIONS OF JITTER AND WANDER ..................................................................................................................... 29
7.5.1 STM-1 interface .............................................................................................................................................. 29
7.5.2 140 Mb/s interface ........................................................................................................................................ 29
7.6 EXTRA BASEBAND OUTPUT ......................................................................................................................................... 29
8 - SERVICE TRAFFIC AND WAYSIDE TRAFFIC .................................................................................................... 30
8.1 GENERAL .................................................................................................................................................................. 30
8.2.2 PABX-adapter ................................................................................................................................................. 31
8.2.3 64 kbit/s service channels ............................................................................................................................. 31
8.2.4 MSOH-adapter ............................................................................................................................................... 31
8.2 SERVICE TRAFFIC ....................................................................................................................................................... 30
8.2.1 Service telephones ......................................................................................................................................... 30
8.2.1.1 Service telephone interface .......................................................................................................................................... 30
8.2.1.2 Service telephone protection switching ......................................................................................................................... 30
8.2.1.3 Service telephone performance characteristics ............................................................................................................ 30
8.2.1.4 Alarm and monitoring of the service telephone equipment ............................................................................................ 31
4 H2580
8.2.2 PABX-adapter ................................................................................................................................................. 31
8.2.3 64 kbit/s service channels ............................................................................................................................ 31
8.2.3.1 General ........................................................................................................................................................................ 31
8.2.3.2 64 kbit/s service channel protection .............................................................................................................................. 31
8.2.3.3 64 kbit/s service channel characteristics ....................................................................................................................... 31
8.2.3.4 Alarm and monitoring of the 64 kbit/s adapters ............................................................................................................ 31
8.2.4 MSOH-adapter ............................................................................................................................................... 31
8.3 WAYSIDE TRAFFIC .................................................................................................................................................... 32
8.3.1 2.048 Mb/s wayside interface ...................................................................................................................... 32
8.3.2 2.048 Mb/s protection switching .................................................................................................................. 32
9 - AIS (ALARM INDICATION SIGNAL) .................................................................................................................... 32
9.1 GENERAL .................................................................................................................................................................. 32
9.2 CHARACTERISTICS OF THE AIS SYSTEM ....................................................................................................................... 32
9.2.1 AU-4 path AIS (Tx & Rx) ............................................................................................................................... 32
9.2.2 MS-AIS (Tx & Rx) ......................................................................................................................................... 32
9.2.3 140 Mb/s AIS (Tx & Rx) ................................................................................................................................. 33
9.3 ALARMS AND MONITORING ........................................................................................................................................ 33
9.3.1 Alarms ............................................................................................................................................................. 33
9.3.2 LEDs ............................................................................................................................................................... 34
10 - RADIO PROTECTION SWITCHING (RPS) ....................................................................................................... 34
10.1 GENERAL ................................................................................................................................................................ 34
10.2 BASEBAND SWITCHING OPERATIONS .......................................................................................................................... 34
10.3 SWITCHING CAPABILITY ........................................................................................................................................... 34
10.4 PRIORITY OF PROTECTION SWITCHING ....................................................................................................................... 34
10.5 POWER DISTRIBUTION .............................................................................................................................................. 34
10.6 SPECIFICATION OF THE PROTECTION SWITCHING SYSTEM ............................................................................................ 34
10.6.1 Alignment specification ............................................................................................................................... 34
10.6.2 Switching criteria ......................................................................................................................................... 34
10.6.2.1 Continuity criteria ....................................................................................................................................................... 34
10.6.2.2 Quality criteria ............................................................................................................................................................ 35
10.6.3 Switching operation time ............................................................................................................................ 35
11 - SYSTEM SUPERVISORY CHARACTERISTICS ................................................................................................. 36
11.1 GENERAL ................................................................................................................................................................ 36
11.2 TMN INTERFACE ..................................................................................................................................................... 36
11.2.1 General ......................................................................................................................................................... 36
11.2.3 Equipment alarm interface characteristics: .............................................................................................. 36
11.3 OTHER COMMUNICATION INTERFACES ....................................................................................................................... 37
11.3.1 Interfaces for external connection: ............................................................................................................ 37
11.3.2 Interfaces for internal connection: ............................................................................................................. 37
11.4 SUPERVISORY BLOCK DIAGRAM AND UNITS ................................................................................................................ 38
11.4.1 Supervisory Unit (SU) .................................................................................................................................. 38
11.4.2 Display Unit ................................................................................................................................................. 38
11.4.3 Alarm Collection Unit (ACU) ....................................................................................................................... 39
11.4.4 Alarm Adapter Unit (AAU) ........................................................................................................................... 39
11.4.5 Alarm Board ................................................................................................................................................. 39
12 - BRANCHING CHARACTERISTICS .................................................................................................................... 41
12.1 RF CHANNEL BRANCHING UNIT ............................................................................................................................... 41
12.1.1 RF-filters and branching system ............................................................................................................... 41
12.1.2 Insertion loss of branching system ............................................................................................................ 41
12.1.3 Circulator attenuatioEquipment Code: .................................................................................................... 41
12.1.4 Circulator insertion loss ............................................................................................................................ 41
12.2 ANTENNA PORTS ..................................................................................................................................................... 42
12.2.1 VSWR at antenna port (point CC) ............................................................................................................ 42
12.2.2 Antenna port arrangements ....................................................................................................................... 42
H2580 5
13 - SYSTEM MONITORING AND ALARMS ............................................................................................................. 43
13.1 UNIT ALARMS AND INDICATORS ................................................................................................................................43
13.1.1 XMTR group alarms, indicators and test points ........................................................................................ 43
13.1.2 RCVR group alarms, indicators and test points ........................................................................................ 44
13.1.3 Modulator alarms, indicators and test points ........................................................................................... 44
13.1.4 Demodulator alarms, indicators and test points ...................................................................................... 45
13.1.5 CMI splitter alarms and indicators ............................................................................................................ 46
13.1.6 Power-supply alarms and indicators ......................................................................................................... 46
13.1.7 Radio Protection Switching (RPS) alarms and indicators ........................................................................ 46
13.1.8 XMTR-Switch-Unit (XSU) alarms and indicators ...................................................................................... 47
13.1.9 Receiver data distribution unit (RDU) alarms and indicators ................................................................. 47
13.1.10 Supervisory Unit (SU) alarms and indicators ......................................................................................... 47
13.1.11 Alarm Collection Unit (ACU) alarms and indicators .............................................................................. 47
13.1.12 RSOH-adapter alarms and indicators .................................................................................................... 48
13.1.13 Optional unit alarms and indicators ....................................................................................................... 48
13.1.13.1 Alarm Adapter Unit (AAU) alarms and indicators ................................................................................................... 48
13.1.13.2 Service telephone alarms and indicators ................................................................................................................... 48
13.1.13.3 PABX-adapter alarms and indicators ....................................................................................................................... 48
13.1.13.4 MSOH-adapter alarms and indicators ...................................................................................................................... 48
13.1.13.5 Synchronization unit alarms and indicators ................................................................................................................ 48
13.1.13.6 64 kbit/s-Adapter alarms and indicators .................................................................................................................... 49
13.2 MONITOR CONNECTORS ........................................................................................................................................... 49
13.2.1 Parallel alarm connector ............................................................................................................................ 49
13.2.2 Analogue monitor connector - J3 ............................................................................................................... 50
6 H2580
1 - NETWORK AND SYSTEM CONSIDERATIONS

This document covers the specifications of the NERA NL290-family of radio-relay equipment. This SDH, STM-1
radio-relay equipment is designed to be used in frequency bands with about 30 and 40 MHz channel spacing. The
equipment is designed for transmission of a multiple of STM-1 signals, realized by N+1 configurations, where N may
have the value from 1 to 7, or realized by N+0 configurations, where N may have the value from 1 to 8. 1+1, Hot
Standby configuration is also available. A C4-mapper is built into the modems, making available the 140 Mb/s PDH
tributary interface. Changeover between 140 Mb/s PDH and STM-1 (155 Mb/s) is easily performed by setting of
switches in the modulator- and demodulator- unit.
A principle block diagram for a digital radio relay system, including the main blocks, is shown in figure 1.1. The block
diagram includes marked interface points which shall serve as reference points for several technical parameters laid
down in this document.
A physical layout of the radio relay system, including all optional units, is shown in figure 1.2.
The equipment specifications are in accordance with relevant international standards laid down by ITU, ETSI, and
IEC.
Z' E' A' B' C' D'

Branching
Modulator Transmitter RF Tx Filter Feeder
Network(*)
D C B A E Z
Feeder Branching RF Rx Filter Receiver Demodulator
Network(*)
MAIN RECEIVER PATH

(**)
DD Cc BB AA
Branching
Feeder RF Rx Filter Receiver
Network(*)
DIVERSITY RECEIVER PATH
(*) no filtering included

(**) connection at IF
A 155 or 140 Mbit/s interface is used at points Z & Z'
Figure 1.1: Principle block diagram for a NL290-family radio system
H2580 7
SVCE CHP CH1 CHN
RELAY UNIT
CMI SPLITTER
AAU1
AAU2
SVCE TEL1
OPTION SVCE TEL2
PABX ADPT
64kb/s ADPT XMTR XMTR XMTR
MSOH or 64kb/s ADPT GROUP GROUP GROUP
DISPLAY UNIT
MAIN MAIN MAIN
OPTION 64kb/s ADPT

RSOH-ADPT RCVR RCVR RCVR
SU GROUP GROUP GROUP
OPTION ALARM BD
ACU SPACE SPACE SPACE
RPS Diversity Diversity Diversity
IF- IF- IF-

Equalizer Equalizer Equalizer
OPTION ALARM BD
ACU
Diversity Diversity Diversity
delay delay delay
cable cable cable
XMTR-SWITCH
DEMODULATOR
DEMODULATOR
DEMODULATOR
MODULATOR
MODULATOR
MODULATOR
OPTION SYNCH UNIT
RCVR DATA
DISTR
PWR SPLY
PWR SPLY
PWR SPLY
PWR SPLY
PWR SPLY
PWR SPLY
PWR SPLY
PWR SPLY
Figure 1.2: Rack-layout for a N+1 terminal
8 H2580
2 - Equipment main characteristics

2.1 General
These paragraphs contain the main characteristics of the SDH - STM-1 radio relay equipment in the frequency bands
4, L6, U6, 7, 8, 11, and 13 GHz.
2.2 Frequency bands and channel arrangement
Equipment Freq Frequency ITU-R Centre Df channel Tx-Rx min.

code band frequency (MHz) (MHz)
NL294 4 GHz 3.6-4.2 GHz Rec. 635-2 3890 MHz 40 80

3.8-4.2 GHz Rec. 382-6 4003.5 MHz 29 68
NL293 5GHz 4.4-5.0 GHz Rec. F.1099 4700 MHz 30 to 40 60
NL290 L6 GHz 5.9-6.4 GHz Rec. 383-5 6175 MHz 29.65 44.49 (1)
NL295 U6 GHz 6.4-7.1 GHz Rec. 384-5 6770 MHz 40 60
NL299 7 GHz 7.4-7.7 GHz Rec. 385-5 7575 MHz 28 42 (1)
NL292 8 GHz 7.7-8.3 GHz Rec. 386-4 8000 MHz 29.65 103.7
Annex-1
7.9-8.4 GHz OIRT-2 8150 MHz 28 70
NL291 11GHz 10.7-11.7 GHz Rec. 387-6 11200 MHz 40 90

Rec. 387-6 11200 MHz 40 130
Annex-1
NL296 13 GHz 12.7-13.3 GHz Rec. 497-4 12996 MHz 28 70
Special branching configurations are needed when using innermost channel separation below 56MHz. Innermost
(1)
channels have to be on separate polarisations. Branching filters for innermost channels have to be the option with
reduced bandwidth.
2.2.1. Frequency tolerance

Frequency tolerance: + 10 ppm
2.3 System configuration

The equipment can be configured as 1+1, Hot Standby, N+0 or N+1 frequency diversity. In N+0 configurations it is
expandable from 1+0 to 8+0. In frequency diversity configurations it is expandable from 1+1 up to 7+1. In protected
systems the protection channel can be utilized for 140 Mb/s or 155 Mb/s occasional traffic. (This feature requires the
XMTR-switch and RCVR-distr.units which is optional for 1+1 systems). All channels (including the protection
channel) can be selected as the high priority channel. Space diversity receivers (option) can be used in all
configurations mentioned above.
2.3.1 Radio terminal configurations

Each radio terminal can be configured with 140 or 155 Mb/s interface. The protection channel will always be
configured with 155 Mb/s interface. The protection channel can also be configured to carry occasional (low priority)
traffic. Occasional traffic can be either 140 Mbit/s or STM-1. 140 Mb/s occasional traffic will be mapped into STM-
1 in the XMTR-switch and demapped in the RCVR-distribution
H2580 9
All STM-1 channels except the protection channel can be configured with an optional 2.048 Mb/s channel inserted
into Section OverHead. The radio terminal will normally be configured as a RST-function according to ITU-T
Rec.G.783. If access to Multiplexer Section OverHead (MSOH) is required, then the radio terminal can be configured
as a MST-function.
2.3.2 Radio repeater configurations

A radio repeater is built by using a standard demodulator- and a standard modulator-unit, and coupling the regenerated
data-signal through on a digital level. The radio repeater will always be configured as an RST-function according to
ITU-T Rec.G.783.
2.3.2.1 Standard repeater

A standard repeater has no access to the main traffic channels. Service channels utilizing Regenerator Section
OverHead (RSOH) will be available through adapters.
2.3.2.1 Add/drop repeater

A repeater can optionally be configured with add and drop of the main traffic (140 Mb/s or 155 Mb/s) if the system is
an unprotected system (N+0 configurations). The 2.048 Mbit/s wayside channel can be dropped or routed through
independent of the main traffic (in N+0 configurations).
2.3.3 Radio channel identification

Each radio channel is identified by two allocated bits in the media specific byte no. 1 (MS#1) in SOH. Channel
identification is selected by switches in the modulator- and demodulator-unit.
2.4 Modes of operation

The system can be operated in single polarisation mode or in alternated crosspolar mode. Co-channel dual polarized
(CCDP) is also available for some of the frequency bands.
2.5 Types of installation

The equipment is designed for use in fixed or transportable applications but not mobile. The equipment is designed for
indoor installation only.
2.5.1 Safety conditions

The equipment conforms to EN60215/IEC215.
2.5.2 Environmental conditions

The equipment conforms to the environmental classes defined in ETS-300-019:
Transportation: ETS-300-019-1-2, class 2.3, public transportation.
Storage: ETS-300-019-1-1, class 1.2, weather protected,
not temperature controlled storage locations.
(extreme temperature range: -25°C to +55°C).
Use: ETS-300-019-1-3, class 3.2, partly temperature controlled
locations (temperature range: -5°C to +45°C).
10 H2580
2.6 ElectroMagnetic Compatibility conditions (EMC)
The equipment conforms to the EMC standard as specified in prETS 300 385 for grade B equipment.
2.7 Mechanical characteristics

The equipment is designed to enable easy and quick installation. The equipment racks are bolted to the floor and
supported at the top. The equipment can be mounted close to the wall or back to back. RF channel branching filters
are mounted within the rack.
Dimensions for one radio channel: 120 mm (W) x 260 mm (D) x 2200 mm (H)
Weight for one Tx and one Rx including modem and baseband units: Approx. 50 kg
Weight for a complete 1+1 terminal: Approx. 130 kg
2.7.1 Coaxial connectors

RF connectors: SMA, 50 ohm.
IF connectors: IEC 169-13, 1.6/5.6 mm and 1.0/2.3 mm.
Baseband connectors: IEC 169-13, 1.6/5.6 mm.
2.7.2 Waveguides
Interface to the antenna feeder system (see also section 12):
Equipment code Frequency Band Flanges
NL294 4 GHz PDR40
NL293 5 GHz PDR48
NL290 L6 GHz PDR70
NL295 U6 GHz PDR70
NL299 7 GHz PDR84
NL292 8 GHz PDR84
NL291 11 GHz PDR100
NL296 13 GHz PDR120
2.8 System synchronization

Each radio channel can be synchronized to an external 2 MHz clock when the system is configured with MS-
termination. A 2 MHz synch. distribution unit is used to distribute the 2 MHz clock to each of the radio channels.
The optional 2 MHz synch. distribution unit is located in the service rack. The 2 MHz synch. unit has two external
clock inputs (INP-1 and INP-2). INP-1 has highest priority. The system will automatically switch to INP-2 if INP-1
is lost. The synch. unit also has four 2 MHz clock outputs derived from the traffic received at one of the
demodulators.
Connector, 2 MHz clock: IEC 169-13, 1.6/5.6 mm.
H2580 11
2.9 Alarm and monitoring facilities
In order to facilitate fault finding, an internal alarm- and supervision system is included. This system performs
monitoring, alarm-collection and quality-data-collection from the different units, and prepares the information for the
TMN-system. The collected information is also available on the built-in display (LCD). An optional PC-software for
system-monitoring is available for connection to the radio system.
2.10 Power supply
2.10.1 General
The equipment operates from a battery supply of nominal 48 V or 24 V DC. Either the positive or negative battery
pole can be grounded. The equipment and the primary power plant shall be properly grounded. The primary DC-
power is supplied to the racks via main fuses and power switches (see fig 2.1 below). An input filter attenuates the
common mode noise before the power is distributed to the individual power supplies.
The radio racks are equipped with two types of power supplies, one for the FET power amplifier and two others
coupled in parallel for the other units.
The FET power supply is mounted together with the power amplifier on a heat sink located in the upper part of the
rack. The two other power supplies are located in the lower part of the rack. These power supplies are connected in
parallel, i.e. the outputs are connected together so that the load is shared by both units. A failure in one power supply
will automatically transfer the full load to the other. Both types of power supplies employ push-pull converters with a
switching frequency of 100 kHz.
48V 48V
Power Switch Input Power +9.4 V For
& Filter Supply FET-
Fuse (1) -5 V amplifiers
+15 V For
Power Tx/Rx,
-15 V
Supply +5 V modem &
(2) -5.2 V baseband
Power
Supply
(3)
Figure 2.1 Power supply arrangements
2.10.2 Power supply fuses
Glass cartridge type fuses are used in the power supplies

Fuses for the 24 Volt option:
Radio rack main fuse: 8 A, 32 V, slow, dimension 31.8 x 6.4 mm
Service rack main fuse: 5 A, 125 V, slow, dimension 31.8 x 6.4 mm
Main power supply fuse: 6.3 A, 250 V, rapid, dimension 20 x 5 mm
TX-group power supply fuse: 5 A, 250 V, rapid, dimension 20 x 5 mm
12 H2580
Fuses for the 48 Volt option:
Radio rack main fuse: 5 A, 125 V, slow, dimension 31.8 x 6.4 mm
Service rack main fuse: 3 A, 125 V, slow, dimension 31.8 x 6.4 mm
Main power supply fuse: 3.15 A, 250 V, rapid, dimension 20 x 5 mm
TX-group power supply fuse: 2.5 A, 250 V, rapid, dimension 20 x 5 mm
2.10.3 Primary supply characteristics

The performance as specified in this document is maintained for the following supply voltage variations:
48 Volt option: 40 - 58 V
Maximum supply voltage variations without causing any damage to the equipment:
Permitted hum from the battery chargers with battery connected: 0.6 V pp.
2.10.4 Primary supply transients

The equipment is protected against transient voltages of up to 220 V DC with a duration of maximum 100
microseconds.
2.10.5 Power consumption

Approximate power consumption from the battery at nominal supply voltage:
Unit name Unit 1+1 Terminal

Transmitter-group - standard version: 65 W 130 W
Transmitter-group - High Power version: (75 W) (150 W)
Receiver-group without space div. 12 W 24 W
Receiver-group with space div. 18 W -
IF - equalizer 0.5 W 1W
Modulator-unit (incl. BB) 14 W 28 W
Demodulator-unit - standard (incl. BB, without XPIC) 20 W 40 W
Demodulator-unit - CCDP (incl. BB and XPIC) (29 W) (58 W)
Alarm Collection-unit 3W 9 W
Alarm Adapter-unit 2W -
Radio Protection Switching 5W 5W
Supervisory-unit 5W 5W
Adapter, RSOH 1.5 W 1.5 W
Adapter, MSOH 1.5 W -
Adapter, 64 kbit/s 1.5 W -
Service-telephone 3W 3W
CMI - splitter 1W 2W
Relay & driver 0.5 W 1W
Synchronization-unit, 2 MHz 1W -
XMTR switch-unit 6W 6W
RCVR data distribution-unit 6W 6W
Power supply 4W 24 W
Total power consumption for a basic 1+1 terminal: 286 W
H2580 13
2.11 System performance
2.11.1 Monitoring of system performance

Transmission quality performance is monitored continuously by the built-in supervisory equipment. The Alarm
Collection Unit (ACU) does performance measurements and calculations based on the BIP-codes in the STM-1 and
on error information from the Viterbi-decoder. These BER-calculations are available on both repeater-and terminal
stations. BER-calculations are performed for single hop and for sections.
2.11.2 B1- & B2- parity-error output

B1- and B2- parity errors are made available on separate connectors at the top of each radio rack. These are parity
error signals from each radio channel and do not indicate the performance of the protected channel. A separate
indication signal showing the radio protection switching status is available, and can be utilized to monitor the protected
channel.
Parity errors on these two B1- and B2-connectors are only available for the traffic transmitted over the radio hop.
Parity errors from the STM-1 signal applied at the transmit side are available on the built-in display.
2.11.3 B1- and B2- parity errors characteristics:

Pulse width: 1.9 µs
Pulse frequency: Min. 3.9 µs between positive edge of two successive pulses
Connector: Snap-On coaxial connector (DIN 47297, type B), series 1.0/2.3
Electrical interface: TTL or Opto-coupler driver selected by straps on the ACU.
2.11.4 System performance calculations

Performance data calculations are available as a software option. Performance data can be presented either according
to ITU-T Rec. G.821 or according to ITU-T Rec. G.826 The following system quality calculations are included in the
performance data software option:
Performance Calculations Regenerator Multiplex Multiplexer

Section Section Section VC-4
Termination Termination Termination
Calculation Calculation Calculation
based on B1 based on B2 based on B3
(BIP-8)| (BIP-24) (BIP8)
Errored Second Ratio (ESR) yes yes no

Severely Errored Second Ratio (SESR) yes yes no
Background Block Error Ratio (BBER) yes yes no
Unavailable state (UAS) yes yes no
System performance can also be calculated on the protection channel as well as the individual channel regardless of
radio protection switching. Calculations on the protected channel are based on B2-parity errors and are available only
on the terminals where B2 is terminated. Performance data are available through the TMN-interfaces or on the
internal display.
2.11.5 Equipment background BER (Residual BER)

Equipment background BER is measured under simulated operating conditions over an artificial hop without
interference. The input signal level at point B is between 15 dB and 40 dB above the level which gives BER = 10-3.
In a measurement period of 24 hours the number of bit errors shall be less than 10 (BER £ 10-12).
14 H2580
2.11.6 System gain
Typical values for system gain are given in the table below. Guaranteed values are <1.5 dB below the typical values:
Equipment Code:
System gain BB (10-3) [dB] NL294 NL293 NL290 NL295 NL299 NL292 NL291 NL296
128 TCM modulation 102 102 102 102 100 100 98 96
64 TCM modulation 105 105 - 105 - - 101 -
System gain CC (10-3) [dB]

128 TCM modulation 95.5*
Co-channel operation
(CCDP)
* High power Transmitters (+2dB) are available.
2.11.7 System signature

System signature is specified including IF Equalizer, Adaptive Time Domain Equalizer (ATDE) and Viterbi decoding.
The system will recover after loss of synchronization if the notch-depth is £ 18 dB for both minimum and non-
minimum phase.
Signature mask (delay = 6.3 ns): BER = 10-3 BER = 10-6

Max. notch depth, minimum phase: 20 dB 17 dB
Max. notch depth, non-minimum phase: 20 dB 17 dB
Signature bandwidth - 128 TCM modulation: < 22 MHz < 26 MHz
Signature bandwidth - 64 TCM modulation: < 28 MHz < 34 MHz
Signature factor, typical value - 128 TCM modulation: 1.50 2.00
Signature factor, typical value - 64 TCM modulation: 1.20* 1.70*
* The typical signature value for 64TCM is improved due to a very good signature value for minimum phase.
2.11.8 Transmission delay

Total transmission delay Tx-side: approx. 4 µs.
Total transmission delay Rx-side: approx. 9 µs.
Total transmission delay for a radio regenerator: approx. 13 µs.
2.12 System reliability

The reliability and stability of the equipment are such as to allow unstaffed stations. As an annual average it is not
necessary with more than two routine visits per year in order to maintain the performance specified in this document.
H2580 15
2.12.1 Mean Time Between Failure (MTBF)
The MTBF values are based on calculations according to MIL-HDBK-217E including correction factors based on
experience.
Modulator including baseband processing: 375,000 hours
Demodulator including baseband processing: 315,000 hours
Transmitter: 300,000 hours
Receiver without space diversity combiner: 290,000 hours
Receiver with space diversity combiner: 250,000 hours
XMTR switch: 555,000 hours
RCVR data distribution: 830,000 hours
RPS (Radio Protection Switch-unit): 1000,000 hours
Power supply: 435,000 hours
CMI splitter: 900,000 hours
Relay Unit: 3300,000 hours
2.13 Interference sensitivity

Interference sensitivity characteristics are according to ETSI recommendation ETS 300 234.
2.13.1 Co-channel interference sensitivity

Limits of co-channel interference sensitivity as given by ETSI for systems with 30 MHz channel spacing are shown
in figure 2.2.
dBm
-59
-60
-61 BER=10E-6
-62
Receiver input level at point B
-63
-64
BER=10E-3
-65
13 GHz
< 10 GHz
-66
-67
-68
13 GHz
-69
< 10 GHz
-70
-71
-72
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 [db]
File: cochan.drw S/I referred at point B
Figure 2.2 Co-channel interference sensitivity limits as given by ETSI
16 H2580
2.13.2 Adjacent channel interference sensitivity
The BER shall be less or equal to the values given in table 2.1 for the corresponding input levels, S/I levels and
frequency bands. All levels are referenced to point B.
Frequency bands
4/5/L6/ 4/5/L6/ 7 GHz 11/13 GHz
U6/8 GHz U6/8 GHz
Co-channel
operation
BER £10-3 S/I 3 dB -12.5dB 7 dB 7 dB

Receiver input level - 128 TCM -67,5 dBm -67,5 dBm -67,5 dBm -66,5 dBm
Receiver input level - 64 TCM -70 dBm -70 dBm -69 dBm
BER £10-6 S/I 7 dB -7.5dB 11 dB 11 dB
Receiver input level - 128 TCM -65 dBm -65 dBm -65 dBm -64 dBm
Receiver input level - 64 TCM -67 dBm -67 dBm -66 dBm
Table 2.1 Adjacent channel interference sensitivity requirements
H2580 17
3 - System characteristics for Space Diversity (SD)

3.1 General
A complete space diversity receiver group including main and space receiver, local oscillator (LO) and combining
circuitry is available as an option. When used, the space diversity receiver group will substitute the standard receiver
group.
3.2 Combining principles and performance

Combining method is IF combining. Maximum difference of waveguide lengths between main- and diversity antennas
is approx. 20 meters. Two versions of the combiner exists. The combiner, 3DK125, was used as standard until mid
1997. After mid 1997 is the combiner 8DK138 used as standard.
3.2.1 Combiner 3DK125:

The combiner algorithm, at signal levels above -65dBm, is based on selecting the best of the two signals, and switch
out the worst. Below approx. -65dBm a maximum power combining algorithm is used if the two signal are about
equal within about 3-6 dB.
3.2.2 Combiner 8DK138:

The combiner algorithm is based on a weighted in-phase combination. Dispersion is measured in both signals before
combining. This is done to avoid using a distorted signal if the other signal is not distorted.
3.3 Alarms and monitoring for the SD-equipment

The space diversity receiver input level is monitored and displayed on the built-in display. See also section 13.2.2
where a monitor connector is described. A phase control alarm is located on the front of the space diversity receiver
group.
18 H2580
4 - Transmitter characteristics
4.1 Transmitter output characteristics
4.1.1 Output power

Output power is measured with modulation (PRBS-data).
Equipment Code: NL294 NL293 NL290 NL295 NL299 NL292 NL291 NL296
Output power at A [dBm] * +30.9 +30.9 +30.7 +30.7 +29.7 +29.7 +28.0 +27.3
(guaranteed values)
Output power at B [dBm] * +29.7 +29.7 +29.6 +29.6 +28.4 +28.4 +26.5 +25.0
(typical values)
* High Power Tx-versions (+2dB) are available for some of the frequency bands.
Transmitter output power can be reduced from the maximum value in three steps (-3dB, -6dB or -10dB).
Guaranteed values for point Bare <0.8 dB below the typical values.
4.1.2 Automatic Transmitter Power Control (ATPC)

ATPC is an optional feature on the NL290-family which is aimed to drive the TX Power amplifier output level from a
proper minimum, which is calculated to facilitate the radio network planning and which is used in the case of normal
propagation, up to a maximum value which is given in section 4.1.1. An ATPC-alarm is activated if the regulated hop
or the backward regulation channel endures an outage for more than a N seconds (N is configurable).
ATPC-figures:
Maximum transmitter power output regulation speed: £ 50 dB/s
ATPC-range (from maximum to minimum output power): ³ 15 dB
Nominal power output at start-up: programmable by straps from

10 dB below maximum power up to maximum power (3 dB steps).
ATPC-alarm delay activation after outage of either direction: 1 sec < N < 15 sec (res.: 1 sec)
Power output when the ATPC-alarm is activated is configurable from

maximum output power down to minimum output power with a
resolution: < 2 dB.
Nominal input level is adjustable on front of each receiver group.

Adjustment range: -25 dBm - -50 dBm
4.1.3 RF coaxial impedance

RF coaxial impedance: 50 ohm
4.1.4 TX-oscillator frequency stability

Frequency tolerance: ± 5 ppm
The frequency stability of the TX-oscillator over one
maintenance period: ± 10 ppm
H2580 19
4.1.5 RF - filter bandwidth and losses A’ - B
The RF-filters used on the TX-side has a 3dB bandwidth of 46 MHz. For some frequency bands are this bandwidth
reduced to 39MHz. Alternatively, are more narrow band filters used for co-channel configurations. The actual RF-
filters used depend on frequency band and system configuration. These alternative RF-filters are specified in para-
graph 5.1.
RF filter 3 dB BW [MHz] 46±2 46±2 46±2 46±2 46±2 46±2 46±2 46±2
Typical losses A’ - B’ [dB] 1.2 1.2 1.1 1.1 1.3 1.3 1.5 2.3
Guaranteed losses A’ - B’ ≤ 1.9 ≤ 1.9 ≤ 1.4 ≤ 1.5 ≤ 1.7 ≤ 1.7 ≤ 1.8 ≤ 2.6
[dB]
4.1.6 RF spectrum mask

The transmitter spectrum mask referenced to point B’ is given in figure 4.1. The mask for about 30 MHz channel
spacing is identical to that considered in ETSI recommendation ETS 300 234, figure 2, and also identical to that
considered in CEPT recommendation T/L 04-04. It allows compatibility between systems defined in ETSI- and
CEPT- recommendations. The innermost mask is for systems with co-channel operation in channel plans with about
30 MHz channel spacing.
dB
10
+1/11,5
0 +1/15
+1/13
-10
40 MHz -10/14,5
channel -20/25
-20 spacing
-20/35
-30
-32/17-18 -35/20-21
-40 Co-channel
-45/22
-50
Alternated,
30 MHz
-60 channel -65/34 -65/60
spacing
-65/31.5
-70
-70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70MHz
Frequency offset from the actual centre frequency
File: spectrum.dsf
Figure 4.1 RF spectrum mask for the NL290-family
20 H2580
4.1.7 Spurious emission within the STM-1 system channel plan.
The levels of spurious emissions from the transmitter, referenced to point B' are specified as given in the table below:
Spurious Emission Frequency Specification limit Controlling factor

Relative to Ch. Assigned
Frequency
± IF (L.O. freq.) £ -60 dBm Within half band, digital into analogue
± 2 x IF (unwanted sideband) £ -90 dBm Other half band, digital into digital
± IF, ± 3 x IF (unwanted £ -90 dBm Other half band, digital into digital
sideband at 2nd IF harmonic)
The levels of all other spurious signals are:

£ -90dBm if spurious signal frequency falls within receiver half-band.
£ -60dBm if spurious signal frequency falls within transmitter half-band.
4.2 IF input characteristics (point E)

Frequency: 70 MHz
Input level: 0 dBm
Input level variation acceptable by the transmitter: ± 1.5 dB
Impedance: 75 ohm unbal.
Return loss, 70 MHz + 16 MHz : ³ 26 dB
4.3 Transmitter monitoring facilities

The following parameters can be monitored and displayed on the built-in display:
- Output power
- Local oscillator level
- Local oscillator AFC voltage
- Secondary power voltage levels
See also section 13.2.2 where a monitor connector is described.
4.4 Transmitter alarms

The transmitter group alarm is displayed on the front of the transmitter group (LED), and consists of the following
alarms:
- IF input alarm. Alarm level 3-6 dB below nominal level.
- Transmitter output alarm. Alarm level 3-6 dB below nominal level.
- Local oscillator alarm (phase lock or level).
H2580 21
5 - Receiver characteristics
5.1 Receiver input characteristics
5.1.1 Input signal range
Maximum input signal levels in point B (Measured with PRBS of 223-1) These limits apply without interference:
BER £ 10-3 [dBm] -15.0 -15.0 -15.0 -15.0 -15.0 -15.0 -15.0 -15.0
BER £ 10-6 [dBm] -18.0 -18.0 -18.0 -18.0 -18.0 -18.0 -18.0 -18.0
BER £ 10-10 [dBm] -21.0 -21.0 -21.0 -21.0 -21.0 -21.0 -21.0 -21.0
Typical receiver threshold in point B with 128 TCM modulation (Measured with PRBS of 223-1):
BER £ 10-3 [dBm] -72.3 -72.3 -72.4 -72.4 -71.6 -71.6 -71.5 -71.0
BER £ 10-6 [dBm] -69.0 -69.0 -69.0 -69.0 -68.0 -68.0 -68.0 -67.5
-10
BER £ 10 [dBm] -65.0 -65.0 -65.0 -65.0 -64.0 -64.0 -64.0 -63.5
Typical receiver threshold in point B with 64 TCM modulation (Measured with PRBS of 223-1):
BER £ 10-3 [dBm] -75.3 -75.3 - -75.4 - - -74.5 -
BER £ 10-6 [dBm] -72.0 -72.0 - -72.0 - - -71.0 -
-10
BER £ 10 [dBm] -68.0 -68.0 - -68.0 - - -67.0 -
5.1.2 RF - filter bandwidth and losses B - A

Option A
RF filter 3 dB 46 ± 2 46 ± 2 46 ± 2 46 ± 2 46 ± 2 46 ± 2 46 ± 2 46 ± 2
bandwidth [MHz]
Typical losses 1.2 1.2 1.1 1.1 1.5 1.5 1.5 2.3
B-A [dB]
Guaranteed losses £ 2.0 £ 2.0 £ 1.6 £ 1.7 £ 1.9 £ 1.9 £ 1.8 £ 2.6
B-A [dB]
Option B:
Equipment Code: NL299 NL291
RF filter 3 dB bandwidth [MHz] 39 ± 2 39 ± 2
Typical losses B-A [dB] 1.5 1.5
Guaranteed losses B-A [dB] £ 1.9 £ 1.8
Option C:
Equipment Code: NL294 NL290 NL295
RF filter 3 dB bandwidth [MHz] 31 ± 2 31 ± 2 31 ± 2
Typical losses B-A [dB] 1.2 1.1 1.1
Guaranteed losses B-A [dB] £ 2.0 £ 1.6 £ 1.7
22 H2580
5.1.3 RF coaxial impedance
RF coaxial impedance: 50 ohm
5.1.4 RF input return loss at point C

RF input return loss: > 26 dB
5.1.5 Local RX-oscillator tolerance and stability

Frequency tolerance: ± 5 ppm
The frequency stability of the RX-oscillator: ± 10 ppm
5.1.6 Spurious and harmonic signal emission

Spurious emission at the local oscillator frequency at point B: £ -100 dBm
5.1.7 Image frequency attenuation

Image frequency attenuation (including RF channel branching filters): ³ 100 dB
5.1.8 Noise figure
Equipment code: NL294 NL293 NL290 NL295 NL299 NL292 NL291 NL296
Typical noise figure

F at point B [dB] £ 4.2 £ 4.2 £ 4.1 £ 4.1 £ 4.5 £ 4.5 £ 4.5 £ 5.3
5.2 IF output characteristics (point E)

Frequency: 70 MHz
Output level: 0 dBm
Output level tolerance: ±1.0 dB
Impedance: 75 ohm unbalanced
Return loss, 70 MHz ± 16 MHz: ³ 26 dB
Filtering roll-off factor (alpha), 128TCM modulation: 0.34 or 0.29
Filtering roll-off factor (alpha), 64TCM modulation: 0.35
IF-filter-bandwidth (3dB), 128TCM modulation: 24 MHz
IF-filter-bandwidth (3dB), 64TCM modulation: 31 MHz
5.2.1 IF-IF group delay and amplitude response

IF group delay variation and IF amplitude variation for various combination of modulation method and RF-filters are
shown in the table below.
Alternated arr. 30 MHz Co-ch. 30 MHz Co-ch. 40 MHz
channel spacing channel spacing channel spacing
3dB bw. RF-filter: 3dB bw. RF-filter: 3dB bw. RF-filter:
TX=RX= (46 or 39) ± 1 MHz TX = 39 ± 1 MHz TX=RX= 31 ± 1 MHz
128 TCM: RX = 31± 1 MHz
Delay 70 ± 12 MHz £ 11ns £ 25 ns £ 40 ns
Amp. resp.: 70 ± 12 MHz £ 2 dB £ 2 dB £ 2 dB
64 TCM:
Delay 70 ± 16 MHz £ 38 ns
Amp. resp.: 70 ± 16 MHz £ 2 dB
H2580 23
5.2.2 IF equalizer
An adaptive slope equalizer is included at IF.
Frequency range: f0 ± 16 MHz
Compensation level: ± 10 dB slope
5.3 Receiver monitoring facilities

An extra IF-output port is provided for measuring purposes.
Interface: 75 ohm, -20 dB coupled.
Connector: IEC 169-13, 1.6/5.6 mm.
Point A and A is available at the equipment front for connecting measuring instruments. A test lamp, mounted on the
receiver unit is lit when the receiver is switched to Manual Gain Control (MGC) operation, i.e. locked condition.
The following parameters can be monitored and displayed on the built-in supervisory unit:
- Received signal level
- Local oscillator level
- Local oscillator AFC voltage
- Secondary power voltage levels
See also section 13.2.2 where a monitor connector is described.
5.4 Receiver alarms

The following alarms are displayed on the front of the receiver group:
- Local oscillator alarm (phase lock or level).
- Receive input level below AGC range
- Diversity phase control alarm (only on space diversity receiver group)
24 H2580
6 - Modem characteristics
6.1 Modulator
The main functions of the modulator unit are:
- Cable-equalizing and CMI-decoding.
- Signal processing necessary to access SOH in the STM-1 signal.
- Signal processing necessary to map 139.264 Mb/s into a STM-1 frame (option).
- Conv./differential encoding and mapping for the Trellis encoder.
- Digital pulse shaping FIR-filtering.
- 64 or 128-cross modulation.
6.1.1 Modulation method

The modulation method used is 4-Dimensional, 128 points, Trellis Coded Modulation (4D-128TCM). Optionally can
a 2Dimensional, 64 points, Trellis Coded Modulation (2D-64TCM) modulation method be used for systems in
channel plans with 40 MHz channel spacing (4,5,U6,11 GHz).
6.1.2 Input aggregate bitrate

The gross transmitted system bit rate is 155.520 Mb/s.
In the 4D-128TCM modem is this extended by 14/13 in the trellis encoder, and transmitted in two subsequent
symbols, each 7 bits. The gross transmitted symbol rate is then 155.520*14/13/7 = 155.520/6.5 = 23.93 Msymbols/
s.
In the 2D-64TCM modem is this extended by 6/5 in the trellis encoder, and transmitted in a 6 bit symbol. The gross
transmitted symbol rate is then 155.520 / 5 = 31.10 Msymbols/s.
6.1.3 IF characteristics
Center frequency: 70 MHz
Output level: 0 dBm
Output level tolerance: ± 1.2 dB
Impedance: 75 ohms, unbalanced
Return loss, 70 MHz + 13 (16*) MHz: ³ 24 dB
* 64 TCM modulation
6.2 Demodulator
The main functions of the demodulator unit are:
- 64 or 128 points, Trellis code demodulation.
- Carrier and clock regeneration.
- Adaptive Transversal Filtering.
- Trellis decoding utilizing the Viterbi algorithm for soft decision.
- Signal processing necessary to access the SOH in the STM-1 frame.
- Signal processing necessary to extract 139.264 Mb/s out of a STM-1 frame (option).
- Alignment and receiver-switching between main- and protection-channel.
- CMI encoding
6.2.1 Demodulation method

The demodulator is a coherent detector. Demodulation method is 64 or 128 points, 8 state, Trellis coded
demodulation including Viterbi soft decision decoding.
H2580 25
6.2.2 IF characteristics
Center frequency: 70 MHz
Frequency tolerance: ± 400 kHz
Input level: 0 dBm
Input level tolerance: ± 1.2 dB
Impedance: 75 ohms, unbalanced
Return loss, 70 MHz + 13 (16*) MHz: ³ 24 dB
* 64 TCM demodulation
6.2.3 Adaptive Time Domain Equalizer (ATDE)

An Adaptive Time Domain Equalizer (ATDE) is provided for each radio channel in order to establish effective
countermeasures against the distortion effects caused by multipath transmission (selective fading).
The complex equalizer is controlled by Least Mean Square error (LMS) or Maximum Level Error (MLE) algorithms.
The optimum algorithm will automatically be selected.
6.2.3.1 Performance and distortion sensitivity

Maximum selective fading notch-speed within power spectrum: ³ 100 MHz/s
Maximum selective fading notch-depth changes: ³ 100 dB/s
Some characteristics and functions of the equalizer-chip are listed below:

Realized in a single chip ASIC containing about 90.000 gates.
Filter length = 13; eight taps Linear Forward Equalizer (LFE) and five taps Decision Feedback Equalizer (DFE).
Automatic switching between the MLE- and LMS-algorithm.
Generates control signal for carrier-recovery and timing-recovery.
Built in digital AGC, DC-offset- and quadrature-phase adjustment.
Prepared for XPIC-operation.
6.2.4 Trellis decoder

Error correction is performed by utilizing a coded modulation technique. A 2-dimensional, 64 points or a 4-
dimensional, 128 points, Trellis code is applied depending on frequency plan. Coding gain of approx. 4 dB is
achieved at BER=10-10 by utilizing an 8 state Viterbi-decoder with maximum likelihood decoding.
Some characteristics and functions of the Trellis decoder chip are listed below:
Realized in a single chip ASIC containing about 46.000 gates.
Fast synchronization between 2-dimensional symbols.
Viterbi depth = 15
26 H2580
7 - Baseband characteristics
7.1 General
This section describes the baseband interfaces and the use of section overhead.
7.2 Transmission interfaces

Three tributary interfaces are available; 140 Mb/s plesiochronous, STM-1 electrical and optionally STM-1 optical .
The STM-1 interface can be configured to terminate either Regenerator Section (RS) or Multiplexer Section (MS).
The electrical interface, including both 140 Mb/s and STM-1, is the standard option. The optical STM-1 interface is
available as an option.
A N+1 system can be configured as a mixture of both the 140 Mb/s option and the STM-1 option, and still perform
errorless switching to the protection channel. The 140 Mb/s signals are mapped into a STM-1 frame as described in
ITU-T Rec. G.707. This mapping is done prior to splitting the signal for transmission on the protection channel. The
protection channel will always carry a STM-1 signal.
7.2.1 Transmission interface characteristics - 139.264 Mb/s:

Electrical interface according to ITU-T Rec. G.703; paragraph 9:
Bitrate: 139.264 Mb/s ± 15 ppm
Gross transmitted bitrate: 155.520 Mb/s
Line code: CMI
Return loss (7 MHz to 210 MHz): ³ 15 dB
Pulse amplitude: 1.0 V ± 0.1 V
Maximum attenuation of input signal at 70 MHz: 12 dB
Connector type: IEC 169-13, 1.6/5.6 mm
7.2.2 Transmission interface characteristics - STM-1 electrical:

Electrical interface according to ITU-T Rec. G.703; paragraph 12:
Line code: CMI
Return loss (8 MHz to 240 MHz): ³ 15 dB
Maximum attenuation of input signal at 78 MHz: 12.7 dB
Connector type: IEC 169-13, 1.6/5.6 mm
7.2.3 Transmission interface characteristics - STM-1 optical:

Optical interface according to ITU-T Rec. G.957; S-1.1:
Operating wavelength range: 1261 - 1360 nm
Source type: MLM
Spectral characteristics:
- maximum RMS width (s): 7.7 nm
Distance: » 15 km
Attenuation range: 0 - 12 dB
Mean launched power: -8 - -15 dBm
Minimum receiver sensitivity: - 28 dBm
Connector type: SC/PC
The baseband interface characteristics towards multiplex equipment complies with ITU-T Rec. G.707.
H2580 27
7.3 Scrambling / descrambling functions
The system contains a radio specific scrambler / descrambler which randomizes the transmitted digital signal in order
to make the RF power spectrum as uniform as possible, irrespective of the transmitted data. The Network Node
Interface (140 Mb/s or 155 Mb/s) is scrambled according to ITU-T Rec. G.707:
Radio specific scrambler type: 15 bit parallel

Radio specific scrambler polynom: 1 + X14 + X15
NNI scrambler type (Rec. G.707 section 6.5): 7 bit parallel
NNI scrambler polynom: 1 + X6 + X7
7.4 Section OverHead (SOH)

Use of Section OverHead bytes conforms to ETSI/TM4-Report on the SDH aspects regarding digital radio-relay
systems. Access to bytes in MSOH at a regenerator is according to ITU-R Rec.750. A description is given below:
A1 A1 A1 A2 A2 A2 J0 N N
B1 MS#1 MS#2 E1 X X F1 N N
D1 MS#3 S1 D2 X X D3 X X
H1 H1 H1 H2 H2 H2 H3 H3 H3
H3
B2 B2 B2 K1 X X K2 X X
D4 X X D5 X X D6 X X
D7 X X D8 X X D9 X X
D10 X X D11 X X D12 X X
S1 Z1#2 Z1#3 Z2#1 Z2#2 M1 E2 P#2 P#3
Table 1 : Utilization of SOH (Section OverHead)
7.4.1 Frameword and parity bytes
The first nine bytes in the STM-1 frame (row 1 in Section OverHead) are unscrambled according to ITU-T Rec.
G.707.
A1: Frameword (11110110)
A2: Frameword (00101000)
J0: Regenerator Section Trace (not used).
B1: BIP-8 (Bit Interleaved Parity) between regenerator sections
B2: BIP-24 (Bit Interleaved Parity) between terminal sections
Byte 8 and byte 9 in row 1 are reserved for national use, and are utilized if the 2.048 Mb/s wayside traffic option is
selected.
7.4.2 Media specific bytes

3 bytes in RSOH (MS#1, MS#2 and MS#3) are used for radio specific purposes:
MS#1: Radio Protection Switching criteria.
MS#2: Radio Protection Switching control.
MS#3: Used for internal alarm and error-pulses and
ATPC control-information.
28 H2580
7.4.3 Other SOH-bytes
E1-byte: Orderwire, 4w / 2w extension.
F1-byte: User channel, V11 or G.703 interface through optional
64kbit/s adapter.
D1-D3 bytes: Data communication channel, prepared for
Q-interface according to ITU-T Rec. G.773
D4-D12 bytes: Data communication channel,
unrestricted channel with V11 electrical interface.
E2-byte: Orderwire, G.703, co-directional interface, only available
when MS-termination is used.
K1/K2-byte: Automatic protection switching (MSP).
S1-byte: Synchronization Status Message (not implemented).
Z1/Z2-byte: Spare bytes, V11 or G.703 interface through optional
64kbit/s adapter.
M1-byte: Multiplex Section - Remote Error Identifier (MS-REI)
(not implemented).
7.4.4 2.048 Mb/s wayside traffic bytes

A 2.048 Mb/s additional channel can be accommodated within the SOH using the 35 shadowed bytes shown in
section 7.4.
7.5 Specifications of jitter and wander
7.5.1 STM-1 interface

Input jitter and wander tolerances are according to ITU-T, Rec.G.783. Detailed parameters are given in ITU-T,
Rec.G.958. Output jitter and wander generation are according to ITU-T, Rec. G.825. Jitter and wander transfer are
according to ITU-T, Rec.G.783 and ITU-T, Rec. G.958.
7.5.2 140 Mb/s interface

Input jitter and wander tolerances are according to ITU-T, Rec.G.823. Jitter and wander transfer are according
ITU-T, Rec.G.783.
7.6 Extra baseband output

The demodulator has two equal outputs, one of which is intended for measuring purposes:
Line code: CMI

The output is protected against short circuits or other accidental mismatching.
H2580 29
8 - Service traffic and wayside traffic

8.1 General
The service channels and wayside traffic channels are transmitted as part of SOH conforming to ITU-T Rec. G.707.
All electrical digital interfaces conform to ITU-T Rec. G.703. The analogue interface conforms to ITU-T Rec. G.711.
Pulse Code Modulation (PCM) of voice frequency is used, using A-law companding characteristics.
Use of 2 Mb/s for wayside traffic will limit the number of channels available for other services. The 2 Mb/s channel,
the express-telephone and omnibus-telephone and the other 64kb/s channels are utilizing Section OverHead as de-
scribed in section 7.4.
The express- and omnibus-telephone will always utilize byte E1, F1 or E2 for transmission, if E&M interface is
required. Byte E1 and F1 are available on all stations. Byte E2 is only available on terminal stations where MSOH is
terminated.
Other protected 64 kb/s channels available for service purposes are the following bytes: S1, Z1#2, Z1#3, Z2#1, Z2#2,
M1, byte 2-5 (row 2, byte number 5), byte 2-6, byte 3-3, byte 3-5, and byte 3-6. All these channels are available
when the 2 Mb/s channel is not used. When the 2 Mb/s channel is used, only the bytes S1, Z1#2, Z1#3, Z2#1, Z2#2,
M1 are available as extra service channels.
Remark:
Use of the S1-, M1, and Z-bytes is restricted since they are part of MSOH, and can only be used when MSOH is
terminated (MST-configuration is selected) or when parity is controlled by P#2 and P#3. Byte S1 and byte Z2#1 are
only available on stations where MST-configuration is used. The bytes Z1#2, Z1#3, Z2#2 and M1 are available on all
stations when parity is controlled by P#2 and P#3.
8.2 Service traffic

8.2.1 Service telephones
Three 64 kbit/s channels are available for transmission of omnibus and express telephone with E&M interfaces.
These three channels, E1, F1 and E2 are all available on the databus coming from the RSOH-adapter. The RSOH-
adapter is performing the switching between channel 1 and channel protection. Switches on the service telephone are
used to select which channel to use. Channel E2 is part of MSOH and can only be selected on terminal stations where
MSOH is terminated.
The same service telephone unit is used for both omnibus and express telephone. Up to two service telephones can be
provided in one service rack. Service telephones can be supplied on all terminal and repeater stations. The service
telephones are provided with both selective and collective call functions. A loudspeaker interface is also provided.
8.2.1.1 Service telephone interface

All electrical digital interface characteristics of the service telephones comply with ITU-T Rec. G.703.
8.2.1.2 Service telephone protection switching

The service telephone channels are automatically switched to the stand-by channel if the regular channel fails.
8.2.1.3 Service telephone performance characteristics

The performance of the VF service channel complies in general with ITU-T Rec. G.712 and G.713.
Code: PCM
Frequency range: 0.3 - 3.4 kHz
Signal level: -6 dBm
Impedance: 600 ohm balanced
Loudspeaker output (no volume control): < 0.5 W
Loudspeaker impedance: > 8 ohm
Psofometric noise (no traffic): -65 dBm0p
Connector: 37-pin, D-sub, female
30 H2580
8.2.1.4 Alarm and monitoring of the service telephone equipment
Each service telephone unit is provided with a main alarm which is connected to the Alarm Collection Unit (ACU).
8.2.2 PABX-adapter
An optional PABX- (Private Automatic Branch eXchange) adapter board is provided to connect the service telephone
to an external PABX subscriber line. It is possible to connect one voice circuit to a maximum of ten PABX subscriber
lines. When making an external call the desired PABX must be selected, and the call can be continued after the
standard dialling tone has been received. An incoming call from any PABX will activate the collective calling of the
omnibus or express voice circuit.
PABX interface: 2W, 600 ohm
8.2.3 64 kbit/s service channels
8.2.3.1 General
Some of the bytes in Section OverHead can be utilized as 64 kbit/s service channels. An optional 64 kbit/s adapter
board is provided to access these bytes. Each adapter board has two 64 kbit/s channels available for the user. If
necessary, it is possible to disable on of the channels. Seven positions are available for 64 kbit/s adapter boards
(fourteen 64 kbit/s channels). Only six positions are available if the optional MSOH-adapter is used. Use of 2.048
Mb/s wayside traffic will limit the number of 64 kbit/s channels that are available since the 2.048 Mb/s wayside
channel is utilizing the same bytes in SOH.
8.2.3.2 64 kbit/s service channel protection

Five (four if the optional MSOH-adapter is used) of the seven 64 kbit/s adapters positions are N+1 protected between
terminals, and unprotected on regenerators. Two of the seven 64 kbit/s adapters positions are 1+1 protected both on
terminals and on regenerators (requires the RSOH-adapter).
8.2.3.3 64 kbit/s service channel characteristics

The electrical interface is according to ITU-T Rec. G.703, co- or contra-directional, or the V.11 specification, contra-
directional only. The G.703/V.11 interface as well as co- or contra-directional mode are selected individually for each
64 kbit/s channel by setting mode switches on the 64 kbit/s adapter board.
Connector: 37-pins, D-sub, female
8.2.3.4 Alarm and monitoring of the 64 kbit/s adapters

Each 64 kbit/s adapter board is provided with a main alarm which is connected to Alarm Collection Unit (ACU).
8.2.4 MSOH-adapter
An optional MSOH- (Multiplexer Section OverHead) adapter board is provided to get access to the DCCM-channel
(byte D4-D12) and the K1 & K2 - bytes in MSOH on radio channel 1. These channels can be used if the radio
equipment is configured to terminate MSOH.
D4-D12 channel interface (576 kbit/s): RS-422
K1-channel interface: CMOS, serial
K2-channel interface: CMOS, serial
H2580 31
8.3 Wayside traffic
As an option, one 2.048 Mb/s channel is available for transmission of wayside traffic on each RF-channel. The 2.048
Mb/s channel can be selected to be either synchronous or asynchronous to the STM-1 frame. The 2.048 Mb/s
channels are protected in the same way as the main traffic, i.e. covered by the N+1 radio protection switching within
a switching section. Drop and insert of 2.048 Mb/s channels on repeater stations will be unprotected. The
connectors for 2.048 Mb/s wayside traffic are located at the top of each radio rack.
8.3.1 2.048 Mb/s wayside interface

The 2.048 Mb/s interface is in accordance with ITU-T, G.703.
Code: HDB-3
Connectors: IEC 169-13, 1.6/5.6 mm
8.3.2 2.048 Mb/s protection switching

The 2.048 Mb/s traffic is inserted into the STM-1-frame before splitting the traffic to the protection channel. It is
therefore protected by the main-traffic N+1 protection switching system within a switching section. The 2.048 Mb/s
can be dropped and inserted in the middle of a main traffic switching section, but is then not protected.
9 - AIS (Alarm Indication Signal)

9.1 General
An Alarm Indication Signal (AIS) is a signal sent downstream as an indication that an upstream failure has been
detected and alarmed. In this section the characteristics of the AIS system and criteria for insertion and removal are
considered.
9.2 Characteristics of the AIS system

The section AIS is detected as all 1s in bits 6, 7, 8 of byte K2 after descrambling according to ITU-T Rec. G.707.
AU-4 path AIS is specified as all 1s in the entire AU-4, including the AU-4 pointer. AU-4 path AIS is carried within
the STM-1 frame having valid SOH.
9.2.1 AU-4 path AIS (Tx & Rx)

AU-4 path AIS is processed in the STM-1-processor in the modulator- and demodulator-units. AU-4 path AIS is
processed only when the radio section is set up with Section Adaptation (MS-termination).
Insertion criteria - Tx & Rx (modulator & demodulator):

AU-4 path AIS is inserted under the following conditions (according to ITU-T Rec. G.783, sect. 2.5).
a) Loss of pointer
b) Received AU-4 path AIS
The AIS signal is inserted after any of the conditions stated above have been detected.
Removal criteria:
AU-4 path AIS is removed immediately when both criteria a) and b) are reset.
9.2.2 MS-AIS (Tx & Rx)

MS-AIS is processed according to ITU-T Rec. G.783, section 2.2.2. Insertion time is less than 3 ms. Deactivation is
done immediately after removal of the AIS-criteria.
32 H2580
Insertion criteria - Tx (modulator):
MS-AIS is inserted under the following conditions (processed in the modulator-unit):
a) Loss of signal (LOS)
b) Loss of frame (LOF)
The MS-AIS is inserted after any of the conditions stated above have been detected.
Insertion criteria - Rx (demodulator):

MS-AIS is inserted under the following conditions (processed in the demodulator-unit):
a) Loss of signal (LOS)
b) Loss of frame (LOF)
c) RF-id alarm (can be disabled by switch in the demodulator)
d) Excessive BER (HBER - can be disabled by switch in the demodulator)
e) Alignment PLL-alarm
f) Control signal from RPS
The MS-AIS is inserted after any of the conditions stated above have been detected.
Removal criteria:
MS-AIS is removed immediately when all insertion criteria are reset.
9.2.3 140 Mb/s AIS (Tx & Rx)

140 Mb/s AIS is processed in the modulator- and demodulator-units. 140 Mb/s AIS is processed when the radio
channel is configured with 140 Mb/s interface.
Insertion criteria - Tx (modulator):

140 Mb/s AIS is inserted when Loss Of Signal (LOS) is detected. Insertion of the AIS signal is delayed
approx. 50 ms.
Insertion criteria - Rx (demodulator):

140 Mb/s AIS is inserted under the following conditions:
a) Loss of pointer (LOP)
b) MS-AIS or AU-4 path AIS inserted
The 140 Mb/s AIS is inserted after any of the conditions stated above have been detected. Insertion of
the AIS signal is delayed approx. 100 ms.
Removal criteria :
140 Mb/s AIS is removed immediately after all insertion criteria are reset.
9.3 Alarms and monitoring
9.3.1 Alarms
All AIS conditions for the main channels are available on the built-in display.
Transmit side:
An AU-4 path AIS indicator will be shown on the display if AU-4 path AIS is inserted in the modulator-unit on a main
channel. Similarly, are MS-AIS shown if MS-AIS is inserted.
Receive side:
An AU-4 path AIS indicator will be shown on the display if AU-4 path AIS is inserted in the demodulator-unit for a
main channel. Similarly, are MS-AIS shown if MS-AIS is inserted.
H2580 33
9.3.2 LEDs
A yellow AIS LED is located on the front of the demodulator unit. This LED is lit when the main traffic at the
demodulator unit output port is carrying an AIS-signal.
10 - Radio Protection Switching (RPS)

10.1 General
This paragraph describes the main features of the Radio Protection Switching equipment. The very compact RPS-
equipment is integrated into the radio system and is controlled by the internal supervisory system. Remote control of
the RPS-system can be achieved through the TMN-interface. The RPS-system is configurable to handle system
configurations from 1+1 to 7+1. It is possible to disable the protection channel and use the system unprotected.
10.2 Baseband switching operations

The protection switching equipment automatically replaces a faulty channel by the standby channel at minor traffic
disturbance. All the channels have the facility to be disabled for maintenance purposes etc.
10.3 Switching capability

The radio protection switching equipment is capable to handle system configurations up to 7+1.
10.4 Priority of protection switching

The protection switching equipment is provided with facilities for setting the priority of any radio channel by means of
local or remote control through the built-in supervisory equipment. Indication of relevant status is provided, both for
the local control display and for remote supervision. Each radio channel can be set up with priority from 0 to 7. 7 is
the highest priority. 1 is the lowest priority. 0 is used to disable the channel from using the protection channel.
Default priority set in the factory is priority 1 on all channels.
10.5 Power distribution

The common units in a N+1 system (CMI splitter-unit and Relay-unit) are powered from two different supply
circuits.
10.6 Specification of the protection switching system

In order to facilitate switching without introducing additional bit-errors, a hitless switching system is provided.
10.6.1 Alignment specification

Automatic synchronization of the incoming digital signals is performed before switching takes place. The alignment is
based on bit-aligning of the STM-1-frames except for the RSOH-bytes which are ignored.
Dynamic range: ± 40 bits
10.6.2 Switching criteria
10.6.2.1 Continuity criteria

The continuity criteria are determined by the Out Of Frame (OOF) signal, and loss of RF identification.
Detection time : 5 x 125 µs = 625 µs
34 H2580
10.6.2.2 Quality criteria
A quality criterion is determined by overrun of preset limits. For a quality criterion, three thresholds are considered as
limits for switching operation. Each criterion can be set to different Bit Error Rate levels by switches in the
demodulator:
HBER - Bit Error Rate exceeds a value of approx. 10-4
LBER - Bit Error Rate exceeds a value of approx. 10-6
EW - Bit Error Rate exceeds a value of approx. 10-10
10.6.3 Switching operation time

The switching operation time will depend on system configuration. The total switching time in a N+1 system will be
larger than in a 1+1 system where the protection channel always is standby for the main channel. The alarm
detection time for L-BER and EW (Early Warning) will strongly depend on the severity of the channel disturbance.
L-BER and EW detection-time will be < 1 ms if a degradation that will cause a bit-error rate of 10-4 or worse is
detected. A table giving approximate detection times at different bit-error-rates is given below. The detection time
will depend on the selected threshold for the different criteria as shown in the table. If switching is initiated in both
directions at the same time this can increase the total switching operation time slightly.
Switching criteria detection time:

BER (Bit Error Rate) L- BER detection time EW detection time
1x10-3 0.05 - 0.4 ms 0.04 - 0.3 ms

1x10-4 0.2 - 1 ms 0.1 - 1 ms
1x10-5 0.5 - 3.5 ms 0.3 - 3 ms
1x10-6 2 - 10 ms 1 - 9 ms
1x10-7 not detected 4 - 30 ms
1x10-10 not detected not detected
N+1 Radio Protection Switching (RPS) H-BER L-BER EW

SW-criteria detection time: £ 1 ms 0.05 - 10 ms 0.04 - 200 ms
Communication and processing time: < 15 ms < 15 ms < 15 ms
Total switching operation time: < 16 ms 15 - 25 ms 15 -215 ms
1+1 Radio Protection Switching (RPS) H-BER L-BER EW

SW-criteria detection time: < 1 ms 0.05 - 10 ms 0.04 - 200 ms
Communication and processing time: < 2 ms < 2 ms < 2 ms
Total switching operation time: < 3 ms 2 - 12 ms 2 - 202 ms
H2580 35
11 - System supervisory characteristics
11.1 General
The SDH radio-relay equipment is capable of functioning as a Network Element (NE) in a managed SDH
transmission network. The radio equipment communicates to and can be controlled from an Element Manager
System. A display unit (built-in) provides control and alarm display facilities to enable the SDH-Radio to be managed
locally. The built-in display unit in the SDH-radio-relay equipment does also provide control and alarm display
facilities for a whole NERA radio network. Control and alarm display facilities for larger NERA SDH-network can be
achieved by interconnecting supervisory units through the built-in Network Interface (NI). A radio element/
subnetwork manager is available as an option to provide management facilities for a whole NERA radio network. See
a separate description for details of this manager. The radio element/subnetwork manager will use the Personal
Computer Interface described in section 11.2.2 to connect to the equipment.
11.2 TMN interface
11.2.1 General
The SDH radio-relay equipment can be connected to a TMN system either by connecting to the serial interfaces
provided by the supervisory system, or by connecting to the equipment alarms individually for equipment monitoring.
Two serial interfaces are built into the equipment in its standard configuration. One serial interface (SIC1) is normally
used to connect to TeleScada|TMN (NERA - TMN system). The connector for the SIC1-interface is located in the
service rack (EW53A, connector J15). Another serial interface (PC-interface) is also provided and normally used for
connection to an element or subnetwork manager (Network Element vieW - NEW). The connector for the PC-
interface is located on the front of the service rack below the display. In addititon to the two standard interfaces will a
Qx-interface be available through a Q-adapter as an option. The radio-relay equipment will eventually support the
management function for a Telecommunication Management Network as defined by ITU-T and ETSI through this Q-
adapter.
11.2.2 Serial interface options:

SIC1 (Proprietary interface to NERA TeleScada|TMN -equipment):
SIC1-protocol: NERA proprietary
Electrical Interface: RS-485 or RS-232
(selected by jumpers on the Supervisory unit)
Baudrate: 1.200-19.200 kbit/s async. or sync.
Location: Service-rack, connector J15 on EW53A
Personal Computer Interface:

Baudrate: 1.200 - 19.200 kbit/s asynchronous
Electrical interface: RS-232
11.2.3 Equipment alarm interface characteristics:

Optional Alarm Board for each radio rack (see also section 11.4.5):
Electrical interface: Opto coupler w/open collector
Location: Top of each radio-rack
Optional Alarm Board for the service rack (see also section 11.4.5):
Electrical interface: Opto coupler w/open collector
Location: Service-rack, connector - J14 on EW53A
36 H2580
11.3 Other communication interfaces
The Supervisory unit handles the different interfaces for communication with a Telecommunication Management
Network (TMN), a Network Interface (NI) for interconnection of supervisory boards, and internal interfaces for
communication towards the Alarm Collection Units (ACU), the optional Alarm Adapter Units (AAU) and the optional
opto-ACU. The characteristics for the communication interfaces are listed below:
11.3.1 Interfaces for external connection:

Network Interface (NI):
Baudrate: 1.200 - 19.200 kbit/s asynchronous or
192 kbit/s synchronous
11.3.2 Interfaces for internal connection:

Two Data Communication Channel (DCC) interfaces are available for remote
station communication:
Baudrate: 192 kbit/s synchronous
Electrical interface: CMOS
Peripheral Units Interface (PUI):

One party line serial bus
Baudrate: 187.5 kbit/s
Parallel Interface:
Two interrupt-driven 8-bit FIFO interfaces are provided. One is used for
communication between the Supervisory unit and the Radio Protection
Switching unit, and one is reserved for future system extensions.
H2580 37
11.4 Supervisory block diagram and units
The Supervisory system is built as shown in the block diagram.
The Supervisory unit will act as the main control unit in the equipment.
The Supervisory unit communicates with the other units in the radio relay equipment to exchange information
between the units.
An Alarm Collection Unit (ACU) is used to collect information from the other equipment units. An optional Alarm
Adapter unit is used for collecting external alarms and/or for remote control of external equipment. An opto-ACU
is included on the optional optical data-interface for monitoring and control of this interface. A built-in display or an
attached PC (optional) provides operator interface to the equipment.The supervisory systems on the different radio-
relay stations are exchanging information over the embedded communication channel DCCR (D1-D3). This means
that information from all stations that are connected within a section, or through the network interface, can be
displayed at one of the stations within the network.
RSOH
DCC DCC MS2
D1 - D3 D1 - D3
SCADA SWITCH CRIT

Qx MCF Para lle l Intf.
NI
SU PC RPS
R ELE C ONT R OL
REL AY &
RS-232
DRIV ER
Local LCD
Int alarms RMT CTRL
Qual B1-B2-B3 ACU AAU

SW
1 1 EXT ALM XSU ASF OUTPUT
Analog inp
CONTROL
SIGNALS Part of Demodulator
Int alarms RMT CTRL

R SOH : R ege nerato r Sectio n Ove rh ead
Qual B1-B2-B3 ACU AAU
EXT ALM DISTR. D C C: D ata Co mmu nicatio n C han nel
Analog inp N 2
Internal bus A SF: Alig nmen t S witch F un ction
R PS: R ad io P ro tectio n U n it A AU : Ala rm A d apter U nit

M S2: M ed ia Spe cific b yte XSU : XM TR S witch U nit
A CU : A la rm Co llect ion U nit SU : Su perviso ry U nit
FILE: ss s.drw
N I: N etwo rk Interface
Fig. 11.1 Supervisory and switching system
11.4.1 Supervisory Unit (SU)

The supervisory system provides operational control of the system configurations and the Radio Protection Switching
(RPS). The supervisory unit is built on a single board and is located in the service rack. One supervisory unit is
serving a complete terminal- or repeater- station independent of configuration.
11.4.2 Display Unit

The Display Unit acts as a front panel for both the Supervisory system and the Radio Protection Switching system.
The Display Unit is equipped with LEDs indicating main alarms for each channel, a graphics LCD and a keyboard for
entering commands. The Display Unit is the local operators interface to control and display all the information
available in the radio-relay equipment. The information is made available by using arrows to select different options
in the menus. The Display Unit is located in the service rack.
38 H2580
11.4.3 Alarm Collection Unit (ACU)
One Alarm Collection Unit is required for each radio channel and one for the service rack. The ACU is
communicating with the Supervisory Unit on an internal communication channel. The ACU has three main functions;
collection of equipment alarms
perform analogue measurements from internal monitoring points
calculate performance data
More details are given in section 13, system monitoring and alarm.
11.4.4 Alarm Adapter Unit (AAU)

The Alarm Adapter Unit is an optional unit used for collection of external alarms, and remote control of external
equipment. The AAU is communicating with the Supervisory-unit on an internal communication channel, and is
located in the service rack.
Characteristics of the AAU:
Number of external alarm inputs: 32
Electrical interface of external alarm input: TTL or Current Loop
Number of remote control outputs: 8
Electrical interface of remote control output: Latched or pulsed relay
Maximum number of AAUs per station: 2
11.4.5 Alarm Board

The alarm board is an optional unit used to provide individual alarm connections from the radio-relay equipment to
external supervisory systems. The equipment alarms can be grouped in different ways (by straps on the alarm board)
to the available alarm outputs. One alarm board can be provided per radio channel and one for the service rack.
Output interface is optocoupler or relay contact. The alarm output is available through a 37-pin D-sub female
connector at the top of each rack (see section 13.2).
Output characteristics for the NPN optocoupler:

Both Collector and Emitter are floating and are separately available for each alarm. When an alarm is activated the
optocoupler will be closed (conducting).
VCEO max: 70 Volt
IC max: 15 mA
VCE: £ 2 Volt for IC £ 12 mA
Isolation voltage: 2500 Vrms
VCE(SAT) £ 0.2 Volt for IC = 1 mA
ICEO < 1 µA for VCE = 40 Volt
Output characteristics for the relays:

Relays are used for the main alarm and the power supply alarm. The relays are normally activated (to give alarm if
power disappears).
The MAIN ALARM has all three relay contacts available. Normally open or normally closed can then be chosen by
selecting the appropriate contact pins.
The POWER SUPPLY ALARM have only two relay contacts available. Normally open or normally closed can be
selected by a strap on the alarm board.
H2580 39
Relay characteristics:
Contacts: Two form C contacts
Contact resistance: < 5 mW after 200.000 operations
Maximum switching power: 100 VDC, 0.3 A or 100 VAC, 0.5 A
Alarm Overview:
Alarm Connector pin no: Alarm outputs Electrical interface

Number
1 1&2 XMTR_GRP_ALM Open collector / Optocoupler

2 3&4 RCVR_GRP_ALM Open collector / Optocoupler
3 5&6 MOD_ALM Open collector / Optocoupler
4 7&8 DEMOD_ALM Open collector / Optocoupler
5 15 & 16 RF_ID_ALM Open collector / Optocoupler

6 9 & 10 CMI_SPLIT_ALM Open collector / Optocoupler
7 11 & 12 H_BER_SEC_ALM Open collector / Optocoupler
8 13 & 14 L_BER_SEC_IND Open collector / Optocoupler
9 19 & 20 AIS_XMTR_ALM Open collector / Optocoupler

10 21 & 22 AIS_RCVR_ALM Open collector / Optocoupler
11 25 & 26 2M_WAY_ALM Open collector / Optocoupler
12 17 & 18 PWR_SPLY_ALM Relay
13 35,36 & 37 MAIN_ALM Relay
Table 11.1 Alarm board, radio rack
Alarm Connector Alarm outputs Alarm interface

Number J14 pin no:
1 1&2 64 kbit/s ADAPTER_ALM Open collector / Optocoupler

2 3&4 XMTR_SW_ALM Open collector / Optocoupler
3 5&6 SUPERVISORY_UNIT_ALM Open collector / Optocoupler
4 7&8 PWR_SPLY_ALM Relay
5 9 & 10 RCVR_DISTR_ALM Open collector / Optocoupler

6 11 & 12 RSOH_ADAPTER_ALM Open collector / Optocoupler
7 13 & 14 MSOH_ADAPTER_ALM Open collector / Optocoupler
8 15 & 16 SERVICE_TEL_ALM Open collector / Optocoupler
9 17 & 18 AAU_ALM Open collector / Optocoupler

10 19 & 20 RPS_ALM Open collector / Optocoupler
11 21 & 22 SYNCH_UNIT/TEST_MODE_ALM Open collector / Optocoupler
12 23,24 & 25 MAIN_ALM Relay
Table 11.2 Alarm board, service rack
40 H2580
12 - Branching characteristics
12.1 RF channel branching unit
For operation on a common branching system, the minimum channel separation and minimum separation between
transmitter and receiver should be as specified in the ITU-R radio frequency channel plans (refer to section 2.2).
12.1.1 RF-filters and branching system

The RF channel filters are connected to the antenna through a branching system consisting of waveguide and
circulators. The RF-filters and branching system are located within the radio-rack.
12.1.2 Insertion loss of branching system

Insertion loss per hop, excluding RF filter loss (B-B):
1+1 system 1.2 dB 1.2 dB 1.2 dB 1.2 dB 1.2 dB 1.2 dB 1.5 dB 1.5 dB
Co-channel configuration. Insertion loss per hop, excluding RF filter loss (B-B):
Equipment Code: NL294
1+1 system 8.5 dB

2+1 system 8.9 dB
3+1 system 9.3 dB
12.1.3 Circulator attenuatioEquipment Code:

Attenuation due to circulator between transmit and receive channels connected to the same antenna:
Attenuation ³30 dB ³30 dB ³30 dB ³30 dB ³30 dB ³30 dB ³27 dB ³27 dB
12.1.4 Circulator insertion loss

Insertion loss <0.2 dB <0.2 dB <0.2 dB <0.2 dB <0.2 dB <0.2 dB <0.25 dB <0.25 dB
H2580 41
12.2 Antenna ports
Separate antenna ports for receiver and transmitter are optionally available.
12.2.1 VSWR at antenna port (point C’C)

VSWR at antenna port at the channel frequencies: ≤ 1.11
12.2.2 Antenna port arrangements

An example of a branching arrangement at the top of the equipment is shown in the figure below. The type of
waveguide flanges is given in section 2.7. Minimum required height for mounting the equipment is approximately
2.40 m (0.20 m above top of the equipment rack) dependent on type of bend used and how the waveguides are
installed. The H-bends shown in the figure below are optional waveguide-units and are not part of our standard
configuration.
PDR WAVEGUIDE
FLANGES
MAIN
CHANNEL SPACE DIV.
CHANNEL
DIGITAL RADIO RELAY DIGITAL RADIO RELAY DIGITAL RADIO RELAY

SDH - STM-1 SDH - STM-1 SDH - STM-1
- NERA - - NERA - - NERA -
Branching arrangements, front view
Branching arrangements, top view
Figure 12.1 Branching arrangement above the slim-racks
42 H2580
13 - SYSTEM MONITORING AND ALARMS

13.1 Unit alarms and indicators
The Alarm Collection Unit (ACU) collects all information about internal alarms, transmission quality and meter
readings from the radio-relay equipment. The information can be shown on the built-in display (LCD), or as an
option on an Element Manager (PC). The alarms are accessible through the serial TMN-connection and/or through
the optional alarm board described in section 11.4.5.
13.1.1 XMTR group alarms, indicators and test points
Signal Name Signal Description: Comments:
LO MON (J4) Local oscillator frequency SMA-connector on front of the XMTR group
RF MON (J3) Output RF power at point A SMA-connector on front of the XMTR group, -30
dB coupling
ALM XMTR-group alarm. This is an ored
alarm of RF_PWR_ALM, IF_INP_ALM
and LO_ALM Red LED on front of the XMTR group
POWER-OUT Alarm if output power is reduced 3-6 dB

below nominal value connected to the ACU
IF-INPUT Alarm if IF input is 3-6 dB below

nominal value connected to the ACU
LO Alarm if LO level is 3-6 dB below

nominal value or PLL out of lock connected to the ACU
TX_LO_VAR Measured LO varactor voltage connected to the ACU
RF OUTPUT LEVEL Measured output power at point A connected to the ACU and monitor connector J3 pin 7.
+9.4 V Measured voltage level on +9.4V,

XMTR PWR supply connected to the ACU
-5 V Measured voltage level on -5.0V,

XMTR PWR supply connected to the ACU
PWR OUT (nom, -3dB, Indicator on TX front indicating power

-6dB or -10dB) output setting in the TX-group Green LED on front of TX-group
H2580 43
13.1.2 RCVR group alarms, indicators and test points
LO MON (J2) Local oscillator frequency SMA-connector on front of the RCVR group
IF TEST (J3) IF-output test signal, -20 dB coupled 1.6/5.6mm-coaxial connector on front of the
RCVR group
RF ALM MAIN RCVR-group alarm. This is an ored alarm of
RF_INP_ALM_MAIN and LO-ALM Red LED on front of the RCVR-group
RF ALM SPACE RCVR-group alarm. This is an ored alarm of Red LED on front of the Space-diversity RCVR-
RF_INP_ALM_SPACE and LO_ALM group
LOW_LVL_MAIN Input power alarm for main channel connected to the ACU
LOW_LVL_SPACE Input power alarm for space diversity channel connected to the ACU
LO Alarm for low LO-level or PLL out of lock connected to the ACU
RX_LO_VAR Measured LO-varactor voltage connected to the ACU
RF INPUT MAIN Measured input power, main channel connected to the ACU and monitor connector J3
pin 3.
RF INPUT SPACE Measured input power, space diversity channel connected to the ACU and monitor connector J3
pin 5.
SPACE-DIV Alarm from the space diversity combiner connected to the ACU
13.1.3 Modulator alarms, indicators and test points
MOD-UNIT-ALM LOS + LOF1 + 2M-SYNC + 311M-PLL +

2M-WAY + TRELLIS + IF Red LED on front of the modulator unit
LOS Alarm indicating loss of CMI-data input

(140 Mb/s or 155 Mb/s) connected to the ACU
LOF1 Loss of frame on STM-1 main data input connected to the ACU
MS-AIS MS_AIS detected on STM-1 main data input connected to the ACU
MS-AIS-INS MS_AIS inserted on STM-1 data output connected to the ACU
MS-RDI MS_RDI detected on STM-1 main data input connected to the ACU
AIS-INP-140 AIS detected on 140 Mb/s data input -
AU-PATH-AIS AU path AIS detected on STM-1 data input connected to the ACU
LOP Loss of pointer on STM-1 main data input connected to the ACU
311M-PLL Alarm indicating 311 MHz VCXO out of lock connected to the ACU
TRELLIS Alarm indicating Trellis PLL out of lock connected to the ACU
IF Alarm indicating IF-output is missing connected to the ACU
2M-WAY Alarm indicating 2 Mb/s traffic is not present

(input alarm) connected to the ACU
2M-SYNC Alarm indicating 2 MHz external sync. is not

present connected to the ACU
XMTRSW-ALM-MOD Alarm to RPS for use to control the XMTR-

switch (LOS + LOF1 + 311M-PLL) connected to the RPS Unit
IF TEST (J3) -10 dB test-point on front of demodulator-unit 1.6/5.6mm-coaxial connector on front of the
demodulator-unit
44 H2580
13.1.4 Demodulator alarms, indicators and test points
LEDs:
Signal Name: Signal Description: Comments:
DEMOD-UNIT-ALM IF-INP + SYNCL-VIT (128TCM) + LOF1 +

LOF2 + ALIGN-PLL + CMI-OUT) Red LED on front of the demodulator unit
AIS AIS-indicator showing there is AIS inserted

on the traffic output port. See also section 9. Yellow LED on front of the demodulator unit
HIGH BER Indicator for excessive BER . Calculations Red LED on front of the demodulator unit and
based on Viterbi error transitions also connected to the ACU
LOW BER Indicator for LOW BER. Calculations Yellow LED on front of the demodulator unit
based on Viterbi error transitions and also connected to the ACU
Alarms:
IF-INP Alarm indicating IF input is missing connected to the ACU

RF-ID Alarm indicating that wrong RF-identifier is received connected to the ACU
SYNCL-VIT (128TCM) Alarm indicating Viterbi-decoder is out of sync

(4D-128TCM). connected to the ACU
HBER-HOP Indicator for BER ³ 10-3, based on Viterbi error Red LED on front of the demod-unit
transitions and also connected to the ACU
HBER-SEC Alarm to ACU (OR-ed HBER-HOP for last and

previous hops) connected to the ACU
LBER-HOP Indicator for BER ³ 10-6, based on Viterbi error Yellow LED on front of the
transitions demod-unit and also connected to the
ACU
LBER-SEC Indicator to ACU and RPS used for error-less switch

control. (LBER-HOP + SEC-LBER-O) connected to the ACU and RPS
EWBER-HOP Early Warning based on Viterbi error transitions

(BER ³ 10-10) connected to the ACU and RPS
140/155Mb/s Signal indicating interface-setting in the demodulator connected to the ACU

LOF1 Loss of frame detected on received traffic connected to the ACU
LOP_DEM Loss of pointer detected on received traffic connected to the ACU
SYNCL-SEC Alarm indicating sync.loss has occurred within the
radio protection switching section. (OR-ed OOF1 +
SEC-SYNC-O + RF-ID for last and previous hops) connected to the ACU
ALIGN-PLL Alarm indicating PLL for errorless switch is out of lock connected to the ACU
LOF2 Data from protection channel is missing (to alignment) connected to the ACU
EXT-SY Signal indicating that the received traffic is synchronized

to an external 2MHz clock connected to the ACU
MS-RDI MS-RDI detected on received traffic connected to the ACU
MS-AIS-INS MS-AIS inserted in the demodulator connected to the ACU
MS-AIS MS-AIS detected on received traffic connected to the ACU
AU-PATH-AIS AU path AIS detected on received traffic connected to the ACU
AIS-OUT-140 AIS on 140 Mb/s data output connected to the ACU
H2580 45
CMI-OUT Alarm indicating PLL (311/280 MHz VCXO) is out

of lock, or CMI-data output is missing connected to the ACU
2M-WAY Alarm indicating 2 Mb/s output is missing or PLL out

of lock connected to the ACU
2M-WAY-AIS Signal indicating 2 Mb/s output is carrying AIS connected to the ACU
RELAY-ALM LOF2 + ALIGN-PLL + CMI-OUT connected to the RPS
SYNCL-ALM HBER-HOP + SEC-HBER-O + SYNCL-VIT

(128TCM) + SYNCL-SEC connected to the RPS
ALIGN-IND Signal indicating that protection traffic is aligned to

main traffic connected to the RPS
13.1.5 CMI splitter alarms and indicators
CMI-SPL-DTA Alarm when data input to the CMI splitter is missing connected to the ACU and the RPS
13.1.6 Power-supply alarms and indicators
POWER SUPPLY IND. Power supply status indicator Green LED when OK
POWER ALARM Power supply alarm Red LED on the unit front, and also
connected to the ACU
+15.0 V Nominal and measured +15.0 V supply level connected to the ACU
-15.0 V Nominal and measured -15.0 V supply level connected to the ACU
+5.0 V Nominal and measured +5.0 V supply level connected to the ACU
-5.2 V Nominal and measured -5.2 V supply level connected to the ACU
13.1.7 Radio Protection Switching (RPS) alarms and indicators
RPS_UNIT_ALM Main alarm from the RPS unit connected to the ACU
46 H2580
13.1.8 XMTR-Switch-Unit (XSU) alarms and indicators
UNIT ALM Main alarm from the XMTR switch unit Red LED on the unit front, and also
AIS INP Signal indicating that incoming traffic
is carrying AIS Yellow LED on the unit front
SEL 140 Signal indicating 140-155 Mb/s mapping

is done in the XMTR switch. Yellow LED on the unit front
HITL SW 7-segment display indicating which channel

is using the protection channel 7-segment display on the unit front
REL SW 7-segment display indicating which channel

is using the protection channel through the
relay switch on the transmit side. 7-segment display on the unit front
13.1.9 Receiver data distribution unit (RDU) alarms and indicators
Signal Name: Signal Description: Comments

:
UNIT ALM Main alarm from the Data distribution unit Red LED on the unit front, and also
AIS 140 Mb/s Signal indicating that outgoing 140 Mb/s
is carrying AIS Yellow LED on the unit front
SEL 140 Signal indicating 155-140 Mb/s demapping

is done in the distribution unit. Used when
140 Mb/s signal is extracted through the data
distribution unit. Yellow LED on the unit front
13.1.10 Supervisory Unit (SU) alarms and indicators
UNIT ALARM Signal generated in the Supervisory Unit

if the unit fails. Connected to the Alarm board in the
service rack
TEST_MODE Test mode indicator from the SU-unit.
Indicating that the manual switch is operated. Connected to the Alarm board in the
service rack
13.1.11 Alarm Collection Unit (ACU) alarms and indicators
ACU malfunction detected by SU based on

communication failure between ACU and SU. SU creates ACU alarm
H2580 47
13.1.12 RSOH-adapter alarms and indicators
RSOH adapter Main alarm from the RSOH-adapter connected to the ACU
13.1.13 Optional unit alarms and indicators
13.1.13.1 Alarm Adapter Unit (AAU) alarms and indicators
AAU Main alarm from the AAU-unit connected to the ACU
13.1.13.2 Service telephone alarms and indicators
Service telephone Main alarm from the service telephone unit connected to the ACU
13.1.13.3 PABX-adapter alarms and indicators
PABX adapter Main alarm from the PABX adapter. connected to the ACU
13.1.13.4 MSOH-adapter alarms and indicators
MSOH adapter Main alarm from the MSOH-adapter connected to the ACU
13.1.13.5 Synchronization unit alarms and indicators
SYNC-UNIT Main alarm from the Synchronization unit

(XMTR1 + XMTR2 + RCVR1 + RCVR2 + PLL) Red LED on the front of the unit
XMTR1 Alarm indicating that XMTR1-clock is missing Connected to the ACU

XMTR2 Alarm indicating that XMTR2-clock is missing Connected to the ACU
RCVR1 Alarm indicating that RCVR1-clock is missing Connected to the ACU
RCVR2 Alarm indicating that RCVR2-clock is missing Connected to the ACU
PLL Alarm indicating 2 MHz PLL out of lock Connected to the ACU
48 H2580
13.1.13.6 64 kbit/s-Adapter alarms and indicators

64 kb adapter Main alarm from the 64 kbit/s adapter Connected to the ACU
13.2 Monitor connectors
13.2.1 Parallel alarm connector

An optional alarm board for parallel alarms is available for each rack. In the radio rack, the alarms from the alarm
board are connected to a 37-pins D-sub-female connector which is located at the top of each radio rack. In the
service rack, the alarms from the alarm board are connected to a 25-pins D-sub-female connector which is located in
the middle of the service rack (connector J14).
Radio rack connector (37-pins D-sub-female):
pin no 1: XMTR-group-alarm -collector

pin no 2: XMTR-group-alarm -emitter
pin no 3: RCVR-group-alarm -collector
pin no 4: RCVR-group-alarm -emitter
pin no 5: Modulator-alarm -collector
pin no 6: Modulator-alarm -emitter
pin no 7: Demodulator-alarm -collector
pin no 8: Demodulator-alarm -emitter
pin no 9: CMI-splitter-alarm -collector
pin no 10: CMI-splitter-alarm -emitter
pin no 11: High-BER-alarm -collector
pin no 12: High-BER-alarm -emitter
pin no 13: Low-BER-indicator -collector
pin no 14: Low-BER-indicator -emitter
Note 1: pin no 15: RF-identifier-alarm -collector
Note 1: pin no 16: RF-identifier-alarm -emitter
pin no 17: Power-supply-alarm -Relay - CENTRE
Note 2: pin no 18: Power-supply-alarm -Relay - NO/NC
pin no 19: AIS XMTR -collector
pin no 20: AIS XMTR -emitter
pin no 21: AIS RCVR -collector
pin no 22: AIS RCVR -emitter
pin no 23: Protection switch status -collector
pin no 24: Protection switch status -emitter
pin no 25: 2Mb/s-wayside-alarm -collector
pin no 26: 2Mb/s-wayside-alarm -emitter
pin no 27: external-alarm-input -standard TTL-input
(used on the hot-standby-controller to include an alarm from external equipment)
pin no 28: GROUND
pin no 29: RF-input-level main channel
pin no 30: GROUND
pin no 31: RF-input-level space diversity channel
pin no 32: GROUND
pin no 33: RF-output-level
pin no 34: GROUND
pin no 35: Main alarm -Relay - NORMAL OPEN
pin no 36: Main alarm -Relay - CENTRE
pin no 37: Main alarm -Relay - NORMAL CLOSED
H2580 49
Service rack connector - J14 (25-pins D-sub-female):
pin no 1: 64 kbit/s-adapter-alarm -collector

pin no 2: 64 kbit/s-adapter-alarm -emitter
pin no 3: XMTR-switch-alarm -collector
pin no 4: XMTR-switch-alarm -emitter
pin no 5: Supervisory-unit-alarm -collector
pin no 6: Supervisory-unit-alarm -emitter
pin no 7: Power-supply-alarm -Relay - CENTRE
Note 2: pin no 8: Power-supply-alarm -Relay - NO/NC
pin no 9: RCVR-distribution-alarm -collector
pin no 10: RCVR-distribution-alarm -emitter
pin no 11: RSOH-adapter-alarm -collector
pin no 12: RSOH-adapter-alarm -emitter
pin no 13: MSOH-adapter-alarm -collector
pin no 14: MSOH-adapter-alarm -emitter
pin no 15: Service telephone-alarm -collector
pin no 16: Service telephone-alarm -emitter
pin no 17: Alarm Adapter Unit-alarm -collector
pin no 18: Alarm Adapter Unit-alarm -emitter
pin no 19: RPS-unit-alarm -collector
pin no 20: RPS-unit-alarm -emitter
Note 3: pin no 21: Synch-unit/Test mode -collector
Note 3: pin no 22: Synch-unit/Test mode -emitter
pin no 23: Main alarm -Relay - NORMAL OPEN
pin no 24: Main alarm -Relay - CENTRE
pin no 25: Main alarm -Relay - NORMAL CLOSED
Note 1: Alternatively, these two pins (p15 and p16) can be configured as two alarm inputs similar
to pin 27 (standard TTL-input). Configuration is done on the Alarm Board.
Note 2: NO (Normally Open) or NC (Normally Closed) is selected by a strap on the Alarm Board
(EJ163A/EJ164A).
Note 3: Sync-unit alarm or Test mode alarm can be selected by a strap on the Alarm Board
EJ164A
13.2.2 Analogue monitor connector - J3
A 9-pins D-sub-female connector is mounted in the middle of each radio rack for monitoring of some equipment
voltage levels:
pin no 1: Main supply -15 Volt

pin no 2: Main supply +15 Volt
pin no 3: RF-input level main channel
pin no 4: Main supply -5.2 Volt
pin no 5: RF-input level space diversity channel
pin no 6: Main supply +5 Volt
pin no 7: RF-output level
pin no 8: Transmitter power supply -5 Volt
pin no 9: Transmitter power supply +9.4 Volt
Body: GROUND
50 H2580
EQUIPMENT DESCRIPTION
NL290 - Family
4 - 13GHz
H2591 Rev. H
© Nera AS
Nera AS
2 L 29005 Rev.H 04.01.96 FS/Oeg

Nera AS
Table of Contents
1.0 GENERAL DESCRIPTION .................................................. 5

1.1 Frequency bands. ...................................................... 6
1.2 Mechanical dimensions.............................................. 6
1.3 Power consumption. .................................................. 7
2.0 System configuration ................................................. 7

2.1 Radio channel arrangements ..................................... 7
2.1.1 Alternated channel arrangements .............................. 7
2.1.2 Co-channel arrangements ......................................... 9
2.2 Station configuration .................................................. 11
2.2.1 Terminal station .......................................................... 11
2.2.2 Repeater station......................................................... 11
2.3 Line interface ............................................................. 13
2.3.1 PDH / SDH interface .................................................. 13
2.3.2 Electrical interface...................................................... 13
2.4 Radio Protection Switching System ........................... 13
2.4.1 Radio Protection Switching (RPS) Unit ...................... 13
2.4.2 Alignment Switch Function (ASF) .............................. 14
2.4.3 RCVR Data Distrib. Unit (RDDU) ............................... 14
2.4.4 Relay Unit (RU) .......................................................... 14
2.4.5 XMTR Switch Unit (XSU) ........................................... 14
2.4.6 Switching criteria ....................................................... 14
2.5 Automatic Transmitter Power Control (ATPC)............ 14
2.5.1 General ...................................................................... 14
2.5.2 Block diagram, functional description ........................ 14
2.6 Section termination (MST/RST) ................................. 15
2.7 System Synchronization ............................................ 15
2.8 Service and wayside traffic ........................................ 16
2.8.1 Section Overhead Configuration ................................ 16
2.8.2 Service telephone ...................................................... 17
2.8.2.1 PABX Adapter ............................................................ 17
2.8.3 Wayside traffic ............................................................ 17
2.8.3.1 2 Mb/s data ................................................................ 17
2.8.3.2 64 kb/s data ............................................................... 17
2.8.4 MSOH adapter ........................................................... 18
2.9.1 General ...................................................................... 19
2.9.2 Network Element vieW (NEW) ................................... 19
2.9.3 TMN Connection ........................................................ 20
2.9.4 Built-in Management .................................................. 21
2.9.4.1 Supervisory unit (SU) ................................................ 21
2.9.4.2 Alarm Collection Unit (ACU) ...................................... 21
2.9.4.3 Alarm Adapter Unit (AAU) .......................................... 21
2.9.5 External connections .................................................. 21
3
L 29005 Rev.H 04.01.96 FS/Oeg
Nera AS
3.0 Block Description........................................................ 22
3.1 Baseband & Modem Equipment ................................ 22
3.1.1 Modulator Unit............................................................ 23
3.1.1.1 Main functions of the mod. unit .................................. 23
3.1.2 Demodulator Unit, without XPIC ............................... 24
3.1.2.1 Main function of the Demod. Unit............................... 25
3.1.3 Demodulator Unit with XPIC ..................................... 25
3.2 Radio Equipment ....................................................... 26
3.2.1 Transmitter Group ...................................................... 26
3.2.1.1 IF Predistortion........................................................... 26
3.2.1.2 Up-Converter ............................................................. 27
3.2.1.3 Power Amplifier .......................................................... 27
3.2.1.4 Oscillator .................................................................... 28
3.2.2 Receiver Group .......................................................... 29
3.2.2.1 LNA & Mixer Unit ....................................................... 29
3.2.2.2 LO Splitter & Phase Shift Unit .................................... 29
3.2.2.3 Space Diversity Combiner ......................................... 30
2.1.2.3.2 Block Diagram ............................................................ 30
3.2.2.3.1 Combining Algorithm .................................................. 30
3.2.2.4 Amplifier, IF & Filter, BP ............................................. 31
3.2.2.5 ATPC .......................................................................... 32
3.2.3 Branching ................................................................... 33
3.2.3.1 Channel filter .............................................................. 34
3.3 Power Supply ............................................................. 34
3.3.1 General ...................................................................... 34
4.0 LIST OF ABBREVIATIONS .................................... 35
4 L 29005 Rev.H 04.01.96 FS/Oeg

Nera AS
1.0 GENERAL DESCRIPTION
The 140/155 Mb/s STM-1 radio-relay equipment is The modulation technique is 4D-128TCM, alterna-
designed to operate in frequency bands with 28MHz tively 2D-64TCM (Trellis Coded Modulation).
to 40MHz channel spacing, according to ITU-R Rec-
ommendations. Each radio can carry one STM-1- The design combines recent achievements in micro-
signal which can be utilized in several ways. A syn- wave component technology and state of the art VLSI
chronous multiplexer for mapping 139.264 Mb/s into circuits based on silicon compiler methodology to
the STM-1 frame is built into the equipment. produce high reliability equipment.
Adaptive techniques involving digital transversal
equalizer and space diversity reception are used to
counteract multipath propagation. The transmission
quality is improved by the strong Viterbi error-correc-
tion algorithm realised in the Trellis-decoder circuit.
The Residual Bit Error Rate is lower than 10-12.
Built-in supervision enables system performance and
availability data to be recorded for both local and
remote stations.
The equipment is designed to meet the various sys-

tem configurations required in large telecommunica-
tion networks. High degree of flexibility with respect to
choice of system configuration is therefore empha-
sized and the following solutions are accounted for:
ü Alternated or co-channel dual polarized

system configuration.
ü N+1 terminal stations prepared for easy
future expansion possibilities.
ü RS or MS-termination for flexible use in
different network configurations.
ü Electrical STM-1 signal interface.
ü Space diversity circuits integrated in the
main receiver (option).
ü Easy conversion from 140 Mb/s PDH
to 155 Mb/s SDH
ü ATPC integrated (option).
ü XPIC integrated (option).
In N+1 Radio Protection Switching configuration, up

to 8 RF-channels can be connected to the same
antenna system with maximum 4 RF-channels on
each antenna polarization (6 RF-channels in 11 GHz
system).
The rack layout is shown in figure 1. One rack

contains the transmitter, receiver, modem and base-
band circuits associated with one bidirectional RF-
channel.
When space diversity reception is required, this can
be accomplished within the same rack by using dual
receivers. One service rack houses the protection
switching system, the service telephones, adapters to
access section overhead, and the internal supervi-
sory system.
Fig.1 Rack layout, 1+1 Terminal

5
L 29005 Rev.H 04.01.96 FS/Oeg
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1.1 Frequency bands.
The following equipment codes are used for the equipment:
Equipment Freq. Frequency ITU-R Centre Channel Tx-Rx spacing
code band (GHz) frequency spacing

NL294 4 GHz 3.6 - 4.2 Rec. 635-2 3890 MHz 40 MHz 80 MHz
3.8 - 4.2 Rec. 382-6 4003.5 MHz 29 MHz 68 MHz
NL293 5 GHz 4.4 - 5.0 Doc. 9/148-E 4700 MHz 30 or 40 MHz 60 MHz
NL290 L6 GHz 5.9 - 6.4 Rec. 383-5 6175 MHz 29.65 MHz 44.49 MHz
NL295 U6 GHz 6.4 - 7.1 Rec. 384-5 6770 MHz 40 MHz 60 MHz
7.4 - 7.9 UK band 7662.5 MHz 245 MHz
NL292 8 GHz 7.7 - 8.3 Rec. 386-4 8000 MHz 29.65 MHz 103.7 MHz
Rec. 387-6 . 11200 MHz 130 MHz
Annex 2
1.2 Mechanical dimensions.

The equipment is based on modular principles allow- System Equipment
ing various system configurations using the basic Weight Rack width
building blocks. The building blocks are mounted in (kg) (mm)
rigid slim-racks which requires front access only.
Dimensions of the racks are (Height x Width x Depth) 1+0 / 1+0 Terminal 80 240
: 2200 mm x 120 mm x 225 mm. Each slim-rack (120 Repeater 130 360
mm) contains one bi-directional radio channel, and
the common service functions for all radio channels 1+1 / 2+0 Terminal 130 360
are located in one slim-rack. See table below for Repeater 230 600
dimensions and weight of various systems. The
equipment is packed in plywood boxes and a maxi- 2+1 / 3+0 Terminal 180 480
Repeater 330 840
mum of 5 slim-racks are packed in each box. The
transmitter and receiver units are extracted and 3+1 / 4+0 Terminal 230 600
packed in a separate box. Repeater 430 1080
When co-channel arrangement is used, the co-chan- 4+1 / 5+0 Terminal 280 720
nels are arranged in a separate system. Interconnec- Repeater 530 1320
tion of the two systems towards the antenna is done
by waveguide components above the racks (see fig. 5+1 / 6+0 Terminal 330 840
8). Repeater 630 1560
6+1 / 7+0 Terminal 380 960

Repeater 730 1800
7+1 / 8+0 Terminal 430 1080

Repeater 830 2040
6 L 29005 Rev.H 04.01.96 FS/Oeg

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separate power feed circuit which supplies a bi-
1.3 Power consumption. directional radio channel or the common service func-
The radio equipment can operate from 48 or 24 Volt tions. Each circuit should be equipped with a 10 A slow
DC power supply. The equipment rack should be blowing circuit breaker. The total power consumption
grounded to the positive pole. Each slim-line has a from the supply voltage is shown below.
Power Consumption vs. System configuration (Watt)

Basic radio system * 1+0 1+1 2+1 3+1 4+1 5+1 6+1 7+1
2+0 3+0 4+0 5+0 6+0 7+0 8+0
Terminal 144 285 409 533 656 780 904 1028
Repeater 265 510 754 999 1243 1488 1732 1977
Service units Watt * Add addition common service units on the left
Service telephone 3 For Space diversity systems, add 6 Watt per channel
Adapter 64 kb/s 1.5
Sync. Unit 2 MHz 1 Hot Stand-by has the same power consumption as
Alarm Adapter Unit 2 a 1+1/2+0 system
Adapter MSOH 1.5
2.1 Radio channel arrangements
2.1.1 Alternated channel

arrangements
The various radio configurations are frequency diver- unswitched (2+0) baseband interface. Each of these
sity n+1 (1 ≤ n ≤ 7), unprotected frequency diversity systems can also have space diversity receivers
n+0 (1 ≤ n ≤ 8) and Hot Stand-by (1+1) systems. The included. See block diagrams below for details of the
Hot Stand-by system may in special cases have an most common radio configurations.
C MI
ch n SPLT R
M OD XM T R ch n M OD XMT R
C MI
ch 1 SPLT R
M OD XM T R ch 2 M OD XMT R
C MI XM T R
ch P SPLT R SW .
M OD XM T R ch 1 M OD XMT R
SER VICE SER VICE

R PS
U NIT S U NIT S
RC VR DE- DE-
ch P R ELAY
D IST . M OD
RC VR ch 1 M OD
RC VR
DE- DE-
ch 1 R ELAY
M OD
RC VR ch 2 M OD
RC VR
DE- DE-
ch n R ELAY
M OD
RC VR ch n M OD
RC VR
n+ 1 S ystem n+0 S ystem
Figure 2 Figure 3
7
L 29005 Rev.H 04.01.96 FS/Oeg
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T x side Tx c h 7
M AIN
Tx c h 6
SP. DIV
Tx c h 5
D IV ER SIT Y
RC VR
Tx c h 4
SP. DIV
RC VR
Tx c h 3
Rx
Tx c h 2 ch 7 -4 P art of an tenn a
Tx c h 1
S pace D iversity S ystem (1+ 1)
Tx c h P
Figure 4
D ual poliarised
branching system Rx
7+1 T x side sh ow n ch 3 -P
Figure 5
Tx
CMI
M AIN
ch 1 SPLT R
MO D XM TR
A lt.1
MO D XM TR
D E-
R C VR
MO D
D IVERS ITY
SER VIC E
R PS
U N IT S DE -
ch 1 R ELAY
MO D
R C VR
D E-
RC VR
MO D
H o t S ta nd -by with Sp a ce D ive rsity Syste m

D E-
ch 1 RE LA Y
MO D
RC VR
Tx
M AIN
H ot Stan d -b y System A lt.2
D E- SP.D IV
DIV ERSITY
MO D R CVR
Figure 6 DE - SP.D IV
ch 1 R ELAY
MO D R CVR
Figure 7
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2.1.2 Co-channel arrangements Rack layout
More bandwidth efficient transmission is obtained by As channels with the same frequency are interrupted
the use of Co-Channel Dual Polarized (CCDP) sys- by fading at the same time, the co-channels have their
tems. The CCDP system is transmitting independent own protection channel and Radio Protection Switch-
signals with the same RF-frequency on two different ing (RPS), see fig. 9 for rack layout.
polarizations, which will double the efficiency com-
pared to a conventional Adjacent Channel Dual Po- Branching
larization (ACDP) system. Both signals are decoupled From fig. 8 it can be seen that power splitters and
by the Cross Polarization Discrimination (XPD) of the combiners are included in the system. This is a
receive antenna. Due to propagation effects on the consequence of the absence of a guard band between
channel (multipath fading, rain etc.), Cross Polar the adjacent spectra. The branching for the even and
Interference (XPI) will arise and the performance is odd channels is combined at the TX side and splitted
degraded. A Cross Polar Interference Canseller at the RX side, which leads to an overall reduction of
(XPIC) is introduced in the demodulator to prevent 6dB of the system gain.
this. In systems with space diversity, the use of the 3dB
loss TX hybrid can be avoided by transmitting the
even and the odd channels on separate antennas.
RX
f= 1 ' f= 3 ' f= 5 '
f= 6' f= 4 ' f= 2 '
TX
f= 5 f= 3 f= 1
PW
1 2 3 4 5 6 1' 2' 3' 4' 5' 6'
1 2 3 4 5 6 1' 2' 3' 4' 5' 6' V
f= 2 f= 4 f= 6
TX RX
RX
f= 2 ' f= 4 ' f= 6 '
f= 1 ' f= 3 ' f= 5 '
TX
f= 6 f= 4 f= 2
f= 5 f= 3 f= 1
Figure 8 Co-channel branching (5+1)
9
L 29005 Rev.H 04.01.96 FS/Oeg
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A NT
H
V
1H 3H 5H 2V 4V 6V 1V 3V 5V 2H 4H 6H
AAU1
AAU2
SVCE TEL1
SVCE TEL2
PABX ADPT
GROU P
GROUP
GROUP
GR O U P
G R OU P
G R OU P
G R OU P
G R O UP
GR O U P
GROUP
GR O U P
GR OU P
XM T R
XM T R
XM T R
X M TR
XM TR
X M TR
X M TR
X MTR
X M TR
XM T R
X M TR
XM TR
64kb/s ADPT
MSOH or 64kb/s ADPT
DISPLAY UNIT
64kb/s ADPT 1H' 3H' 5H' 2V' 4V' 6V' 4H'

1V' 3V' 5V' 2H' 6H'
RSOH-ADPT RCVR RCVR RCVR RCVR RCVR RCVR RCVR RCVR RCVR RCVR RCVR RCVR
SU GROUP GROUP GROUP GROUP GROUP GROUP GROUPGROUP GROUP GROUP GROUP GROUP
ALARM BD
ACU IF- IF- IF- IF- IF- IF- IF- IF- IF- IF- IF- IF-
Splitter Splitter Splitter Splitter Splitter Splitter Splitter Splitter Splitter Splitter Splitter Splitter
RPS
IF- IF- IF- IF- IF- IF- IF- IF- IF- IF- IF- IF-
Equalizer Equalizer Equalizer Equalizer Equalizer Equalizer Equalizer Equalizer Equalizer Equalizer Equalizer Equalizer
ALARM BD
ACU
Diversity Diversity Diversity Diversity Diversity Diversity Diversity Diversity Diversity Diversity Diversity Diversity
delay delay delay delay delay delay delay delay delay delay delay delay
cable cable cable cable cable cable cable cable cable cable cable cable
XMTR-SWITCH
SYNCH UNIT
D E M O DU LA TO R
D E M O D U LA TO R
D E M O D U LA TO R
DE M O D UL A TO R
D E M O D UL A TO R
D E M O D UL A TO R
D E M O D UL A TO R
D E M O D UL A TO R
D E M O D UL A TO R
DE M O D U LA TO R
DE M O D U LA TO R
D E M O DU L A TO R
M O D U L ATO R
M O D U L ATO R
M O D U L ATO R
M O D U LA TO R
M O D U LA TO R
M O D U LA TO R
M O D U LA TO R
M O D U LA TO R
M O D U L ATO R
M O D U L ATO R
M O D U L ATO R
M O D U LA TO R
RCVR DATA
DISTR
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
P W R S P LY
SVCE H
CHP
CHP CH1 CH2 CVH 3
CH3 CH4 CH5 SVCE CHP CH1 CH2 CVH 3
CH3 CH4 CH5
Figure 9 Rack layout with XPIC 2x (5+1)
10 L 29005 Rev.H 04.01.96 FS/Oeg

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2.2 Station configuration The transmission performance is supervised by reg-
The equipment configuration is either terminal or istration of parity errors in the STM-1 signal.
repeater. The terminal equipment is start and end
points of a section. If the equipment is configured for
n+1, the terminal equipment has radio protection 2.2.2 Repeater station
switching (RPS) equipment. The RPS is prepared for
A basic repeater station is shown in figure 12.
up to 7+1 configurations. The actual switch in the
receiver side is part of the demodulator unit.
The transmit and receive units are identical to the
corresponding units in the terminal station.
The repeater stations are intermittent points in this
line and access to the main traffic is normally not
The inserted digital service channels are accessible at
possible at these stations. If the system is configured
the repeater station, and are automatically through-
for n+0 operation, the repeater can be configured as
connected if access to the service channels is not
an Add/Drop Repeater and access to main traffic is
required at the repeater station.
then available at this station.
2Mb/s wayside traffic can be dropped and inserted at
repeater stations, but are then unprotected.
2.2.1 Terminal station
A standard terminal station is based on frequency In systems without protection (N+0 configurations)
diversity and N+1 protection switching. The equip- the traffic can easily be dropped at repeater stations.
ment is prepared for transmission of occasional traffic
on the protection channel. A repeater can be arranged in two possible physical
arrangements. The difference between these is in the
The 1+1 terminal station can be equipped with all placement of the modulator in the equipment. In the
common units necessary for future expansion to N+1 normal configuration the modulator is placed in the
systems. RF-channel 1 and the protection channel in same rack as the demodulator on the receiving side of
an N+1 system transfer data for the radio protection the repeater. In the alternative configuration the
switching, remote alarm information, service tel- modulator is placed in the same rack as the transmit-
ephones and auxiliary data channels. At the receive ter to which it is associated . This arrangement is only
side the N+1 hitless switching function is integrated in required in a n+0 add/drop repeater configuration.
the demodulator of each main radio channel. See also the figure on the left side.
Direction 1 Direction 2 Direction 1 Direction 2

TRANSMITTER
TRANSMITTER
TRANSMITTER
TRANSMITTER
TRANSMITTER
TRANSMITTER
TRANSMITTER
TRANSMITTER
SERVICE RACK
SERVICE RACK
RECEIVER
RECEIVER
RECEIVER
RECEIVER
RECEIVER
RECEIVER
RECEIVER
RECEIVER
DEMODULATOR
DEMODULATOR
DEMODULATOR
DEMODULATOR
DEMODULATOR
DEMODULATOR
DEMODULATOR
DEMODULATOR
MODULATOR
MODULATOR
MODULATOR
MODULATOR
MODULATOR
MODULATOR
MODULATOR
MODULATOR
Ch1
Ch1
Ch1
Ch1
ChP
ChP
ChP
ChP
Normal configuration.
configuration. Alternative
Alternativeconfiguration.
configuration.
Units assosiated
Units associatedwith
withone
one Units
Unitsassosiated
associatedwith one
with one
traffic direction
traffic directionshown
showngreyed.
greyed. traffic
trafficdirection
directionshown
showngreyed.
greyed.
Figure 10
11
L 29005 Rev.H 04.01.96 FS/Oeg
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2 M b /s W a y side t raf f ic
2 M H z S ynch. In p.
CHN
13 9. 264 M b /s C M I S pli tt er
CHN
M o dul ator U ni t X M T R G roup
CH A NN E L N
G .7 03
2 M b /s W a yside t r af f ic 2 M b/ s B U S
2 M H z S ync h. Inp.
CH 1
15 5. 520 M b /s CH 1 C HANN EL 1 X M TR
C M I S pli tt er M o dul at or U ni t X M T R G roup B ranch ing
G .7 03
2 M b /s W a y side t raff ic 2 M b/s B U S
2 M H z S ynch. In p.
CHP
15 5. 520 M b /s C M I S pli tt er
CHP
X M T R G roup
C HA N NE L P
M o dul at or U ni t
G .7 03
+ 5V 2 M b/ s B U S
-5V
P ow er
S u ppl y +1 5V
-15V
X M TR S w it ch
RPS M S O H - A d apt ers
O m nib us S v ce. Te lep h.
S upe rvisory RSOH E xpre ss S vc e . Tel eph . 64 kb/ s ada pt ers. C H 1
Adapter P A B X A da pt . S vce. Tel.
A A U No1 A A U N o2 ACU C HN A C U CH 1 A CU CH P 64 k b/ s A d apt ers 64 kb/ s ada pt ers. C H N
D at a D i stri but io n
2 M b /s B U S
CHN CH A NN E L N
1 39.26 4 M b/ s R ela y & CH N D em od ula to r U nit R CV R G roup
G. 703 D rive r U nit
2 M H z S y nch. out
2 M b/ s W ay sid e tra ffic 2 M b /s B U S IF Equal
CH1 C HANN EL 1
R ela y & CH 1 RCVR
1 55.52 0 M b/ s D em od ula to r U nit R CV R G roup
D rive r U nit B ranc h ing
G. 703
2 M H z S ynch. out
2 M b/ s W ay sid e tra ffic 2 M b /s B U S IF Equal
CHP
1 55.52 0 M b/ s R ela y & CH P C HA N NE L P
D em od ula to r U nit R CV R G roup
G. 703 D rive r U nit
2 M H z S ynch. out
2 M b/ s W ays id e tra f f ic IF Equal
Fig. 11 Block Diagram N+1 Terminal Station, electrical interface
2M H z S y nc h o u t
S T M -1
D e m o d u l a t or M o d u la t o r
R C V R G rou p U n it Un it X M T R G ro u p
C trl . sig n .
2 M b / s W ay s id e t ra f fic 2M b / s W a y s id e tra ffic
IF E q ua l
2 M H z S y n c h ou t
S TM - 1
RCVR D e m o d u la to r M o d u la t o r XM TR
R C V R G ro up Un it X M T R G ro u p
B ra n c hi ng U n it B ra nc h in g
C tr l. s ig n .
2 M b / s W a ys id e t ra ffic 2 M b/s W a y s id e tra ff ic
IF E q u a l
2M H z S y nc h o u t
S TM - 1
D e m o d u l a t or M o d u la t o r
R C V R G rou p U n it Un it X M T R G ro u p
C tr l. s ig n .
2 M b / s W ay s id e t ra f fic 2M b / s W a y s id e tra ffic
I F Eq u a l
AAU N o 1 A C U C H N , D IR 1 A C U C H 1, D IR 1 A C U C H P, D IR 1
RS O H O m n ib u s S v c e. Te le p h . 6 4 k b /s ad ap t e rs . C H 1
S u pe rvis o ry
A d a pt er E x p re s s S v ce . Te le p h.
PA B X A d a p t. S v ce . Tel .
A A U No 2 A C U C H N , D IR 2 A CU CH 1, DIR 2 A C U C H P, D I R 2 6 4 kb / s a d ap te r s. C H N
2 M b/ s W a ys id e tra ff ic
2M b /s w a y s ide tra ff ic
S T M -1
M o d u l a t or D e m od u la to r
X M T R G r ou p U n it U n it R C V R G ro u p
C trl. si g n .
2M b/ s Wa ys id e tr a ffic I F E qu a l
2M b / s w a ys ide t r a ffic
S T M -1
X MT R X M T R G rou p M o d u l a to r D e m o d u la to r R C V R G ro u p RCV R
B ra n c hi ng U n it U n it B ra nc h in g
C trl. si g n .
2 M b / s W a y s id e tra ffic I F E qu a l
2 M b/ s w a y s id e t ra ff ic
S T M -1
X M T R G ro up M o d u l a to r D e m o d u la to r R C V R G ro u p
U n it U n it
C t rl. si g n .
IF E qu a l
Fig. 12 Block Diagram N+1 Repeater Station

12 L 29005 Rev.H 04.01.96 FS/Oeg
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2.3 Line interface
the “errorless” switching to and from the protection
2.3.1 PDH / SDH interface channel. The microprocessor control renders a supe-
The signal interface on each of the radio channels can rior system flexibility compared to conventional fixed
be configured as 140 Mb/s PDH or 155 Mb/s STM-1. hardware logic circuit solutions.
The interface is selectable by switch setting and each The user interface is an LCD display, which through a
channel in a n+1/n+0 configuration is individually parallel interface is controlled by the Supervisory Unit
selectable. (SU). The operator is able to configure the system from
the control panel located on the front of the LCD panel.
2.3.2 Electrical interface All RF-channels can be assigned to a customer speci-
fied priority, and all switching criteria can be enabled/
The data interface to the DRR is in accordance with
disabled when required. As an option, the switching
ITU-T Rec. G.703, para. 12.
functions can also be controlled via the Qx/SCADA
interface located on the SU.
2.4 Radio Protection
Switching System On the receiver side a Relay Unit (RU) connects the
The main function of the Protection Switching System 144/155 Mb/s main traffic outside the demodulator
is to handle the automatic and manual switching from when necessary.
a main channel to a common protection channel in an
N+1 system. The switching system is designed to Figure 13 shows a block diagram of a switching
control a complete SDH-Radio relay section with two network with two terminals and one repeater.
terminal stations and up to fourteen repeater stations
in an N+1 configuration, where N is a maximum of 7 On the receiver side the switching network consists of
RF-channels. The switching system can also handle 3 units, (ASF, Data Distribution and Relay Unit) which
Hot Stand-by systems as well as N+0 systems, where are controlled by the RPS. The RPS is “master” in its
N is a maximum of 8 RF-channels. own receiver direction. This means that all automatic
switching is initiated from the receiver side.
On the transmitter side the switching network con-

2.4.1 Radio Protection Switching sists of 2 units, (XMTR Switch and Modulator) which
(RPS) Unit are controlled by the RPS. The RPS is “slave” in its
The RPS is a microprocessor based unit which controls own transmit direction.
C MI C MI DEMOD DEMOD CMI

MO D M OD R EL AY
SPL IT ASF ASF
C H1 C H1
C TR L C TRL CT RL C TRL CT RL
S IGN . SIGN . SIGN . SIG N. SIGN.
C MI CM I MO D DEMOD M OD DEMOD R EL AY CMI

C H2 SPL IT ASF ASF C H2
C TR L C TRL CT RL C TRL CT RL
S IGN . SIGN . SIGN . SIG N. SIGN.
C MI CM I MO D DEMOD M OD DEMOD R EL AY CMI

C H7 SPL IT ASF ASF C H7
C TR L C TRL CT RL C TRL DATA CT RL

S IGN . SIGN . SIGN . SIG N. DIST R SIGN.
C MI CM I DEMOD DEMOD CMI

XM TR SW ITC H MO D M OD R EL AY
SPL IT ASF ASF
CHP C HP
CTRL CT RL CT RL
SIGN . SIGN . SIGN .
C TRL
SIGN.
FIF O BU S
RPS RP S FIFO BU S
to SU
to SU
64 Kb /s, V.11 64 Kb /s, V.11 64 Kb /s, V.11 64 Kb /s, V. 11

M S2 MS 2 M S2 MS2
(C han P - Chan 1) (Chan P - Ch an 1)
Fig. 13 Switching Network
13
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2.4.2 Alignment Switch Function (ASF) based on a priority evaluation of the different criteria.
The ASF is an integrated part of the demodulator unit For details of the switching criteria, see the technical
and performs synchronization of the two received specifications.
data signals (140/155 Mb/s) with each other. There is
one ASF for each RF-channel with a dynamic range 2.5 Automatic Transmitter
of +/- 64 bits. Based on switching criteria, priority or Power Control (ATPC)
manual operation, the RPS sends control signals to
the ASF which switches the selected channel to the
output of the demodulator. 2.5.1 General
The RPS reads the status of the ASF to ensure ATPC is an optional feature on the NL290-family,
correct output at regular intervals. used to achieve a number of advantages in a Radio
System. Instead of a fixed operation condition, the TX
Power Amplifier is operated with variable output
power in a dynamic range of 15dB, from a minimum
2.4.3 RCVR Data Distrib. Unit (RDDU) value to a maximum value. The minimum TX output
The RCVR Data Distribution (RDDU) located on the power value is according to the calculated RCVR-
receiver side distributes the protection channel to all group input value which is used in the case of normal
7 regular channels and the protection channel for propagation.
occasional traffic. The RPS can via control signals
select if the protection channel output shall be 140 The main benefits are listed below:
Mb/s or 155 Mb/s and in addition disable the output. 1) Reduce digital to digital distant interference
At regular intervals the RPS reads the status of the between radio-hops which use the same
RDDU to ensure correct output. frequency.
2.4.4 Relay Unit (RU) 2) Improve analogue / digital compatibility in the

The Relay Unit is located on the receiver side and case of antennas with poor Cross Polarisation
executes the switching in case the ASF fails to Discrimination (XPD) performance.
perform the switching function. The RU is controlled
by the RPS which decides, according to the different 3) Eased frequency co-ordination in crowded nodal
alarm conditions, when the relay should be operated. stations due to reduced nominal receive level.
Under normal conditions, with traffic on regular chan-
nel, the relay is not operated. 4) Reduce the effects of up-fading propagation
conditions on the system.
NOTE! The RPS will not read the status of the RU.
5) Reduction in power consumption, with benefit in
MTBF of the power amplifier.
2.4.5 XMTR Switch Unit (XSU)
The XMTR Switch Unit is located on the transmitter side
and can perform two different switching functions. 2.5.2 Block diagram, functional
description
The standard switching function is to connect the Fig.14 illustrates the ATPC function for a radio hop in
selected radio channel, channel 1-7, distributed from both directions. The following description is for one
the modulators to the protection channel. direction. ATPC-lower and ATPC-higher are the con-
The other function which is optional, uses an internal trol signals generated by the AGC voltage in the
relay switching function. This connects the selected RCVR-group and inserted into MS#3 bit 0 and 1 in the
radio channels 1-7, distributed from the CMI splitters, to modulator (station 2). The two control signals are
the protection channel. This switching function is per- extracted from the STM-1 signal and applied to an
formed if the modulator fails or is under test. ATPC-ctrl function in the demodulator (station 1). Two
control signals ATPC-CTRL1 and ATPC-CTRL2 are
The XSU is also capable of transmitting occasional coming from the Supervisory Unit / ACU. These four
(unsecured) traffic on the protection channel. The control signals will create an analogue 0-10Volt refer-
XSU handles both 140 Mb/s and 155 Mb/s data ence voltage which is applied to the XMTR-group and
signals. adjusts the output power (station 1).
The RPS reads the status of the XSU to ensure The RCVR-group nominal input level is adjustable on
correct output at regular intervals. the receiver group between
-25dBm and -50dBm.
2.4.6 Switching criteria An ATPC-alarm is activated if the regulation loop is
Switching to the protection channel is initiated by not working. Indicators on the transmitter and the
defined switching criteria. The switching action is receiver are lit if the ATPC is active.
14 L 29005 Rev.H 04.01.96 FS/Oeg

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Station 1 Station 2
M o du lato r D e m o d u la t o r
IF IF 14 0 /1 55 M b/ s
14 0 /1 5 5 M b/ s X MTR RC V R
S T M -1 S TM - 1
C M I , ele c t ric al C M I , ele c t ric a l
AT PC -ctrl
A TPC- CTRL1
A TP C-CTRL2
AT PC -X M TR
regulat io n
v olta ge
A T P C -a la rm
0-10 V
A T PC -hig he r
A T P C -low e r
R EF -LE V E L
S u pe rv is ory
U nit A CU
A T P C -hig he r
A T P C -low e r
A T P C -a la rm
ATP C -XM T R
S up erv is ory
reg ula tion

AC U
U n it
v olt age
RE F-LE VE L
0 -1 0 V
A TP C- CTRL1
AT PC -CTR L2
ATPC -ctrl
14 0 /15 5 M b / s IF
S T M -1 RC V R X MT R 1 4 0 /1 5 5 M b / s
C M I, e lec tr ic a l S T M -1 C M I, e le c tr ic a l
IF
D em od u la to r M od ula tor
Fig. 14 ATPC Block Diagram
2.6 Section termination (MST/RST) synchronising signal. This feature is only relevant if
the MST function is used.
Each of the radio channels of the radio relay equip-
ment can be configured for Multiplex Section Termi-
nation (MST) or Regenerator Section Termination
The equipment is automatically synchronised to the
(RST) according to the ITU-T Rec. G.709.
incoming STM-1 signal if the RST function is used (the
interface is STM-1).
If 140 Mb/s interface is selected, the equipment is
always configured for MST with or without pointer
When 140 Mb/s interface is used and the terminals
processing.
are configured for MST, the Sync Unit can be used if
any of the 64 kb/s data signals in the SOH are to be
If the line interface is STM-1, the equipment is nor-
through-connected without byte-slip to other sections
mally configured for RST, as the MST is performed
or other terminals. All STM-1 traffic is then
elsewhere on the STM-1 path, i.e. in the SDH multi-
syncronized and the 64 kb/s data rates are identical at
plexer equipment. The equipment can also be
all channels.
configured for MST when the interface is STM-1, if
access and termination of the MSOH bytes are re-
At the receiving side the 2 MHz Sync. signal is derived
quired.
from the demodulated STM-1 signal and can be
distributed to 4 output ports. The format of this 2MHz
2.7 System Synchronization signal is according to ITU-T Rec. G.703, 75 ohm un-
By use of an optional 2 MHz Sync Unit 2SF219A, the balanced, 1.5 - 3.0 volt.
equipment can be synchronised to an external 2 MHz
15
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2.8 Service and wayside traffic
2.8.1 Section Overhead

Configuration
Regenerator A1 A1 A1 A2 A2 A2 C1 NU NU A1 Frame word 1111 0110
A2 Frame word 0010 1000
Section B1 MS1 MS2 E1 MS X F1 NU NU C1 STM-1 identifier
Overhead D1 MS3 MS D2 MS X D3 X X B1 BIP-8 check sum for STM-1 frame
E1 Order wire
Pointers AU POINTERS F1 User channel / Order wire
D1-D3 Data Communication Channel 192 kb/s (DCC)
Multiplexer B2 B2 B2 K1 X X K2 X X MS Media Specific bytes
NU Bytes reserved for national use
Section D4 X X D5 X X D6 X X
X Unallocated bytes
Overhead D7 X X D8 X X D9 X X B2 BIP-24 check sum for the STM-1 frame except RSOH
K1-K2 Multiplexer Protection Switching signalling
D10 X X D11 X X D12 X X D4-D12 Data Communication Channel 576 kb/s (DCC)
S1 Z12 Z13 Z21 Z22 M1 E2 NU NU S1 Synchronizing status
Z1-Z2 Reserved for future use / User channels
M1 FEBE (Far End Block Errors)
E2 Order wire
Figure 15 STM-1 frame, Section OverHead Bytes.
In the STM-1 processing part in the modulator and ing end the SOH bytes can be extracted before or after
demodulator units the SOH bytes are inserted/ex- the alignment switch. By extracting the data after the
tracted and made available in the service rack in form alignment switch, the SOH bytes on the Data 2 bus
of 2 Mb/s buses (32 timeslots with 64 kb/s data). can be transmitted protected between terminals, but if
Some bytes are accessed by 64 kb/s adapters via the the bytes are inserted/extracted at repeater stations
RSOH adapter or directly by the 64 kb/s adapter , they will be unprotected.
while others can only be directly accessed by the 64 The RSOH adapter receives the SOH bytes from both
kb/s adapters, see fig. 16. channel 1 and channel protection before the alignment
switch,and switches between these, thus providing
The SOH bytes are inserted into the STM-1 frame in protected data at all stations.
both modulators in a protected system. At the receiv-
Bytes available
via the RSOH adapter B1 MD1 MD2 E1 MD X F1 NU NU
in the service rack, or at the adapter D1 MD3 MD D2 MD X D3 X X
shelf in the service rack

Bytes available X X X X
in the adapter shelf X X X X X X
in the service rack. X X X X X X
X X X X X X
Bytes used by the S1 Z12 Z13 Z21 Z22 M1 E2 NU NU
SSS and RPS.
Figure 16 Access to SOH bytes
16 L 29005 Rev.H 04.01.96 FS/Oeg

Nera AS
M O D U LA TO R C H A N N E L 1
1 3 9 .2 6 4 M b /s o r
1 5 5 .5 2 0 M b /s IF 7 0 M H z
M O D U L A TO R C H A N N E L P
S O H D a ta
S O H D ata
S e rvic e 6 4 k b /s
b u s to RSOH
A d a p ter
S e rvic e c h . A d a p ter
6 4 k b /s A d ap te rs...
D E M O D U L A TO R C H A N N E L P
1 3 9 .2 6 4 M b /s o r
1 5 5 .5 2 0 M b /s IF 7 0 M H z
D E M O D U L A TO R C H A N N E L 1
Figure 17 SOH Data buses routing.
2.8.2 Service telephone regular traffic channel. This 2 Mb/s data is transmitted
For orderwire communications the DRR can be on the Media Specific bytes (MS) not used by the SSS,
equipped with up to two service telephones. Each of National Use bytes (NU) and unallocated bytes (X). If
these will be transmitted on one byte in the SOH. The the 2 Mb/s data is inserted in equipment configured for
service telephone(s) will be transmitted on the bytes RST, two bytes (NU bytes in MSOH) are used to keep
that the RSOH adapter access in the SOH, i.e. the the MSOH BIP-24 checksum (B2 bytes) correct. The
communication will be protected between all stations, data is inserted in the STM-1 frame before the signal
transmitted on both channel protection and channel is split to the protection channel and extracted after the
1. At repeater stations the orderwire traffic is transmit- alignment switch, thus being protected together with
ted in both directions. The Orderwire can be the main data traffic. If the system is 2+1 or higher,
configured as omnibus (available at all stations) or additional 2 Mb/s data can be carried on channel 2 to
express (available only at the terminals). The E2 byte channel n (if available).
can only be used if the equipment is configured for
MST, otherwise this must not be used as the B2 If 2 Mb/s wayside traffic is required at repeater sta-
checksum can not be corrected for this byte. tions, this will be unprotected.
Each telephone has a two digit selective number and When 2 Mb/s wayside traffic option is used, this will
an ‘all stations’ call number. In addition each service have priority and these bytes will then not be available
telephone can have an extension telephone with its for other purposes. If the use of these bytes conflicts
own selective number. with other allocations for these, the 2 Mb/s wayside
traffic feature can be disabled and these SOH bytes
2.8.2.1 PABX Adapter will then be transmitted transparently between the
NNIs.
It is possible to connect the orderwire circuit to a
PABX or PSTN network by use of a PABX Adapter
2N504A. This adapter converts the 4 wire interface 2.8.3.2 64 kb/s data
with E/M from the service telephone to a standard 2 Individual 64 kb/s data channels are available by use
wire telephone interface, and emulates a subscriber of the optional Adapter 64 kb/s 2N507A unit in the
in the PABX/PSTN network. The signalling used is service rack. This adapter accesses a timeslot in a 2
DTMF, Q23. Mb/s bus. By selecting the timeslot number and the
bus, actual byte in the SOH is selected. Each adapter
2.8.3 Wayside traffic has two 64 kb/s data circuits and the electrical inter-
face can be G.703 (co- or contra-directional) or V.11
The DRR can carry both 2 Mb/s and 64 kb/s wayside
(contra directional) format.
traffic.
The adapter can physically be located in two shelves.
2.8.3.1 2 Mb/s data In the first shelf there are two positions available and
One 2 Mb/s data stream can be transmitted on each the 2 Mb/s data bus is the RSOH bus. The 64 kb/s data
17
L 29005 Rev.H 04.01.96 FS/Oeg
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channels on these adapters are transmitted protected sure that configuration of adapters does not affect the
between all stations as the RSOH adapter performs multiplexer operation, as terminating or changing
the switching. Up to four 64 kb/s data channels can be bytes that should have been carried transparently
utilised this way. through the radio network, could affect other parts of
the transmission network. The M1 byte may carry Far
The adapters placed in the adapter shelf access the End Block Error between the MST terminals (multi-
2 Mb/s databuses to/from modulator/demodulator plexers).
ch1 directly, and will only be transmitted protected
between terminals. This adapter shelf can hold 5 2.8.4 MSOH adapter
adapters (4 if MSOH adapter is present) and the bytes The DRR can be equipped with a MSOH adapter
available for these 10 (8) data channels are shown in 2N507A if access to D4-D12 bytes and/or K1-K2
fig. 17. If 64 kb/s data are inserted in MSOH bytes in bytes in the section overhead is required. This is only
equipment configured for RST, the checksum correc- used when the radio relay is configured for MST
tion must be enabled. function. The MSOH adapter signals are switched
together with channel 1 main data.
Care should be taken when configuring the 64 kb/s
adapters, as accessing the wrong SOH byte may Access to D4-D12 or K1-K2 can be individually ena-
affect both the other service functions and the main bled/disabled on the MSOH adapter. The interface for
data traffic. The S1 and Z21 bytes should not be used the DCC 576 kb/s channel D4-D12 is V.11 and for the
at RST, as the B2 checksum can not be corrected for K1/K2 data and timing (bit + byte timing) is NRZ,
these bytes, and the S1 byte might carry synchroniza- CMOS (5V).
tion status of the SDH network. Please also make
2.9 NETWORK MANAGEMENT

S D H STM -1 R ad io-R elay S ub-N etwo rk
W el co me
to
Nera
SU SU SU SU SU
SU SU
EM
SU SU SU
NI
4x2Mb/s Radio-Relay Sub-Network 34M b/s / 16x2Mb/s Radio-Relay Sub-Network
Welcome to
NI SU Nera
SU SU SU SU S U SU
SU SU
HH T
Welcome
to
Nera
WeN
lceorameto SU SU
SU SU SU
W e lc om e
to
Nera
HH T NEW
S U = S upe rvisor y U nit
NI = N et w or k Inte rf a ce
= T ermina l or N EW N E W = N e t w o r k E le m e n t v ie W
repeate r
Fig.18 SDH Radio management
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2.9.1 General The NEW is a MS-DOS based PC program with multi-
window user interface. The user interface is built in a
Windows like fashion with pop-up menus at the top, a
A radio network management system is integrated into
desktop in the middle and a status line in the bottom.
the SDH-Radio relay equipment where each terminal or
The menu structure is equivalent with Windows,
repeater represents a Network Element (NE) in the
which makes the software easy to learn and use. It is
SDH Telecommunication Management Network
possible to have many windows open concurrently, so
(TMN).
that information from various parts of the network can
be presented at the same time.
The system is designed to supervise several radio
sections and can handle up to 256 NE.
The EM needs a minimum of hardware to be opera-
tional. The PC itself can be a standard IBM compatible
The integrated management system serves three main
PC with a 80386 processor or higher. The required
functions:
minimum of RAM is 1 Mbytes. For storage of alarms
to disk, a harddisk of 100 Mbytes or more is recom-
1. Interface to SDH-TMN
mended. For communication between the PC and the
2. Alarm and meter functions
radio system, a RS232 communication port is used.
3. Radio protection switching functions
The distance is recommended to be less than 15
meters, otherwise RS232 to RS422 converters or
The Qx/Scada interface port will provide management
modems are required. A printer is required for event
information available on a serial form. This interface will
listing and reporting to printer.
evolve to a standardized management interface ac-
cording to ITU-T and ETSI recommendations.Thealarm
The NEW uses the configuration contained in the
and meter functions undertakes collection of alarms, meter
network element to configure a new network. Names
readings and quality supervision of all channels and sta-
of the individual NEs and other configuration data may
tions within the system. This function is based on three
be defined or changed by the user, and stored in a
hardware units communicating with each other via an
configuration file. This makes the configuration down
internal serial bus. The units are as follows:
to a minimum - plug & play.
ü Supervisory Unit, (SU)
The main features of the NEW includes :
ü Alarm Collection Unit, (ACU)
ü Automatic configuration of networks.
ü Alarm Adapter Unit, (AAU) ü Networks may be stored with user defined
names and alarm thresholds.
Fig. 15 shows an example of six NEs connected together. ü Continuously updated display of network status.
ü Multi-window user interface.
The Radio protection switching (RPS) functions handle ü Data from various NEs can be presented at the
the automatic and manual switching from a main channel same time.
to a common protection channel in an N+1 system. The ü Remote control.
RPS is designed to control a complete SDH - radio relay ü The system can monitor alarms, system
section with two terminal stations and up to fourteen performance quality, analog measurements
repeater stations in an N+1 configuration, where N is a (Receiver input level - AGC voltage) and error
maximum of 7 RF-channels. This function is based on four detector error pulses.
hardware units where the RPS sends control signals to the ü The software have alarm filtering capabilities
different sub units. and thresholds may be set for the input levels
The units are as follows: and quality measurements.
ü Logging of data to files and/or printer.
üRadio Protection Switching Unit, (RPS) ü Protection Switching
üXMTR Switch Unit, (XSU)
üRCVR data Distribution Unit, (RDU) The NEW communicates with the supervisory unit in
üAlignment Switch Function, (ASF) the radio relay equipment using a Nera specific proto-
(part of the Demodulator unit) col SIC-1. The NEW may be connected to any termi-
üRelay Unit, (RU) nal or repeater station in the network. This makes it a
powerful tool for field maintenance purposes. Used on
a laptop PC, it is a convenient system for supplying the
2.9.2 Network Element vieW maintenance personnel with data for individual NEs or
the whole radio network.
(NEW) The EM communicates with the radio internal super-
The Network Element vieW (NEW) is designed to visory system. Each supervisory unit (SU) is polled for
perform radio relay network management functions status and data on a regular basis. Each poll is a
on network elements or whole radio networks. message with a destination address (SU address)
19
L 29005 Rev.H 04.01.96 FS/Oeg
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and a source address (NEW PC). If an answer is not protocol used is a Q1 Nera proprietary protocol. The
received within a predefined time (user selectable) or electrical characteristics of the interface is RS-485 or
the answer is corrupted, the NEW will re-transmit the RS-232, 1.200 - 19.200 baud.
message.
Q Adapter.
For future implementation of the Qx/Q3 interface to
2.9.3 TMN Connection TMN, a Q Adapter will be used to handle the MCF. The
The supervisory system has a Qx/SCADA interface DRR will support the management functions defined
for connection to the Nera TELE-SCADA system. The by ITU-T and ETSI. Please contact Nera for details
and availability of this function.
DRR DRR DRR

Int. alarms Int. alarms Int. alarms
ACU ACU ACU
Ext. alarms Ext. alarms
AAU Remote cont. AAU AAU
Remote cont.
SU SU SU
Internal 64 kb/s Internal 64 kb/s
communication communication
RS-232
Figure 19 Example of a radio network managed by Nera NEW PC system
RSO H
DCC DCC
D1 - D3 D1 - D3 MS 2 MS2
192 Kb/s RS-485 192 Kb/s RS-485 64 K b/s V.1 1 64 Kb /s V.11
SC ADA / Q x SWITCH CRIT

MCF Parallel In tf.
NI
SU
PC RP S
RELE C O NT ROL
RELAY
RS -232
UNIT
Local L CD
Int alarm s RMT CTRL

Q ual B1-B 2- B3 ACU AA U
XSU ASF SW
A nalog inp
1 1 EXT AL M OU T PU T
CONT RO L
SIG NALS Part of Dem od u lato r
Int alarm s RMT CTRL

RSOH: R egen era tor S ec tio n Overhead
Q ual B1-B 2- B3 ACU AA U
A nalog inp N 2 EX T A L M RDDU DCC: Data Co mmu nicatio n Chann el
In tern al bu s ASF: A lig nment Sw itc h Fun ctio n
RDDU: R eceive r Dat a D istrib ut io n Un it
RP S: Radio Protection Unit A AU: Alarm A dapter Unit
MS 2: M ed ia S pe cifi c b y t e X SU: XMT R S w itch U n it
ACU: A larm C ollectio n Un it SU: S up er v i so r y U n i t
HHT : H an d Held T erminal N I: Netw o rk Interface
Fig. 20 Integrated management system.
20 L 29005 Rev.H 04.01.96 FS/Oeg

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Fig. 20 shows a block diagram of the integrated the SU communicates via the parallel interface with he
management system. RPS to display all switching information processed by
The information is presented on an 16x16 character the RPS.
LCD located together with the SU. A Network Ele-
ment Manager (NEM) software for a Personal Com- 2.9.4.2 Alarm Collection Unit (ACU)
puter is available as an option.
The ACU is a micro controller based system which
2.9.4 Built-in Management performs three main functions:
As described, the integrated management system ü alarm collection

consists of three units communicating with each other ü meter readings
via an internal point to multipoint serial bus. The units ü quality measurements
are as follows:
These functions are performed on a channel by
ü Supervisory Unit, (SU) channel basis with one ACU located in each radio
ü Alarm Collection Unit, (ACU) channel plus one ACU located in the service rack.
ü Alarm Adapter Unit, (AAU)
The ACU communicates with the Supervisory Unit (SU)
via a serial bus interface, RS422, in a point to multipoint
configuration. All units connected to this bus have
2.9.4.1 Supervisory unit (SU) individually fixed addresses. The SU polls the different
ACUs at regular intervals to update the status.
The SU gives comprehensive supervision and control Each ACU has a fixed address which is set by a DIP-
facilities to the user by collecting information from the switch in the backplane; one DIP-switch for each ACU.
ACUs and AAUs.
The Supervisory Unit provides the following functions: 2.9.4.3 Alarm Adapter Unit (AAU)
ü Local alarm and status monitoring
ü Remote alarm and status monitoring The AAU is a micro controller based system which
ü Local control and metering collects all external equipment alarms and performs
ü Remote control and metering remote control functions. The AAU is located in the
ü Local performance measurement service rack with a maximum of two AAUs for each
ü Remote performance measurement service rack. If more than two AAUs are needed, an
extra rack is required. The maximum number of AAUs
The communication between the SUs uses the on each terminal/repeater are 8.
DCC (D1-D3) channels within the STM-1 frame Each AAU can handle up to 32 external equipment
structure. Within each radio switching section the
alarms and 8 remote control outputs.
maximum numbers of SUs are 16, i.e. 14 radio
hops. An internal Network Interface (NI) port is The AAU communicates with the SU via a serial bus
provided for the purpose of connecting two Super- interface, RS422, in a “point to multipoint” configura-
visory Units together. The NI port makes it tion, same as the ACU bus. The SU polls the AAUs at
possible to configure network solutions, where the regular intervals to update the alarm status. Each
maximum number of SU addresses within a net- AAU has a fixed address which is set by a dip-switch
work are 256. The SU supports the following main in the backplane; one dip-switch for each AAU.
functions:
ü Human Computer Interface

ü Local LCD 2.9.5 External connections
ü ACU/AAU communication
ü SCADA/Qx interface From each rack certain alarms may be connected to
ü DCC communication an external supervisory system through an optional
ü Network Interface Alarm board and a connector on top of the rack.
ü Parallel interface to the RPS 13 alarms may be connected to the alarm board
together with detected RF-input and output levels for
To transfer management information to a TMN sys- monitoring.
tem the SU uses the SCADA/Qx interface. The SU Important voltages (power supply and RF input/out-
uses either a proprietary protocol or a standardized put) are available for monitoring via a connector on
protocol according to ITU-T Rec. G.784. In addition front of each radio rack.
21
L 29005 Rev.H 04.01.96 FS/Oeg
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3.0 Block Description 3.1 Baseband & Modem Equipment
Electrical interface:
SVCE CHP CH1 CHN On the transmit side the incoming CMI data signal is
passed through a CMI splitter unit where the signal is
RELAY UNIT
splitted and applied to the main modulator unit and
CMI SPLITTER
the XMTR-switch unit. The purpose of the CMI
splitter is only to split the CMI data into two equal
AAU1 outputs, and also to detect if incoming data is lost
AAU2
SVCE TEL1 (input alarm). A block diagram of these units is shown
OPTION SVCE TEL2 in fig. 22 and 23. Connection to the electrical CMI-
PABX ADPT
data-input is made at the top of each radio rack.
64kb/s ADPT
MSOH or 64kb/s ADPT
XMTR XMTR XMTR
GROUP GROUP GROUP
Connectors are of type: IEC 169-13, 1.6/5.6mm
(coaxial connectors).
DISPLAY UNIT
MAIN MAIN MAIN

1 4 0/ 1 5 5 Mb /s
OPTION 64kb/s ADPT C M I- D A TA IN P U T
RSOH -ADPT RCVR RCVR RCVR
G.7 0 3 CMI-DATA IF, 7 0 M H z
SU GROUP GRO UP GROUP C M I S P L ITT ER U N IT
G.703 0dB m
MO D U L A TO R U N IT
OPTION ALARM BD IF TE ST
ACU SPACE SPACE SPACE - 1 0 dB
RPS Diversity Diversity Diversity CM I-DA TA C M I-DA TA
G .7 03 EC L
IF- IF- IF-
Equalizer Equalizer Equalizer
OPTION ALARM BD
ACU T O X M TR -S WIT C H TO XM T R -S WI TC H
UNI T U N IT
Diversity Diversity Diversity
delay delay delay
cable cable cable
Fig 22 Baseband and modem, transmit side.

XMTR-SWITCH
DEMODULATOR
DEMODULATOR
DEMODULATOR
MODULATOR
MODULATOR
MODULATOR
OPTION SYNCH UNIT

140 /155M b/s
C M I-DA TA O UT PU T
RCVR D ATA G .703
DISTR IF , 7 0M H z
0dB m DE M O D U LA T O R
140 /155M b/s
U NI T
C M I-T ES T O UTP UT
PW R SPLY
PW R SPLY
PW R SPLY
PW R SPLY
PWR SPLY
PW R SPLY
PW R SPLY
PW R SPLY
FR OM RC VR -DA TA
Figure 21Rack Layout Terminal N+1 D IS TRI BU TI ON
Fig 23 Baseband and modem, receive side.
On the receive side, all the demodulation and

baseband functions are included in the demodula-
tor unit. A block diagram of the signal flow is shown
in fig. 25. Connection to the electrical CMI-data
output is made at the top of each radio rack.
Connectors are of type IEC 169-13, 1.6/5.6mm
(coaxial connectors).
22 L 29005 Rev.H 04.01.96 FS/Oeg

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3.1.1 Modulator Unit
The modulator unit contains all baseband and modem unit. Functions for mapping a 139.264 Mbit/s
functions for the transmit side. Functions are provided plesiochronous bit stream into the STM-1-frame is
both for Regenerator Section Termination (RST) and built into the unit. Reconfiguration between the two
for Multiplexer Section Termination (MST) according interfaces (140/155Mb/s) can easily be performed. A
to ITU-T recommendations. The different modes of block diagram of the main functions of the modulator-
the modulator unit are selected by switches within the unit is shown in fig.24.
2 M b/s G.703
Way s ide traff ic
TCM- IF
CMI C4 D/A
CMI CABLE STM I ENCODING O UT
CODEC MUX MAPPING & M O D.
G.703 EQUALIZER (ASIC)
(ASIC) (ASIC) FIR-filter IF
(ASIC) D/A
39 MH z TE S T O UT
C LK
POH INSERT 48 MHz PLL
PLL CLK SIGN A L
SIG NAL
2 80/311 MH z 311 MHz 48 MHz

VCXO VCXO
SOH IN/OUT
HIGHER
CMI
ENCODER
LOWER
CM I TO
PRO T. CH ANN EL
Fig 24 Main Functions of the Modulator Unit
3.1.1.1 Main functions of the mod. unit STM-1-interface) and also rebuilding the STM-1
frame according to the rules specified in ITU-T
• CABLE EQUALIZER: Rec. G.707-709 and Rec. G.782-784. All extrac-
The CMI input data signal is applied to the cable tion of Section OverHead (SOH)-bytes from the
equalizer which automatically compensates for incoming STM-1-frame and insertion of new
varying cable attenuation according to ITU-T SOH-information is done in this circuit. The
Rec. G.703. circuit also splits the signal before it is applied to
the CMI ENCODER, and further to the XMTR-
• CMI CODEC: switch unit (See section 2.9, Network and
The CMI CODEC is an Application Specific Inte- Management).Other main functions performed
grated Circuit (ASIC), realized in ECL-technol- in this circuit are:
ogy. It has functions for CMI-data decoding, a) STM-1-frame synchronization
clock recovery, split and converting of the data- b) Descrambling and Scrambling
signal prepared for CMOS technology. The c) Bit Interleaved Parity (BIP)-checking
CMI CODEC is also used to CMI-encode and generation
the data signal going to the XMTR-switch-unit. d) AU-4 pointer processing
e) Burst encoding and decoding
• C4-MUX:
The C4-MUX is an ASIC,performing the The burst-encoder is a bit-interleaver used to
mapping of 139.264Mbit/s into a STM-1 frame rearrange the bits in the STM-1-frame to counter-
generated by this circuit. This function is only act the burst behaviour of the TCM process.
used if the 139.264Mbit/s interface is selected. After leaving the burst-encoder, the signal is
Traffic is carried straight through this circuit if the passed to the TCM-encoder and FIR-filter.
STM-1 interface is selected. The C4-mapping is
done according to ITU-T Rec. G.707-709 and • TCM-ENCODER AND FIR FILTER:
Rec. G. 782-784. These functions are also realised in an ASIC in
CMOS technology. The Trellis Code Modulation
• STM-1 PROCESSOR: (TCM)-encoder function is the transmit part of
The STM-1 processor is an ASIC, performing the modulation coding used to perform error cor-
the termination of incoming STM-1 signal (for rection.Trellis coded modulation is a combined
23
L 29005 Rev.H 04.01.96 FS/Oeg
Nera AS
coding and modulation scheme for improving the by a lowpass filter to remove the repetitive part
reliability of a digital transmission system with- of the spectrum generated in the preceding dig-
out increasing the transmitted power or the re- ital FIR-filter. The I- and Q-signals are modu-
quired bandwidth. The TCM-encoder consists lated on individual 70MHz carrier frequencies
of a differentional encoder, a convolutional en- which are 90° phase shifted. The two modulated
coder and the four-dimensional mapper. The signals are combined at the modulator output. In
differentional encoder is used to make the trans- order to satisfy the mask requirement for the
mitted symbols invariant to phase rotations. The transmitted spectrum, two band pass filters are
four dimensional symbol is transmitted in two inserted prior to the IF output. An IF equalizer is
consecutive two-dimensional symbols (I & Q) in a used to equalize the delay and amplitude re-
128/64 points cross constellation. sponse of the IF-filters. An IF-output alarm is
The FIR-filter function performs half of activated if the IF-level falls below about -6dBm.
the total system filtering. The other half of the
system filtering is done in a Surface Acoustic
Wave (SAW)-filter in the receiver group. The FIR- 3.1.2 Demodulator Unit, without XPIC
filter function realized is a 28 taps digital square
root cosine rolloff-filter. Filter for both I & The demodulator unit contains all baseband and
Q-channel is included in this ASIC. modem functions for the receive side. Functions are
provided both for Regenerator Section Termination
• D/A (DIGITAL TO ANALOG-CONVERTER): (RST) and for Multiplexer Section Termination (MST)
One 10-bit D/A-converter is used on each chan- according to the ITU-T recommendations. The differ-
nel (I & Q). The D/A-converters for the I & Q- ent modes of the demodulator unit are selected by
channel convert the 10-bit input data to an ana- switches within the unit. Demapping functions of a
log signal prepared for modulation. The D/A- 139.264 Mbit/s plesiochronous bit stream out of the
converters are standard commercial devices. STM-1-frame are also built into the unit.
Reconfiguration between the two interfaces (140/155
• MODULATOR (MOD): Mb/s) can easily be performed. A block diagram of
This is the analog part of the modulator-unit. The the main functions of the demodulator unit is shown
spectrum applied to the modulator is bandlimited in fig. 25.
70 M Hz 4 8 MHz 39 M H z 280/ 311 M Hz

VC XO VC X O VC XO VCXO
CA R R IE R T IM ING A LIG N M E NT C M I O UT
PLL PLL P LL PLL

F IL TER F ILTER F ILT ER F ILT E R
I D A TA
I D ATA D ATA
I
A /D C MI G .703
I and Q T CM C4
I F IN C LK A T DE C LK S TM I CL K C LK CMI
De m od u- d ec o de r D E MU X C M I TE S T O UT
Q (A SIC ) C LK ( A S IC ) C O D EC
lato r ( A SIC) (A SI C)
Q Q C M I FR OM
A /D
(AS I C ) P R O T. C H A N N E L
C LK
ATPC
SU/ACU CTRL
TIM ING
R ECO VE RY
To Tx SO H POH
OUT OUT
Fig 25 Main Functions of the Demodulator Unit
24 L 29005 Rev.H 04.01.96 FS/Oeg

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3.1.2.1 Main function of the Demod. Unit
ing of the rotational invariant coding made in the
• I & Q DEMODULATOR: TCM-encoder on the transmit side.
This is the analog part of the demodulator unit.
The IF-signal from the receiver is split in two • STM-1-PROCESSOR:
branches at the input. In one of the branches the The STM-1-processor is the same ASIC as used
IF signal is mixed with the LO-signal with 0° on the transmit side. It is used to perform the
phase shift, and in the other branch with the LO- burst decoding, system synchronization,
signal 90° phase shifted. This implies that the in- descrambling and Secion OverHead (SOH)-ter
phase component of the demodulated signal is mination.
retained in the first branch and the quadrature The burst-decoder is used to rearrange the
component in the other. The output of the mixers STM-1 frame to its original state.The circuit
contains the sum- and difference-products of regenerates the STM-1 frame according to the
the IF- and LO-signal. The sum and higher rules specified in ITU-T Rec.G.707-709 and
order mixing products are suppressed in an LP- Rec.G.782-784.
filter. The resulting signal is amplified to the The entire extraction of Section OverHead
proper level for the following A/D-converters. (SOH)-bytes from the incoming STM-1-frame
and insertion of new SOH-information is carried
• A/D (ANALOG TO DIGITAL-CONVERTER) out in this circuit.
One 10-bit A/D-converter is used on each chan- The alignment and switch function for the N+1
nel (I&Q). The A/D-converters for the I- and Q- radio protection switching is also built into this
channel convert the analog input data to a 10- circuit.
bit digital signal at a sampling rate of The switch function is controlled from the Radio
24Msamples/s. The A/D-converters are stand- Protection Switch (RPS)-unit.
ard commercial devices.
• C4-DEMUX:
• ATDE (ADAPTIVE TIME DOMAIN EQUALIZER): The C4-DEMUX is the same ASIC as used for
A 13-taps Adaptive Time Domain Equalizer C4-mapping on the transmit side. Here it is used
(ATDE) is provided in order to establish effective to map out the 139.264kbit/s of the STM-1-frame.
countermeasures against the distortion effects This function is only used if the 139.264kbit/s
caused by multipath transmission (selective interface is selected. Traffic is carried straight
facing). The complex equalizer is controlled by through this circuit if the STM-1-interface is se-
the Least Mean Square error (LMS) and the lected. The C4-demapping is done according to
Maximum Level Error (MLE) algorithms. The ITU-T Rec. G.707-709 and Rec. G.782-784.
optimum algorithm will be automatically se-
lected. The digital ATDE is implemented in one • CMI CODEC:
single ASIC in CMOS technology. The circuit The CMI CODEC is the same ASIC as used on
also has built-in functions for Automatic Gain the transmit side. It performs the combining and
Control (AGC), DC-offset- and quadrature- CMI-encoding of the data coming from the C4-
phase adjustment. It also generates control sig- DEMUX. The CMI-data signal is then applied to
nals for carrier-recovery and timing recovery. a CMI-driver before it is made available on the
front of the demodulator unit. A CMI test output
• TCM-DECODER (UTILIZING THE VITERBI- for in-service monitoring is available on the
ALGORITHM): front of the demodulator unit. The same CMI
The Trellis Code Modulation (TCM) decoder is CODEC- circuit is used to CMI-decode the
implemented in an ASIC in CMOS technology. data signal coming from the protection channel.
The TCM-decoder function is the receiver part
of the modulation coding used to perform error
correction. The Viterbi algorithm is used in the 3.1.3 Demodulator Unit with XPIC
decoder to improve the system performance.
The realized 8-state Viterbi-decoder, with
Viterbi-depth=15, gives a coding gain of approx. A demodulator unit including XPIC is currently under
4dB for 128 TCM-4D and 7 dB for 64 TCM at developement. This unit will contain the same func-
BER=10 -6 . The TCM-decoder consists of a 2-4 tions as in the demodulator without XPIC (para 3.1.2).
dimensional synchronizing function, a 4-dimen In addition it contains an additional demodulator
sional Viterbi-decoder and the differential function for the signal from the co-channel. The signal
decoder. The 2-4 dimensional synchronizing from the co-channel is then demodulated and fed into
function sets the two consecutive transmitted the XPIC-ASIC together with error-signals from the
2-dimensional symbols together to form a ATDE in the main channel demodulator. The XPIC-
4-dimensional symbol.This is used throughout demodulator unit will have the same physical size and
the calculation in the Viterbi-algorithm. The dif- be located in the same position as the demodulator
ferential decoder is used to perform the decod- without XPIC.
25
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3.2 Radio Equipment
The equipment is heterodyne with spectrum shaping Dielectric Resonator Oscillator (DRO) which is
equally shared between the transmit and receive side. The phase locked to a crystal reference oscillator. The
radio frequency part of the equipment consists of two IF-signal is processed in a fixed IF predistortion
units: The Transmitter Group and the Receiver Group. unit and up-converted to the desired radio
channel frequency.
3.2.1 Transmitter Group A linear wideband GaAs FET amplifier provides

A block diagram of the Transmitter Group is shown the required output level. A level control circuit
in figure 26. enables adjustment of the output power.
The local oscillator signal is generated in a SHF
LO MONITOR
OSCILLATOR
~
UPCONVERTER
IF INPUT PR E-
D IST ORT ION
RF OUT
dB dB
0 dBm
ALARM BOARD
AGC
AL C
RF POWER OUT
+ ALM.
+
FET AMPLIFIER
INDICATOR
BOARD 0 dB - 3 dB -6 dB -10 dB
RE LATIVE
OUTP UT
POWER
Fig. 26 Block Diagram of Transmitter Group
3.2.1.1 IF Predistortion
The IF Predistortion circuit is laid out on a multilayer be selected for +90° and -90°. The 180° branch
board. This board also contains an IF alarm detector, compensates for the amplitude distortion of the ampli-
a variable attenuator with external control voltage, fier, while the +90° branch compensates for the
and an equalizer at the input. Tests on the Up- phase shift. The selectable phase shift of +90° and -
converter are performed with and without predis- 90° is necessary since the phase shift is dependent on
tortion. U-links are therefore incorporated on the whether the up-converter is used with LO-signal
board to bypass the predistortion function. above or below the RF-signal. The limiters in the
circuit are temperature compensated to ensure
The IF signal is amplified prior to the predistortion constant limiting performance over a wide tempera-
circuit to obtain correct levels for the limiters in the ture range. The three branch signals are added to-
circuitry. The signal is split into 3 branches. One gether prior to application to the level detector. By
branch has no phase shift, but a variable attenuator individual adjustment the limiting performance, and
and a time delay circuit compensates for the delay in hence the amplitude- and phase shift of the signal
the limiters of the other branches. A second branch supplied to the amplifier, may be adjusted. Figure 27
has 180° phase shift and a variable attenuator and shows the circuit block diagram of the IF predistortion
limiter, and a third branch where the phase shift may Circuit.
26 L 29005 Rev.H 04.01.96 FS/Oeg

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0°
180° dB
75 ½ 90 °
IF
IN P UT 50½ dB 0°
IF
dB OUT
180°
0°
I F IN P U T L E VE L
A LA R M D E T E CT O R
dB t
Fig. 27 IF Predistortion Circuit
3.2.1.2 Up-Converter
Two mixer units are individually supplied with Interme- the LO frequency is obtained by a phase shift circuit
diate Frequency- and Local Oscillator- signals which in the up-converter. The IF level of the two mixers are
are combined. The LO frequency is suppressed by individually adjustable in order to enable maximum
employing balanced mixers. The unwanted sideband attenuation of the unwanted sideband. The IF predis-
is removed by image rejection. Further attenuation of tortion circuit is part of the up-converter.
D C-BIAS
70 M Hz 90 °
0° LO 0° RF
IF
9 0° INPUT 90° OU TPUT
IN P U T 0°
V de t
D C-BIAS
dB
LO CANC ELLAT ION
Fig. 28 Up-Converter (without predistortion)
3.2.1.3 Power Amplifier

The Power Amplifier is a GaAs-FET amplifier design stages of the amplifier. Each stage consists of a
using microstrip technique. A balanced attenuator at GaAs FET internally matched at input and output.
the amplifier input provides constant gain over the The transistors are DC-supplied from a separate
temperature range. The amplifier is divided into three regulator board located in a separate chamber. To
sections each separated by a microstrip isolator to achieve sufficient linearity a selected 8 W GaAs-FET
reduce coupling and to enable testing of the individual is used in the output stage.
RF INP RF OUT
- 6 dBm/50½ dB
RF ATT
VOS
VOS
VOS
VOS
VOS
VDS
VDS
VDS
VDS
VDS
RF DET
-5V
GND REGU LATOR BOARD
+ 9.4 V
Fig. 29 Power Amplifier

27
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3.2.1.4 Oscillator
The unit consists of a dielectric resonator oscillator divides the 10 MHz signal to the desired frequency for
which is locked to a crystal reference frequency by comparison. The various division factor values in the
means of a synthesizer circuit. A block schematic synthesizer circuit are programmed into a Program-
diagram of the synthesizer is shown in figure 30. mable Read Only Memory (PROM). Frequency se-
lection is carried out by means of a Dual In-line
The signal from the DRO is divided by 8 in a GaAs Package (DIP)-switch which sets the address in the
prescaler. The output frequency of this divider circuit PROM. The oscillator maintains a frequency stability
is approx. 750 MHz. A two modulus counter of - ±5 ppm in the temperature region +5° C to
operates together with the divider circuits in the +40° C.
synthesizer circuit and produces a programmable
division factor. The reference oscillator is a For the 11 and 13GHz equipment, the oscillator
temperature compensated 10 MHz crystal oscillator. operates at half the LO-frequency, and is followed by
A programmable divider in the synthesizer circuitry a FET based frequency doubler.
LO MON
RF
x 5.9 - 6.4 GHz
+ 17 dBm
7 3 7.5 - 8 00 M Hz
128
1 29
10 MHz
SWITCH RE F
PROM PL 6 OS C
ARRAY
Fig. 30 Frequency Synthesizer (Block diagram shown for 6 GHz version)
COMP
DE T
LN A & T X LV L C O R R E C T
M IX E R
RF
INP
( m a in ) dB MON
A TP C
REF LVL
O S C. D ET
DET L O S P L IT T E R & A GC
P H AS E S H IF T CA A M P LI F I ER I F & F I LT E R
f
FB E QL IF
D ET SL O PE OUT
dB
AGC DET
CA
RF D ET
IN P
(S p a c e dB
D i ve r s ity )
DE T
R ECE IV ER
EQL
GR O U P
D EL AY
EQL EQL
GROUP A BS
D E L AY D EL AY
EQ UALIZ E R, I F
Fig. 31 Block Diagram of Receiver Group
28 L 29005 Rev.H 04.01.96 FS/Oeg
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3.2.2 Receiver Group
The Receiver Group is designed to include space fixed reference voltage (adjusted for -5 dBm IF out) which
diversity IF combining as an option. A block diagram again controls the LNA attenuator.
of the Receiver Group is shown in figure 31
For space diversity operation the unit consists of two

LNA & Mixer units. The local oscillator is identical RF 0° LO INPU T 0° IF
INP dB 90° 90° OUT
to the unit in the transmitter group. The local oscillator
signal supplied to the space diversity branch is adap-
tively phase adjusted to allow IF-combining of the two
signals. Phase adjustment is provided by the splitter
& phase shift unit and is microprocessor controlled +
- REF.
using Minimum Dispersion algorithm. At the output
of the diversity combining unit the received signal Fig. 32 LNA & Mixer Unit
spectrum is corrected by a set of slope equalizers.
The receiver selectivity is controlled by a Surface
Acoustic Wave (SAW) filter in the AGC-amplifier 3.2.2.2 LO Splitter & Phase Shift Unit
following the diversity combining unit.
The LO input signal is split into two signals. One
3.2.2.1 LNA & Mixer Unit of these is transferred to the direct (12 dBm) output,
while the other one is fed through a circuitry for
amplitude and phase adjustment. This signal is first
The LNA & Mixer Unit consists of Low Noise Amplifier
divided into two identical signals, 90° phase shifted
(LNA) with Automatic Gain Control (AGC), a Single
with respect to each other. These two signals are
Sideband (SSB) balanced mixer, an IF amplifier and
controlled by a pair of diodes which reflect a portion of
a detector. The LNA consists of a two-stage FET
the signal power, causing a multiplication of the
amplifier and a balanced PIN-diode attenuator for AGC,
signals by a factor between -1 and +1. The factor
which is an integral part of the LNA. This attenuator has
value is dependent on the diode impedance and
a dynamic range of 10 dB. The Mixer is of the image
consequently on the voltage controlling the diode
rejection type.
currents. The resultant signal is amplified to a level
For selection of sideband, an electronic switch is inserted
of 12 dBm before it is applied to the other output.
at the output of the mixer. The IF amplifier at the output
The buffer amplifier contains a level control to
consists of two stages with a total gain of 13 dB. Part of the
counteract amplitude variations due to phase, tem-
IF amplifier output is decoupled to a temperature compen-
perature and component variations.
sated detector. The detector voltage is compared with a
L O O UT
( M A IN R C V R )
C O N TR O L
IN P U T 1
MOD
LO
IN P
0° L O O UT
90° dB ( S P A C E D I V E R S IT Y R C V R )
DET
MO D
C O N TR O L
IN P U T 2 +
- R E F.
Fig. 33 LO Splitter & Phase Shift Unit
29
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3.2.2.3 Space Diversity Combiner 3.2.2.3.1 Combining Algorithm
The space diversity combiner is integrated into the On the basis of the respective input power levels the
main receiver group and is available as an option for combiner algorithm is working as shown in the figure
all frequency bands. The combiner is working at IF as below:
shown in fig. 35.
3DK125A Space Diversity Combiner:

Combining Algorithm in Software rev R2B.
in pu t lev e l M A IN rc v r
dBm
switch out SPACE
-65
~10 dB switch out MAIN

er
w
ng Po
bi m
m mu
co a xi
ni
M
-80
Fig. 34 Combining Algorithm input level SPACE rcvr
-80 -65 dBm
All limits have about 1 dB hysteresis.
3.2.2.3.2 Block Diagram
IF I N P
A G C /C A
M AIN R CV R
LE V EL SUM IF O U T
D E T EC T O R
IF IN P F IL T E R
A G C /C A BANK
S P A C E D IV E R C IT Y R C V R
CO NTR OL
LE V EL A G C/MG C C O M B IN E R
S IG N A L S T O
D E T EC T O R CON TRO L C ONTR OL
P H A S E S H IF T E R
Fig. 35 Space Diversity Combiner
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Level Detector (LD) information is received from level detectors, AGC-
voltages and from the FB. A/D conversion is carried out
The level detectors are used together with the AGC- with 8 bits resolution.
voltages from the LNA to measure the received RF The Micro Controller controls the Splitter & Phase Shift
power level. The dynamic range of the level detector unit via two D/A converters. The MC also controls the
is 45 dB. AGC/CA so that the output signals can be individually
attenuated instead of added together. A “watchdog”-
Automatic Gain Control and Controlled Attenu- function supervises the proper functioning of the MC-
ation (AGC/CA) unit
The AGC ensures that signals are combined at equal Filter Bank (FB)
levels (-13 dBm). The dynamic range of the gain
control is 37 dB. The level detection of the gain control The Filter Bank is used to measure amplitude devia-
is carried out via a BP-filter with f0= 70 MHz. The unit tion and power of the combined spectrum. The FB
may be controlled from the Combiner Control (see consists of three BP-filters each with a 3 dB band-
below) to attenuate the output signal, and from the width of 10 MHz., and centre frequencies located at
AGC/MGC for manual level control. 60 MHz, 70 MHz and 80 MHz respectively. Each filter
is followed by a detector with a dynamic range of 15
Switching Between Automatic and Manual Gain dB.
Control (AGC/MGC Control)
3.2.2.4 Amplifier, IF & Filter, BP
The diversity combiner may be set for 3 different
modes by a switch on the front panel: The main function of this unit is to amplify and filter the
applied signal spectrum. The amplification is con-
Mode 1. In position MGC MAIN the diversity receiver trolled to obtain a constant output level of 0 dBm with
is attenuated, the phase shifter is set to input level variations in the range of 0 dBm to -20 dBm.
MID POSITION phase shift and the Possible spectrum slope within ±10 dB in the 70 ±12.5
main receiver is set to manual level control. MHz range is also equalized in this unit. A block
The subsequent “Amplifier IF & Flt BD” is diagram of these functions is shown in fig.36.
switched from automatic level control to a The Amplifier, IF & Filter, BP consists of the following
fixed amplification of 10 dB. functional blocks:
The slope equalizer is switched to “fixed
slope” (=0 dB). 1) AGC amplifier
The LED alarm “MGC ALM” on the front 2) Slope equalizer
is activated. This switch position is used 3) Phase equalizer
when manual control of the total system 4) SAW-filter
amplification is carried out. Total amplifi
cation can be adjusted, provided that the 1) AGC amplifier:
receiver input level is lower than approx.
-31 dBm. (AGC in LNA is inactivated). A switch at the front panel of the receiver can be set
Mode 2. The AGC is the normal operating position. in two positions:
The LED alarm “MGC ALM” is deactivated. a: AGC: Normal Operation
Mode 3. In position MGC SPACE the same actions as in b: MGC: Manual Operation
mode 1 take place, except that the main
receiver is attenuated and the diversity receiver The Automatic Gain Control has a dynamic range of
set to manual level control. Position MGC MAIN 34dB. Open loop gain from IF input to IF output is
is used for initial adjustment of the “Equalizer IF”, corrected by a voltage controlled attenuator to give a
main receiver part. constant output level of 0dBm over the specified
dynamic range.
Positions MGC MAIN or MGC SPACE are used to set
a fixed absolute time delay between the main- and The IF output level is detected and amplified in the
diversity receiver. feedback control circuit and used as control voltage
to the voltage controlled attenuator. A reference
The summation of the two signals is carried out in a voltage in the feedback control circuit is used to set
power combiner. the IF output level to 0dBm.
Combiner Control (COMB.CONTR.) In the MGC position the system is set to manual gain
control.The Amplifier, IF, is set to 10dB gain and the
The Combiner Control consists of an 8 bits Micro slope equalizer is set to 0dB slope.This position is
Controller (MC) with associated circuitry. The control used for initial adjustments of the Amplifier, IF.
31
L 29005 Rev.H 04.01.96 FS/Oeg
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2) Slope equalizer: 4) SAW filter:
Tilt of the signal spectrum, mainly because of selec- Half of the Nyquist filtering of the signal spectrum is
tive fading, is corrected by the slope equalizer. made by a SAW filter.
A deviation from flat signal spectrum is detected by
two resonant circuits, and is used to generate two
IF INP
control voltages. -20dBm
to 0dBm IF OUT
VOLTAGE SLOPE
Each control voltage adjusts the gain in two resonant CONTR.
ATTEN.
EQUA--
LIZER
PHASE
EQUALIZER
SAW
FILTER
0dBm
circuits (fo = 58MHz, 82MHz) in the slope equalizer to

optimize for flat and symmetrical spectrum.
fo = 58MHz
IF TEST
3) Phase equalizer: fo = 82MHz
FEEDBACK
CONTROL
-20dBm
The delay equalizer consists of two 2.order all- SWITCH

AGC
pass sections. These are adjusted to bring the MGC

+10V
AGC Amplifier delay deviations from flat delay of

the signal frequency range within the specified
requirements. Fig 36 Amplifier, IF & Filter, BP
3.2.2.5 ATPC The RF INP LVL may vary inside a window without
The automatic Transmitted Power Control-function activating the ATPC. Typical value for the window is
in the receiver is integrated in the Amplifier IF & Filter 10dB.
BP unit.
If the ATPC control signals are activated, two diodes
Fig. 37 illustrates the ATPC-function in the receiver mounted on the front of the receiver will indicate
group. A pot. meter available on front of the RCVR active control signals, respectively ATPC HIGHER or
can be used to set RF INP LVL (REF LVL). Adjust- ATPC LOWER. In order to avoid oscillation, a hyster-
ment range -25 to -50 dBm. esis is introduced, typical value 1 - 2 dB.
RF Inp
W indow H ysteres is
A T P C Low er O N
A T P C Low er O F F
R ef LV L
R F Inp
LV L
A T P C H igher O F F
A T P C H igher O N
TIME
Fig. 37 ATPC-function in the receiver
32 L 29005 Rev.H 04.01.96 FS/Oeg

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A simplified electrical diagram of the ATPC function is 3.2.3 Branching
shown in fig. 38.
DE T RF INP LVL
Two versions of the antenna branching system exist
+ A TP C LO W E R
as shown in figure 39 and figure 40.
RE F LVL A simplified sketch of a 3+1 branching system is
- shown in figure 39. The space diversity branching
system is shown in the lower part of the figure. The
T P901 channel filters are terminated by waveguide isolators
on both transmitter and receiver sides in order to
meet the required return loss specification. The
receiver side includes adaptors for SMA-connectors
+ A TP C HIGHE R to waveguide.
Co-channel branching, see para 2.1.2.
-
R EPE AT ER 3 + 1 S YST E M
T P902
XM TR / X MTR /
R CV R R C VR
SP-D IV SP-D IV
Fig. 38 Realization of ATPC function R C VR R C VR
PD R 7 0
The control signals ATPC HIGHER and ATPC

LOWER are transmitted to the XMTR-station via the D I G I T A L R A D I O -R E L A Y
S D H - S T M -1
D I G I T A L R A D I O -R E L A Y
S D H - S TM - 1
D I G I T A L R A D I O - R E LA Y
S D H - S T M -1
S D H - S T M-1
S D H - S T M -1
S D H - S TM - 1
DIG IT A L RA D IO- RE L A Y
S D H - S T M-1
S D H - S T M-1
DIG IT A L RA D IO- RE L A Y
S D H - S T M-1
modulator on the receiving station. EQ PTCOD E:

CH ANNEL:
ALARM
EQPTC ODE:
CHANN EL:
ALARM
EQPT CO DE:
C HANNE :L
ALARM
EQP TCO DE:

C HANN EL:
ALARM
E QPTCO DE:
C HAN NEL:
ALARM
EQP TCO DE:

C HANN EL:
ALARM
EQPTC ODE:
CHAN NEL:
L A
A RM
EQP TCO DE:

C HANN EL:
ALARM
EQPT CO DE:
C HANNE :L
ALARM
DI RECTIO N: DIR EC TION : D IRECTI ON: D IRECT O

IN: D IRE CTION : D IRECT O
IN: DIR ECTIO N: D IRECT O
IN: D IRECTI ON:
A B B N era MAIN SWITC HI NSID E A B B N er a M AIN SWI TCH N

I SIDE A B B N era MAIN SWITCH IN SIDE A BB N era MAIN SWITCH IN SIDE A B B N era MAI NSWIT CH N
I SID E A BB N era MAIN SWITCH IN SIDE A B B Ne ra MA
INW
S I TCH N
I SID E A BB N era MAIN SWITCH IN SIDE A B B N era MAIN SWITCH IN SIDE
SVC E C ha n Chan C ha n C h an C ha n C ha n C ha n Ch a n
Test points TP901 and TP902 allow continuous moni- ra ck pr ot 1 2 3 p ro t 1 2 3
toring of control signal status. T E R M IN A L 3 + 1 SY S TE M
ATPC HIGHER ATPC LOWER TX POWER Fig 39 Common branching, Transmitter/Receiver

0 0 No change 3+1 (Shown for 6 GHz version)
1 0 Increase
0 1 Decrease
R E PE ATE R 3+ 1 SY STE M
1 1 Incorrect state
S P -D IV M AI N
X M TR XMT R R CV R
RCV R
Truth table for the ATPC function MAI N S P - DIV

RC V R R CV R
PD R 7 0
D I G I T A L R A D I O - R E LA Y D IG I TA L R A D OI -R E L A Y D IG IT A L R A D I O - R E LA Y D I G I T A L R A D I O -R E L A Y D I G I T A L R A D I O -R E L A Y D I G I T A L R A D I O -R E L A Y D I G I T A L R A D I O -R E L A Y DIGIT A L RA D OI -R E L A Y D IG I TA L R A D OI -R E L A Y
SD H - S T M - 1 S D H - S T M-1 S D H - S T M-1 S D H - S T M-1 S D H - S T M-1 S D H - S T M-1 S D H - S TM - 1 S D H - S T M -1 S D H - S T M- 1
ALARM ALARM A L
A RM A L
A RM ALA RM ALAR M ALAR M
A LARM ALARM
E QP TCO DE: E QPT CO DE: EQ PT CO DE: EQ PTC OD E: EQ PTC OD E: EQP TCO DE : EQP TCO DE :
EQ PT CO DE: EQP TCO DE :
CH AN NEL: CHA NNEL : C HA NNEL: C HANN EL: C HANN EL: CH ANN EL: CH ANN EL: CHA NNE L: CHA NNE L:
DI REC TIO N: DR
I ECTI ON : D IR ECTI ON: D IREC TIO N: D IREC TIO N: DI REC TIO N: DI RECT O
I N: DR
I ECTI ON : DR
I ECTI ON :
ABB Nera MA IN SWI TCH I NSI DE ABB Nera M AI N SWITC HI NS D

I E A B B N era M AI NS WI TC HI NS D
IE A B B N e ra M AIN SWI TCH I NSI DE A B B N e ra MA IN SWIT CH I NSI DE A B B N e ra MAI N SWIT CH N
I SID E A B B N e ra MAI N SWIT CH N
I SID E A B B N er a M AI N SWITC H N
I SID E A B B N era M AI NS WI TC HI NS D
IE
SVC E Ch an C han Ch an C han Cha n Ch an Cha n Ch an

chan pro t 1 2 3 prot 1 2 3
TE R MI N AL 3+ 1 S YS TE M
Fig 40 Separate branching, Transmitter/Receiver

3+1 (Shown for 6 GHz version)
33
L 29005 Rev.H 04.01.96 FS/Oeg
Nera AS
T O A N TE NN A
C' C
B 'p B '1 B '2 B '3 Bp B1 B2 B3
A 'p A '1 A '2 A '3 Ap A1 A2 A3
PR O T C H AN C HAN 1 C HA N 2 CHAN 3 P R O T C H AN C H AN 1 C HAN 2 CHAN 3
F RO M A N TE NN A
X M T R 's R C V R 's
Bp B1 B2 B3
Ap A1 A2 A3
P R O T C H AN C H AN 1 C HAN 2 CHAN 3
S P A C E D I V E R S IT Y R C V R 's
Fig 41 3+1 branching with space diversity
3.2.3.1 Channel filter

The channel filters, one for each half-band, are of The radio racks are equipped with two types of power
waveguide bandpass type. The filter is constructed of supplies, one for the FET amplifier and two others for
silver coated invar. For frequencies below 5.9 GHz, the XMTRs and RCVRs. The FET power supply is
dielectric resonator filters are used. These types of mounted together with the Power Amplifier on a heat
filters presents very low insertion loss and excellent sink located in the upper part of the rack. The two
temperature stability. other power supplies are located in the lower part of
the rack. These power supplies are connected in
parallel, i.e. the outputs are connected together so
3.3 Power Supply that the load is shared by both units. If a failure in one
power supply occurs, the other supply will take over
the full load.
3.3.1 General
The primary DC-power is supplied to the racks via Both types of power supplies employ push-pull con-
main fuses and power switch. An input filter attenu- verters with a switching frequency of 100 kHz. The
ates the "Common Mode" noise before the power is XMTR/RCVR power supply has three converters
distributed to the individual power supplies. (+5 V, -5 V and ±15 V).
Power +9.4V
Power Switch
48V 48V Input Supply For
&
Filter FET-amplifiers
Fuse (1) -5V
+15V
Power +15V
-15V
Supply -15V For
+5V
+5V XMTR/RCVR
-5V
(2) -5V
Power +15V
Supply -15V
+5V
(3) -5V
Fig. 42 Power Supply
34 L 29005 Rev.H 04.01.96 FS/Oeg

Nera AS
4.0 LIST OF ABBREVIATIONS
A/D Analog to Digital Converter

AAU Alarm Adapter Unit
ACU Alarm Collection Unit
AIS Alarm Indication Signal
AGC Automatic Gain Control
ALC Automatic Level Control

ASF Alignment Switch Function
ASIC Application Specific Integrated Circuit
ATDE Adaptive Time Domain Equalizer
ATT Attenuator
BER Bit Error Ratio

CA Controlled Attenuator
CB Control Board
CEPT European Conference of Postal and Telecommunications Administration
CLK Clock
CMI Coded Mark Inversion

CPU Central Processor Unit
DC Direct Current
DIP Dual In-line Package
DM Degraded Minutes
DRO Dielectric Resonator Oscillator

DTMF Dual Tone Multi-Frequency
ECL Emitter Coupled Logic
EMC Electromagnetic Compatibility
EOW Engineering Order Wire
EPROM Erasable Programmable Read-Only Memory

EQL Equalizer
ES Errored Seconds
FB Filter Bank
FEC Forward Error Correction
FET Field Effect Transistor

FM Frequency Modulation
GaAs Gallium Arsenide
HBER High Bit Error Ratio
HDB3 High Density Bipolar (max. 3 "0")
I/O Input/Output
IF Intermediate Frequency
ITU-R International Telecom. Union (former CCIR)
ITU-T International Telecom. Union (former CCITT)
LBER Low Bit Error Ratio
35
L 29005 Rev.H 04.01.96 FS/Oeg
Nera AS
LCD Liquid Crystal Display
LD Level Detector
LED Light Emitting Diode
LIF Line Interface
LMS Least Mean Square
LNA Low Noise Amplifier

LO Local Oscillator
LPF Low Pass Filter
MC Micro Controller
MGC Manual Gain Control
MIL-STD Military Standard

MLE Maximum Level Error
MOD Modulator
MSOH Multiplexer Section Overhead
MST Multiplexer Section Termination
NE Network Element
NRZ Non Return to Zero
OSC Oscillator
PABX Private Automatic Branch Exchange
PAL Programmable Array Logic
PLL Phase Locked Loop

PLO Phase Locked Oscillator
PROM Programmable Read-Only Memory
PROT CH Protection Channel
PSCU Protection Switching Control Unit
PSK Phase Shift Keying

PWM Pulse Width Modulation
QPSK Quadrature Phase Shift Keying
RAM Random Access Memory
RCVR Receiver
RDDU Receiver Data Distribution Unit

REG CH Regular Channel
RF Radio Frequency
RPS Radio Protection Switching
RSOH Regenerator Section Overhead
RST Regenerator Section Termination

RU Relay Unit
SAW Surface Acoustic Wave
SCADA Supervision, Control And Data Acquisition
SDH Synchronous Digital Hierarchy
36 L 29005 Rev.H 04.01.96 FS/Oeg

Nera AS
SES Severely Errored Seconds

SIC Serial Interface Controller
SOH Section Overhead
SSB Single Side Band
SSS SDH Supervisory System
STM-1 Synchronous Transport Module (1 stands for 1x155 Mb/s)

SU Supervisory Unit
TCM Trellis Coded Modulation
TMN Telecommunication Management Network
TTL Transistor-Transistor Logic
UAT Unavailable Time

VC Virtual Container
VCO Voltage Controlled Oscillator
VCXO Voltage Controlled X-tal Oscillator
VLSI Very Large Scale Integration
XMTR Transmitter
XSU XMTR Switch Unit
37
L 29005 Rev.H 04.01.96 FS/Oeg
SYSTEM BLOCK DIAGRAMS
NL290 - Family
H2766 Rev. A
© Nera AS
System Diagrams NL290-Family
2
H2766
H2766
I-33455
CHN
140/155 Mb/s CMI splitter Modulator XMTR Group CHN
G.703
CH1
140/155 Mb/s CMI splitter Modulator XMTR Group CH1 XMTR
G.703 Branching
2 Mb/s BUS
CHP
140/155 Mb/s CMI splitter Modulator XMTR Group CHP
G.703
2 Mb/s BUS
XMTR Switch
Display unit
ACU SVCE ACU CHN AAU No1
MSOH Adapter SU
RSOH RPS ACU CHP ACU CH1 AAU No2
64 kb/s Adapter Adapter
64 kb/s Adapter 64 kb/s Adapter 64 kb/s Adapter
64 kb/s Adapter 2 Mb/s BUS
64 kb/s Adapter
Omnibus SVCE Teleph. Express SVCE Teleph.
RCVR Data Distribution
PABX Adapter
CHN
140/155 Mb/s Relay unit Demodulator RCVR Group CHN
G.703
IF-Equalizer
BLOCK DIAGRAM, N+1 TERMINAL

CH1
140/155 Mb/s Relay unit Demodulator RCVR Group CH1 RCVR
G.703 Branching
2 Mb/s BUS
IF-Equalizer
CHP
140/155 Mb/s Relay unit Demodulator RCVR Group CHP
G.703
2 Mb/s BUS
IF-Equalizer
I - 33455 BL O C K D IA G R A M , N + 1 TE R M IN AL
3
4
H2766
H2766
I-33481
CHN
140/155 Mb/s Modulator XMTR Group CHN
G.703
CH2
140/155 Mb/s Modulator XMTR Group CH2 XMTR
G.703 Branching
2 Mb/s BUS
CH1
140/155 Mb/s Modulator XMTR Group CH1
G.703
2 Mb/s BUS
Display unit
ACU SVCE ACU CHN AAU No1
MSOH Adapter SU
RSOH ACU CHP ACU CH1 AAU No2

64 kb/s Adapter Adapter
64 kb/s Adapter
PABX Adapter
CHN
140/155 Mb/s Demodulator RCVR Group CHN
G.703
IF-Equalizer
BLOCK DIAGRAM, N+0 TERMINAL

CH2
140/155 Mb/s Demodulator RCVR Group CH2 RCVR
G.703 Branching
2 Mb/s BUS
IF-Equalizer
CH1
140/155 Mb/s Demodulator RCVR Group CH1
G.703
2 Mb/s BUS
IF-Equalizer
5
I - 33481 B L O C K D IA G R A M , N + 0 T E R M IN A L
6
H2766
H2766
I-33479
CHN RCVR Group Demodulator Modulator XMTR Group CHN
IF-Equalizer
RCVR CH1 RCVR Group Demodulator Modulator XMTR Group CH1 XMTR
Branching Branching
2 Mb/s BUS
IF-Equalizer
CHP RCVR Group Demodulator Modulator XMTR Group CHP
2 Mb/s BUS
IF-Equalizer
Display unit
ACU CHP DIR2 ACU CH1 DIR2 ACU CHN DIR2 ACU SVCE AAU No1
SU
RSOH ACU CHP DIR1 ACU CH1 DIR1 ACU CHN DIR1 AAU No2
64 kb/s Adapter
Adapter
64 kb/s Adapter
PABX Adapter
CHN XMTR Group Modulator Demodulator RCVR Group CHN
IF-Equalizer
BLOCK DIAGRAM, N+1 REPEATER

XMTR CH1 XMTR Group Modulator Demodulator RCVR Group CH1 RCVR
Branching Branching
2 Mb/s BUS
IF-Equalizer
CHP XMTR Group Modulator Demodulator RCVR Group CHP
2 Mb/s BUS
IF-Equalizer
I - 33479
B LO C K DIA G RA M , N+ 1 R E P E A TE R
7
8
H2766
H2766
I-33482
CHN RCVR Group Demodulator Modulator XMTR Group CHN
IF-Equalizer
RCVR CH2 RCVR Group Demodulator Modulator XMTR Group CH2 XMTR
Branching Branching
2 Mb/s BUS
IF-Equalizer
CH1 RCVR Group Demodulator Modulator XMTR Group CH1
2 Mb/s BUS
IF-Equalizer
Display unit
ACU CHP DIR2 ACU CH1 DIR2 ACU CHN DIR2 ACU SVCE AAU No1
SU
RSOH ACU CHP DIR1 ACU CH1 DIR1 ACU CHN DIR1 AAU No2
64 kb/s Adapter
Adapter
64 kb/s Adapter
PABX Adapter
CHN XMTR Group Demodulator CHN

Modulator RCVR Group
IF-Equalizer
BLOCK DIAGRAM, N+0 REPEATER

XMTR CH2 XMTR Group Modulator Demodulator RCVR Group CH2 RCVR
Branching Branching
2 Mb/s BUS
IF-Equalizer
CH1 XMTR Group Modulator Demodulator RCVR Group CH1
2 Mb/s BUS
IF-Equalizer
I - 33482
B L O C K D IA G R AM , N +0 R E P EA T E R
9
TRANSMITTER GROUPS, incl. ATPC
NL290 - Family
H2600 Rev. C
© Nera ASA
Transmitter Groups, SDH
TABLE OF CONTENTS
Paragraph Page
Block Schematic Diagrams, Transmitters 3-8
1. TECHNICAL DATA 9
2. DESCRIPTION 9
2.1 General 9
2.2 Functional Description 9
2.2.1 Transmitter Groups without ATPC 9
2.2.2 Transmitter Groups with ATPC 10
3. UNIT DESCRIPTIONS 12
3.1 Upconverter 12
3.1.1 Technical Data 12
3.1.2 General Description 13
3.2 Amplifier, Power 14

3.3 Oscillator, w/PLL 16

3.3.3 Functional 18
3.3.4 Channel Frequency Setting 18
3.4 Multiplier x2 19
3.4.2 Functional Description 19
3.5 Alarm Circuit Board, EJ148A 19

3.5.3 Alarms 19
3.5.4 Meter Reading/Recording 20
3.6 Alarm Circuit Board, EJ48B/C (with ATPC) 20

3.6.3 Alarms 20
3.6.4 Meter Reading/Recording 20
3.7 Indicator Board, EJ156A 21
2 H2600
UPCONVERTER AMPLIFIER, POWER
IF INP DET PRE DET DET RF OUT

dB DIST. dB
RF MON
15 19
P1
18
MATCH R16
OSCILLATOR MATCH R11
PLL DET
OSC
MATCH R18
LO MON.
MATCH R1, R3, R 5, R7

STRAP
P2
16
MA TCH R2, R4, R6, 68

STRAP 2 1 RF
POWER OUT ALARM
13
XMTR ALM
5
1 +15 V
+5 V
2 MATCH R56
-3dB
3
2 5 XMTR LO ALARM
4
-6dB
-10dB
DISPLAY BOARD 7
EJ156A MATCH R59
2 3 IF INPUT ALARM
ALARM BOARD, EJ148A
Fig. 1a Block Schem. Diagram, TX- Groups, SDH, 10XNU442/443, 4GHz
H2600
3
UPCONVERTER AMPLIFIER, POWER

DET PRE DET DET
IF INP RF OUT
dB DIST. dB
RF MON
15 18 19 P1
ADJ R24
ADJ R22
OSCILLATOR
PLL DET
OSC ref
LO MON. r ef
28 ATPC XMTR
ADJ R50, R14, R16, R18

DIP SWITCH
Nom.
-3 P2
MTPC -6
- 10
16 32 ATPC ALM
17 ADJ R4, R6, R8, R10
DIP SWITCH
-1 21 RF
13 -2
POWER OUT ALARM
ATPC
XMTR ALM -4
5 -8
1 +15V
+5V
2 ADJ 84
RED
3
25 XMTR LO ALARM
ATPC ON 4
ATPC ALM ref
DISPLAY BOARD 7
EJ156A
ref
23 IF INPUT ALARM
ref
ALARM BOARD, EJ148B/C
Fig. 1b Block Schem. Diagram, TX- Groups, SDH, 10XNU442/443, 4GHz with ATPC
4 H2600
UPCONVERTER AMPLIFIER POWER
DET P RE DET DET

IF INP R F OUT
dB DIST . dB
15 18 19
P1
MATCH R16
O SC ILL AT O R MATCH R11
PLL DET
OSC
MATCH R18
L O M ON.
MATC H R 1, R3, R5, R7

STRA P
P2
16
17 MA TCH R2, R4, R6, 68

STRA P 21
RF
POW ER OUT ALA RM
13
X MTR ALM
5
1
1 + 15 V
+5 V
2 MATCH R56
3
2 5 XM TR L O A LA RM
4
DISPLAY BOARD 7
E J156A
MATCH R59
2 3 IF INPU T AL AR M
A LA RM BO ARD , EJ148A
Fig. 2a Block Schematic Diagram, Transmitter Groups, SDH, incl. 6GHz - 8GHz.
H2600
5
DE T P RE DET
IF IN P DET RF OUT
dB D IS T. dB
15 18 19 P1
ADJ R24
ADJ R22
O S C ILLA TO R
PLL D ET
OSC ref
LO MON. r ef
28 ATPC XMTR
ADJ R50, R14, R16, R18

DIP SWITCH
Nom.
-3 P2
MTPC -6
- 10
16 32 ATPC ALM
17 ADJ R4, R6, R8, R10
DIP SWITCH
-1 21 RF
13
POWER OUT ALARM
ATPC -2
XM TR A LM -4
5 -8
NOM 1 +15V
+5V
2 ADJ 84
RED
3
25 XMTR LO ALARM
ATPC ON 4
ATPC ALM ref
DISPLAY BO ARD 7
E J156A
ref
23 IF INPUT ALARM
ref
ALARM BOARD, EJ1 48 B/C
Fig. 2b Block Schem. Diagram, TX-Groups, SDH, incl. 6GHz - 8GHz with ATPC
6 H2600
DET PR E DET DET

IF INP R F OUT
dB DIS T. dB
15 18 19
P1
MATCH R16
MU LT IP LI ER X2 MATCH R11
f DET
2f
MATCH R18
L O MON .
O SC IL L AT O R MAT CH R1, R3 , R5, R7

STRA P
P LL
P2
OS C
16
17 M AT CH R 2, R4, R6, 68
STRA P
21
RF
13
POWER OUT ALA RM
X MTR ALM
5
1
1 + 1 5V
+ 5V
2 MATCH R56
3
2 5 XM TR L O AL A RM
4
DISPLA Y BOARD 7
EJ1 56A
MATCH R59
2 3 IF INPUT A LA RM
A LA RM B OAR D, EJ14 8A
Fig. 3a Block Schematic Diagram, Transmitter Groups, SDH, 11GHz & 13GHz
H2600
7
DET PR E DET
IF IN P DET RF O UT
dB DIS T. dB
15 18 19 P1
ADJ R24
M U LTI PL IE R X 2 ADJ R22
f D ET
2f ref
LO MO N. ref
28 ATPC XMTR
O SC ILL AT O R ADJ R 50, R 14, R16, R18

DIP SWITCH
Nom.
PLL -3 P2
OSC MTPC -6
- 10
16 32 ATPC ALM
17 ADJ R4, R6, R8, R10
DIP SWITCH
-1 21 RF
13 -2
POWER OUT ALARM
AT PC
XMT R AL M -4
5 -8
NOM 1 +15V
+5V
2 ADJ 84
RED
3
25 XMTR LO ALARM
ATPC ON 4
ref
ATPC ALM
DIS PLAY BOARD 7
E J156A
r ef
23 IF INPUT ALARM
ref
AL ARM BOARD, EJ148B/C
Fig. 3b Block Schem. Diagram, TX-Groups, SDH, 11GHz & 13GHz with ATPC
8 H2600
1 TECHNICAL DATA
Input frequency : 70MHz The transmitted specter is modulated by 128
Input level : 0dBm TCM or 64 TCM. This modulation require
Input impedance : 75ohm high linearity. To provide high linearity of the
Output frequency range : *) transmitter group, the transmitter is linearized
Frequency stability : ±5 ppm by an IF-predistortion circuit.
Output level : *) The upconverter is a high linearity single
Output port : *) sideband converter. Input level from the LO is
17dBm. A voltage controlled phase shifter is
*) See Table, page 11 used for the cancellation of the LO-signal at
the RF-output of the upconverter. In addition a
2 DESCRIPTION predistortion circuit, a slope equalizer, an IF-
2.1 General: amplifier and an attenuator, which is used to
controll the output level, are placed in the
upconverter. The predistortion circuit has to be
The Transmitter Groups, SDH, are composed
adjusted at the actual RF-channel.
of the following units:
The local oscillator is a voltage tuned DRO.
Upconverter, : *)
The VTDRO is locked to a 10MHz reference
Amplifier Power, : *)
oscillator.A programable synthesizer circuit is
Oscillator, : *)
used in the PLL-circuit. The unit has output for
Multiplier x2, : *)
PLL alarm and output level detector. These
Alarm Circuit Board : EJ148A/B/C
outputs are combined to an XMTR LO alarm
Indicator Circuit Bd : EJ156A
at the alarm circuit board. In addition, the
alarm circuit board provides outputs to the me-
*) See Table, page 11
ter unit for varactor voltage reading and output
level reading.
Power Supply, 48V : 0PR147B
Power Supply, 24V : 0PR159B
An attenuator is included at the input of the
power amplifier, and a level detector at the
(See separate description for Power Supplies)
output. Both the attenuator and the detector
are used in the AGC-loops of the transmitter.
The detected voltage is used for RF PWR
2.2 Functional: OUT ALM and meter reading.
2.2.1 Transmitter Groups
without ATPC: The transmitter group is controlled by an
AGC-loop and an ALC-loop, which is located
(Ref. Block Schem. Diagrams, page 3-8) at the alarm circuit board. At high output lev-
els, from nominal to -6dB, the AGC-loop that
The 70MHz IF input signal is converted by the
control the power amplifier is constant, and the
local oscillator (LO) to a channel in the RF-
output level is regulated by the ALC-loop. At
frequency band. The output power from the
lower output levels the gain in the AGC-loop
Transmitter Group can be set to four different
that control the power amplifier is reduced.
output levels by a dipswitch at the alarm circuit
The ALC-loop provide right output level. At
board. These output levels are: nominal, -3dB,
EJ148A, MGC/AGC is set by 2 mini-jumpers
-6dB and -10dB. An LED at the front of the
at the alarm circuit board. A switch at the front
transmitter group shows the output level from
of the transmitter group turns the power ampli-
the transmitter group.
fier ON/OFF.
H2600
9
2.2.2 Transmitter Groups with

ATPC
The 70MHz IF input signal is converted by the output. Both the attenuator and the detector
local oscillator (LO) to a channel in the RF- are used in the AGC-loops of the transmitter.
frequency band. The output power from the The detected voltage is used for RF PWR
Transmitter Group can be set to four different OUT ALM and meter reading. Amplifiers used
output levels by a dipswitch at the alarm circuit in transmitter groups with ATPC, include a cir-
board. These output levels are: nominal, -3dB, cuit that reduces the power consumption at
-6dB and -10dB. An LED at the front of the low output levels. The reduction in power con-
transmitter group indicates if the output level sumption is linear and will start when the out-
is nominal or reduced. put level is reduced to -3dB of nominal output
The transmitted specter is modulated by 128 level. Max. reduction is close to 10W at
TCM or 64 TCM. This modulation require approx. -15dB reduced output level.
high linearity. To provide high linearity of the
transmitter group, the transmitter is linearized The transmitter group is controlled by an
by an IF-predistortion circuit. AGC-loop and an ALC-loop,which is located
The upconverter is a high linearity single at the alarm circuit board. At high output lev-
sideband converter. Input level from the LO is els, from nominal to -6dB, the AGC-loop that
17dBm. A voltage controlled phase shifter is control the power amplifier is constant, and the
used for the cancellation of the LO-signal at output level is regulated by the ALC-loop. At
the RF-output of the upconverter. In addition a lower output levels the gain in the AGC-loop
predistortion circuit, a slope equalizer, an IF- that control the power amplifier is reduced.
amplifier and an attenuator, which is used to The ALC-loop provide right output level. In
controll the output level, are placed in the ATPC- mode, an input control voltage regu-
upconverter. The predistortion circuit has to be lates the output level. Maximum attenuation in
adjusted at the actual RF-channel. ATPC-mode is -15dB. When the transmitter
group is in ATPC-mode, an LED at the front of
The local oscillator is a voltage tuned DRO. the transmitter group will be ligthed. An input
The VTDRO is locked to a 10MHz reference ATPC alarm regulates the output level to a pre-
oscillator.A programable synthesizer circuit is set ATPC-level. The preset level can be preset
used in the PLL-circuit. The unit has output for by a DIP-switch to nominal output level, or to
PLL alarm and output level detector. These a preset value from -1dB to -15dB in step of
outputs are combined to an XMTR LO alarm 1dB. When the transmitter group has received
at the alarm circuit board. In addition, the an ATPC alarm, this is indicated by an LED at
alarm circuit board provides outputs to the me- the front of the group. At EJ148B, MGC/AGC
ter unit for varactor voltage reading and output is set by 2 mini-jumpers at the alarm circuit
level reading. board. At EJ148C this function is moved to a
switch at the front of the Transmitter group. It
An attenuator is included at the input of the is the same switch that turns the power ampli-
power amplifier, and a level detector at the fier ON/OFF.
10 H2600
Table for Chapter 2.1, General. Transmitter Groups
Freq. Range XMTR XMTR XMTR XMTR XMTR XMTR Output Output
GHz 48V 24V w/ATPC w/ATPC +2dB +2dB Port Power
10XNU.... 10XNU.... 48V 24V 48V 24V dBm
10XNU.... 10XNU.... 10XNU.... 10XNU....
3.6 -3.7 443AF SMA, F 31.0

3.6 - 3.9 443AA 442AA 460AA 482AA 477AA 490AA SMA, F 31.0
3.6 - 3.9 443AB 442AB 460AB 482AB 477AB 490AB SMA, F 31.0
3.9 - 4.2 443BD 442BD 460BD 482BD 477BD 490BD SMA, F 31.0
3.8 - 4.0 443CC 442CC 460CC 482CC SMA, F 31.0
4.0 - 4.2 443DE 442DE 460DE 482DE 477DE 490DE SMA, F 31.0
4.4 - 4.7 461A 483A SMA, F

4.7 - 5.0 461B 483B SMA, F
5.9 - 6.175 433A 434A 462A 484A UER 70 30.5

6.175 - 6.4 433B 434B 462B 484B UER 70 30.5
6.4 - 6.77 447A 448A 463A 485A 478A 493A UER 70 30.5
6.77 - 7.1 447B 448B 463B 485B 478B 493B UER 70 30.5
7.1 - 7.275 464AA 486AA UER 84 29.5

7.275 - 7.45 464AB 486AB UER 84 29.5
7.4 - 7.55 441BB 452BB 464BB 486BB UER 84 29.5
7.4 - 7.66 441BC 452BC UER 84 29.5
7.58 - 7.725 441BD 452BD 464BD 486BD UER 84 29.5
7.7 - 7.9 441CE 452CE UER 84 29.5
7.7 - 8.0 453A 454A 465A 487A UER 84 29.5

8.0 - 8.3 453B 454B 465B 487B UER 84 29.5
10.7 - 11.2 455A 456A 479A 496A UER120 27.9

11.2 - 11.7 455B 456B 479B 496B UER 120 27.9
12.75 -13.0 446A 457A 467A 489A UER 120 27.5

13.0 - 13.25 446B 457B 467B 489B UER 120 27.5
H2600
11
3 UNIT DESCRIPTIONS
3.1 Upconverter:
3dB
180 ° dB
0 dB m 75 ohm 3dB
dB 90°
5 0oh m
Σ
IF
dB
IN P U T IF O U T
3dB
180 °
LEVE L
IF IN P U T D ET E C T O R
ALA RM dB τ
IF-Predistortion
Fig.4
Σ
Upconverter Section
3.1.1 Technical Data:

Frequency range, RF : See Table, page 13 Without predistortion:
Frequenxy range, LO : See Table, page 17 3rd order IMD : <-44dBc
IF frequency : 70MHz (Two carriers, 70 ± 5MHz, each 3dB below
IF level in : 0 ±0.5dBm nominal output level)
LO level in : 17 ±1.0dBm
RF level out : -6 ±1.0dBm Amplitude/frequency response:
Group delay : < 1.0ns FO ± 18MHz : <0.2dB
IF return loss, IF connector : IEC 169-13 (1.6/5.6)
70± 18MHz : 26dB LO, RF connector : SMA, female
RF return loss : >10dB
LO return loss : >14dB Required sideband can be selected by
strappings in the box. LO leakage and
Spurious: unwanted sideband can be adjusted by
IF : <-40dBm potentiometers.
LO : <-33dBm
Unwanted sideband : <-38dBm
Temp.range : -5°C to +65°C
DC bias : +15, ±0.5V
12 H2600
3.1.2 General Description:

the main signal.
The Upconverter consists of the following The Amplifier IF Board contains low pass
subunits: (See Table below) filter, 90° power splitter and amplifiers for the
Predistortion IF Board, EFUR290A, Amplifier two outputs. The low pass filter reduces the
IF Board EU156, SSB Upconverter substrate LO ±2 x IF component in the output
and Phase-shifter substrate. spectrum. Two outputs with 90° phase
See the Block Schematic Diagram, page 12. difference is needed for SSB conversion. The
two output signals can be adjusted in amplitude
The Predistortion IF Board has the following and phase to reduce unwanted sideband. The
functions (listed in signal path order): board also contains necessary DC network for
IF input detector, voltage controlled attenuator LO cancellation control and bias to the mixing
for AGC, slope equalizer, IF amplifier, predis- diodes.
tortion network and IF output detector. The The SSB upconverter is a linear image reject
slope equalizer is adjusted for the actual frequ- type. Some of the LO signal at the input is
ency to maintain flat response through the trans- tapped off and applied to a 360º phase shifter.
mitter group. The predistortion function is based By adjusting two DC voltages, this LO
on two limiters, operating with 90° phase component is controlled in amplitude and
difference and individual level control. This gives phase. This LO component is added in the
a distortion component controllable in amplitude upconverter output and is adjusted to cancel
and phase. This distortion component is added to the upconverter LO leakage.
Table for Chapter 3.1.1. Frequency Dependent Technical Data.

UPCONVERTERS in Tx-Groups with or without ATPC.
Upconverter Upconverter
in TX-groups in TX-groups RF-frequency Output level Ampl.IF
with ATPC without ATPC GHz dBm Board
10NU475A 10NU475A 3.6-3.9 -8 ±1 EU156C

10NU475B 10NU475B 3.8-4.2 -8 ±1 EU156C
10NU429A 10NU429A 5.9-6.4 -8 ±1 EU156A
10NU477A 10NU477A 6.4-7.1 -8 ±1 EU156A

- 10NU513A 7.1-7.7 -8 ±1 EU156A
10NU513B 10NU513B 7.4-7.9 -8 ±1 EU156A
- 10NU460A 7.7-8.3 -8 ±1 EU156A

10NU419A 10NU419A 10.7-11.7 -9 ±1 EU156B
- 10NU419B 11.2-11.7 -9 ±1 EU156B
- 10NU525A 12.75-13.25 -11 ±1 EU156A
10NU571A - 4.4-5.0 -8±1 EU156A
H2600
13
3.2 Amplifier, Power:

Amplifier, Power in Tx-Groups with or without ATPC.
Ampl. Ampl. RF freq., Nom gain Outp.pwr,dBm No of ampl. Output Ref.fig.

with without GHz dB Low High stages port
ATPC ATPC
- 10U382A 3.6-3.9 44 ±2 30.9 32.9 2+1+2 SMA, F 5a

- 10U382B 3.8-4.2 44 ±2 30.9 32.9 2+1+2 SMA, F 5a
10U427A - 3.6-3.9 46 ±2 32.7 2+1+2 SMA, F 5a

10U427B - 3.8-4.2 47 ±2 33.0 2+1+2 SMA, F 5a
10U420B - 3.8-4.2 45 ±2 31.0 2+1+2 SMA, F 5a
10U414A - 4.4-5.0 44 ±2 30.7 2+1+2 SMA, F 5a
- 10U377A 5.9-6.4 44 ±2 30.7 2+1+2 UER70 5b

10U421A - 5.9-6.4 39 ±1 31.0 2+1+2 UER70 5b
10U384A 10U384A 6.4-7.1 44 ±2 30.7 32.6 2+1+2 UER70 5b

10U384B 10U384B 6.75-7.1 39 ±1 31.0 32.6 2+1+2 UER70 5b
10U422A - 6.4-7.1 42 ±2 31.0 2+1+2 UER70 5b
10U430A - 6.4-7.1 44 ±2 32.8 2+1+2 UER70 5b
- 10U401A 7.1-7.7 43 ±1 29.6 2+1+2 UER84 5b

- 10U401B 7.4-7.7 43 ±2 29.7 2+1+2 UER84 5b
10U431B - 7.4-7.9 44 ±2 29.7 2+1+2 UER84 5b
- 10U370A 7.7-8.3 43 ±2 29.7 2+1+2 UER84 5b
- 10U330A 10.7-11.2 42 ±2 28.0 2+2+2 UER120 5b

- 10U330B 10.2-11.7 42 ±2 28.0 2+2+2 UER120 5b
- 10U408A 12.75-13.00 46±1 27.3 3+2+2 UER120 5b

- 10U408B 13.00-13.25 46±1 27.3 3+2+2 UER120 5b
14 H2600
R F IN DET RF OUT
dB
RF ATT RF MON .
RF DET
REGULATOR BOARD
Fig. 5a
R F IN RF OUT
DET
dB
RF ATT RF DET
REGULATOR BOARD
Fig.5b
Frequency range : See Table 3.2.1 (Measured with 2 carriers; output level on each
Frequency range : * carrier is 29.0dBm.)
Input impedance : 50ohm
Output impedance : 50ohm
Input level : -6dBm
Output level : *
Gain : *
3.order IMD : <-37dBc
*) See Table.
H2600
15
The amplifier is designed for high linearity. It has A temperature stable diode detector at the am-
3 GaAs FET amplifier sections. A regulator plifier output is used for AGC and power moni-
board, URR6 provides adjustable bias for the tor. Variants above 4.2GHz have integrated tran-
FETs. The first section has a voltage controlled sition to waveguide output. The 4GHz variant
attenuator for AGC followed by 2- to 3-stage has a directional coupler for XMTR monitor.
amplifier depending on frequency band. The sec- The regulator board used in the transmitter
ond section is a 1- to 2-stage medium power groups with ATPC is URR9. URR9 has a circuit
amplifier. The third section is a 2-stage power which reduces the power consumption at low
amplifier with internal matched GaAs FETs. output levels.
3.3 Oscillator w/PLL:
Fig.6 Block Schematic Diagram Oscillator
3.3.1 Technical Data: 3.3.2 General Description:
Frequency range : See Table, 3.3.1, page 17 The Oscillator contains the Phase Lock Board,
Output power : 17.5 ±1dBm EXD118A--K, according to Table 3.3.1,
Monitor power : >-10dBm page 18.
Freq.stability : ±5 ppm
Power det. level : >100mV For frequency range, ref. Table 3.3.1.
PPL alarm
alarm : 5V
no alarm : 0-0.5V
Varactor voltage : 0 to +13V
Input voltage : +15V/35mA, +5V/250mA
16 H2600

OSCILLATORS in Tx-Groups with or without ATPC.
In TX-groups In TX-groups
with without
ATPC ATPC Frequency band PLL-Board
10X398A 10X398A 3680.0-3780.0 EXD118E

10X398B 10X398B 3740.0-3840.0 EXD118E
10X398C 10X398C 3840.0-3953.0 EXD118E
10X398D 10X398D 3980.0-4080.0 EXD118F
10X398E 10X398E 4054.0-4165.0 EXD118F
10X468A - 4.480-4.600 EXD118M

10X468B - 4.800-4.920 EXD118M
10X372A 10X372A 5993.80-6104.15 EXD118A

10X372B 10X372B 6245.84-6356.19 EXD118A
10X401A 10X401A 6510-6670 EXD118D

10X401B 10X401B 6850-7010 EXD118D
- 10X430A 7051.0-7163.0 EXD118G

10X430B 10X430B 7368.5-7484.0 EXD118G
10X430C 10X430C 7452.5-7568.5 EXD118G
10X430D 10X430D 7666.0-7781.5 EXD118H
10X430E 10X430E 7753.5-7869.0 EXD118H
- 10X391A 7796.30-7906.65 EXD118C

- 10X391B 8107.62-8217.97 EXD118C
10X384A 10X384A 5392.5-5542.5 EXD118B

10X384B 10X384B 5657.5-5807.5 EXD118B
- 10X440A 6403.5-6459.5 EXD118K

- 10X440B 6536.5-6592.5 EXD118K
H2600
17
3.3.3 Functional:
Ref. Osc. Block Schem. Diagram, page 16.

The output from the phase detector is filtered
The main oscillator is a Voltage Tuned Dielectric through the loop filter and goes to the varactor
Resonator Oscillator (VTDRO). diode in the VTDRO. The values for the different
This oscillator can be coarsely tuned 120MHz dividers are programmed in the PROM, and the
by a tuning screw. The electronic tuning range channel frequencies can be chosen by the channel
of this oscillator is approx. 5MHz. switch.
The SHF-oscillator is locked to a 10MHz 3.3.4 Channel Frequency

Crystal Oscillator (TCXO) through a single Setting:
loop synthesizer circuit. The main purpose of this
loop is to control the frequency drift of the Channel frequency is set by selecting the
VTDRO caused by temperature changes and corresponding combination channel switch S1
aging. A major part of this loop consists of a on EXD118 (CHAN SELECT), a 5-bit
synthesizer IC. mechanical dual in-line switch.
A tuning screw (FREQ TUNE), which coarsely
A part of the output from the VTDRO is divided tunes the VTDRO, is then adjusted until the
by 8 to approx. 750MHz with a GaAs tuning voltage (13CP13 VCO VOLT) on the
prescaler.This signal goes into a dual modulus VTDRO is stable at about 4.5V.
counter (128/129). This counter is controlled by This is to be the voltage when the nut is locked.
the synthesizer IC, and works together with Output power is adjusted to nominal level by
the internal counters (/N,/A) as a programmable tuning a variable resistor, R20 on EXD118
counter. (PWR ADJ). Frequency can be fine adjusted by
The signal from the reference oscillator is a tuneable capacitor included in the refe-
divided by internal counters (/R,/2) to the rence oscillator IC7 on EXD118 (FREQ ADJ).
appropriate frequency, and the signals from the Functions needed for channel frequency setting
reference and the SHF-oscillator are compared at are reached by removing a small cover placed
approx. 50 kHz. above the phaselock loop board.
RF MON
RF IN F RF OUT
2F
DET
PWR DET
+5V DC NETWORK
- 5V
Fig. 7 Block Schematic Diagram, Multiplier x2
18 H2600
3.4 MULTIPLIER x2:

10N457A: 10N527A:
Frequency range, input : 5.392-5.808MHz 6.403-6.593MHz

Frequency range, output : 10.785-11.615MHz 12.806-13.186MHz
Power level input : 17 ±1dBm
Power level output : 18 ±1dBm
Power level monitor : > -10dBm
Power detector level : >100mV
Return loss : < -14dB
1. and 3. harmonic : < -40dBc
Input voltage : -5V/5mA
+5V/65mA
3.4.2 Functional Description: for the XMTR GROUP.

(ref. Schematic Diagram, Fig.7, page 18) * to amplify analogue voltages for meter
reading and recording.
The Multiplier Unit is a single substrate microstrip * to distribute voltages to XMTR GROUP
design, fitted into a separate box. The required units.
±5VDC power supplies and the RF level detector * contains loop amplifiers for AGC in
are fed through RF filters, and the RF-connectors PREDISTORTION UNIT and POWER
are SMA female. AMPLIFIER with straps to select
between four different RF-output
The 17dBm RF input signal is initially attenuated powers.
to an optimum input level for the succeeding FET
based multiplier stage. A nominal output level of
3.5.3 Alarms:
18dBm is obtained by means of a balanced buffer
Three alarms are generated and again combi-
amplifier, thus also achieving a good output
ned to one main alarm for the unit. This is done
return loss.
by operational amplifiers which have positive
3.5 ALARM CIRC. BD, EJ148A: feedback giving a hysteresis of 0.5-1dB.
(see XMTR Main Block Diagram, page3-8) NPN-transistors give alarm with open collector,
protected by 5.2V zener diodes.
1) LO ALM: when the oscillator-power has
Input voltages :+15V/20mA dropped about 4dB below nominal level
+5V/35mA, nominal or when the oscillator phase locked loop
50mA max. at ALARM is out of lock.
3.5.2 Functional Description: 2) IF INP ALM: when input level on the

group has dropped about 4dB below
The board has the following functions: nom. level.
* to generate alarms from analogue
detected voltages. 3) RF PWR OUT ALM: when output level
* to combine alarms to one main alarm has dropped about 4dB below nom.
level.
H2600
19
3.5.4 Meter Reading/Recording:
1) LO VARACTOR VOLTAGE to meter

power, or from -1dB to -15dB in steps of
is nom. +5V.
1dB.
* contains a MGC/AGC-operation. At
2) RF PWR OUT to meter +2V at
EJ148B the MGC/AGC-operation is set by
nom. output power.
2 mini-jumpers at the alm. circ. board.
When EJ148C is mounted in the TX-group,
3) RF PWR OUT to recorder is +2V at
the MGC/AGC-switch is placed at the front
nom. output power.
of the TX-group. It is the same switch
which turns the Power Amplifier ON/OFF.
4) LO LEVEL to meter is +2V at nom.
oscillator power.
3.6.3 Alarms:
3.6 ALARM CIRCUIT BOARD,
Four alarms are generated and combined to one
EJ148B/C, with ATPC: main alarm for the unit. This is done by operational
amplifiers which have positive feedback giving
3.6.1 Technical Data: hysteresis of 0.5-1dB. NPN- transistors give
alarm with open collector, protected by 5.2V
Input voltages :+15V/20mA zenerdiodes.
+5V/35mA, nominal 1. LO ALM when the oscillator-power has
50mA max. at ALARM dropped about 4dB below nominal level or
when the oscillator phase locked loop is out
3.6.2 Functional Description: of lock.
2. IF INP ALM when the input level on the
The board has the following functions: group has dropped 4dB below nom. level.
* to generate alarms from analogue
detected voltages. 3. RF PWR OUT ALM when the output level
* to combine alarms to one main alarm has dropped about 4dB below the selected
for the XMTR GROUP. output level.
* to amplify analogue voltages 4. MGC ALM when the XMTR GROUP is
for meter reading and recording. strapped or switched to MGC.
* to distribute voltages to XMTR GROUP
units. When a ATPC ALM is received, this is indicated
* contains loop amplifiers for AGC in at the front of the XMTR GROUP, but this ALM
Predistortion Unit and Power Amplifier is not combined with the main alarm for the unit.
with DIP-switch to select between 4
different RF-output powers (nominal 3.6.4 Meter Reading/Recording:
output level, -3dB, -6dB and -10dB).
* contains Automatic Transmit Power 1. LO VARACTOR VOLTAGE to meter
Control (ATPC) which regulates the RF- is nom. +5V.
output power from a control voltage. The 2. RF PWR OUT to meter is +2V at nom.
control voltage is received from the output power (ref. to XMTR GROUP
Receiver at the opposite station. with standard output level, not High Pwr.)
* contains an ATPC-alarm unit, which locks 3. RF PWR OUT to recorder is +2V at nom.
the RF-output power to a preset value, output power (ref. to XMTR GROUP
each time the alm.cir.board receives an with standard outp. level, not High Pwr.)
ATPC-alarm. The preset values can be 4. LO LEVEL to meter is +2V at nom. output
preset with DIP-switch to nominal output level from oscillator.
20 H2600
3.7 INDICATOR BOARD,

EJ156A:
(See XMTR Main Block Schematic,

page 3-8)
One LED indicates XMTR GROUP
ALARM.
A four-part LED indicates nominal output
power; NOM, or reduced output level;
RED, ATPC ON on and ATPC ALM.
H2600
21
RECEIVER GROUPS, incl. ATPC
NL290 - Family
H2598 Rev. D
© Nera ASA
Receiver Groups, SDH
TABLE OF CONTENTS
Paragraph Page
1. TECHNICAL DATA 3
2. DESCRIPTION 3
2.1 General 3
2.2 Functional 3
2.2.1 MGC Mode 3
2.2.2 Meter/Recorder Readings Aalarms 3
3. UNIT DESCRIPTION 5
3.1 LNA & Mixer Unit 5
3.2 OSCILLATOR 6
3.2.2 Functional 6
3.2.4 Channel Frequency Setting 7
3.3 MULTIPLIER x2 8
3.4 AMPL IF & FILTER,BP,8UF337C 9

3.5 AMPLIFIER IF, 8U357A 11

3.5.3.1 Input Match and Buffer 12
3.5.3.2 AGC/MGC 12
3.5.3.3 Output Match 12
3.5.3.4 Input Power Measurement 12
3.5.3.5 AGC/MGC Switch 12
3.5.3.6 AGC/MGC Switch (New, October 1997) 12
2 H2598
1 TECHNICAL DATA
Input freq. range : See Table, page 4 2.2 Functional:
Input level : Max. -19dBm 2.2.1 MGC Mode:
Input impedance : 50 ohm
Output frequency : 70Mhz The MGC mode (Manual Gain Control) is
Output level : 0dBm selected by switch 19S1 to pos. MGC MAIN.
Output impedance : 75 ohm The AGC/MGC switch 19S1,MGC ALM
Test output level : -20dBm indicator 19H1 and MGC ADJ potmeter are part
Test output impedance : 75 ohm of Amplifier IF (8U357A), but are all available
Noise figure : 3.0dB measured at an at the front of the receiver group.
inp.level of <-50dBm
Frequency stability : ±5 ppm When operating the switch, an MGC CONTROL
signal will set Amplifier IF & Filter,BP to a fixed
2 DESCRIPTION gain of 10dB. The LNA is still in AGC mode, but
2.1 General: for RF input levels lower than -31dBm, the AGC
will not regulate and gain will be maximum.
The Receiver Group is composed of:
LNA & MIXER UNIT : See Table, p.4 When adjusting the HOP EQUALIZER (not
OSCILLATOR : See Table, p.4 part of receiver group) to equalize the phase
MULTIPLIER x2 : See Table, p.4 and group delay response for the entire radio
AMPL.IF & FILTER, BP : 8UF337C hop, the RF input level must be lower than -
AMPL.IF : 8U357A 31dBm.
The main function of the receiver group is to Adjust MGC potmeter at the front of the group
convert the RF signal to the IF frequency of 70 for IF output of 0dBm.
MHz.
In addition, the low level input signal must be NOTE: MGC mode should not be used during
amplified to a constant output level suitable for normal traffic transfer as output level
the demodulation process. Three units have built- variation from the receiver group may disturb
in AGC facilities. the demodulation process and give bit error or
sync loss as a result.
To meet the requirement of maximum RF input
level of -19dBm, the LNA has a dynamic range 2.2.2 Meter/Recorder
of minimum 10dB. Readings - Alarms:
Amplifier IF (8U357A) has a dynamic range of RF INPUT LEVEL: To determine the RF

minimum 31dB and the Amplifier IF & Filter,BP input level, the AGC voltage of the LNA is
(8UF337C) a dynamic range of minimum 13dB. added to the detected voltage at input of
This means that the RF input signal can vary Amplifier IF. For a nominal RF input level of
between -19dBm to -73dBm with a constant IF -35dBm the voltage to meter is normalized to
output of 0dBm. 3.0V by adjusting R414 on Amplifier IF and
voltage to recorder by matching R242 on
For monitor purposes, an IF test output is included. Amplifier IF & Filter, BP.
The test level is about -20dBm.
For test purposes, an IF break-loop excluding the LO LEVEL: For a nominal output of 17dBm
SAW filter is brought to the front of the group. the voltage to meter is normalized to 2V by
Nominal impedance is 75 ohm. Nominal level is matching R217 on Amplifier IF & Filter, BP.
-10dBm with RF input >- 62dBm.
H2598
3
LO VARACTOR VOLTAGE: The nominal nominal, R220 on Amplifier IF & Filter, BP
control voltage is normalized to 5V for meter
reading by matching R209 on Amplifier IF & is matched to give alarm. In addition loss of
Filter, BP. phase lock (LO PLL ALM) will give LO alarm.
RF INPUT ALARM: With RF input level of RCVR GROUP ALARM: All the other alarms
-67dBm, R245 on Amplifier IF & Filter, BP, is are "OR"ed to make the MAIN RCVR ALM
matched to give alarm. which is visualized by LED 2H1 at the front of
LO ALARM: With oscillator level 4dB below receiver group.
Table for Chapter 2.1 General
Receiverer groups, main:
Freq. Range RCVR RCVR RCVR RCVR RCVR LNA & Mult. x2 RF input
(GHz) ATPC ATPC ATPC COCH mixer port
128 TCM 128 TCM 64 TCM 64 TCM 128TCM
8NUF.... 8NUF.... 8NUF....
New New
SAW-filter SAW-filter
3.6 - 3.7 555AF SMA, F

3.6 - 3.9 530AA 555AA 607AA 620AA 591AA 8UND383A SMA, F
3.6 - 3.9 530AB 555AB 607AB 620AB 8UND383A SMA, F
3.9 - 4.2 530BD 555BD 607BD 620BD 8UND383B SMA, F
3.8 - 4.0 530CC 555CC 591CC 8UND383B SMA, F
4.0 - 4.2 530DE 555DE 607DE 620DE 591DE 8UND383B SMA, F
4.4 - 4.7 557A 608A 621A 593A 8UND415A SMA,F

4.7 - 5.0 557B 608B 621B 8UND415A SMA,F
5.9 - 6.175 520A 559A 595A 8UND336A SMA,F

6.175 - 6.4 520B 559B 8UND336A SMA,F
6.4 - 6.77 537A 561A 583A 622A 597A 8UND385A SMA,F

6.77 - 7.1 537B 561B 583B 622B 8UND385A SMA,F
7.1 - 7.275 563AA 599AA 8UND402A SMA,F

7.275 - 7.45 563AB 8UND402A SMA,F
7.4 - 7.55 526BB 563BB 8UND402B SMA,F
7.4 - 7.66 526BC 563BC 8UND402B SMA,F
7.58 - 7.725 526BD 563BD 8UND402B SMA,F
7.7 - 7.9 563CE 8UND371A SMA,F
7.7 - 8.0 540A 565A 601A 8UND371A SMA,F

8.0 - 8.3 540B 565B 8UND371A SMA,F
10.7 - 11.2 542A 567A 588A 623A 603A 8UND358A-1 10N457A UER 120
11.2 - 11.7 542B 567B 588B 623B 603B 8UND358A-1 10N457A UER 120
12.75 - 13.0 535A 569A 605A 8UND409A-1 10N527A UER 120

13.0 - 13.25 535B 569B 8UND409A-1 10N527A UER 120
4 H2598
3 UNIT DESCRIPTION
3.1 LNA & Mixer Unit:
3dB 3dB
L O IN PU T IF O U T
dB 90 o 90 o
R F IN P U T
R EF .
Fig. 1 Block Schematic Diagram, LNA & Mixer Unit
RF frequency range : See Table, page 4 Figure shows the block diagram of the LNA &
LO freq.range : See Osc. Table, page 7 Mixer Unit. It consists of a low - noise amplifier
IF frequency : 70MHz (LNA) with automatic gain control (AGC) an
LO level in : 12±1.5dBm image reject mixer and an IF amplifier.
RF level in, min/max : -73dBm/-19dBm
IF level out, nom. The LNA consists of two FET stages.
(at max in-level) : -5dBm
Noise figure : <2.5dB The AGC network consists of a balanced PIN-
3rd order IMD : <-50dBc diode attenuator and is integrated with the LNA.
LO/RF connector : SMA, F The mixer, which is an image rejection mixer,
Voltages : +15 ±0.5V has a noise figure better than 6dB and has 18dB
+5.0 ±0.3V attenuation of the image frequency.
-5.2 ±0.3V
The IF amplif. has a temperature compensated
3.1.2 General Description: detector on the output which by use of an internal
The units contain the following sub units: AGC loop gives a maximum outlevel set by
Vref.
Amplifier IF, Bd : EU157A
Detector Board : ED92A
LNA Substrate
Mixer Substrate
H2598
5
3.2 Oscillator:
Fig. 2 Block Schematic Diagram of Oscillator Board
Frequency range : See Table next page

Output power : 17 ±1dBm The SHF-oscillator is locked to a 10MHz Crystal
Monitor power : >-10dBm Oscillator (TCXO) through a single loop
Frequency stability : ±5ppm synthesizer circuit. The main purpose of this loop
Power detector level : >100mV is to control the frequency drift of the VTDRO
PLL alarm caused by temperature changes and aging. A
alarm : 5V major part of this loop consists of a synthesizer
no alarm : 0-0.5V IC.
Varactor voltage : 0 to +13V
Input voltage : +15V/35mA, A part of the output from the VTDRO is divided
+5V/250mA by 8 to approx. 750MHz with a GaAs prescaler.
This signal goes into a dual modulus counter
3.2.2 Functional: (128/129). This counter is controlled by the
synthesizer IC, and works together with the
Ref. Oscillator Block Schematic Diagram internal counters (/N, /A) as a programmable
counter.
The main oscillator is a Voltage Tuned Dielectric The signal from the reference oscillator is divided
Resonator Oscillator (VTDRO). This oscillator by internal counters (/R, /2) to the appropriate
can be coarsly tuned 120MHz by a tuning screw. frequency, and the signals from the reference and
The electronic tuning range of this oscillator is the SHF-oscillator are compared at about 50kHz.
approx. 5MHz. The output from the phase detector is filtered
6 H2598
through the loop filter and goes to the varactor mechanical dual in-line switch. A tuning screw
diode in the VTDRO. The values for the different (FREQ TUNE), which coarsly tunes the VTDRO,
dividers are programmed in the PROM, and the is then adjusted until the tuning voltage (13CP13
channel frequencies can be chosen by the channel VCO VOLT) on the VTDRO is stable at about
switch. 4.5V.
3.2.3 General Description: This is to be the voltage when the nut is locked.
The Oscillator w/PLL contains the Phase Lock Output power is adjusted to nominal level by
Loop Board, the VTDRO substrate and Buffer tuning a variable resistor, R20 on EXD118 (PWR
& Prescaler substrate. ADJ). Frequency can be fine adjusted by a
tuneable capacitor included in the reference os-
3.2. 4 Channel Frequency cillator IC7 on EXD118 (FREQ ADJ).
Setting:
Functions needed for channel frequency setting
Channel frequency is set by selecting the are reached by removing a small cover placed
corresponding combination channel switch S1 over the phaselock loop board.
on EXD118 (CHAN SELECT), a 5-bit
Table for Chapter 3.2.1. Frequency Dependent Technical Data, Oscillator
Oscillator Frequency band PLL-Board
10X398A 3680.0-3780.0 EXD118E

10X398B 3740.0-3840.0 EXD118E
10X398C 3840.0-3953.0 EXD118E
10X398D 3980.0-4080.0 EXD118F

10X398E 4054.0-4165.0 EXD118F
10X468A 4480.0-4600.0 EXD118M
10X468B 4800.0-4920.0 EXD118M
10X372A 5993.80-6104.15 EXD118A

10X372B 6245.84-6356.19 EXD118A
10X401A 6510-6670 EXD118D
10X401B 6850-7010 EXD118D
10X430A 7051.0-7163.0 EXD118G

10X430B 7368.5-7484.0 EXD118G
10X430C 7452.5-7568.5 EXD118G
10X430D 7666.0-7781.5 EXD118H

10X430E 7753.5-7869.0 EXD118H
10X391A 7796.30-7906.65 EXD118C
10X391B 8107.62-8217.97 EXD118C

10X384A 5392.5-5542.5 EXD118B
10X384B 5657.5-5807.5 EXD118B
10X440A 6403.5-6459.5 EXD118K

10X440B 6536.5-6592.5 EXD118K
H2598
7
3.3 MULTIPLIER x2:

10N457A: 10N527A:

+5V/65mA
3.3.2 Functional Description:

(ref. Schematic Diagram, Fig.3 below)
The 17dBm RF input signal is initially attenuated
The Multiplier Unit is a single substrate microstrip to an optimum input level for the succeeding FET
design, fitted into a separate box. The required based multiplier stage. A nominal output level of
±5VDC power supplies and the RF level detector 18dBm is obtained by means of a balanced buffer
are fed through RF filters, and the RF-connectors amplifier, thus also achieving a good output
are SMA female. return loss.
RF MON
RF IN F RF OUT
2F
DET
PWR DE
+5V DC NETWORK
- 5V
Fig. 3 Block Schematic Diagram, Multiplier x2
8 H2598
3.4 Amplifier IF & Filter, BP,

8UF337C:
E U 1 10 B
ATTEN. SLOPE
IF IN P . VARAB. IF O U T
EQUAL.
-2 0 /-1 0 d B m 0 dBm
E R 5 0A E F2 71 A / EU 12 4C SAW FIL T ER
E F2 71 B
EQUALIZER
GROUP DELAY
AGC VOLT E U 1 23 B
DE-
TECTOR 6 0M H z IF T E S T
-2 0 d B m
M G C C O N TR O L /
CON- E F U2 8 3 A
TROLLER
80M H z
E U D1 4 4 A E FU 28 5A
Fig. 4 Block Schematic Diagram, Amplifier IF & Filter, BP, 8UF337C
H2598
9
3.4.1 Technical Data: The control signal comes from 8U357A,
Amplifier, IF.
IF input level : -20dBm/-10dBm
IF output level : 0dBm ±0.5dB Amplification takes place in surface mount
IF test level : -20dBm ±1.5/- amplifiers MAR3 and MSA0104 and EU110B
2.0dB (made on thickfilm board).
Impedance : 75ohm (inp./output)
Return loss, input : >26dB over The gain from input to output of 8UF337C is
70+18MHz controlled by the supplied control voltage to
Return loss, output : >26dB over attenuator module ER50A.
70+18MHz 8UF337C thus has 2 identical attenuators
Return loss, IF-test : >26dB over incorporated in the amplifier chain. The
70+18MHz attenuation can be regulated between approx.
Center frequency,fo : 70MHz 6dB and 35dB. With the control signal in AGC-
Attenuation at fo position, (MGC CONTROL = "0") control volt-
±12.1 MHz(Nykvist- age is delivered from EUD144A.
bandwidth) : 1.1dB
Atten. for f<54MHz : >33dB IF level out is detected and amplified on one of
Atten. for f>86MHz : >33dB the two inputs of an operational amplifier which
Noise factor : <12dB at -55dBm, is incorporated in EUD144A. The other
level in operational amplifier input can be set to a choice
Power Supply : +5.0V +0.3V/280mA reference voltage by R111. Normally this volt-
: +15V +0.5V/75mA age is set to ensure 0dBm level on the IF-output
in the dynamic working range of 8UF337C.
By means of BP-filters EFU283A and
Amplifier, IF & Filter, BP, 8UF337C consists EFU285A, IF-level at respectively 60 and
of the following sub-units: 80MHz is detected and applied to the inputs of
Attenuator, Board 2pcs ER50A an operational amplifier on EUD144A.
Amplifier, IF, Board 2 " EU110B
Ampl. & Detector, Board 1 " EUD144A This OP-amplifier controls the slope equalizers
Amplifier, IF, Board 1 " EU124A EF271A and EF271B by means of the signal
Amplifier, IF, Board 2 " EU123B "CONTROL VOLT". Normally "CONTROL
Equalizer, Amplitude,Bd 1 " EF271A VOLT" =8.0V. The voltage can be set by R112.
Equalizer, Amplitude,Bd 1 " EF271B
Filter BP, 60MHz & Ampl. 1 " EFU283A EUD144A delivers a voltage which is
Filter BP, 80MHz & Ampl. 1 " EFU285A approximately linear with logarithmic increases
Surface mount amplifier 2 " MAR3 of IF input level and voltage in CP1 (AGC
Surface mount amplifier 2 " MSA0104 VOLT) is used as an indication of RF level to
the receiver group.
3.4.3 Functional Description: The return loss on the output is set by R-
matched.The group delay is set by L106, C112.
The main purpose of this unit is to equalize, slope, Flatness of bandpass curve is set by R108, C106
amplify and filter the input signal. By the control and R110, R123.
signal "MGC CONTROL", the gain and slope The gain is set by R103 with the signal "MGC
equalization is chosen to be constant or CONT".
automatically regulated.
The IF level is set by R111 with the signal
"MGC CONTROL" = logic "0" gives automatic "MGC CONTROL" =0 when 8UF337C works
regulation, and "MGC CONTROL" = logic "1" within its dynamic range. The IF TEST LVL is
gives manual regulation, respectively. set 20dB below IF OUT LVL.
10 H2598
3.5 Amplifier IF, 8U357A:
Fig. 5, Block Schematic Diagram, 8U357A
19J1 : IF INP:
Frequency : 70±16MHz MGC Control:
Impedance : 75 ohm (Used for MGC/AGC Control on "IF
Return loss 70±13MHz: <-26dB Ampl. & Filter, Board")
Level : -49 to -5dBm
MGC control : Current sink
19J3: IF OUT: Maximum voltage : +5V
Frequency : 70±16MHz Max. current sink : 25mA
Impedance : 75ohm
Return loss 70±13MHz: <-24dB Power Supply: : +5.0V
Level : -20 to 10dBm +15V
-15V
AGC/MGC:
Maximum gain 3.5.2 General Description:
IF IN to IF OUT : +29dB
Time constant in AGC : 24mS The Amplifier, IF, 8U357A is an automatic gain
control with 29dB dynamic range. The AGC can
Input Power Measurement: be switched to MGC, and the MGC-level can be
Measured RF level : -72 to -18dBm adjusted. This unit also measures the RF input
Monitored voltages : 0 to 4VDC level and presents it to "Meter and Alarm" unit as
Transition from DC a DC voltage.
volt to dBm : not linear
H2598
11
3.5.3 Functional Description: 3.5.3.5 AGC/MGC Switch:

(Ref. to Block Schem. Diagram)
With the switch 19S1 mounted on the front of
3.5.3.1 Input Match and Buffer: the receiver it is possible to switch the
8U357A in 2 modes:
Input match is used by test department to match
for minimum return loss. 1) AGC (= mid pos.) :
The buffer used (NERA EU110A) isolates the This is the normal position
AGC and input level detectors from the input.
2) MGC (=upper pos.):
3.5.3.2 AGC/MGC:
* AGC is switched over to MGC.
The Automatic Gain Control consists of an
amplifier (NERA EU123B), two variable * Amplifier IF & Filter, BP is
attenuators (NERA ER50A), a level detection switched over from AGC and
circuit and AGC voltage control board (NERA Automatic slope equalizer to
EY171A). constant gain (+20dB) and
constant slope (0dB).
The level detection circuit measures the IF-level
out of the 8U357A through a bandpass filter * LED "MGC ALM" on the front
with fo=70MHz. Bandpass filter is used to avoid if the receiver is activated.
detecting level from adjacent channel.
3.5.3.6 AGC/MGC Switch.
In Manual Gain Control, the gain is controlled by (New as pr. October 1997)
potentiometer 19R1 mounted on the front of the
receiver. With the switch 19S1 mounted on the front of
the receiver it is possible to switch the
3.5.3.3 Output Match: 8U357A in 3 modes:
Output match is used by the test department to 1) AGC : =upper position. (Normal pos.)
match for minimum return loss in the IF output.
2) OFF : =mid pos. (RCVR Group OFF)
3.5.3.4 Input Power
Measurement: 3) MGC : =lower position:
The RF input level is presented for the "Meter * AGC is switched over to MGC.
and Alarm" unit as a DC monitor voltage. This
monitor voltage consists of the sum of LNA * Amplifier IF & Filter, BP is
AGC voltage and the detected input level into switched over from AGC and
8U357A. Automatic slope equalizer to
Input level to 8U357A is detected by a logarithmic constant gain (+20dB) and
amplifier and detector (NERA EU153A) with constant slope (0dB).
more than 45dB dynamic range.
The monitor voltage is not linear function of the * LED "MGC ALM" on the front
RF input level. if the receiver is activated.
12 H2598
RECEIVER GROUPS, incl. ATPC
Space Diversity
NL290 - Family
H2599 Rev.E
© Nera ASA
Receiver Groups, Space Div., SDH
TABLE OF CONTENTS
1. TECHNICAL DATA ....................................................... 3
2. DESCRIPTION ............................................................. 3
2.1 General ............................................................ 3
2.2 Functional ......................................................... 3
2.2.1 MGC Mode ...................................................... 3
2.2.2 Meter/Recorder Readings-Alarms .................... 4
3. UNIT DESCRIPTION .................................................... 5

3.1 LNA & Mixer Unit .............................................. 5
3.1.1 Technical Data ................................................. 6
3.1.2 General Description .......................................... 6
3.2 OSCILLATOR .............................................................. 7

3.2.1 Technical Data ................................................. 7
3.2.2 Functional Description ...................................... 7
3.2.4 Channel Frequency Setting ............................... 8
3.3 MULTIPLIER x2 ........................................................... 8

3.3.1 Technical Data ................................................. 8
3.3.2 Functional Description ...................................... 8
3.4 AMPL IF & FILTER,BP................................................. 9

3.4.1 Technical Data ................................................. 9
3.4.2 8UF337C/D/E (old version) .............................. 10
3.4.3 8UF337G/H ...................................................... 10
3.4.4 Signal Level Settings ........................................ 11
3.5 SPLITTER & PHASE SHIFT UNIT ............................... 12

3.5.1 Technical Data ................................................. 12
3.6 SPACE DIVERSITY COMBINER .................................. 13

3.6.1 3DK125A/B ...................................................... 13
3.6.2 8DK138A .......................................................... 18
2 H2599
1 TECHNICAL DATA 2.2 Functional:

Input freq. range : See Table, page 4 2.2.1 MGC Mode
Input level : Max. -19dBm NOTE: MGC mode should not be used during
Input impedance : 50 ohm normal traffic transfer as output level variation
from the receiver group may disturb the demodu-
Output frequency : 70Mhz
lation process and give bit error or sync loss as a
Output level : 0dBm
result.
Output impedance : 75 ohm
Test output level : -20dBm 2.2.1.1 3DK125A/B
Test output impedance : 75 ohm The MGC mode (Manual Gain Control) is selected
Noise figure : 3.0dB measured at an by switch 19S1 to pos. MGC MAIN or MGC Space.
inp.level of <-50dBm The AGC/MGC switch 19S1,MGC ALM indicator
Frequency stability : ±5 ppm 19H1 and MGC ADJ potmeter 19R1 are part of Space
Div. Combiner,but are available at the front of the
2 DESCRIPTION receiver group.
When operating the switch to pos. MGC MAIN, the
2.1 General space div. signal will be switched off. An MGC CON-
The Receiver Group is composed of: TROL signal will set Ampl. IF & Filter,BP to a fixed
LNA & MIXER UNIT : See Table, p.4 gain of 21dB. The LNA is still in AGC mode, but for
OSCILLATOR : See Table, p.4 RF input level lower than -31dB, the AGC will not
MULTIPLIER x2 : See Table, p.4 regulate and gain will be maximum.
AMPL.IF & FILTER, BP : 8UF337C/D/E When adjusting the HOP EQUALIZER for the main
SPLITTER & PHASE SHIFT : See Table, p.4 branch(not part of the receiver group) in order to equal-
SPACE DIV. COMBINER : 8DK138A ize the phase and group delay response for the entire
(New version) radio hop, the RF input level must be lower than -
SPACE DIV. COMBINER : 3DK125A/B 31dBm.
(Old version) Adjust MGC potmeter at the front of the group for IF
output of 0dBm.
The main function of the receiver group is to convert
the RF signal from the main and space antenna, rang- When operating the switch to pos. MGC SPACE, the
ing to the IF frequency of 70 MHz. main signal will be switched off. To adjust the HOP
In addition, the two signals are combined and ampli- EQUALIZER for the space diversity branch, the same
fied to a constant output level suitable for the de- procedure has to be used.
modulation process. Three units have built- in AGC
facilities. 2.2.1.1 8DK138A
The MGC mode (Manual Gain Control) is selected
To meet the requirement of maximum RF input level by switch 19S1 to pos. MGC.
of -19dBm, the LNA has a dynamic range of mini- The AGC/MGC switch 19S1,MGC ALM indicator
mum 10dB. The dynamic range for the Space Diver- 19H1 and MGC ADJ potmeter 19R1 are part of Space
sity Combiners are 31dB for 3DK125A/B and 40dB Div. Combiner,but are available at the front of the
for 8DK138A. The Amplifier IF & Filter BP has a receiver group.
dynamic range of min.13dB. This means that RF in- When operating the switch to pos. MGC MAIN, a
put signal can vary between -19dBm to -73dBm with MGC CONTROL signal will set Ampl. IF & Filter,BP
a constant IF output of 0dBm. to a fixed gain of 21dB. The LNA is still in AGC
mode, but for RF input level lower than -31dB, the
For monitoring purposes, an IF test output is AGC will not regulate and gain will be maximum.
included.The test level is about -20dBm. For test pur- When adjusting the HOP EQUALIZER for the main
poses, an IF break-loop excluding the SAW filter is branch(not part of the receiver group) in order to equal-
brought to the front of the group. Nominal imped- ize the phase and group delay response for the entire
ance is 75W. radio hop, the RF input level must be lower than -
Nominal level with 8DK138A is -10dBm. Nominal 31dBm.
level with 3DK125A/B is -10dBm with RF input >- Adjust MGC potmeter at the front of the group for IF
62dBm. output of 0dBm.
H2599
3
Table for Chapter 2.1 General
Freq. Range RCVR RCVR RCVR RCVR RCVR Mult. x2 RF Input

Ghz w/SPACE w/SPACE w/SPACE w/SPACE w/C0-CH ports
&ATPC &ATPC &ATPC 128 TCM
128 TCM 128 TCM 64 TCM 64 TCM 8NUF....
8NUF.... 8NUF.... 8NUF.... 8NUF....
New New
SAW-filter SAW-filter
3.6 - 3.9 531AA 556AA 609AA 616AA 592AA SMA, F

3.6 - 3.9 531AB 556AB 609AB 616AB SMA, F
3.9 - 4.2 531BD 556BD 609BD 616BD SMA, F
3.8 - 4.0 531CC 556CC 592CC SMA, F
4.0 - 4.2 531DE 556DE 609DE 616DE 592DE SMA, F
4.4 - 4.7 558A 610A 617A 594A SMA, F

4.7 - 5.0 558B 610B 617B SMA, F
5.9 - 6.175 519A 560A 596A SMA, F

6.175 - 6.4 519B 560B 596B SMA, F
6.4 - 6.77 538A 562A 584A 618A 598A SMA, F

6.77 - 7.1 538B 562B 584B 618B 598B SMA, F
7.1 - 7.275 564AA 600AA SMA, F

7.275 - 7.45 564AB SMA, F
7.4 - 7.55 544BB 564BB SMA, F
7.4 - 7.66 544BC 564BC SMA, F
7.58 - 7.725 544BD 564BD SMA, F
7.7 - 7.9 544CE 564CE SMA, F
7.7 - 8.0 541A 566A 602A SMA, F

8.0 - 8.3 541B 566B SMA, F
10.7 - 11.2 543A 568A 611A 619A 604A 10N457A UER 120
11.2 - 11.7 543B 568B 611B 619B 10N457A UER 120
12.75 - 13.0 536A 570A 606A 10N527A UER 120

13.0 - 13.25 536B 570B 10N527A UER 120
2.2.2 Meter/Recorder LO LEVEL: For a nominal output of 17dBm the

Readings-Alarms: voltage to meter is normalized to 2V by match-
ing R217 on Amplifier IF & Filter, BP.
RF INPUT LEVEL,MAIN: To determine the RF
input level, the AGC voltage of the LNA is added to LO VARACTOR VOLTAGE: The nominal
the detected voltage at input of Amplifier IF. For a control voltage is normalized to 5V for meter
nominal RF input level of -35dBm the voltage to me- reading by matching R209 on Amplifier IF &
ter is normalized to 3.0V by adjusting R414 on Am- Filter, BP.
plifier IF and voltage to recorder by matching R242
on Amplifier IF & Filter, BP.
RF INPUT ALARM, MAIN: With RF input level of
-67dBm, R245 on Amplifier IF & Filter BP is matched
RF INPUT LEVEL, SPACE:
to give alarm.
To determine the RF input level the AGC voltage of
the LNA is added to the detected voltage at input of
RF INPUT ALARM, SPACE: With RF input level
Space Div. Combiner.
of -67dBm, R249 on Ampl. IF & Filter BP is matched
to give alarm.
For a nominal RF input level of -35dBm the voltage
to meter is normalized to 3.0V by adjusting R415 on
LO ALARM: With oscillator level 4dB below nomi-
Space Div. Combiner and voltage to recorder by
nal, R220 on Ampl. IF & Filter BP is matched to give
matching R246 on Amplifier IF & Filter BP.
alarm. In addition, loss of phase lock (LO PLL ALM)
will give LO alarm.
4 H2599
DIVERSITY ALARM: This is a processor alarm "OR"-ed to make this alarm which is visualized by
which is activated if the test mode is selected or the LED 2H1 at the front of the receiver group.
program execution has stopped. This alarm is part of
both MAIN RECEIVER ALM and SPACE DIV. SPACE DIV RCVR ALARM: All the other alarms
RCVR ALARM. with the exception of RF INPUT ALARM, are "OR"-
ed to make this alarm which is visualized by a LED
MAIN RCVR ALARM: All the other alarms with 2H2 at the front of the receiver group.
the exception of RF INPUT ALARM,SPACE, are
3 UNIT DESCRIPTION
3.1 LNA & Mixer Unit:
3dB 3dB
LO INPUT IF OUT
dB 90o 90o
RF INPUT
REF.
Fig.1 Block Schematic Diagram, LNA & Mixer Unit
H2599
5
3.1.1 Technical Data: Figure 1 shows the block diagram of the LNA &
RF freq. range, see Table, page 4 Mixer Unit. It consists of a low- noise amplifier
LO freq. range, see Table for Chapter 3.2.1 (LNA) with automatic gain control (AGC), an
SSB balanced mixer, an IF amplifier and a
IF frequency : 70MHz temperature compensated detector.
LO level in : 12±1.5dBm
RF level in, min/max : -73dBm/-19dBm The LNA consists of two stages.
IF level out, nom.
(at max in-level) : -5dBm The AGC network consists of a balanced PIN-
Noise figure : <2.5dB diode attenuator and is integrated with the LNA.
3rd order IMD : <-50dBc
LO/RF connector : SMA,F The mixer, which is an image rejection mixer,
Voltages : +15 ±0.5V has a noise figure better than 6dB and offers good
+5.0 ±0.3V attenuation of the image frequency.
-5.2 ±0.3V
The IF amplif. has a temperature compensated
3.1.2 General Description: detector on the output which by use of an internal
This unit contains the following sub units: AGC loop gives a maximum outlevel set by
Amplifier IF, Board : EU157A Vref.
Detector Board : ED92A
Table for Chapter 3.2.1, Technical Data, Oscillator:
Oscillator Frequency band PLL-Board
10X398A 3680.0-3780.0 EXD118E

10X398B 3740.0-3840.0 EXD118E
10X398C 3840.0-3953.0 EXD118E
10X398D 3980.0-4080.0 EXD118F

10X398E 4054.0-4165.0 EXD118F
10X468A 4480.0-4600.0 EXD118M
10X468B 4800.0-4920.0 EXD118M
10X372A 5993.80-6104.15 EXD118A

10X372B 6245.84-6356.19 EXD118A
10X401A 6510-6670 EXD118D
10X401B 6850-7010 EXD118D
10X430A 7051.0-7163.0 EXD118G

10X430B 7368.5-7484.0 EXD118G
10X430C 7452.5-7568.5 EXD118G
10X430D 7666.0-7781.5 EXD118H

10X430E 7753.5-7869.0 EXD118H
10X391A 7796.30-7906.65 EXD118C
10X391B 8107.62-8217.97 EXD118C

10X384A 5392.5-5542.5 EXD118B
10X384B 5657.5-5807.5 EXD118B
10X440A 6403.5-6459.5 EXD118K

10X440B 6536.5-6592.5 EXD118K
6 H2599
3.2 Oscillator:
Fig. 2
Frequency range : See Table, page 6. The SHF-oscillator is locked to a 10MHz Crystal
Output power : 17 ±1dBm Oscillator (TCXO) through a single loop
Monitor power : >-10dBm synthesizer circuit. The main purpose of this
Frequency stability : ±5ppm loop is to control the frequency drift of the
Power detector level : >100mV VTDRO caused by temperature changes and
PLL alarm aging. A major part of this loop consists of a
alarm : 5V synthesizer IC.
no alarm : 0-0.5V
Varactor voltage : 0 to +13V A part of the output from the VTDRO is divided
Input voltage : +15V/35mA, by 8 to approx. 750MHz with a GaAs prescaler.
+5V/250mA This signal goes into a dual modulus counter
(128/129). This counter is controlled by the
3.2.2 Functional: synthesizer IC, and works together with the
Ref. Fig. 2. internal counters (/N, /A) as a programmable
counter.
The main oscillator is a Voltage Tuned Dielectric The signal from the reference oscillator is divided
Resonator Oscillator (VTDRO). This oscillator by internal counters (/R, /2) to the appropriate
can be coarsly tuned 120MHz by a tuning screw. frequency, and the signals from the reference
The electronic tuning range of this oscillator is and the SHF-oscillator are compared at about
approx. 5MHz. 50kHz.
The output from the phase detector is filtered
H2599
7
through the loop filter and goes to the varactor A tuning screw (FREQ TUNE), which coarsly
diode in the VTDRO. The values for the different tunes the VTDRO, is then adjusted until the
dividers are programmed in the PROM, and the tuning voltage (13CP13 VCO VOLT) on the
channel frequencies can be chosen by the channel VTDRO is stable at about 4.5V.
switch. This is to be the voltage when the nut is locked.
3.2.3 General Description Output power is adjusted to nominal level by

The Oscillator contains the Phase Lock Loop tuning a variable resistor, R20 on EXD118 (PWR
Board, the VTDRO substrate and Buffer & ADJ). Frequency can be fine adjusted by a tuneable
Prescaler substrate . capacitor included in the reference oscillator IC7
on EXD118 (FREQ ADJ).
3.2.4 Channel Frequency Setting
Channel frequency is set by selecting the Functions needed for channel frequency setting
corresponding combination channel switch S1 are reached by removing a small cover placed
on EXD118 (CHAN SELECT), a 5-bit above the phaselock loop board.
mechanical dual in-line switch.
3.3 MULTIPLIER x2:

10N457A: 10N527A:

+5V/65mA
3.3.2 Functional Description: The 17dBm RF input signal is initially attenuated

(ref. Schematic Diagram, Fig.3, below) to an optimum input level for the succeeding FET
based multiplier stage. A nominal output level of
The Multiplier Unit is a single substrate microstrip 18dBm is obtained by means of a balanced buffer
design, fitted into a separate box. The required amplifier, thus also achieving a good output return
±5VDC power supplies and the RF level detector loss.
are fed through RF filters, and the RF-connectors
are SMA female.
RF MO
RF IN F RF OU
2F
DET
PWR D
+5V DC NETWORK
- 5V
Fig.3 Block Schematic Diagram, Multiplier x2

8 H2599
3.4 Amplifier IF & Filter,BP
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Fig.4a Block Schematic Diagram, Amplifier, IF & Filter, BP, 8UF337G/H
EU110B
ATTEN. SLOPE
IF INP. VARAB. IF OUT
EQUAL.
-20/-10dBm 0 dBm
ER50A EF271A/ EU124A SAW FILTER

EF271B EU124C
EQUALIZER
GROUP DELAY
AGC VOLT EU123B

DE-
TECTOR 60MHz IF TEST
-20 dBm
MGC CONTROL /
CON- EFU283A
TROLLER
80MHz
EUD144A EFU285A
Fig.4b Block Schematic Diagram, Amplifier, IF & Filter, BP, 8UF337C/D/E (old versions)
IF input level : -20dBm/-10dBm Attenuation at fo

IF output level : 0dBm ±0.5dB ±11.96 MHz(Nyquist-
IF test level : -20dBm ±1.5/-2.0dB bandwidth) : 1.1dB
Impedance : 75ohm (inp./output) Atten. for f<54MHz : >33dB
Return loss, input : >26dB over Atten. for f>86MHz : >33dB
70+18MHz Noise factor : <12dB at -55dBm,
Return loss, output : >26dB over level in
70+18MHz Power Supply : +5.0V +0.3V/320mA
Return loss, IF-test : >26dB over (for 8UF337G-H) : +15V +0.5V/100mA
70+18MHz Power Supply : +5.0V +0.3V/280mA
Center frequency,fo : 70MHz (for 8UF337C-E : +15V +0.5V/75mA
H2599
9
3.4.2 8UF337C/D/E (old version) By means of BP-filters EFU283A and EFU285A,

3.4.2.1 General Description IF-level at respectively 60 and 80MHz is detected
Amplifier, IF & Filter, BP, 8UF337C/D/E and applied to the inputs of an operational
consists of the following subunits: amplifier on EUD144A.
Attenuator, Board 2pcs ER50A This OP-amplifier controls the slope equalizers
Amplifier, IF, Board 2" EU110B EF271A and EF271B by means of the signal
Ampl. & Detector, Board 1" EUD144A "CONTROL VOLT". Normally "CONTROL
Amplifier, IF, Board 1" EU124A/C VOLT" =8.0V. The voltage can be set by R112.
Amplifier, IF, Board 2" EU123B
Equalizer, Amplitude,Bd 1" EF271A EUD144A delivers a voltage which is
Equalizer, Amplitude,Bd 1" EF271B approximately linear with logarithmic increases
Filter BP, 60MHz & Ampl. 1" EFU283A of IF input level and voltage in CP1 (AGC
Filter BP, 80MHz & Ampl. 1" EFU285A VOLT) is used as an indication of RF level to the
Surface mount amplifier 2" MAR3 receiver group.
Surface mount amplifier 2" MSA0104
SAW- Filter 1" IC4 3.4.3 8UF337G/H
3.4.3.1 General Description
3.4.2.2 Functional Description Amplifier, IF & Filter, BP, 8UF337G/H, being a
The main purpose of this unit is to equalize, part of the receiver unit, shall amplify the re-
slope, amplify and filter the input signal. By the ceived IF-signal in order to ensure a constant
control output level. In addition the received signal shall
signal "MGC CONTROL", the gain and slope be filtered through a bandpass filter (a SAW-fil-
equalization is chosen to be constant or ter is being used) and a possible slope in the
automatically regulated. incoming IF signal shall be equalized. The unit
"MGC CONTROL" = logic "0" gives automatic is realised by means of surface mounted compo-
regulation, and "MGC CONTROL" = logic "1" nents.
gives manual regulation, respectively. The A control signal MGC CONTROL will choose
control signal comes from the Space Diversity whether the gain and the slope equalization shall
Combiner. be automatically or manually regulated.
Power supply for the receiver group may be
Amplification takes place in surface mount switched on and off via a Soft power on func-
amplifiers MAR3 and MSA0104 and EU110B tion. Both the functions are operated via a switch
(made on thickfilm board). located on front of the receiver unit.
The gain from input to output of 8UF337C/D/E
is controlled by the supplied control voltage to The difference between 8UF337G and 8UF337H
attenuator module ER50A. relates to radio frequency in the equipment.
8UF337C/D/E thus has 2 identical attenuators 8UF337G will be used in equipment with radio
incorporated in the amplifier chain. The frequency below 11GHz, 8UF337H will be used
attenuation can be regulated between approx. in equipment with radio frequency equal to or
6dB and 35dB. With the control signal in AGC- above 11GHz.
position, (MGC CONTROL = "0") control volt-
age is delivered from EUD144A. The return loss on the output is set by R-
matched.The group delay is set by L106, C112.
IF level out is detected and amplified on one of Flatness of bandpass curve is set by R108, C106
the two inputs of an operational amplifier which and R110, R123.
is incorporated in EUD144A. The other
operational amplifier input can be set to a choice The gain is set by R103 with the signal "MGC
reference voltage by R111. Normally this volt- CONT".
age is set to ensure 0dBm level on the IF-output The IF level is set by R111 with the signal "MGC
in the dynamic working range of 8UF337*. CONTROL" =0 when 8UF337* works within its
10 H2599
dynamic range. The IF TEST LVL is set 20dB level and the control signal AGC VOLT is used as an
below IF OUT LVL. indication of RF level to the receiver group.
3.4.3.2 Functional Description Amplification is carried out via surface mount ampli-
Automatic or manual gain control is selected via switch fiers MAR3 and MAR6. A transistor BFQ18 is used
S1 located on the front of the receiver group. The as the last amplifier stage before IF OUT, in order to
switch generates a control signal (MGC CONTROL ) improve linearity.
which is transmitted from the Space Diversity
Combiner to the amplifier. MGC CONTROL = logic As a result of fading activities a slope in the incoming
0 gives Automatic Gain Control (AGC), and MGC spectrum may occur. By means of two BP-filters with
CONTROL = logic 1 gives Manual Gain Control, centre frequencies respectively at 60 MHz and 80
respectively. Normal position for the switch is AGC. MHz and a 3 dB BW of approximately 4 MHz, the
signal level on both sides of centre frequency fo is
Likewise the Soft power on function is activated via compared and the shape of the incoming signal deter-
switch S1. The soft power on function shall prevent mined. Two frequency dependent circuits are included
momentary power on in the receiver group as this in series with the signal, one of them tilting the signal
may result in a short dip in the secondary voltages, upward and the other tilting the signal downward.
i.e. +5 and +15 Volt. The function is realised by means These circuits may be bypassed by means of pin di-
of R-C circuits, introducing a smooth power increase odes. The signal SLOPE CTRL VOLT will regulate
before the signal reaches their final values within a the current and thereby the resistance in the pin di-
few milliseconds. odes, resulting in a varying influence of the tilting cir-
cuits dependent of the shape of the IF signal. The
Switch S1 has three possible positions: AGC (auto- SLOPE CTRL voltage may vary between app. 1 and
matic gain control), OFF (power off) and MGC 14 volt, with 8 volt as factory setting assuming a flat
(manual gain control). Normal position is AGC. IF input signal.
The level adjustment of the unit is carried out via a The purpose of the ATPC function (Automatic Trans-
voltage dependent attenuator. The attenuator, being mitter Power Control) is to control the transmitter
realised by means of pin-diodes may adjust the signal output power level. The detected RF level is com-
amplification approximately 29 dB. If the unit is op- pared to a fixed reference. If the received level is
erated in AGC (Automatic Gain Control) a detector in below the ref. level, a control signal, ATPC HIGHER
the feedback circuit will determine the output level is generated. Similarly a control signal ATPC LOWER
and compare it to a fixed value. The difference is is generated if the received signal is above ref. level.
used as feedback to the attenuator (AGC VOLT-sig- In order to avoid unnecessary regulation or in worst
nal). If MGC is selected, the control voltage to the case oscillations, a window which detected RF in-
attenuator is fed directly from a potensiometer. IF put level may vary within, is introduced. As long as
output level is normally set to 0 dBm from factory. the received level is within this window no changes in
The AGC VOLT from the comparator is approxi- the transmitter level is introduced.
mately linear with logarithmic increases of IF input The ATPC control signals is fed back to the transmit-
ter.
3.4.4 Signal Level Settings
Signal Level / Measure point Adjustor Remarks

Factory default
IF out lvl 0 dBm 20J2 R426
SLOPE CTR VOLT 8 ± 0.5 V TP1/TP2 R423 O dBm IF output lvl
Manual gain control 10 dB 20J2 R401 Switch S1 in pos MGC
Manual slope control 8 ± 0.5 V 20J2 R404
Switch S1, position AGC - -
H2599
11
3.5 Splitter & Phase Shift Unit:
Fig. 5
3.5.1 Technical Data

Frequency range : See Table Each component is multiplied by a factor between
Level in : 17 ±1dBm -1 and 1 when passing the MOD block. The
Level out (both outports) : 12 ±1.5dBm factor is controlled by the CNTRL voltage
Return loss, in : >14dB applied, where -10V gives the minimum value
Return loss, out (dir. outp.) : >14dB and 0V gives the maximum.
Control signals,two : -10, -0V The signals are added in phase to produce a sum
Connectors in/out : SMA, Female signal with the desired phase. To maintain the
Connectors for contr. signals : IEC169-13 desired power level, an ALC amplifier is attached.
(1.6/5.6) The power level is set by an internal pot.meter,
Temp.range : -5°C to +65°C R212.
DC bias : +5V ±0.3V
-5.2 ±0.3V
Splitter & Phase Frequency
Shift Unit Band, GHz
3.5.2 General Description
The splitter and phase shift unit splits a single
10F288A 3.680-4.165
tone signal and introduces any desired phase
10F307A 4.054-4.600
difference between the two outputs.The phase
10F266A 5.993-6.357
between the outputs is set by two control voltages,
10F385A 6.510-7.010
CTRL1 and CTRL2. (Ref. is made to Block
Schematic Diagram).
10F298B 7.368-7.869
10F285A 7.796-8.218
The dir.out signal is coupled from the input
before two equal components with 90º phase
10F277A 5.392-5.808
difference are produced as base vectors to cover
10F301A 6.403-6.593
the entire phase circle.
12 H2599
3.6 Space Diversity Combiner
3.6.1 3DK125A/B
IF INPUT MAIN INPUT MATCH & AGC, MGC & SWO

BUFFER MAIN MAIN
IF OUT
POWER COMBINER OUTPUT MATCH
IF INP SPACE INPUT MATCH & AGC, MGC & SWO

BUFFER SPACE SPACE
2 MGCALM
AGC VOLT LNA MAIN 1 RE D
AGC VOLT LNA SPACE
INPUT POWER AGC/MGC SWITCH OUT SPECTRUM SHAPE

MONITOR VOLTAGE MEASUREMENT SWITCH CONTROL DETECTOR
MAIN
MONITOR VOLT.SPACE
MGC CONTROL VOLTAGE
SPACE DIV ALM

SPACE DIVERSITY COMBINATION CONTROLLER
LP-FILTER & LP-FILTER &

BUFFER 1 BUFFER 2
PHASE CONTROL VOLT. 1 & 2
Fig.6 Block Schematic Diagram
H2599
13
3.6.1 .1 Technical Data: 19J4 and 19J5, Phase Control 1 and

Phase Control 2:
IF: LP-filter, 3dB freq. :1kHz
Level :-10 to 0V
19J1 and 19J2, IF INP MAIN and IF INP Max current :20mA
SPACE: Phase step :1.4 degrees
Frequency :70±16MHz
Impedance :75ohm Spectrum Shape Detector:
Return loss,70±13MHz :<-26dB Numer of filters :3
Level :-5 to -49dBm 3 dB bandwidth of
filters :10MHz
19J3 : IF OUT: Center frequencies
Frequency :70±16MHz of filters :60,70 &80MHz
Impedance :75ohm Dynamics in detectors :Min.15dB
Return loss 70±13MHz : <-24dBm
Level :-7 to -20dBm Alarm:
Space Div. Alarm :Current Sink
AGC/MGC: Maximum voltage :+5V
Maximum gain Maximum current sink :25mA
IF IN to IF OUT :+29dB
Time constant in AGC :»24ms MGC control:
(Used for MGC/AGC control on "IF
Input Power Measurement: Ampl. & Filter, BP)
Measured RF level :-72 to -18dBm
Monitored voltage :0 - 4VDC MGC Control :Current Sink
Translation from DC Maximum voltage :+5V
volt to dBm :Not linear Maximum current sink :25mA
Space Diversity Combiner Controller: Power Supply:

-Microcontroller and Perifer Circuits: +5V
8 bit Microcontroller :Intel D8751H -5.3V
On chip EPROM memory :4K Byte -15.0V
Program code size :3K Byte -15.0V
Constant size :1K Byte
Oscillator :12MHz crystal 3.6.1.2 General Description:
oscillator
Watchdog and reset :NERA ES145A The 3DK125A/B Space Diversity Combiner
8 channel multiplier :IH6108 combines the signals from Main- and Space-
8 bit A/D converter :ADC0820 receiver at IF after a limited AGC.
Phase Control: By controlling the endless phase shifter and two

A/D reference, 4.0V :LM385 squelch functions, a micro-controller takes care
14 bit D/A converters :AD7534 of the combining algorithms.
D/A reference, 10.0V :AD587
By switching 19S1 on the front it is possible to
chose one of the receivers (and squelch out the
other) and set it in MGC (Manual Gain Control).
14 H2599
The MGC level can then be adjusted with pot- detected in the Space Diversity Combiner Con-
meter 19R1 on the front of the receiver. troller.
3DK125A/B also measures and presents the RF
input levels (into LNAs) for the Meter and To detect the input level to Space Div. Combiner,
Alarm Unit. a logarithmic amplifier and detector board
(NERA EU153A/EU179A in 3DK125A and
3.6.1.3 Functional Description: 3DK125B respectively) with more than 45 dB
Ref. to Block Schematic Diagram, page 12. dynamic range is used.
3.6.1.3.1 Input Match and Buffer: 3.6.1.3.6 AGC/MGC Switch:

Input match is used by the test department to With the switch 19S1, mounted on the front, the
match for minimum return loss. The buffer used 3DK125A/B is set in three different modes:
(NERA EU110A) isolates the AGC and input
level detectors from the input. 1) In pos. AGC( =mid position) the combiner
works as normal, the Space Div. Combiner
3.6.1.3.2 AGC, MGC and SWO: Controller has fully control.
The Automatic Gain Control consists of three
amplifiers (NERA EU123B), two variable 2) In pos. MGC MAIN (=upper pos.) the following
attenuators (NERA ER50) a level detection is done:
circuit and a AGC Voltage Control Board (NERA
EY171A). * The space receiver is squelched out.
The level detection circuit measures the IF level * The phase shifter (10F288A) is controlled to
into the power combiner, through a bandpass zero degrees phase shift.
filter fo=70MHz. Bandpass filter is used to * The main "AGC, MGC and SWO" is switched
avoid detecting from adjacent channel. to MGC.
* The LED "MGC ALM" on the front is activated.
In Manual Gain Control, the gain is controlled * The unit Amplifier IF & Filter BP is switched
with potentiometer 19R1 (placed in front of the to constant gain (+10dB) and to constant slope
receiver). The same potmeter is used for Main (0dB).
and Space.
3) In position MGC SPACE (=down position)
Switch Out is a squelch function that, when the following is done:
activated, tells the AGC voltage control board to
set the variable attenuators to max. attenuation. * The main receiver is squelched out.
* The phase shifter is controlled to zero degrees
3.6.1.3.3 Power Combiner: phase shift.
The two signals are summed in power combiner * The space "AGC, MGC and SWO" is switched
at -in most cases- equal levels. to MGC.
* The LED "MGC ALM" on the front is activated.
3.6.1.3.4 Output Match: * The unit "Amplifier IF & Filter BP" is switched
Output match is used by test department to to constant gain (+10dB) and to constant
match for minimum return loss in the output. slope (0dB).
3.6.1.3.5 Input Power Measurement: 3.6.1.3.7 Switch out Control:

The RF input levels are presented for the meter Switch out control is a circuit that establishes the
and alarm unit as DC monitor voltages. Each switch (squelch) out (and switch in) commands
ofthe monitor voltages consists of the sum of from Space Diversity Combiner Controller
AGC voltage in LNA amplifier and input level without giving errors in the data traffic.
H2599
15
3.6.1.3.8 Spectrum Shape By using input power and inband amplitude

Detector (SSD): dispersion as input variables, the microcontroller
The SSD is used for measuring the inband am- establishes combining as described in chapt.2.3.
plitude dispersion and total combined power. It
consists of three BP-filters and three level A "watchdog" board (NERA ES145A) gives
detectors. reset to microcontroller when power is switched
on, if the microcontroller does not read its input
3.6.1.3.9 LP-Filter and Buffer: variables, or if push-button S601 is pressed.
The two phase control voltages are made in each
D/A converter, then buffered through a third 3.6.1.4 Combining Algorithms:
degree low pass filter and an OP-amplifier. Depending on different input powers (RF) the
SDCC uses different combining algorithms.
3.6.1.3.10 Space Diversity Figure 7 shows different situations and
Combiner Controller combining algorithms:
(SDCC):
The SDCC consists of an analog multiplexer, an
A/D converter, a micro-controller and two D/A
converters.
3DK125A (rev R2D) and 3DK125B (rev R1B)

Space Diversity Combiner.
Combinating algorithm in software:
dBm
switch out SPACE
-65
switch out MAIN
-80
input level SPACE rcvr
-80 -65 dBm
All limits have about 1 dB hysteresis.

In the maximum power combining area, signals are equal within 3 dB
Below - 65 dBm combinig is done before AGC.
Fig. 7 The Different Combining Situations.
16 H2599
3.6.1.5 Absolute Delay Adjustment:
Fig 8 Hook-up Illustration for Absolute Delay Adjustment
1) PRBS Sequence over the hop.
2) Approx. same input level in Main and Space.
3) Take off the unit cover.
4) 3DK125A/B is set in MGC MAIN position
5) Connect equal lengths of cables to the oscillator according to hook-up illustration.
6) Find the sequences on the oscilloscope.
7) Adjust the absolute delay switches until both sequences are matching, i.e. covering
each other on the oscilloscope (±1ns).
8) If this procedure doesnt work out, proceed as follows:

- 8ns switch ON, the others OFF.
- Read on the oscilloscope how many ns are lacking.
- Cut a measured length off the coax cable beneath the unit according to this formula:
number of ns
~5ns/m
- Refit cable connector - try again.
H2599
17
3.6.2 8DK138A

0DLQ
FB 0DLQ'HWHFWRU
,)'HWHFWRU
$*&
0DLQ
,)LQ
0DLQ
0DLQDWWHQ
'HWHFWRU
DWWHQ
0*& 0*&
OHYHO

,)RXW FB 6XP'HWHFWRU
0*& 0*&
OHYHO
6SDFH
6SDFHDWWHQ
'HWHFWRU
DWWHQ
$*&
6SDFH
,)LQ
6SDFH
,)'HWHFWRU
FB 6SDFH'HWHFWRU
Fig. 8 Block Schematic Diagram, 8DK138A
3.6.2 .1 Technical Data:
IF: AGC/MGC:
Maximum gain
19J1 and 19J2, IF INP MAIN and IF INP IF IN to IF OUT :+29dB
SPACE: Time constant in AGC :»24ms
Impedance :75ohm Input Power Measurement:
Return loss,70±13MHz :<-26dB Measured RF level :-72 to -18dBm
Level :-5 to -49dBm Monitored voltage :0 - 4VDC
Translation from DC
19J3 : IF OUT: volt to dBm :Not linear
Impedance :75ohm 19J4 and 19J5, Phase Control 1 and
Return loss 70±13MHz : <-24dBm Phase Control 2:
Level :-7 to -13dBm LP-filter, 3dB freq. :1kHz
Level :-10 to 0V
Max current :20mA
Phase step :1.4 degrees
18 H2599
Filterbanks: 3.6.2.3 Functional Description:

Numer of filters :3 Ref. to Block Schematic Diagram, page 17.
3 dB bandwidth of
filters :10MHz The purpose of the AGC amplifier is to present a
Center frequencies constant signal level to the Main, Space and Sum
of filters :60,70 &80MHz detector. Because there is a constant level pre-
sented to the filterbank detectors, whether the
Alarm: signal is subject to selective fading or not, the
Space Div. Alarm :Current Sink detectors do not need a lot of dynamic range.
Maximum voltage :+5V
Maximum current sink :25mA After the AGC amplifier, the signals are splitted
into a detector path and a signal path.
MGC control:
(Used for MGC/AGC control on "IF In the signal path, two attenuators, Main and Space
Ampl. & Filter, BP) Atten., control by which amount the two signals
are to be combined. This is subject to an algorithm
MGC Control :Current Sink described in chapter 3.6.2.4.
Maximum voltage :+5V
Maximum current sink :25mA The AGC amplifiers can be set in MGC mode.
Both amplifiers respond to the same signals,
Power Supply: +5V switch 19S1 and attenuator 19R1, at the front of the
-5.3V receiver group. In MGC mode, 19R1 is simulta-
-15.0V neously controlling both AGC amplifiers, and bot
-15.0V Main and Space Atten are set to minimum attenu-
ation.
3.6.2.2 General Description:
The 8DK138A Space Diversity Combiner In the detector path, the signals are splitted and
combines the signals from Main- and Space- combined into three filterbank detectors. The
receiver at IF after AGC. filterbanks are identical (three filters at 60, 70 and
80 MHz) but they act on different signals. The
By controlling the endless phase shifter and two Main and Space detectors act as level detectors
squelch functions, a micro-controller takes care for the AGC amplifiers. In addition, all detectors
of the combining algorithms. can measure in band dispersion such as tilt or
selective fading.
By switching 19S1 on the front it is possible to
set it in MGC (Manual Gain Control). The Sum detector always measures the combined
sum of the two signals, and the output is input to the
The MGC level can then be adjusted with pot- phase shifting algorithm. In this way, the two
meter 19R1 on the front of the receiver. signals are always in phase even if one of them is
8DK138A also measures and presents the RF not present at IF Out (due to dispersion etc).
input levels (into LNAs) for the Meter and
Alarm Unit. 3.6.2.4 Combining Algorithm
The main and space signals are almost always
combined, but at the relative signal strength level
at which they are received. The exception is if one
signal has excessive dispersion (e.g. tilt or selec-
tive fading). The poor signal is then not combined
with the good one. If both signals have excessive
dispersion, the signals are combined.
H2599
19
3.6.2.5 Main/space delay measurement

IF output RCVR side: Equalizer output
Main
IF in Equalizer Combiner
Space IF output RC
Delay cable
Fig. 10. Set-up for main/space delay measurement.
To switch signal between main and space, follow this procedure:

1. Turn off the receiver. Adjust potmeter to max ccw.
2. Switch on receiver in MGC. Wait for a LED flash.
3. Within 5 sec, turn potmeter to max cv. Wait for LED on.
4. Turn potmeter to ccv. Wait 5 sec. Observe: LED OFF. Wait 5 sec.
Until the receiver is switched off, the combiner switches between main and space. This is indicated by a
flashing LED. (Frequency: 20Hz) By means of S1, S2, S3, S4 (fig 5b) and delay cable (fig 10), adjust to
min delay difference. Delay test cables: 1 ns = 20 cm, 2 ns = 40 cm, 4 ns = 80 cm. (Normal delay cable:
approx 2 m)
Fig. 11. IF equalizer 8F267A Fig. 12 IF equalizer 8F264A
Input 7J4 - Output 7J3 Input 7J2 - Output 7J1
Adjustment Adjustment
IF response : R101/R103 IF response: R201/R203
Delay, low freq.: L102/C101 Tilt: R205
High freq.: 103/C102 Gain: R302
Tilt: R105 * Delay, low freq.: L202/C201
Delay: C103, C104 ** Delay, high freq: L203/C202
*) Resistor 2kW, 10kW (nom) or ¥ (Matching: C203, C204)

**) Add 10 pF if necessary.
Absolute delay can be adjusted by means of S1, S2, S3
and S4. (1 ns, 2 ns, 4 ns and 8 ns)
On Site:
Tilt: R303
Cable loss: R302
20 H2599
BRANCHING EQUIPMENT
NL290 - Family
H2854 Rev. A
© Nera AS
Branching Eqpt., NL290 - Family
TABLE OF CONTENTS
Page
1 BRANCHING EQUIPMENT 3
1.1 Branching for N+1 Systems 3

1.2 Hot Standby Systems 4
1.3 Channel Filters 4
2 H2854
1 BRANCHING EQUIPMENT
1.1 Branching for N+1 Systems
The branching equipment comprises transmitter and At the equipment side, the filters are terminated in
receiver microwave filters connected together via waveguide isolators in order to meet the required
circulators to the antenna port. return loss specifications.
The connection between the branching and the trans-
Figure 1 shows schematically the signal path through mitter and receiver varies with frequency. For fre-
the channel branching filters for a 3+1 radio-relay quencies from lower 6Ghz band and up to 13GHz, the
system. The transmit and receive sections are con- connections between the transmitter and branching
nected to the antenna run via a common antenna are made by flexible waveguide. For the 4GHz and
circulator. Optionally it is possible to connect the two 5GHz frequency bands, coaxial connection is used.
sections to separate antenna runs for dual polarization On the receive side, coaxial connection is used for
transmission. freqencies below 11GHz. The complete branching
Additional branching for space diversity transmission equipment is normally mounted within the radio-
is shown in Figure 2. relay cabinet.
TO ANTENNA
C’ C
B’p B’1 B’2 B ’3 Bp B1 B2 B3
Figure 1 Branching for N+1 Systems
A’p A’1 A’2 A ’3 Ap A1 A2 A3
PROT C HAN C HAN 1 CHA N 2 CHA N 3 PROT CH AN CH AN 1 C HAN 2 CHAN 3
F ROM ANTE NNA

XMT R’s R CVR’s
Bp B1 B2 B3
Figure 2 Branching for Space Diversity

Ap A1 A2 A3
P ROT CH AN CH AN 1 C HAN 2 CHAN 3
SPACE DIVERSITY RCVR’s
H2854 3
1.2 Hot Standby Systems
The branching system for a 1+1 hot standby configu-

ration is shown in Figure 3. mitter will take place if the alarm is activated on the
At the transmit side, a coaxial switch selects the transmitter which is carrying the traffic. At the
signal from one of the transmitters. The transmitter receive side, the incoming signal is divided in a 3dB
which has been assigned priority, will normally be hybrid. The output signal from one of the receivers is
connected to the antenna system. Switching to the selected by the RPS (Radio Protection Switching).
other trans
PROT CH
XMTRS
CHAN 1
HOT STBY LOGIC
TO ANTENNA
PROT CH
RCVRS
CHAN 1
Figure 3 Radio Channel Branching System for 1+1 Hot Standby
1.3 Channel Filters
The channel filters, one for each half-band, are type. These filters present a very low insertion loss.
waveguide filters (Butterworth) except for the 4GHz They are made from silver coated invar in order to
and 5GHz filters which are of the dielectric resonator obtain the best temperature stability.
NOTE:
Reference is made to attached principle
mechanical layout drawings for 11GHz 1+1,
6GHz 2+1, 6GHz HOT STANDBY and 3+1,
4GHz systems.
4 H2854
TABLE OF CONTENTS (Main items)
1,2,3 AFP310 FILTER BP 3.6-3.8GHz

4,5 AFP311 FILTER BP 3.8-4.0GHz
V28002 6,7,8 AFP312 FILTER BP 4.0-4.2GHz
10 87H84-3 CIRCULATOR, 3PORT, R40
11 AAK94-1 ADAPTOR UER40/SMA 3.6-3.9GHz
12 AWF165 CORNER UER40 90E X 2
13 AWF107 CORNER UER40 90H
Branching Assembly, 4GHz, 3+1 14 ARH58 TERMINATION UER40
15 AWW23-220 WG STRAIGHT UER40
Principle Drawing 16 AWW23-120 WG STRAIGHT UER40
17 AAF37 ADAPTOR PDR/UER40
20-23 BRACKETS
H2854 5
TABLE OF CONTENTS (Main items)

1 AFP286 FILTER BP 5925-6175MHz
2 AFP287 FILTER BP 6175-6425MHz
3 AGD42 COUPLER R70/SMA
4 AWF147 CORNER UER70 90E
V27706 5 AWH12 WG FLEX UER70
6 AAK84 ADAPTOR UER70/SMA
7 MKA99 ADAPTER UER70
8 87H7-1 ISO CIRCULATOR R70
9 87H8-1 CIRCULATOR R70
10 AWWA103-27.7 STRAIGHT UER70 AL
11 AAFA33 ADAPTOR UER70/UER70 TERM
12 AWWA103-37.4 STRAIGHT UER70
13 AWWA103-120 STRAIGHT UER70 AL
14 ARHA72 TERMINATION UER70 AL
15 AWF117 CORNER UER70 180E
Branching Assembly, 6GHz, 2+1 16 AWF118 CORNER UER70 90H
Principle Drawing 17 AAFA34 ADAPTOR UER70/PDR70
6 H2854
V2100630
TABLE OF CONTENTS (Main items) TABLE OF CONTENTS (Main items)
1 AFP286 FILTER BP 5925-6175MHz 12 87T20-3 POWER DIVIDER
2 AFP287 FILTER BP 6175-6425MHz 13 87R108-1M RESISTOR, TERMINATING
3 AGD42 COUPLER R70/SMA 14 ARHA76 TERMINATION UER70
4 AAK29-2 ADAPTOR UER70/SMA 15 AWFA171 CORNER UER70
5 AAK103 ADAPTOR UER70/SMA 16 UWMH2313 HF CABLE ASSY
6 10S226A SWITCH, COAXIAL ASSY 17 UWMH2314 HF CABLE ASSY
7 MKA99 ADAPTER UER70 18 UWMH2315 HF CABLE ASSY
8 87H7-1 ISO CIRCULATOR R70 19 UWMH2316 HF CABLE ASSY
9 87H8-1 CIRCULATOR R70 26 UWMH2323 HF CABLE ASSY
10 AAFA34 ADAPTER UER70/PDR70 27 87H42-8 ISO-CIRCULATOR COAXIAL
11 AAFA33 ADAPTOR UER70/UER70 THR.
Branching Assembly, 6GHz, Hot Standby

Principle Drawing
H2854 7
V27462 TABLE OF CONTENTS (Main items)
1 10F284A FILTER ASSEMBLY

2 AFP295 FILTER BP 11.2-11.7GHz
3 AGD40 COUPLER R120/SMA 10.7-11.2GHz
4 ARHA80 TERMINATION UER120
6 87H72-1 CIRCULATOR R120
7 AWFA178 CORNER UER120
8 AWFA177 CORNER UER120
9 AWH15 WG FLEX UER120
10 AWWA121-50 WG STRAIGHT UER120
11 AWWA121-73.2 WG STRAIGHT UER120
Branching Assembly, 11GHz, 1+1 12 MKA67 ADAPTER UER120
13 AWWA121-120 WG STRAIGHT UER120
Principle Drawing 14 AWFA180 CORNER UER120
16 AAH64 ADAPTER PDR100/UER120
8 H2854
POWER SUPPLY, 48V
0PR147B
H2189 Rev.A
© Nera AS
0PR147B
1. Technical Data:
Input voltage : 40 to 60Vnom. 48V

Output voltages : -5.0V ±0.25V, 50mA
+9.4V ±0.2V, 6.5A
48V INPUT POW ER TRANSFORMER -5V

FILTER RECTIFIER & FILTER +9.4V
GATE DRIVE
AUX.
14V
REG. PW M FEEDBACK
(14V)
Fig. 1 Block Diagram, 0PR147B.
2. Basic Principles of
Operation:
2.1 Converting Principle:
expected because of the energy which is stored in
The power supply contains a push-pull converter the primary inductance. This is not the case
with a switching frequency of 100 kHz. Push-pull because the rectifying diodes on the secondary side
means that a transformer is used with a center clamp the voltage. Unfortunately we do get a
tapped primary winding. The input voltage is transient because of the leakage inductance.
connected to the center-tap. The other 2
terminations are connected through semiconductor
switches to the return conductor of the input 2.2 Regulating Principle:
voltage.
In order to obtain output voltage, regulation is
The semiconductor switches are Field Effect needed. Feedback from the output voltage is
Transistors (FET). Those 2 transistors should needed and this feedback signal must change
never be switched on at the same time, otherwise a something in order to correct for the observed
short circuit is put across the input voltage and output error.
destroys the switches. It follows that they must be This power supply uses Pulse Width Modulation
switched on one at a time. (PWM). PWM means that the on-time of the
semiconductor switches is varied according to the
When one transistor is switched off before the feedback signal (see fig. 2). The system has a fixed
other one is switched on, a large transient could be frequency.
2 H2189
0PR147B
The converter uses a PWM-IC. This IC has two resistive divider) with a reference voltage. If a
outputs, each driving a FET. The IC uses an deviation occurs, the error is compensated for by
oscillator that runs at 200 kHz. That means that the feedback by either increasing or decreasing the
every output is switching at 100 kHz. The current that is sent through the LED of the
transformer is being switched with a 100 kHz optocoupler. This current is converted to a voltage
frequency. The outputs have a 200 kHz ripple and fed to pin 2 on the PWM-IC. This voltage is
voltage, due to the split windings on the compared with a triangular voltage. When the
transformer. triangular voltage overtakes the feedback voltage,
the output is switched off (that means the FET is
The feedback signal is generated by comparing switched off).
the output voltage (in our case scaled down by a
ON OFF
10 usec 10 usec 10 usec
Fig. 2 Timing and Modulation of 1 Output of the IC.
3. Circuit Description:
Power Supply 0PR147B contains the following These components are needed for the proper
blocks: (See fig. 1). operation of the IC.
* input filter The power transformer is a push-pull transformer.

* auxiliary voltage generator By switching the MOSFET's "on" and "off" a
* pulsewidth modulator square wave is generated at the transformer output.
* power transformer, rectifiers and filter This square wave is rectified and filtered by a LC-
filter on the main output (9.4V). The -5V output is
The main function of the input filter is to series regulated by a voltage regulator IC. An
attenuate the power supply switching noise. The auxiliary voltage is also generated to drive the error
filter provides attenuation for COMMON MODE amplifier in the feedback.
NOISE and "differential" noise.
The feedback samples the output voltage on the
The auxillary supply generates about 14V, which 9.4V output through a resistor divider. This sample
drives the pulse width modulator and the power voltage is compared with a reference voltage. Any
MOSFET gate drivers. difference between these two voltages is amplified
The pulse width modulator consists of one and transmitted through the optocoupler to the
integrated circuit and additional components. pulse width modulator.
H2189
3
0PR147B
%/2&.',$*5$0
+5V
V-in 15 REFERENCE 16 VREF
REGULATOR
U.V. Power to 12 CA
sense internal FLIP
circuitry FLOP
OSC 3 T 11 E
A
RT 6 CLOCK
OSC
CT 7
RAMP R
+ S
PW M 13 CB
COMP S
COMP 9 - LATCH
V-in
14 EB
INV INPUT 1 -
E/A 1K
+
N.I INPUT 2 10 SHUTDOW N
V-in
200mV 10K
4 - 8
C.L. (+) SENSE C/L GND
C.L. (-) SENSE 5 +
&211(&7,21',$*5$0
',/7239,(:
-RU13DFNDJH
INV. INPUT 1 16 +5V VREF
NON-INV. INPUT 2 15 +VIN
OSC./SYNC 3 14 EMITTER B
C.L.(+) SENSE 4 13 COLLECTOR B
C.L.(-) SENSE 5 12 COLLECTOR A
RT 6 11 EMITTER A
CT 7 10 SHUTDOW N
GROUND 8 9 COMPENSATION
Fig. 3A/B Integrated Circuit, UC1524A
4 H2189
POWER SUPPLY, 24V
0PR159A
H2066 Rev. A
© Nera AS
0PR159A
1. Technical Data:
Input voltage : 20 to 30v, nom. 24V

Output voltages : -5.0V ±0.25V, 50mA
+9.4V ±0.2V, 6.5A
24V INPUT POW ER TRANSFORMER -5V

FILTER RECTIFIER & FILTER +9.4V
GATE DRIVE
AUX.
14V
REG. PW M FEEDBACK
(14V)
Fig. 1 Block Diagram, 0PR159A.
2. Basic Principles of
Operation:
The power supply contains a push-pull converter one is switched on, a large transient will occur
with a switching frequency of 100 kHz. Push-pull because of the energy stored in the primary leakage
means that a transformer is used with a center tapped inductance.
primary winding. The input voltage is connected to
the center-tap. The other 2 terminations are 2.2 Regulating Principle:
connected through semiconductor switches to the
return conductor of the input voltage. In order to obtain output voltage, regulation is
needed. Feedback from the output voltage is needed
The semiconductor switches are Field Effect and this feedback signal must change something in
Transistors (FET). These (2) transistors should never order to correct for the observed output error.
be switched on at the same time, otherwise a short This power supply uses Pulse Width Modulation
circuit is put across the input voltage and destroys the (PWM). PWM means that the on-time of the
switches. semiconductor switches is varied according to the
feedback signal (see fig. 2). The system has a fixed
When one transistor is switched off before the other frequency.
2 H2066
0PR159A
The converter uses a PWM-IC. This IC has two resistive divider) with a reference voltage. If a
outputs, each driving a FET. The IC uses an oscillator deviation occurs, the error is compensated for by the
that runs at 200 kHz. That means that every output is feedback by either increasing or decreasing the
switching at 100 kHz. The transformer is being current that is sent through the LED of the
switched with a 100 kHz frequency. The outputs optocoupler. This current is converted to a voltage
have a 200 kHz ripple voltage, due to the split and fed to pin 2 on the PWM-IC. This voltage is
windings on the transformer. compared with a triangular voltage. When the
The feedback signal is generated by comparing the triangular voltage overtakes the feedback voltage,
output voltage (in our case scaled down by a the output is switched off .(Which means that the
FET is switched off).
ON OFF
Power Supply 0PR159A contains the following

blocks: (See fig. 1).
components are needed for the proper operation of
* input filter the IC.
* auxiliary voltage generator
* pulsewidth modulator The power transformer is a push-pull transformer.
* power transformer, rectifiers and filter By switching the MOSFET's "on" and "off" an
square wave is generated at the transformer output.
The main function of the input filter is to attenuate the This square wave is rectified and filtered by a LC-
power supply switching noise. The filter provides filter on the main output (9.4V). The -5V output is
attenuation for COMMON MODE NOISE and series regulated by a voltage regulator IC. An
"differential" noise. It also contains an "inrush auxiliary voltage is also generated to drive the error
current limiter" resistor, NTC (R26). amplifier in the feedback.
The feedback samples the output voltage on the 9.4V
The auxillary supply generates about 14V, which output through a resistor divider. This sample
drives the pulse width modulator and the power voltage is compared with a reference voltage. Any
MOSFET gate drivers. difference between these two voltages is amplified
The pulse width modulator consists of one integrated and transmitted through the optocoupler to the pulse
circuit and additional components. These width modulator.
H2066
3
0PR159A
%/2&.',$*5$0
+5V
REGULATOR
U.V. Power to 12 CA
sense internal FLIP
circuitry FLOP
OSC 3 T 11 EA
RT 6 CLOCK
OSC
CT 7
RAMP R
+ S
PWM 13 CB
COMP S
COMP 9 - LATCH
V-in
- 14 E B
INV INPUT 1 E/A
+ 1K
V-in
200mV 10K
4 - 8
5 +
C.L. (-) SENSE
&211(&7,21',$*5$0
',/7239,(:
-RU13DFNDJH
RT 6 11 EMITTER A
CT 7 10 SHUTDOW N
Fig. 3A/B Integrated Circuit, UC2524AN
4 H2066
8MNF83A
MODULATOR
8MNF83A
H2805 Rev. B
© Nera AS
1
H2805
8MNF83A
TABLE OF CONTENTS
Page:
1 TECHNICAL DATA 3
1.1 Data and IF Connections 3
1.2 Alarm Indicator 3
1.3 Power Requirements 3
2 GENERAL DESCRIPTION 4
3 FUNCTIONAL DESCRIPTION 5
3.1 Main Functions 5
3.2 Other Functions 7
2
H2805
8MNF83A
1 TECHNICAL DATA
1.1 Data and IF Connections:
Main Inputs:
CMI INPut (J2) : Data 155.520 Mb/s or 139.264 Mb/s
CMI/1V, 75W (G.703)
PROTection INPut CMI (J16) : Data 155.520 Mb/s, CMI/ECL, 75 W/-2V.
DATA 2.048 Mb/s (J14) : Data 2.048 Mb/s, HDB3, G.703
Available as an option (wayside traffic).
Main Outputs:
IF OUTput CMI (J1) : 70 Mhz, 0DbM, 75 W
IF TEST output -10 dB (J3) : 70 MHz, 10 dB attenuation, 75W
PROTection OUTput (J15) : Data 155.520 Mb/s, CMI/ECL, 75W/ -2V
1.2 Indicator:
Name: Description: Comments:
MOD_UNIT_ALM LOS_ALM_MOD Red LED on front of the unit
+LOF1_MOD
+2M_SYNC_ALM_MOD
+311_PLL_ALM_MOD
+2M_WAY_ALM_MOD
+TRELLIS_PLL_ALM
+IF_OUT_ALM_MOD
1.3 Power Requirements:
: +5.0V / 1.0A
: -5.2V / 0.9A
: +15.0V / 0.18A
: -15V / 2mA
3
H2805
8MNF83A
2 GENERAL DESCRIPTION
The modulator unit contains all baseband and Functions for mapping a 139.264 Mbit/s
modem functions for the transmit side. Functions plesiochronous bit stream into the STM-1-frame
are provided both for Regenerator Section Ter- is built into the unit. Reconfiguration between the
mination (RST) and for Multiplexer Section Ter- two interfaces (140/155Mb/s) can easily be per-
mination (MST) according to ITU-T recommen- formed.
dations. The different modes of the modulator A block diagram of the main functions of the
unit are selected by switches within the unit. modulator-unit is shown in fig.1.
2 MHz ext SYNC
2 Mb/s G.703
Wayside traffic
TCM- IF
D/A
CMI C4 ENCODING O UT
CMI CABLE STM I
CODEC MUX MAPPING & M OD.
(ASIC) D/A
TEST OUT
39 MHz
PROT INP CLK
CMI POH INSERT 48 MHz PLL
PLL CLK SIGNAL
SIGNAL
311 MHz 311 MHz 48 MHz

VCXO VCXO
SOH IN/OUT
CMI
ENCODER
CMI TO
PROT. CHANNEL
Fig. 1 Main Functions of the Modulator Unit
The modulator unit is built on one circuit Details of the switch settings are given in Chapter
board and mounted in a box as shown in fig.2. 4 (Configuration).
The modulator unit has a number of switches The same modulator unit is used both for protection
which is used to configure the unit. channels and for main channels.
4
H2805
8MNF83A
3 FUNCTIONAL DESCRIPTION
3.1 Main Functions:
A block diagram of the main functions of the modulator is shown in fig1.
A brief description of these functions is given here:
· CABLE EQUALIZER: · TCM-ENCODER AND FIR FILTER:
The CMI input data signal is applied to the cable These functions are also realised in an ASIC in
equalizer which automatically compensates for CMOS technology. The Trellis Code Modulation
varying cable attenuation according to ITU-T (TCM)-encoder function is the transmit part of the
Rec. G.703. modulation coding used to perform error
correction.Trellis coded modulation is a combined
· CMI CODEC: coding and modulation scheme for improving the
The CMI CODEC is an Application Specific Inte- reliability of a digital transmission system without
grated Circuit (ASIC) realized in ECL-technol- increasing the transmitted power or the required
ogy. It has functions for CMI-data decoding, bandwidth. The TCM-encoder consists of a differ-
clock recovery, split and converting of the data- entional encoder, a convolutional encoder and the
signal prepared for CMOS technology. The four-dimensional mapper. The differentional encod-
CMI CODEC is also used to CMI-encode er is used to make the transmitted symbols invariant
the data signal going to the XMTR-switch-unit. to phase rotations. The four dimensional symbol is
transmitted in two consecutive two-dimensional sym-
· C4-MUX: bols (I & Q) in a 128 points cross constellation.
The C4-MUX is an ASIC performing the mapping
of 139.264Mbit/s into a STM-1 frame generated The FIR-filter function performs half of the total
by this circuit. This function is only used if the system filtering. The other half of the system filter-
139.264Mbit/s interface is selected. Traffic is ing is done in a Surface Acoustic Wave (SAW)-filter
carried straight through this circuit if the STM-1 in the receiver group. The FIR-filter function real-
interface is selected. The C4-mapping is done ized is a 26 taps digital square root cosine rolloff-
according to ITU-T Rec. G.707-709 and filter with a=0.34. Filter for both I & Q-channel is
Rec. G. 782-784. included in this ASIC.
· STM-1 PROCESSOR:
· D/A (DIGITAL TO ANALOG-CONVERTER):
The STM-1 processor is an ASIC performing the
One 10-bit D/A-converter is used on each chan-
termination of incoming STM-1 signal (for STM-
nel (I & Q). The D/A-converters for the I & Q-
1-interface) and also rebuilding the STM-1 frame
channel converts the 10-bit input data to an ana-
according to the rules specified in ITU-T Rec.
log signal prepared for modulation. The D/A-
G.707-709 and Rec. G.782-784. All extraction
converters are standard commercial devices.
of Section OverHead (SOH)-bytes from the in-
coming STM-1-frame and insertion of new SOH-
· MODULATOR (MOD):
information is done in this circuit. The circuit is
This is the analog part of the modulator-unit. The
also splitting the signal before it is applied to the
spectrum applied to the modulator is bandlimited
CMI ENCODER, and further to the XMTR-switch
by a lowpass filter to remove the repetitive part
unit. Other main functions performed in this circuit:
of the spectrum generated in the preceding dig-
a) STM-1-frame synchronization
tal FIR-filter. The I- and Q-signals are modu-
b) Descrambling and Scrambling
lated on individual 70MHz carrier frequencies
c) Bit Interleaved Parity (BIP)-checking
which are 90° phase shifted. The two modulated
and generation
signals are combined at the modulator output. In
d) AU-4 pointer processing
order to satisfy the mask requirement for the
transmitted spectrum two band pass filters are
The burst-encoder is a bit-interleaver used to rear- inserted prior to the IF output. An IF equalizer is
range the bits in the STM-1-frame to counteract the used to equalize the delay and amplitude response
burst behaviour of the TCM process. After the burst- of the IF-filters. An IF-output alarm is activated if the
encoder, the signal is passed to the TCM-encoder and IF-level falls below about -6dBm.
FIR-filter.
5
H2805
8MNF83A
3J11
3J1
3J12
3J13
3J3
ANALOGUE MODULATOR
3P1
D/A CONVERTERS 3H1
TRELLIS CODER
& FIR - FILTER
PLL w/VCXO 48 MHz
STM - 1
PROCESSING
C4 - MUX
PLL w/VCXO 311 M

3P2
CMI CODEC
CABLE
EQUALIZER 3J14
3J15
3J13
Fig.2 Unit Board Diagram

6
H2805
8MNF83A
3.2 Other Functions:
The modulator also includes circuits for

2 Mb/s wayside input, 2 MHz external sync · SOH Bus Output/Input:
input, B1 and B2 parity error outputs, POH-bus
input, SOH-bus output/input, alarm outputs and Section OverHead may be extracted/inserted
different alarm- and control signal inputs. from/to the STM-1-frame. Bus receivers/drivers
are included to transport the SOH-bus to/from
· 2Mb/s Wayside: the service rack where different adapters can be
connected for access to the SOH-bytes.
Line receiver and HDB-3 decoding circuits for
2.048Mb/s wayside traffic are included in the · POH BUS Input (Optional):
modulator. The interface is 75ohm, unbalanced
(G.703). By use of adapters, it is possible to insert Path
Overhead in the STM-1 Frame when C4-map-
ping is active (140 Mb/s input).
· B1 and B2 parity error pulses are available out
of the modulator. · Alarm Outputs:
· 2MHz external sync (optional): Circuits for alarm detection and alarm
combinations are included in the unit.
It is possible to use external 2MHz sync-signal An overview of the alarms and their combinations
for synchronization of the 155 Mb/s bit rate. is given below:
Alarm Name: Alarm Description: Comments:

LOS_ALM_MOD Alarm indicating CMI connected to ACU
input is missing
LOF1_MOD Alarm indicating loss of connected to ACU

frame (STM-1)
2M_SYNC_ALM_MOD Alarm indicating loss of connected to ACU

2MHz_EXT_SYNC
311 M_PLL_ALM_MOD Alarm indicating connected to ACU

311 MHz PLL out of lock
2M_WAY_ALM_MOD Alarm indicating loss of connected to ACU

2 Mb/s wayside traffic
Trellis_PLL_ALM Alarm indicating connected to ACU

48 Mhz PLL out of lock
IF_OUT_ALM_MOD Alarm indicating IF level connected to ACU

dropped below abt. -6 dBm
PJE_MOD Pointer justification connected to ACU

Event (STM-1)
AIS_INP_140 Indicating AIS in received connected to ACU

140 Mb/s traffic (C4-MUX)
7
H2805
8MNF83A
MS_AIS_MOD Indicating received connected to ACU

MS_AIS in STM-1
MS_FERF_MOD Alarm indicating connected to ACU

received MS_FERF
AU_PATH_AIS_MOD Indicating received connected to ACU

AU_PATH_AIS
LOP_MOD Alarm indicating connected to ACU

loss of Ponter (STM-1)
155 MB_INT Indicating STM-1 data connected to ACU

into the modulator
XMTR_SW_ALM_MOD LOS_ALM_MOD connected to ACU

+LOF1_MOD
+311M_PLL_ALM_MOD
Alarms and Control Signal Inputs:

B3_ERR_DEM B3 parity error pulses from demodulator
POH_RFAIL_DEM from demodulator
MS_RFAIL_DEM from demodulator
RMT_RESET_SU_MOD Remote SU-reset
ATPC1_HIGHER ATPC control signals
ATPC2-LOWER ATPC control signals
SYNC_IND_EN 2M Sync Indicator from back panel
DIS_WAY_MOD Disables 2 Mb/s wayside traffic from back panel
EWBER_SEC_IND section alarm, repeater
SYNCL_ALM_DEM section alarm, repeater
L_BER_SEC_IND section alarm, repeater
VIT_SEC_ERR section alarm, repeater
SEC_ALM_DIS Disables section alarms from back panel
CMI_INP_SEL Selects regular or protection input from back panel
EN_REP For future use with repeater from back panel
EN_PROT_MOD Selects protection ch mode from RPS

8
H2805
8MNF83A
ENABLE RPS control signals from RPS
READ RPS control signals from RPS
9
H2805
MODULATOR, 128TCM
8MNF83C
H2972 Rev. A
8MNF83C
2 H2972
8MNF83C
Table of Contents
1. TECHNICAL DATA 4
1.1 Data and IF connections 5

1.2 Indicator 5
1.3 Power requiremensts 5
2. GENERAL DESCRIPTION 6
3. FUNCTIONAL DESCRIPTION 8

3.3 Alarm Outputs 10
3.4 Alarm and Control Signal Inputs 11
4. OVERVIEW of DIL-SWITCH and STRAP FUNCTIONS 12
4.1 DIL-switch Functions 12

4.2 Strap Functions 12
5. INTERFACE ON CONNECTORS 3P1 AND 3P2 14
5.1 Upper Connector, 3P1 14

5.2 Lower Connector, 3P2 15
H2972
3
8MNF83C
1. Technical Data
Main Inputs Connectors:
CMI Input 3J2 Data 155.520 Mb/s or 139.264 Mb/s

CMI/1V, 75 W ( G.703 )
Protection Input CMI 3J16 Data 155.520 Mb/s, CMI/ECL, 75 W / -2V
Data 2.048 Mb/s 3J14 Data 2.048 Mb/s, HDB3, 75 W ( G.703 )

Available as an option ( wayside traffic )
Main Outputs:
IF Output 3J1 70 MHz, 0 dBm, 75 W
IF Test Output 3J3 70 MHz,10 dB attenuation, 75 W
Protection Output CMI 3J15 Data 155.520 Mb/s, CMI/ECL, 75 W / -2V
2 MHz Sync Input:
2 MHz clock 3P1, pin 20A & 20C 2.048 MHz sync clock, RS422
2 MHz Sync Output:
2 MHz clock ( strapable option ) 3J11 2.048 MHz sync clock,

±1V, capasitive coupled, 75 W unbalanced.
( from BUS1- clock in the 155 Mb/s data input )
720 kb/s O-bit Channel:
O-bit input ( strapable option ) 3J11 Data 720 kb/s, NRZ, CMOS-level
O-bit clock output ( strapable option ) 3J12 Clock 720 kHz, CMOS-level
O-bit byte output ( strapable option ) 3J13 Syncpulse, CMOS-level
This 720 kb/s channel is used for insertion of overhead bits when the C4-MUX is active. Not in use.
External LO Synchronization:
LO Master Output ( strapable option ) 3J12 70 MHz, -5dBm, 75 W

LO Slave Input (strapable option ) 3J13 70 MHz, -5dBm, 75 W
4 H2972
8MNF83C
1.2 Indicator:
MOD_UNIT_ALM LOS_ALM_MOD Red LED on the front of the unit

+LOF1_MOD
+2M_SYNC_ALM_MOD
+311_PLL_ALM_MOD
+2M_WAY_ALM_MOD
+TRELLIS_PLL_ALM
+IF_OUT_ALM_MOD
1.3 Power requirements:
Power Requirements : +5.0V / 1.0A

: -5.2V / 0.9A
: +15.0V / 0.18A
: -15V / 2mA
H2972
5
8MNF83C
The modulator unit is built on one circuit board and mounted Functions for mapping a 139.264 Mbit/s plesiochronous bit
in a box. stream into the STM-1-frame is built into the unit. Reconfig-
The unit contains all baseband and modem functions for the uration between the two interfaces (140/155Mb/s) can easily
transmit side. Functions are provided both for Regenerator be performed.
Section Termination (RST) and for Multiplexer Section The same modulator unit is used both for protection channels
Termination(MST) according to ITU-T recommendations. and for main channels.
The different modes of the modulator unit are selected by
Details of the switch settings are given in Chapter 4 (Config-
switches within the unit. uration) in the User manual.
2 MHz ext SYNC
2 MHz SYNC OUT

2 Mb/s G.703
Wayside traffic PROM
TCM- IF
D/A
CMI C4 ENCODING OUT
CMI CABLE STM I
(ASIC) D/A
39 MHz TEST OUT
PROT INP CLK
POH INSERT 48 MHz PLL
CMI
PLL CLK SIGNAL
SIGNAL
LO LO
311 MHz 48 MHz SLAVE MASTER
311 MHz
VCXO VCXO INP OUT
SOH IN/OUT
CMI
ENCODER
CMI TO PROTECTION CHANNEL
6 H2972
8MNF83C
3J11
3J1
3J12
3J13
3J3
ANALOG MODULATOR
3P1
D/A CONVERTERS 3H1
TRELLIS CODER
& FIR - FILTER
PLL w/VCXO 48 MHz
STM - 1
PROCESSING
C4 - MUX
PLL w/VCXO 311 M

3P2
CMI CODEC
CABLE
EQUALIZER 3J14
3J15
3J13
Fig. 2 Unit Board Diagram
H2972
7
8MNF83C
3.1 Main Functions: · TCM-ENCODER AND FIR FILTER:

These functions are realised in a programmable ASIC in
A block diagram of the main functions of the modulator is
CMOS technology. The Trellis Code Modulation (TCM)-
shown in fig1. A brief description of these functions is given
encoder function is the transmit part of the modulation
here:
coding used to perform error correction. Trellis coded
· CABLE EQUALIZER: modulation is a combined coding and modulation scheme
The CMI input data signal is applied to the cable equalizer for improving the reliability of a digital transmission system
which automatically compensates for varying cable attenu- without increasing the transmitted power or the required
ation according to ITU-T Rec. G.703. bandwidth. The TCM-encoder consists of a differentional
encoder, a convolutional encoder and the four-dimensional
mapper. The differentional encoder is used to make the
· CMI CODEC: transmitted symbols invariant to phase rotations. The four-
The CMI CODEC is an Application Specific Integrated Circuit dimensional symbol is transmitted in two consecutive two-
(ASIC) realized in ECL-technology. It has functions for CMI- dimensional symbols (I & Q) in a 128 points cross
data decoding, clock recovery, split and converting of the data- constellation. T h e
signal prepared for CMOS technology. T h e FIR-filter function performs half of the total system filtering.
CMI CODEC is also used to CMI-encode the Protection The other half of the system filtering is done in a Surface
channel data signal going to the XMTR-switch-unit. Acoustic Wave (SAW)-filter in the receiver group. The
FIR-filter function realized is a 28 taps digital square root
cosine rolloff-filter with a= 0.29. Filter for both I & Q-
channel is included in this ASIC. Configuration data for the
· C4-MUX:
ASIC and the FIR-filter coefficients are loaded from an
The C4-MUX is an ASIC performing the mapping of
external serial PROM and stored in
139.264Mbit/s into a STM-1 frame generated by this circuit.
RAMs.
This function is only used if the 139.264Mbit/s interface is
selected. Traffic is carried straight through this circuit if the · D/A (DIGITAL TO ANALOG-
STM-1 interface is selected. The C4-mapping is done CONVERTER):
according to ITU-T Rec. G.707-709 and Rec. G. 782-784.
One 10-bit D/A-converter is used on each channel (I & Q). The
· STM-1 PROCESSOR: D/A-converters for the I & Q-channel convert the 10-bit input
data to an analog signal prepared for modulation. The D/A-
The STM-1 processor is an ASIC performing the termination
of incoming STM-1 signal (for STM-1-interface) and also
rebuilding the STM-1 frame according to the rules specified in
ITU-T Rec. G.707 and Rec. G.782-784. · MODULATOR (MOD):
All extraction of Section OverHead (SOH)-bytes from the
This is the analog part of the modulator unit. The spectrum
incoming STM-1-frame and insertion of new SOH-informa-
applied to the modulator is bandlimited by a lowpass filter to
tion is done in this circuit. The circuit is also splitting the signal
remove the repetitive part of the spectrum generated in the
before it is applied to the CMI ENCODER, and further to the
preceding digital FIR-filter. The I- and Q-signals are modulated
XMTR-switch unit.
on individual 70MHz carrier frequencies which are 90° phase
Other main functions performed in this circuit:
shifted. The two modulated signals are combined at the
a) STM-1-frame synchronization modulator output. In order to satisfy the mask requirement for
b) Descrambling and Scrambling the transmitted spectrum two band pass filters are inserted prior
c) Bit Interleaved Parity (BIP)-checking and generation to the IF output. An IF equalizer is used to equalize the delay
d) AU-4 pointer processing and amplitude response of the IF-filters. An IF-output alarm
is activated if the IF-level falls below about -6dBm.
8 H2972
8MNF83C
3.2 Other Functions: · 2MHz sync output (optional):

A 2MHz sync-signal derived from the incoming 155 Mb/s
The modulator also includes circuits for 2 Mb/s wayside data is fed to a coax connector. To be used in connection with
input, 2 MHz external sync input, B1 and B2 parity error an external Sync Unit.
outputs, POH-bus input, SOH-bus output/input, 2 MHz
sync clock output, alarm outputs and different alarm- and · SOH Bus Output/Input:
control signal inputs.
Section OverHead may be extracted/inserted from/to the
· 2Mb/s Wayside: STM-1-frame. Bus receivers/drivers are included to trans-
port the SOH-bus to/from the service rack where different
Line receiver and HDB-3 decoding circuits for 2.048Mb/s adapters can be connected for access to the SOH-bytes.
wayside traffic are included in the modulator. The interface
is 75ohm, unbalanced (G.703).
· POH BUS Input (Optional):
· B1 and B2 parity error pulses: By use of adapters in the service rack, it is possible to insert
B1 and B2 parity error pulses from incoming 155 Mb/s data Path Overhead in the STM-1 Frame when
are available out of the modulator. C4-mapping is active (140 Mb/s input).
· 2MHz external sync input (optional): · External 70 MHz LO Synchronizing
It is possible to use external 2MHz sync-signal for synchro- (Optional):
nization of the 155 Mb/s bit rate.
It is possible to syncronize the 70 MHz LO in two
modulator units in a master / slave configuration.
The 70 MHz carrier from the master modulator is then used
as LO in the slave modulator. This function may be used in
co-channel systems.
H2972
9
8MNF83C

Circuits for alarm detection and alarm combinations are included in the unit.
An overview of the alarms and their combinations is given below:
LOS_ALM_MOD Alarm indicating CMI-data connected to ACU

input is missing

frame (STM-1)

2MHz_EXT_SYNC


TRELLIS_PLL_ALM Alarm indicating connected to ACU


PJE_MOD Pointer Justification Event connected to ACU

(STM-1)


MS_AIS in STM-1

received MS_FERF

AU_PATH_AIS

loss of Pointer (STM-1)
155 MB_INT Indicating STM-1- data connected to ACU

into the modulator

+LOF1_MOD
+311M_PLL_ALM_MOD
MASTER_IND_MOD Indicating 70 MHz LO connected to ACU

master status in the modulator
10 H2972
8MNF83C
3.4 Alarm and Control Signal Inputs:
External alarm and control signal inputs to the Modulator are listed below:
Alarm / Signal Name: Alarm/ Signal Description: Comments:
H2972
11
8MNF83C
4. OVERVIEW of DIL-SWITCH and STRAP FUNCTIONS
4.1 DIL-switch Functions:
Function ( Switch ON ): Function ( Switch OFF ):
S501 (C4-MUX/STM1)
S1 Byte C2 = 1 Byte C2 =0
S2 Byte C2: switch-controlled Byte C2: 2M BUS-controlled
S3 Descrambler ; Radio Descrambler ; SDH
S4 Scrambler enabled Scrambler disabled
S5 Serial AU-alarms enabled Parallell AU-alarms
S6 Not used Not used
S502 ( STM1 )
S1 SOH - C1; bit 0 = 1 SOH - C1; bit 0 = 0
S503 ( Config. switch )
S1 155.520 Mb/s interface 139.264 Mb/s interface

S2 RF ID 0 = 1 RF ID 0 = 0
S3 RF ID 1 = 1 RF ID 1 = 0
S4 Multiplexer Section Terminal Regenerator Section Terminal
S5 New frameword inserted Frameword retransmitted
S6 AU-Pointer Pros enabled AU-Pointer disabled
S7 RSOH Insert from 2Mb/s BUS RSOH Insert ctrld by 2Mb/s BUS
S8 New C1-byte inserted C1-byte retransmitted
4.2 Strap Functions:
Function Function
W101 Pos 1-2 : CMI-ECL on Pos 2-3 : CMI-capasitive on Prot Out Data
Prot Out Data (3J15) (3J15)
W103 Pos 1-2 : CMI-Decoder: 155 Mb/s Pos 2-3 : CMI-Decoder : 140 Mb/s
12 H2972
8MNF83C
Function Function
W401 Pos 1-2 : Select data input : Prot Inp (3J16) Pos 2-3 : Select data input : Reg Inp (3J2)
(Strap W401 is used for test and default setting
( pos 1-2 ), the inputs are normally selected by
external control signal from back panel. )
W402 Pos 1-2 : Enable protection channel : Pos 2-3 : Input from Reg Inp (3J2)
Protection data input (3J16)
( Strap W402 is used for test and default setting
( pos 2-3 ), the function is normally controlled by
external control signals from the RPS-unit. )
W403 Pos 1-2 : BUS1 Byte = POH Sync Out Pos 2-3 : BUS1 Byte = RSOH Sync Out
W404 Pos 1-2 : BUS1 Clk = POH Clock Out Pos 2-3 : BUS1 Clk = RSOH Clock Out
W405 Pos 1-2 : BUS1 D1+ =POH Data1 Inp Pos 2-3 : BUS1 D1+ = RSOH Data1 Out
W406 Pos 1-2 : BUS1 D1- =POH Data1 Inp Pos 2-3 : BUS1 D1- = RSOH Data1 Out
W407 PosOpen : BUS1 = POH-modus PosClosed (1-4/2-3) : BUS1 D2+/D2-

= RSOH Data2 Out
W601 Pos 1-4 : Normal ;( Q-Channel D/A-output to
Q-Channel BB-LP-filter ) Pos Open : Test
W602 Pos Open: Normal ; Used as Testpoint for

Q-channel BB-LP-filter
W702 Pos 1-4 : Normal, ( Modulator to Filter

1 BP 70MHz ) Pos Open : Test
W801 Pos 1-4 : Normal, ( Filter 1 BP 70MHz to

Equalizer ) Pos Open : Test
W901 Pos 1-4 : Normal; ( I-Channel D/A-output to

I-Channel BB-LP-filter ) Pos Open : Test

I-channel BB-LP-filter.
W911 Pos 1-2 : 2 MHz Sync Clk output on 3J11. Pos 2-3 : 720 kb/s O-Data input on 3J11.
W912 Pos 1-2: 70 MHz LO Master out on 3J12. Pos 2-3 : 720 kHz O-CLK output on 3J12.
W913 Pos 1-2 : 70 MHz LO Slave inp on 3J13. Pos 2-3 : Sync O-Byte output on 3J13.
H2972
13
8MNF83C
5. INTERFACE on CONNECTORS 3P1 and 3P2

5.1 Upper Connector, 3P1:
Pin nr: Signal name: Pin nr: Signal name:
01a BUS1_DISABLE 17a ALM_SEL_C

01c GND 17c ALM_SEL_B
02a BUS1_D1- 18a ALM9_16_MOD
02c BUS1_D1+ 18c ALM1_8_MOD
03a BUS1_CLK- 19a GND

03c BUS1_CLK+ 19c CMI_INP_SEL
04a BUS1_BYTE- 20a 2M_SYNC_MOD-
04c BUS1_BYTE+ 20c 2M_SYNC_MOD+
05a BUS1 D2- 21a GND

05c BUS1_D2+ 21c 2M_SYNC_MOD_DIS
06a NC 22a XMTR_SW_ALM_MOD
06c GND 22c NC
07a NC 23a EN_REP

07c NC 23c NC
08a NC 24a EWBER_SEC_IND
08c NC 24c EN_PROT_MOD
09a NC 25a SYNCL_ALM_DEM

09c NC 25c LBER_SEC_IND
10a NC 26a GND
10c NC 26c PJE_MOD
11a BUS3_DISABLE 27a GND

11c GND 27c B1_ERR_MOD
12a BUS3_D1- 28a GND
12c BUS3_D1+ 28c B2_ERR_MOD

13c BUS3_CLK+ 29c B3_ERR_DEM
14a BUS3_BYTE- 30a GND
14c BUS3_BYTE+ 30c SEC_ALM_DIS

15c BUS3_D2+ 31c SYNC_IND_EN
16a ALM_SEL_A 32a GND
16c GND 32c VIT_SEC_ERR
14 H2972
8MNF83C
5.2 Lower Connector, 3P2:
01a GND 17a +5V

01c GND 17c +5V
02a -15V 18a +5V
02c -15V 18c +5V
03a -15V 19a +5V

03c -15V 19c +5V
04a GND 20a +5V
04c GND 20c +5V
05a +15V 21a +5V

05c +15V 21c +5V
06a +15V 22a +5V
06c +15V 22c +5V
07a +15V 23a +5V

07c +15V 23c +5V
08a NC 24a GND
08c GND 24c GND
09a -5.2V 25a GND

09c -5.2V 25c GND
10a -5.2V 26a RMT_RESET_SU_MOD
10c -5.2V 26c READ
11a -5.2V 27a POH_RFAIL_DEM

11c -5.2V 27c MS_RFAIL_DEM
12a -5.2V 28a NC
12c -5.2V 28c NC
13a -5.2V 29a NC

13c -5.2V 29c NC
14a -5.2V 30a NC
14c -5.2V 30c NC
15a GND 31a ATPC1_HIGHER

15c GND 31c ATPC2_LOWER
16a NC 32a ENABLE
16c NC 32c DIS_WAY_MOD
H2972
15
MODULATOR, 64TCM
8MNF89A
H2970 Rev. A
8MNF89A
2 H2970
8MNF89A
Table of Contents
1. TECHNICAL DATA 4
1.1 Data and IF connections 5

1.2 Indicator 5
1.3 Power requiremensts 5

3.3 Alarm Outputs 10
3.4 Alarm and Control Signal Inputs 11
4. OVERVIEW of DIL-SWITCH and STRAP FUNCTIONS 12
4.1 DIL-switch Functions 12

4.2 Strap Functions 12
5. INTERFACE ON CONNECTORS 3P1 AND 3P2 14
5.1 Upper Connector, 3P1 14

5.2 Lower Connector, 3P2 15
H2970 3
8MNF89A
1. Technical Data
Main Inputs Connectors:
CMI Input 3J2 Data 155.520 Mb/s or 139.264 Mb/s

CMI/1V, 75 W ( G.703 )
Protection Input CMI 3J16 Data 155.520 Mb/s, CMI/ECL, 75 W / -2V
Data 2.048 Mb/s 3J14 Data 2.048 Mb/s, HDB3, 75 W ( G.703 )

Available as an option ( wayside traffic )
Main Outputs:
IF Output 3J1 70 MHz, 0 dBm, 75 W
IF Test Output 3J3 70 MHz,10 dB attenuation, 75 W
Protection Output CMI 3J15 Data 155.520 Mb/s, CMI/ECL, 75 W / -2V
2 MHz Sync Input:
2 MHz clock 3P1, pin 20A & 20C 2.048 MHz sync clock, RS422
2 MHz Sync Output:
2 MHz clock ( strapable option ) 3J11 2.048 MHz sync clock,

±1V, capasitive coupled, 75 W unbalanced.
( from BUS1- clock in the 155 Mb/s data input )
720 kb/s O-bit Channel:
O-bit input ( strapable option ) 3J11 Data 720 kb/s, NRZ, CMOS-level
O-bit clock output ( strapable option ) 3J12 Clock 720 kHz, CMOS-level
O-bit byte output ( strapable option ) 3J13 Syncpulse, CMOS-level
This 720 kb/s channel is used for insertion of overhead bits when the C4-MUX is active. Not in use.
External LO Synchronization:
LO Master Output ( strapable option ) 3J12 70 MHz, -5dBm, 75 W

LO Slave Input (strapable option ) 3J13 70 MHz, -5dBm, 75 W
This synch-function is not used on 8MNF89A.
4 H2970
8MNF89A
1.2 Indicator:
MOD_UNIT_ALM LOS_ALM_MOD Red LED on the front of the unit

+LOF1_MOD
+2M_SYNC_ALM_MOD
+311_PLL_ALM_MOD
+2M_WAY_ALM_MOD
+TRELLIS_PLL_ALM
+IF_OUT_ALM_MOD
1.3 Power requirements:
Power Requirements : +5.0V / 1.0A

: -5.2V / 0.9A
: +15.0V / 0.18A
: -15V / 2mA
H2970 5
8MNF89A
The modulator unit is built on one circuit board and Functions for mapping a 139.264 Mbit/s plesiochronous bit
mounted in a box. stream into the STM-1-frame is built into the unit.
The unit contains all baseband and modem functions for the Reconfiguration between the two interfaces (140/155Mb/
transmit side. Functions are provided both for Regenerator s) can easily be performed.
Section Termination (RST) and for Multiplexer Section The same modulator unit is used both for protection
Termination(MST)according to ITU-T recommendations. channels and for main channels.
The different modes of the modulator unit are selected by
switches within the unit. Details of the switch settings are given in Chapter 4
(Configuration) in the User manual.
2 MHz ext SYNC
2 MHz SYNC OUT

2 Mb/s G.703
Wayside traffic PROM
TCM- IF
D/A
CMI C4 ENCODING OUT
CMI CABLE STM I
(ASIC) D/A
39 MHz TEST OUT
PROT INP CLK
POH INSERT 62MHz PLL
CMI
PLL CLK SIGNAL
SIGNAL
311 MHz 311 MHz 62 MHz

VCXO VCXO
SOH IN/OUT
CMI
ENCODER
CMI TO PROTECTION CHANNEL
6 H2970
8MNF89A
3J11
3J1
3J12
3J13
3J3
ANALOG MODULATOR
3P1
D/A CONVERTERS 3H1
TRELLIS CODER
& FIR - FILTER
PLL w/VCXO 62 MHz
STM - 1
PROCESSING
C4 - MUX
PLL w/VCXO 311 M

3P2
CMI CODEC
CABLE
EQUALIZER 3J14
3J15
3J13
Fig. 2 Unit Board Diagram
H2970 7
8MNF89A
3.1 Main Functions: · TCM-ENCODER AND FIR FILTER:

These functions are realised in a programmable ASIC in
A block diagram of the main functions of the modulator is
CMOS technology. The Trellis Code Modulation
shown in fig1. A brief description of these functions is given
(TCM)-encoder function is the transmit part of the
here:
modulation coding used to perform error correction.
· CABLE EQUALIZER: Trellis coded modulation is a combined coding and
The CMI input data signal is applied to the cable equalizer modulation scheme for improving the reliability of a
which automatically compensates for varying cable attenu- digital transmission system without increasing the
ation according to ITU-T Rec. G.703. transmitted power or the required bandwidth.
The TCM-encoder consists of a differentional encoder,
a convolutional encoder and the two-dimensional map-
· CMI CODEC: per. The differentional encoder is used to make the
The CMI CODEC is an Application Specific Integrated Circuit transmitted symbols invariant to phase rotations.
(ASIC) realized in ECL-technology. It has functions for CMI- The two-dimensional symbols (I & Q) is transmitted in a
data decoding, clock recovery, split and converting of the data- 64 points cross constellation.
signal prepared for CMOS technology. T h e The FIR-filter function performs half of the total system
CMI CODEC is also used to CMI-encode the Protection filtering. The other half of the system filtering is done in a
channel data signal going to the XMTR-switch-unit. Surface Acoustic Wave (SAW)-filter in the receiver group.
The FIR-filter function realized is a 28 taps digital square
root cosine rolloff-filter with a= 0.35. Filter for both I & Q-
· C4-MUX: channel is included in this ASIC. Configuration data for the
The C4-MUX is an ASIC performing the mapping of ASIC and the FIR-filter coefficients are
139.264Mbit/s into a STM-1 frame generated by this circuit. contained in an external PROM.
This function is only used if the 139.264Mbit/s interface is
selected. Traffic is carried straight through this circuit if the · D/A (DIGITAL TO ANALOG-
STM-1 interface is selected. The C4-mapping is done CONVERTER):
according to ITU-T Rec. G.707-709 and Rec. G. 782-784.
One 10-bit D/A-converter is used on each channel (I & Q). The
· STM-1 PROCESSOR: D/A-converters for the I & Q-channel convert the 10-bit input
data to an analog signal prepared for modulation. The D/A-
The STM-1 processor is an ASIC performing the termination
of incoming STM-1 signal (for STM-1-interface) and also
rebuilding the STM-1 frame according to the rules specified in
ITU-T Rec. G.707 and Rec. G.782-784. · MODULATOR (MOD):
All extraction of Section OverHead (SOH)-bytes from the
This is the analog part of the modulator unit. The spectrum
incoming STM-1-frame and insertion of new SOH-informa-
applied to the modulator is bandlimited by a lowpass filter to
tion is done in this circuit. The circuit is also splitting the signal
remove the repetitive part of the spectrum generated in the
before it is applied to the CMI ENCODER, and further to the
preceding digital FIR-filter. The I- and Q-signals are modulated
XMTR-switch unit.
on individual 70MHz carrier frequencies which are 90° phase
Other main functions performed in this circuit:
shifted. The two modulated signals are combined at the
a) STM-1-frame synchronization modulator output. In order to satisfy the mask requirement for
b) Descrambling and Scrambling the transmitted spectrum two band pass filters are inserted prior
c) Bit Interleaved Parity (BIP)-checking and generation to the IF output. An IF equalizer is used to equalize the delay
d) AU-4 pointer processing and amplitude response of the IF-filters. An IF-output alarm
is activated if the IF-level falls below about -6dBm.
8 H2970
8MNF89A
3.2 Other Functions: · 2MHz sync output (optional):

The modulator also includes circuits for 2 Mb/s wayside A 2MHz sync-signal derived from the incoming 155 Mb/s
input, 2 MHz external sync input, B1 and B2 parity error data is fed to a coax connector. To be used in connection with
outputs, POH-bus input, SOH-bus output/input, 2 MHz an external Sync Unit.
sync clock output, alarm outputs and different alarm- and
control signal inputs. · SOH Bus Output/Input:
Section OverHead may be extracted/inserted from/to the
· 2Mb/s Wayside: STM-1-frame. Bus receivers/drivers are included to trans-
Line receiver and HDB-3 decoding circuits for 2.048Mb/s port the SOH-bus to/from the service rack where different
wayside traffic are included in the modulator. The interface adapters can be connected for access to the SOH-bytes.
is 75ohm, unbalanced (G.703).
· POH BUS Input (Optional):
· B1 and B2 parity error pulses:
By use of adapters in the service rack, it is possible to insert
B1 and B2 parity error pulses from incoming 155 Mb/s data
Path Overhead in the STM-1 Frame when
are available out of the modulator.
C4-mapping is active (140 Mb/s input).
· 2MHz external sync input (optional):
· External 70 MHz LO Synchronizing
It is possible to use external 2MHz sync-signal for synchro- (Optional):
nization of the 155 Mb/s bit rate.
It is possible to syncronize the 70 MHz LO in two
modulator units in a master / slave configuration.
This function is not used in 8MNF89A.
H2970 9
8MNF89A

LOS_ALM_MOD Alarm indicating CMI-data connected to ACU

input is missing

frame (STM-1)

2MHz_EXT_SYNC


TRELLIS_PLL_ALM Alarm indicating connected to ACU


PJE_MOD Pointer Justification Event connected to ACU

(STM-1)


MS_AIS in STM-1

received MS_FERF

AU_PATH_AIS

loss of Pointer (STM-1)
155 MB_INT Indicating STM-1- data connected to ACU

into the modulator

+LOF1_MOD
+311M_PLL_ALM_MOD
MASTER_IND_MOD Indicating 70 MHz LO connected to ACU

master status in the modulator
10 H2970
8MNF89A
3.4 Alarm and Control Signal Inputs:
External alarm and control signal inputs to the Modulator are listed below:
Alarm / Signal Name: Alarm/ Signal Description: Comments:
H2970 11
8MNF89A
4. OVERVIEW of DIL-SWITCH and STRAP FUNCTIONS
4.1 DIL-switch Functions:
Function ( Switch ON ): Function ( Switch OFF ):
S501 (C4-MUX/STM1)
S1 Byte C2 = 1 Byte C2 =0
S2 Byte C2: switch-controlled Byte C2: 2M BUS-controlled
S3 Descrambler ; Radio Descrambler ; SDH
S4 Scrambler enabled Scrambler disabled
S5 Serial AU-alarms enabled Parallell AU-alarms
S502 ( STM1 )
S503 ( Config. switch )
S1 155.520 Mb/s interface 139.264 Mb/s interface

S2 RF ID 0 = 1 RF ID 0 = 0
S3 RF ID 1 = 1 RF ID 1 = 0
S4 Multiplexer Section Terminal Regenerator Section Terminal
S5 New frameword inserted Frameword retransmitted
S6 AU-Pointer Pros enabled AU-Pointer disabled
S7 RSOH Insert from 2Mb/s BUS RSOH Insert ctrld by 2Mb/s BUS
S8 New C1-byte inserted C1-byte retransmitted
4.2 Strap Functions:
Function Function
W101 Pos 1-2 : CMI-ECL on Pos 2-3 : CMI-capasitive on Prot Out Data
Prot Out Data (3J15) (3J15)
12 H2970
8MNF89A
Function Function
W401 Pos 1-2 : Select data input : Prot Inp (3J16) Pos 2-3 : Select data input : Reg Inp (3J2)
(Strap W401 is used for test and default setting
( pos 1-2 ), the inputs are normally selected by
external control signal from back panel. )
W402 Pos 1-2 : Enable protection channel : Pos 2-3 : Input from Reg Inp (3J2)
Protection data input (3J16)
( Strap W402 is used for test and default setting
( pos 2-3 ), the function is normally controlled by
external control signals from the RPS-unit. )
W403 Pos 1-2 : BUS1 Byte = POH Sync Out Pos 2-3 : BUS1 Byte = RSOH Sync Out
W404 Pos 1-2 : BUS1 Clk = POH Clock Out Pos 2-3 : BUS1 Clk = RSOH Clock Out
W405 Pos 1-2 : BUS1 D1+ =POH Data1 Inp Pos 2-3 : BUS1 D1+ = RSOH Data1 Out
W406 Pos 1-2 : BUS1 D1- =POH Data1 Inp Pos 2-3 : BUS1 D1- = RSOH Data1 Out
W407 PosOpen : BUS1 = POH-modus PosClosed (1-4/2-3) : BUS1 D2+/D2-

= RSOH Data2 Out
W601 Pos 1-4 : Normal ;( Q-Channel D/A-output to
Q-Channel BB-LP-filter ) Pos Open : Test

Q-channel BB-LP-filter
W702 Pos 1-4 : Normal, ( Modulator to Filter

1 BP 70MHz ) Pos Open : Test
W801 Pos 1-4 : Normal, ( Filter 1 BP 70MHz to

Equalizer ) Pos Open : Test
W901 Pos 1-4 : Normal; ( I-Channel D/A-output to

I-Channel BB-LP-filter ) Pos Open : Test

I-channel BB-LP-filter.
W911 Pos 1-2 : 2 MHz Sync Clk output on 3J11. Pos 2-3 : 720 kb/s O-Data input on 3J11.
W912 Pos 1-2: 70 MHz LO Master out on 3J12. Pos 2-3 : 720 kHz O-CLK output on 3J12.
(Not used)
W913 Pos 1-2 : 70 MHz LO Slave inp on 3J13. Pos 2-3 : Sync O-Byte output on 3J13.
( Not used )
H2970 13
8MNF89A
5. INTERFACE on CONNECTORS 3P1 and 3P2

5.1 Upper Connector, 3P1:
01a BUS1_DISABLE 17a ALM_SEL_C

01c GND 17c ALM_SEL_B
02a BUS1_D1- 18a ALM9_16_MOD
02c BUS1_D1+ 18c ALM1_8_MOD

03c BUS1_CLK+ 19c CMI_INP_SEL
04a BUS1_BYTE- 20a 2M_SYNC_MOD-
04c BUS1_BYTE+ 20c 2M_SYNC_MOD+
05a BUS1 D2- 21a GND

05c BUS1_D2+ 21c 2M_SYNC_MOD_DIS
06a NC 22a XMTR_SW_ALM_MOD
06c GND 22c NC
07a NC 23a EN_REP

07c NC 23c NC
08a NC 24a EWBER_SEC_IND
08c NC 24c EN_PROT_MOD
09a NC 25a SYNCL_ALM_DEM

09c NC 25c LBER_SEC_IND
10a NC 26a GND
10c NC 26c PJE_MOD
11a BUS3_DISABLE 27a GND

11c GND 27c B1_ERR_MOD
12c BUS3_D1+ 28c B2_ERR_MOD

13c BUS3_CLK+ 29c B3_ERR_DEM
14a BUS3_BYTE- 30a GND
14c BUS3_BYTE+ 30c SEC_ALM_DIS

15c BUS3_D2+ 31c SYNC_IND_EN
16a ALM_SEL_A 32a GND
16c GND 32c VIT_SEC_ERR
14 H2970
8MNF89A
5.2 Lower Connector, 3P2:
01a GND 17a +5V

01c GND 17c +5V
02a -15V 18a +5V
02c -15V 18c +5V
03a -15V 19a +5V

03c -15V 19c +5V
04a GND 20a +5V
04c GND 20c +5V
05a +15V 21a +5V

05c +15V 21c +5V
06a +15V 22a +5V
06c +15V 22c +5V
07a +15V 23a +5V

07c +15V 23c +5V
08a NC 24a GND
08c GND 24c GND
09a -5.2V 25a GND

09c -5.2V 25c GND
10a -5.2V 26a RMT_RESET_SU_MOD
10c -5.2V 26c READ
11a -5.2V 27a POH_RFAIL_DEM

11c -5.2V 27c MS_RFAIL_DEM
12a -5.2V 28a NC
12c -5.2V 28c NC
13a -5.2V 29a NC

13c -5.2V 29c NC
14a -5.2V 30a NC
14c -5.2V 30c NC
15a GND 31a ATPC1_HIGHER

15c GND 31c ATPC2_LOWER
16a NC 32a ENABLE
16c NC 32c DIS_WAY_MOD
H2970 15
DEMODULATOR, 128TCM
2DNF129B
H2996 Rev. A
2DNF129B
2 H2996
2DNF129B
TABLE OF CONTENTS
Page:
1. TECHNICAL DATA 4
1.1. IF and Data Connections: 4
1.2 Indicators: 4
1.3 Power Requirements: 5
2. CONFIGURATION 6
2.1 Default DIL-switch settings 6
2.2 Strap settings 7
4.1 Main Functions: 9

4.1.1 I & Q DEMODULATOR: 9
4.1.2 A/D (ANALOG TO DIGITAL CONVERTER): 9
4.1.3 ATDE (ADAPTIVE TIME DOMAIN EQUALIZER): 9
4.1.4 VITERBI (4D-128TCM-DECODER
utilizing the VITERBI-Algorithm): 9
4.1.5 STM-1 & alignment switch: 9
4.1.6 C4 demapper: 9
4.1.7 CMI CODEC: 10
4.1.8 BER monitor and control logic. 10
4.1.8.1 Bit error rate monitor 10
4.1.8.2 Viterbi-hop-error-pulse processing 10
4.1.8.3 B1/B2 block error processing 10
4.1.8.4 ATPC logic 10
4.2 Other Functions: 10

4.2.1 2Mb/s Wayside traffic: 10
4.2.2 Parity Error 10
4.2.3 SOH Bus-Outputs: 10
4.2.4 SOH BUS Input (Optional): 11
4.2.5 POH BUS Output (Optional): 11
4.2.6 RF_ID: 11
4.2.7 MS_RFAIL_DEM: 11
4.3 Alarm Outputs: 12
H2996 3
2DNF129B
1.TECHNICAL DATA
1.1 IF and Data Connections:
Main Inputs:
IF INPUT (J1) : 70 MHz, 0 dBm, 75 ohm

Protection input CMI (J13) : Data 155.520 Mb/s, CMI/ECL, 75 ohm/-2V.
Used for input from protection chan.
Main Output:
DATA OUTput CMI (J2) : Data 155.520Mb/s or 139.264 Mb/s,

CMI/1V, 75 ohm (G.703)
Test Output:
CMI TEST OUTput (J3) : Data 155.520Mb/s or 139.264 Mb/s, CMI/1V,

75 ohm. Available for test purposes.
2.048Mb/s Data Output:
DATA 2.048 Mb/s (J11) : Data 2.048 Mb/s, HDB3, G.703.

1.2 Indicators:
UNIT_ALM IF_INP_ALM Red LED

+ LOF1 + LOF2
+ CMI_OUT_ALM_DEM
+ SYNCL_VIT
AIS_OUT_IND AIS-indicator.
For SDH output its showing there is AIS Yellow LED
inserted on the traffic output port.
For PDH output its showing there is AIS
inserted or detected on the traffic output port.
140_Mb_INT Illuminates when unit is set up with Yellow LED

140 Mb (PDH) on traffic output port
HBER Indicator for excessive BER. Red LED

Calculations based on also connected to the ACU
Viterbi pseudo errors
LBER Indicator for BER > 5.10-7. Yellow LED

POWER_ON Indicates power on Green LED

4 H2996
2DNF129B
Power Requirement : 16 W : +5.0V / 1.9A

: -5.2V / 0.35A
: +15.0V / 0.3A
: -15V / 10mA
: GND
The 4D-128TCM contains all functions from IF-input to Synchronous Physical Interface -(SPI) output.
A 140Mbit/s (C4) synchronous demultiplexer is built into the unit, and if this option is used, then the output is a
H2996 5
2DNF129B
2. CONFIGURATION
2.1 Default DIL-switch settings
S401 Function Description

Norm.
S1 ON ETSH.1 Selects error-threshold for built-in
S2 OFF ETSH.0 algorithm switch.
S3 OFF BETA.1 Selects blind-threshold level
S4 OFF BETA.0 (MLE).
S5 OFF RESET_LE Linear equalizer coefficients reset.
S6 OFF RESET_DE Decision feedback coefficients reset.
S7 OFF RESET_DC DC-offset compensation reset.
S8 OFF RESET_GAIN AGC (I and Q) reset.

Norm.
S1 ON SYCTRL.5
S2 ON SYCTRL.4 System control for Viterbi decoder
S3 ON SYCTRL.3
S4 ON SYCTRL.2
S5 ON SYCTRL.1
S6 ON SYCTRL.0
S7 ON FEC_EN Enable hard/soft decision Viterbi (1=enable)
S8 OFF INP_SEL Selects test input to Viterbi (0=norm, 1=Test)

Norm.
S1 ON EW0 Setting of Early-warning
S2 OFF EW1 alarm treshold
S3 OFF LBER0 Setting of Low-BER
S4 ON LBER1 alarm treshold
S5 OFF HBER0 Setting of High-BER
S6 ON HBER1 alarm treshold
S7 OFF ERP0 Setting of error pulse
S8 ON ERP1 division

Norm.
S1 ON 155Mb INT ON:155Mb OFF:140Mb
S2 OFF RF_ID0 RF-id bit 0
S4 OFF EN_MS MS-/ RS - terminal (ON=MS, OFF=RS)
S5 OFF FRW_IN ON= transparent for incoming Frameword
S6 ON STAT_DEL0 Setting of static delay
S7 OFF STAT_DEL1 length alignment function
S8 OFF RF_ID_ALM Enable RF-id alarm (ON= enabled)
6 H2996
2DNF129B
2.2 Strap Settings
Strap settings and description are listed in the table below:
Norm Pos = Default position, nm = not mounted
Strap Test Pos. Normal Description

Position
W101 1 -2 nm Voltage on/off on Eye-driver
W102 2-3 1-2 Control voltage for 70 MHz VCO
W401 1-2 1-2 48 MHz Clk in to Viterbi
W403 nm nm Mode IC403
W404 nm nm Reset IC403
W405 nm nm Program IC403
W412 1-2 1-2 MODE.0 (mode control of ATDE)
W501 1-2 1-2 Treshold for ALIGN_PLL_ALM
W502 2-3 2-3 Treshold for pulse lenght limit in allign-PLL
W503 2-3 2-3 Tresh. for comp and shift of phase det. in allign-PLL
W601 1-2 1-2 Ctrl.Volt to 279/311 MHz VCXO (1-2=311, 2-3=279)
W602 1-2 1-2 Pwr to 279/311 MHz VCXO (1-2=311, 2-3=279)
W603 1-2 1-2 CMI Clk from 279/311 MHz VCXO (1-2=311, 2-3=279)
W604 1- 2 2-3 HBER criteria for AIS (1-2=ON, 2-3=OFF)
W605 1-2 1-2 Enable repeater (nm= enable, 1-2= enable/disable from back-panel)
W606 1-2 1-2 B1-Parity Errors or B1-Block Errors (1-2=Parity Errors, 2-3=Block Errors)
W607 1 -2 1-2 B2-Parity Errors or B2-Block Errors (1-2=Parity Errors, 2-3=Block Errors)
W701 1-2 1-2 BUS3/POH (1-2=BUS3-Clk, 2-3=POH-Clk on BUS3-Clk out from Dem
W702 1-2 1-2 BUS3/POH (1-2=BUS3-Sync, 2-3=POH-Sync on BUS3-Sync out from Dem
W703 1-2 1-2 2M-sync control function: 1-2=backplane enabling overrides SOH, nm=SOH
W704 2-3 2-3 BUS3/POH (2-3 Þ BUS3-data1 in, 1-2Þ POH-data out )
W706 nm nm Remote reset demod (nm = remote reset disable 1-2= enable, 2-3= reset demod)
H2996 7
2DNF129B
3. GENERAL DESCRIPTION
Fig. 1 shows how the demodulator unit is incorporated in the receiver part of the system.
From main RF &

antenna down
conv. Space
IF-filter 2DNF129B CMI
diversity
RF & & AGC Demodulator data out
From space comb.
down
antenna
conv.
)LJ5HFHLYHU%ORFN'LDJUDP
140Mbit/s Physical Interface (PI) according to G.703.

The same demodulator unit is used for both protection channels and main channels.
The demodulator unit has a number of switches and straps which are used to configure the unit.
Details of the switch settings are given in Section 2 (Configuration) and in the Handbook chapter 4.
Some of the parameter settings are:

· Regeneration Section Termination (RST)
· Multiplexer Section Termination (MST)
· Enable/Disable of 140Mb/s demultiplexing.
· Selection of high BER, - low BER and EWBER-limits
· RF-identification bits.
8 H2996
2DNF129B
4. FUNCTIONAL DESCRIPTION
4.1 Main Functions: SOH POH
in/out out
IF INP I&Q ATDE Viterbi STM-1 C4 CMI CMI

demod (asic) (asic) & alignment demapper codec (asic) G.703
switch (asic)
(asic)
A/D conv
Data from
protection
channel
A brief description of these functions is given here: )LJ'(02'%ORFN'LDJUDP
4.1.1 I & Q DEMODULATOR:

This is the analog part of the demodulator unit. The IF- decoder is implemented in an ASIC in CMOS technology.
signal from the receiver is split into two branches at the The TCM-decoder function is the receiver part of the
input. In one of the branches the IF signal is mixed with modulation coding used to perform error correction. The
LO-signal with 0° phase shift, and in the other branch, Viterbi algorithm is used in the decoder to improve the
mixed with the LO-signal 90° phase shifted. This implies system performance.
that the in-phase component of the demodulated signal is The realized 8- state Viterbi-decoder, with Viterbi-depth=15,
retained in the first branch and the quadrature component gives a coding gain of approx. 4 dB at BER=10-6 compared
in the other. The output of the mixers contains the sum- with uncoded 128 QAM modulation.
and difference-products of the IF- and LO-signal. The
sum and higher order mixing products are suppressed in
an LP-filter. The resulting signal is amplified to the 4.1.5 STM-1 & alignment switch:
proper level for the following A/D-converters. The STM-1-processor is used to perform the system
synchronization, descrambling, Section OverHead (SOH)-
termination and alignment switching.
4.1.2 A/D (ANALOG TO DIGITAL A burst-decoder is used to rearrange the STM-1 frame to
CONVERTER:) its original state before the signal is applied to the other
The two A/D-converters for the ATDE are 10 bit con- functions in the unit.
verters and works at a sampling rate of 24 Msamples/s. The circuit rebuilds the STM-1 frame according to the rules
specified in CCITT Rec.G.707-709 and Rec.G.782-784.
4.1.3 ATDE (ADAPTIVE TIME DOMAIN All extraction of Section OverHead (SOH)-bytes from the
EQUALIZER): incoming STM-1-frame and insertion of new SOH-
information is done in this circuit.
A 13-taps Adaptive Time Domain Equalizer (ATDE) is
Alignment and switch function for the N+1 radio
provided in order to establish effective countermeasures
protection switching is built into this circuit. The switch
against the distortion effects caused by multipath
function is controlled from the Radio Protection Switch
transmission (selective fading). The complex equalizer is
(RPS)-unit.
controlled by the Least Mean Square error (LMS) and the
Maximum Level Error (MLE) algorithms. The optimum
algorithm will be automatically selected.The digital ATDE
4.1.6 C4 demapper:
is implemented in one single ASIC in CMOS technology.
The circuit has built-in functions for Automatic Gain The C4-DEMAPPER (demux) is used to map out the
Control (AGC), DC-offset- and quadrature-phase 139.264 kbit/s of the STM-1-frame. This function is only
adjustment. It also generates control signals for carrier- used if the 140 Mb interface is selected. Traffic is carried
recovery and timing recovery. straight through this circuit if the STM-1-interface is selected.
The C4-demapping is done according to CCITT Rec.
4.1.4 VITERBI (4D-128TCM-DECODER G.707-709 and Rec. G.782-784.
utilizing the VITERBI-Algorithm): This circuit also extracts the Path Overhead (POH) bytes
The 4-dimensional Trellis Code Modulation (TCM) from the incoming STM-1 frame.
H2996 9
2DNF129B
4.1.7 CMI CODEC:

The CMI CODEC (ECL-asic), performs the combining This voltage is a function of control signals from thesuper-
and CMI-encoding of the data coming from the C4- visory system and two bits in the incomming SOH to the
DEMUX. The CMI-data signal is then applied to a CMI- demod.The two bits in SOH comes from the reciever on
driver before it is made available on the front of the opposite side and are inserted in the corresponding modu-
demodulator unit. A CMI test output for in-service lator.
monitoring is available on the front of the demodulator Within IC403 we have placed the control logic and presents
unit. a 6bit word to a D/A converter, giving the Acontrol voltage
The same CMI CODEC- circuit is used to CMI-decode to the transmitter.
the data signal coming from the protection channel. A regulation cycle, max to min or min to max, will take
place in min 300ms. The regulation speed varies over the
total range in a manner to compensate for the logarithmic
4.1.8 BER monitor and control logic. behaviour of the power control in the transmitter.
The following functions are implemented in a FPGA
(IC403). The configuration program is located in serial
prom IC404. 4.2 Other Functions:
4.1.8.1 Bit error rate monitor: The demodulator also includes circuits for 2 Mb/s
The error pulses from the trellis decoder CNF22A are used wayside output, B1, B2 and B3 parity error output,
to carryout the error measurements leading to the gener- SOH-bus outputs, SOH-bus input, POH- bus output,
ation of three programmable performance threshold indi- RF_ID identification and alarm outputs.
cators:
EWBER(Early warning) :Integration time 128ms
LBER :Integration time 8ms 4.2.1 2Mb/s Wayside traffic:
HBER :Integration time 1ms HDB-3 coding and line driver circuits for 2.048Mb/s
These indicators will be activated immediately when an wayside traffic is included in the demodulator. The
on-threshold violation is detected and stays active until an interface is 75ohm, unbalanced (G703).
integration period without an off-threshold violation is
elapsed. An active out of frame alarm from the STM-1
processor will also activate the indicators. 4.2.2 Parity Error
B1, B2 and B3 parity error pulses are available out
from the demodulator .
4.1.8.2 Viterbi-hop-error-pulse processing: B1_ERR_DEM and B2_ERR_DEM can be taken from
Error pulses from Viterbi decoder CNF36A are processed either B1_ ERR_STM1 / B2_ ERR_STM1
in order to get a viterbi-hop-error-pulse of approx. 1us or
duration and a frequency less than 32kHz at BER BLOCK_ERR_B1 / BLOCK_ER_B2 by means of the
< 1 x 10-2. Straps W606 / W607.
These outputs are routed to the Alarm Collection Unit
(ACU).See Configuration for details.
4.1.8.3 B1/B2 block error processing:
B1 ,B2 and STM-1 frame pulses from the STM-1 proces- B1- and B2 parity error outputs are available from the
sor CNF19D are processed in order to generate B1 and B2 ACU at the top of the slimracks for each STM-1
block error-pulses. One pulse is generated for each frame channel.
containing B1 or B2 error pulses.
4.2.3 SOH Bus-Outputs:

4.1.8.4 ATPC logic: Section OverHead is extracted from the STM-1-frame
The purpose of this function is to control the transmitted and bus drivers are included to transport the SOH-bus
power. to the service rack where different optional adapters can
From the demod , we present an output power control connect to the bus for access to the SOH-bytes.
voltage to the transmitter in opposit direction.
10 H2996
2DNF129B
4.2.4 SOH BUS Input (Optional):

By use of adapters, it is possible to insert Section An RF_ID_Alm is given if there is any difference.
Overhead into the STM-1 Frame out from the RF_IO_ALM can be disabled with S501.
demodulator. See "Configuration" for details.
4.2.5 POH BUS Output (Optional): 4.2.7 MS_RFAIL_DEM:

By use of adapters, it is possible to extract Path The Demodulator alarm MS_RFAIL_DEM report the
Overhead from the incoming STM-1 Frame when C4- quality of the data comming out of the STM-1 ASIC.
demapping is active (140Mb output). (IC 503):
If regular channel is selected by RPS:

MS_RFAIL_DEM = LOF1_DEM or MS_AIS_DEM
4.2.6 RF_ID:
Comparison of the two RF_ID bits in the incoming else
STM-1 frame with the two bits selected on S501, is if protection channel is selected by RPS:
performed in the demodulator unit.
H2996 11
2DNF129B
4.3 Alarm Outputs:

IF_INP_ALM_DEM Alarm indicating IF connected to the ACU

input is missing
RF_ID_ALM Alarm indicating that wrong connected to the ACU,

RF-id is received can be disabled on S501
HBER_HOP_ALM Alarm for BER > 5*10-4 Red LED

based on Viterbi pseudo errors also connected to the ACU
HBER_SEC_ALM OR-ed HBER_HOP_ALM connected to the ACU

for last and previous hops
LBER_HOP_IND Indicator for BER > 5*10-7, Yellow LED

LBER_SEC_IND OR-ed LBER_HOP_IND connected to the ACU and RPS

EWBER_HOP_IND Early warning BER indicator connected to the ACU

based on Viterbi pseudo errors
EWBER_SEC_IND OR-ed EWBER_HOP_IND connected to the RPS

LOF1_DEM Loss of frame (after 3 ms) connected to the ACU

detected on received traffic.
LOP_DEM Loss of pointer detected on connected to the ACU

received traffic.
SYNCL_SEC_ALM OR-ed OOF1_DEM+ connected to the ACU

SYNCL_SEC_ALM+RF_ID_ALM
Alarm indicating sync. loss has
occured within the radio
protection switching section.
ALIGN_PLL_ALM Alarm indicating PLL for connected to the ACU

errorless switch is out of lock
LOF2_DEM Data from protection channel connected to the ACU

is missing (to alignment)
12 H2996
2DNF129B
POH_FERF_DEM POH FERF detected on received connected to the ACU

traffic
MS_FERF_DEM MS_FERF detected on connected to the ACU

received traffic
MS_AIS_DEM MS_AIS detected on connected to the ACU

received traffic
AU_PATH_AIS_DEM AU path AIS detected on connected to the ACU

received traffic
AIS_OUT_140 AIS detected on 140 Mb/s data outp. connected to the ACU
CMI_OUT_ALM_DEM Alarm indicating 311/280 PLL connected to the ACU

(VCXO) is out of lock,
or CMI-data output is missing
EXT_SYNC_IND_DEM Signal indicating received connected to the ACU

STM-1 is locked to a 2MHz
external clock
2M_WAY_ALM_DEM Alarm indicating 2 Mb/s output connected to the ACU

is missing or PLL out of lock
AIS_OUT_WAY Signal indicating 2 Mb/s output connected to the ACU

is carrying AIS
MS_AIS_X Signal indicating MS_AIS connected to the ACU

in STM-1 data out from demod
RELAY_ALM_DEM LOF2 +CMI_OUT_ALM connected to the RPS
SYNCL_ALM_DEM HBER_SEL_ALM connected to the RPS

+ SYNCL_SEC_ALM
+ SYNCL_VITERBI
ALIGN_IND_DEM Signal indicating that protection connected to the RPS

traffic is aligned to main traffic
MS_RFAIL_DEM Signal reporting the quality of data connected to the modulator

comming out of the demod.
Note: The RPS-alarm outputs are high impedance outputs if loss of operating voltages.
H2996 13
DEMODULATOR, 64TCM
2DNF133A
H2969 Rev. A
2DNF133A
2 H2969
2DNF133A
Table of Contents
1. TECHNICAL DATA 4
1.1 IF and Data Connections 4

1.2 Indicators 4
3.1.1 I & Q DEMODULATOR 6

3.1.2 A/D (ANALOG TO DIGITAL CONVERTER) 6
3.1.3 ATDE (ADAPTIVE TIME DOMAIN EQUALIZER) 6
3.1.4 2D-64TCM-DECODER (Utilizing the VITERBI-Algorithm) 6
3.1.5 STM-1-PROCESSOR 6
3.1.6 C4-DEMAPPER 6
3.1.7 CMI CODEC 6
3.2 BERMONITOR AND CONTROL LOGIC 7
3.2.1 General 7
3.2.2 Bit error rate monitor 7
3.2.3 Viterbi-hop-error-pulse processing 7
3.2.4 B1/B2 block error processing 7
3.2.5 Sweep_control 7
3.2.6 ATPC logic 7
3.3 Alarm Outputs 8
3.4 Other Functions
3.4.1 2Mb/s Wayside 11

3.4.3 SOH Bus-Outputs 11
3.4.4 SOH BUS Input (Optional) 11
3.4.5 POH BUS Output (Optional) 11
3.4.6 RF_ID 11
3.4.7 MS_RFAIL_DEM 11
3.5 Overview of DIL-switch and Strap Functions 12
3.5.1 DIL-switch Functions 12

3.5.2 Strap Functions 13
H2969
3
2DNF133A
1. TECHNICAL DATA
1.1 IF and Data Connections:
Main Inputs:
IF INPut (J1) : 70 MHz, 0 dBm, 75 ohm
PROTection INPut CMI (J13) : Data 155.520 Mb/s, CMI/ECL, 75 ohm/-2V.
Main Output:
CMI/1V, 75 ohm (G.703)
Test Output:
CMI TEST OUTput (J3) : Data 155.520Mb/s or 139.264 Mb/s, CMI,
2.048Mb/s Data Outputs:

1.2 Indicators:
DEMOD_UNIT_ALM IF_INP_ALM Red LED on front of the

+LOF1+LOF2 demodulator unit
+CMI_OUT_ALM_DEM
AIS_OUT_IND AIS-indicator showing there is AIS Yellow LED on front of the

inserted on the traffic output port. demodulator unit
See also section 1,
«Technical Specifications»
HBER_HOP_ALM Indicator for excessive BER. Red LED on front of the demod. unit and
LBER_HOP_IND Indicator for BER>10-6. Yellow LED on front of the demod.

Calculations based on unit and also connected to the ACU
Power Requirements: : +5.0V / 2A

: -5.2V / 0.4A
: +15.0V / 0.35A
: -15V / 10mA
: GND
4 H2969
2DNF133A
RF &
FROM MAIN
DOWN- DATA OUT
ANTENNA DEMODULATOR
CONV. STM-1 OR
ATDE,
SPACE IF- 140Mb/s
AGC TRELLIS-
DIVERSITY FILTER
DECODER AND
COMBINER
BASEB. SIGNAL
RF & PROCESSING
FROM SPACE
DOWN-
ANTENNA
CONV.
Fig. 1 Receiver Block Diagram
The 2D-64TCM demodulator unit is built on one circuit board and mounted in a box as shown in fig.3, page 10.
The Unit contains all functions from IF-input to Synchronous Physical Interface -(SPI) output.
I
IF IN I&Q C4 CMI CMI
ATDE VITERBI STM I
DEMODU- DEMUX CODEC
(ASIC) (ASIC) (ASIC) G.703
LATOR (ASIC) (ASIC)
SOH SOH POH

OUT IN OUT
Fig.2 Main Functions of the 2D-64 TCM Demodulator
The demodulator unit has a number of switches and straps which is used to configure the unit.
Details of the switch settings are given in Chapter 4 (Configuration) in the User manual.
- Regeneration Section Termination (RST)
- Multiplexer Section Termination (MST)
- Enable/Disable of 140Mb/s demultiplexing.
- Selection of high BER, - low BER and EWBER- limits
- RF-identification bits.
H2969
5
2DNF133A
3.1 Main Functions:
A block diagram of the main functions of the demodulator Viterbi algorithm is used in the decoder to improve the
unit is shown in fig. 2. system performance. The realized 8- state Viterbi-decoder,
A brief description of these functions is given here: with Viterbi-depth=15, gives a coding gain of approx. 6.6
dB at BER=10-10 compared with uncoded 64 QAM
modulation.
3.1.1 I & Q Demodulator:
This is the analog part of the demodulator unit. The IF-
signal from the receiver is split into two branches at the 3.1.5 STM-1-Processor:
input. In one of the branches the IF signal is mixed with The STM-1-processor is the same ASIC as used on the
LO-signal with 0° phase shift, and in the other branch, transmit side. It is used to perform the system
mixed with the LO-signal 90° phase shifted. This implies synchronization, descrambling and Section OverHead
that the in-phase component of the demodulated signal is (SOH)-termination.
retained in the first branch and the quadrature component
in the other. The output of the mixers contains the sum- The burst-decoder is used to rearrange the STM-1 frame
and difference-products of the IF- and LO-signal. The sum to its original state before the signal is applied to the other
and higher order mixing products are suppressed in an LP- functions in the unit.
filter. The resulting signal is amplified to the proper level The circuit is also rebuilding the STM-1 frame according
for the following A/D-converters. to the rules specified in CCITT Rec.G.707-709 and
Rec.G.782-784.
All extraction of Section OverHead (SOH)-bytes from
3.1.2 A/D (Analog to Digital Converter): the incoming STM-1-frame and insertion of new SOH-
One 10-bit A/D-converter is used on each channel (I&Q). information is done in this circuit.
The A/D-converters for the I- and Q-channel convert the
analog input data to a 10-bit digital signal at a sampling The alignment and switch function for the N+1 radio
rate of 31M samples/s. protection switching is also built into this circuit. The
switch function is controlled from the Radio Protection
Switch (RPS)-unit.
3.1.3 ATDE (Adaptive Time Domain Equalizer):
A 13-taps Adaptive Time Domain Equalizer (ATDE) is
provided in order to establish effective countermeasures 3.1.6 C4-DEMAPPER:
against the distortion effects caused by multipath The C4-DEMAPPER is the same ASIC as used for C4-
transmission (selective fading). The complex equalizer is mapping on the transmit side. Here it is used to map out
controlled by the Least Mean Square error (LMS) and the the 139.264kbit/s of the STM-1-frame. This function is
Maximum Level Error (MLE) algorithms. The optimum only used if the 139.264kbit/s interface is selected. Traffic
algorithm will be automatically selected.The digital ATDE is carried straight through this circuit if the STM-1-
is implemented in one single ASIC in CMOS technology. interface is selected. The C4-demapping is done according
The circuit also has built-in functions for Automatic Gain to CCITT Rec. G.707-709 and Rec. G.782-784.
Control (AGC), DC-offset- and quadrature-phase This circuit also extracts the Path Overhead (POH) bytes
adjustment. It also generates control signals for carrier- from the incoming STM-1 frame.
recovery and timing recovery.
3.1.4 2D-64TCM-Decoder (Utilizing the 3.1.7 CMI CODEC:

VITERBI-Algorithm): The CMI CODEC is the same ASIC as used on the
The 2-dimensional Trellis Code Modulation (TCM) transmit side. It performs the combining and CMI-
decoder is implemented in an ASIC in CMOS technology. encoding of the data coming from the C4-DEMUX. The
The TCM-decoder function is the receiver part of the CMI-data signal is then applied to a CMI-driver before it
modulation coding used to perform error correction. The is made available on the front of the demodulator unit. A
6 H2969
2DNF133A
CMI test output for in-service monitoring is available on elapsed. An active out of frame alarm from the STM-1
the front of the demodulator unit. The same CMI CODEC- processor will also activate the indicators.
circuit is used to CMI-decode the data signal coming from
the protection channel.
3.2.3 Viterbi-hop-error-pulse processing:
Error pulses from Viterbi decoder CNF36A are proc-
3.2 BERMONITOR AND CONTROL LOGIC: essed in order to get a viterbi-hop-error-pulse of approx.
1us duration and a frequency less than 32kHz at BER
3.2.1 General < 1 x 10-2
(IC403) of type XILINX : XC3164APC84-3. The configu-
ration program is located in a serial prom (IC404) of type 3.2.4 B1/B2 block error processing:
XILINX 1765DPC. B1 ,B2 and STM-1 frame pulses from the STM-1
processor CNF19D are processed in order to generate
The design is captured with use of Mentor Graphics Design B1 and B2 block error-pulses. One pulse is generated for
Architect and Xilinx design kit for Mentor: XACTstep each frame containing B1 or B2.
v 5.2.0
Most of the functions are synchronous operating on
31.104MHz.
3.2.5 Sweep_control
The purpose of this function is to obtain an effective
3.2.2 Bit error rate monitor: synchronisation in the demodulator.
The error pulses from the trellis decoder CNF36A are used
to carry out the error measurements leading to the genera-
tion of three programmable performance threshold indica- 3.2.6 ATPC logic:
tors: This functions contains parts of the ATPC logic. The
EWBER(Early warning) :Integration time 128ms purpose of this function is to control the transmitted
LBER :Integration time 8ms power. A regulation cycle max/min or min/max will
HBER :Integration time 1ms take place in min 200ms. The regulation speed varies
These indicators will be activated immediately when an on- over the total range in a manner to compensate for the
threshold violation is detected and stays active until an logarithmic behaviour of the power control in the
integration period without an off-threshold violation is transmitter.
H2969
7
2DNF133A
3.3 Alarm Outputs:

input is missing
RF_ID_ALM Alarm indicating that wrong connected to the ACU

RF-id is received
HBER_HOP_ALM Indicator for BER>10-3, Red LED on front of the demod-unit

based on Viterbi pseudo errors and also connected to the ACU
HBER_SEC_ALM Alarm to ACU (OR-ed HBER_ connected to the ACU

(HOP_ALM for last and
previous hops)
LBER_HOP_IND Indicator for BER>10-6, Yellow LED on front of the demod-

based on Viterbi pseudo errors unit and also connected to the ACU
LBER_SEC_IND Indicator to ACU and RPS used connected to the ACU and RPS
for error-less switch control.
(OR-ed LBER_HOP_IND
for last and previous hops)
EWBER_HOP_IND Early warning based on Viterbi connected to the ACU and RPS
pseudo errors (BER >10-10)
EWBER_SEC_IND Early warning based on Viterbi connected to the RPS

pseudo errors (BER >10-10)
(OR-ed EWBER_HOP_IND
155Mb_INT Indicates STM-1 data out from connected to the ACU

the demod.


received traffic.
SYNCL_SEC_ALM Alarm indicating sync. loss has connected to the ACU

(OR-ed OOF1_DEM+
8 H2969
2DNF133A



traffic

received traffic

received traffic

received traffic
AIS_OUT_140 AIS detected on 140 Mb/s connected to the ACU

data outp.
CMI_OUT_ALM_DEM Alarm indicating PLL connected to the ACU

(311/280 MHz VCXO) is out
of lock, or CMI-data output
is missing

STM-1 is locked to a 2 MHz
external clock


is carrying AIS


+SYNCL_SEC_ALM

MS_RFAIL_DEM Signal reporting the quality of data conected to th modulator

cata comming out of th STM-1 ASIC
H2969
9
2DNF133A
4J13 4J12 4J11

SP602
SP501
4J2
SP502
SP605
SP613
SP606
CMI CODEC
SP601
4J3
P1
SP703
C4
4H1
SP704
CAT.
SP401
DEMAPPING SP402
SP701
4H2
SP702
SP403
STM-1
CAT.
SP404
PROCESSING
VITERBI
ATDE
A/D
P2
FROM 4J1
I&Q
DEMODULATOR
SP607
4J14
J1
SP609
4J15
4J16
SP611
Fig.3 Unit Board Diagram
10 H2969
2DNF133A
3.4 Other Functions: 3.4.4 SOH BUS Input (Optional):
By use of adapters, it is possible to insert Section
The demodulator also includes circuits for 2 Mb/s wayside Overhead into the STM-1 Frame out from the
output, B1, B2 and B3 parity error output, SOH-bus demodulator.
outputs, SOH-bus input, POH- bus output, RF_ID
identification and alarm outputs.
3.4.5 POH BUS Output (Optional):
By use of adapters, it is possible to extract Path Overhead
3.4.1 2Mb/s Wayside: from the incoming STM-1 Frame when C4-demapping is
HDB-3 coding and line driver circuits for 2.048Mb/s active (140Mb output).
wayside traffic is included in the demodulator. The
interface is 75ohm, unbalanced.
3.4.6 RF_ID:
Comparison of the two RF_ID bits in the incoming STM-1
3.4.2 Parity Error frame with the two bits selected on S501, is performed in
B1, B2 and B3 parity error pulses are available out from the demodulator unit.
the demodulator . B1_ERR_DEM AND B2_ERR_DEM An RF_ID_Alm is given if there is any difference.
can now be taken from either B1_ ERR_STM1 / B2_
ERR_STM1 or BLOCK_ERR_B1 / BLOCK_ER_B2 by
means of the Straps W606 / W607. These outputs are 3.4.7 MS_RFAIL_DEM:
routed to the Alarm Collection Unit (ACU). The Demodulator alarm MS_RFAIL_DEM report the
quality of the data comming out of the STM-1 ASIC.
B1- and B2 parity error outputs are available from the (IC 503):
ACU at the top of the slimracks for each STM-1 channel.
IF REG CH is selected by SEL_PROT:

3.4.3 SOH Bus-Outputs:
Section OverHead is extracted from the STM-1-frame and else
bus drivers are included to transport the SOH-bus to the
service rack where different optional adapters can connect IF PROT CH is selected by SEL_PROT:
to the bus for access to the SOH-bytes.
H2969
11
2DNF133A
3.5 Switch and Strap Overview
3.5.1 DIL-switch settings
DIL-switch settings and description are listed in the table below:

Norm.

Norm.
S1 - NOT IN USE
S2 - NOT IN USE
S3 - NOT IN USE
S4 - NOT IN USE
S5 ON SELMOD Select 32TCM/64TCM (0=32TCM, 1=64TCM)
S6 OFF OFC_EN Enable signal for OFC output (1=enable).

Norm.
S8 ON ERP1 division

Norm.
S4 OFF EN_MS MS-/ RS - terminal (1=MS, 0=RS)
S5 OFF FRW_IN Setting of Frameword
S7 OFF STAT_DEL1 length, alignment function
S8 OFF RF_ID_ALM Enable RF-id alarm
12 H2969
2DNF133A
3.5.2 Strap Settings
Norm Pos = normal position, nm = not mounted
Strap Norm Description

Pos
W101 nm Testpoint for 70 MHz VCO

W102 1-2 Control voltage for 70 MHz VCO
W103 nm Voltage on/off on Eye-driver
W401 1-2 62 MHz Clk in to Viterbi

W403 nm Mode XILINX
W404 nm Reset XILINX
W405 nm Program XILINX
W501 1-2 Treshold for ALIGN_PLL_ALM

W502 2-3 Treshold for pulse lenght limit in allign-PLL
W503 2-3 Tresh. for comp and shift of phase det. in allign-PLL
W601 1-2 Ctrl.Volt to 279/311 MHz VCXO (1-2=311, 2-3=279)

W602 1-2 Pwr to 279/311 MHz VCXO (1-2=311, 2-3=279)
W603 1-2 CMI Clk from 279/311 MHz VCXO (1-2=311, 2-3=279)
W604 1-2 HBER criteria for AIS (1-2=ON, 2-3=OFF)
W605 1-2 Enable repeater (1-2= enable, nm=disable)
W606 1-2 B1-Parity Errors or B1-Block Errors (1-2=Parity Errors, 2-3=Block Errors)
W607 1-2 B2-Parity Errors or B2-Block Errors (1-2=Parity Errors, 2-3=Block Errors)
W701 1-2 BUS3/POH (1-2=BUS3-Clk, 2-3=POH-Clk on BUS3-Clk out from Dem

W702 1-2 BUS3/POH (1-2=BUS3-Sync, 2-3=POH-Sync on BUS3-Sync out from Dem
W703 1-2 2M-sync Dem disable (EXT_SY_IND disable (nm=enable, 1-2=disable)
W704 2-3 BUS3/POH (1-2 Þ BUS3-data1 in, 2-3Þ POH-data out to/from Demod)
W705 2-3 BUS3/POH (1-2 Þ BUS3-data1 in, 2-3Þ POH-data out to/from Demod)
W706 nm Remote reset of demodulator (1-2 = remote reset enable, 2-3= reset demod)
W707 1-2 LOF1_DEM included in alarm RES_ATDE_VIT (1-2 = incl., nm = not incl.)
W708 nm Testpoint fot LOF1_DEM
H2969
13
DEMODULATOR, XPIC, 128TCM
2DNF135A with EDNF100A
H2971 Rev. A
2DNF135A
2 H2971
2DNF135A
TABLE OF CONTENTS
Page:
1. TECHNICAL DATA 1
1.1.1 IF and Data Connections: 1
1.1.2 Indicators: 1
1.1.3 Power Requirements: 2
2. CONFIGURATION 6
2.1 2DNF135A 6
2.1.1 Default DIL-switch settings 2DNF135A 6
2.1.2 Strap settings 2DNF135A 7
2.2 EDNF100A 8
2.2.1 Default DIL-switch settings EDNF100A 8
2.2.2 Strap settings EDNF100A 8

4.1.1 I & Q DEMODULATOR: 10
4.1.2 A/D (ANALOG TO DIGITAL CONVERTER): 10
4.1.3 ATDE (ADAPTIVE TIME DOMAIN EQUALIZER): 10
4.1.4 XPIC (Cross Polar Interference Canceller): 10
utilizing the VITERBI-Algorithm): 11
4.1.6 STM-1 & alignment switch: 11
4.1.7 C4 demapper: 11
4.1.8 CMI CODEC: 11
4.1.9 BER monitor and control logic. 11
4.1.10 XPIC timing and control logic. 12
4.2 Other Functions: 12

4.2.1 2Mb/s Wayside traffic: 12
4.2.3 SOH Bus-Outputs: 12
4.2.4 SOH BUS Input (Optional): 12
4.2.5 POH BUS Output (Optional): 12
4.2.6 RF_ID: 12
4.2.7 MS_RFAIL_DEM: 12
4.3 Alarm Outputs: 13
H2971
3
2DNF135A
1.TECHNICAL DATA
1.1.1 IF and Data Connections:
Main Inputs:

Protection input CMI (J13) : Data 155.520 Mb/s, CMI/ECL, 75 ohm/-2V.
IF from CO-polar channel
Main Output:

CMI/1V, 75 ohm (G.703)
Test Output:
CMI TEST OUTput (J3) : Data 155.520Mb/s or 139.264 Mb/s, CMI,

2.048Mb/s Data Output:

1.1.2. Indicators:
UNIT_ALM IF_INP_ALM Red LED

+ LOF1 + LOF2
+ CMI_OUT_ALM_DEM
+ SYNCL_VIT
+ XPIC_ALM
AIS_OUT_IND AIS-indicator.
For SDH output its showing there is AIS Yellow LED
inserted on the traffic output port.
For PDH output its showing there is AIS
inserted or detected on the traffic output port.
140_Mb_INT Illuminates when unit is set up with Yellow LED

140 Mb (PDH) on traffic output port
HBER Indicator for excessive BER. Red LED

4 H2971
2DNF135A
LBER Indicator for BER > 5.10-7. Yellow LED

XPIC_ALM IF_INP_ALM (to xpic demod Red LED

EDNF100A)
and XPIC_ON
IF comes from co-polar channel.
POWER_ON Indicates power on Green LED
XPIC_ON Indicates xpic function turned on. Green LED
1.1.3 Power Requirements:
Power Requirement : 23.5 W : +5.0V / 2.4A

: -5.2V / 0.4A
: +15.0V / 0.6A
: -15V / 10mA
: GND
H2971
5
2DNF135A
2. CONFIGURATION
2.1 2DNF135A:
2.1.1 Default DIL-switch settings 2DNF135A

Norm.

Norm.
S1 ON SYCTRL.5
S2 ON SYCTRL.4 System control for Viterbi decoder
S3 ON SYCTRL.3
S4 ON SYCTRL.2
S5 ON SYCTRL.1
S6 ON SYCTRL.0

Norm.
S8 ON ERP1 division

Norm.
S4 OFF EN_MS MS-/ RS - terminal (ON=MS, OFF=RS)
S5 OFF FRW_IN ON= transparent for incoming Frameword
S7 OFF STAT_DEL1 length alignment function
S8 OFF RF_ID_ALM Enable RF-id alarm (ON= enabled)
6 H2971
2DNF135A
2.1.2 Strap Settings 2DNF135A
Norm Pos = Default position, nm = not mounted
Strap Test Pos. Norm Description

Pos
W101 1 -2 nm Voltage on/off on Eye-driver

W102 2-3 1-2 Control voltage for 70 MHz VCO
W401 1-2 1-2 48 MHz Clk in to Viterbi

W501 1-2 1-2 Treshold for ALIGN_PLL_ALM

W502 2-3 2-3 Treshold for pulse lenght limit in allign-PLL
W503 2-3 2-3 Tresh. for comp and shift of phase det. in allign-PLL
W601 1-2 1-2 Ctrl.Volt to 279/311 MHz VCXO (1-2=311, 2-3=279)

W602 1-2 1-2 Pwr to 279/311 MHz VCXO (1-2=311, 2-3=279)
W603 1-2 1-2 CMI Clk from 279/311 MHz VCXO (1-2=311, 2-3=279)
W604 1- 2 2-3 HBER criteria for AIS (1-2=ON, 2-3=OFF)
W605 1-2 1-2 Enable repeater (nm= enable, 1-2= enable/disable from back-panel)
W606 1-2 1-2 B1-Parity Errors or B1-Block Errors (1-2=Parity Errors, 2-3=Block Errors)
W607 1 -2 1-2 B2-Parity Errors or B2-Block Errors (1-2=Parity Errors, 2-3=Block Errors)
W701 1-2 1-2 BUS3/POH (1-2=BUS3-Clk, 2-3=POH-Clk on BUS3-Clk out from Dem
W702 1-2 1-2 BUS3/POH (1-2=BUS3-Sync, 2-3=POH-Sync on BUS3-Sync out from Dem
W703 1-2 1-2 2M-sync control function: 1-2=backplane enabling overrides SOH, nm=SOH
W706 nm nm Remote reset demod (nm = remote reset disable 1-2= enable, 2-3= reset demod)
H2971
7
2DNF135A
2.2 EDNF100A
2.2.1 Default DIL-switch settings EDNF100A
S1 OFF MLE MLE algorithm Enable ON = enabled

S2 OFF MLE_L.1 MLE level
S3 OFF MLE_L.0 MLE level
S4 ON FRACT ON = Fractional OFF = Baudspaced
S5 OFF SPARE 4
S6 ON SDEL.2
S7 ON SDEL.1 Static delay in front of XPIC
S8 OFF SDEL.0
S1 OFF SPARE 1
S2 OFF SPARE 2
S3 OFF SPARE 3
S4 ON CONV_SIGN Data format from ADCs to XPIC
S5 OFF MULCONH R/D
S6 OFF MULENH R/D
S7 ON ERRADJ Timing ISEN & QSEN
S8 OFF FIFOBYP ON = disabling of Static delay.
2.2.2 Strap settings EDNF100A
Norm Pos = Default position.

nm = not mounted
Strap Test Norm Description

Pos Pos
W401 2-2 2-3 Reset control of XPIC chip. (1-2 => reset XPIC, 2-3 => Auto)
8 H2971
2DNF135A
From main RF &

antenna down
conv. Space
IF-filter IF- 2DNF135A CMI
diversity
RF & & AGC splitter Demodulator data out
From space comb.
down
antenna EDNF100A
conv.
XPIC
From main RF & EDNF100A

Co-polar down XPIC
antenna conv. Space
IF-filter IF- 2DNF135A CMI
diversity
From space RF & & AGC splitter Demodulator data out
comb.
Co-polar down
antenna conv.
)LJ5HFHLYHU%ORFN'LDJUDP
The 4D-128TCM XPIC demodulator unit is built on two circuit boards, 2DNF135A and EDNF100A, mounted in
the same box .
The Unit contains all functions from IF-input to Synchronous Physical Interface -(SPI) output.
The demodulator unit has a number of switches and straps which are used to configure the unit.
Details of the switch settings are given in Section 2 (Configuration) and in the Handbook chapter 4.

· Regeneration Section Termination (RST)
· Multiplexer Section Termination (MST)
· Enable/Disable of 140Mb/s demultiplexing.
· Selection of high BER, - low BER and EWBER-limits
· RF-identification bits.
H2971
9
2DNF135A
4.1 Main Functions:
A block diagram of the main functions of the demodulator unit is shown in fig. 2.
SOH POH
in/out out
IF INP I&Q ATDE Viterbi STM-1 C4 CMI CMI

demod (asic) (asic) & alignment demapper codec (asic) G.703
switch (asic)
(asic)
A/D conv
Data from
protection
channel
I&Q XPIC
IF INP (asic)
from
demod
co-polar
A/D conv
EDNF100A “XPIC” 2DNF135A “DEMOD”
)LJ'(02'%ORFN'LDJUDP
A brief description of these functions is given here:
4.1.1 I & Q DEMODULATOR: 4.1.3 ATDE (ADAPTIVE TIME

This is the analog part of the demodulator unit. The IF- DOMAIN EQUALIZER):
signal from the receiver is split into two branches at the A 13-taps Adaptive Time Domain Equalizer (ATDE) is
input. In one of the branches the IF signal is mixed with provided in order to establish effective countermeasures
LO-signal with 0° phase shift, and in the other branch, against the distortion effects caused by multipath
mixed with the LO-signal 90° phase shifted. This transmission (selective fading). The complex equalizer is
implies that the in-phase component of the controlled by the Least Mean Square error (LMS) and
demodulated signal is retained in the first branch and the Maximum Level Error (MLE) algorithms. The
the quadrature component in the other. The output of optimum algorithm will be automatically selected.The
the mixers contains the sum- and difference-products digital ATDE is implemented in one single ASIC in
of the IF- and LO-signal. The sum and higher order CMOS technology. The circuit has built-in functions for
mixing products are suppressed in an LP-filter. The Automatic Gain Control (AGC), DC-offset- and
resulting signal is amplified to the proper level for the quadrature-phase adjustment. It also generates control
following A/D-converters. signals for carrier-recovery and timing recovery.
The I & Q demodulator for the xpic is similar. This ATDE asic performs the control of, and sumates
data from, the XPIC asic.
4.1.2 A/D (ANALOG TO DIGITAL

CONVERTER): 4.1.4 XPIC (Cross Polar Interference
The two A/D-converters for the ATDE are 10 bit Canceller):
converters and works at a sampling rate of 24 A 10-taps fractionally spaced, adaptive Cross-Polar
Msamples/s. Interference Canceller is provided in order to establish
The two A/D-converters for the XPIC are 8 bit effective countermeasures against variations in cross-
converters and works at a samplingrate of of 48 polar discrimination. The variations are caused by
Msample/s different transmission effects in between the
10 H2971
2DNF135A
antennas.The xpic is implemented in one single asic in monitoring is available on the front of the demodulator
CMOS technology. unit.
The same CMI CODEC- circuit is used to CMI-decode
the data signal coming from the protection channel.
utilizing the VITERBI-Algorithm):
The 4-dimensional Trellis Code Modulation (TCM) 4.1.9 BER monitor and control logic.
decoder is implemented in an ASIC in CMOS The following functions are implemented in a FPGA
technology. The TCM-decoder function is the receiver (IC403). The configuration program is located in serial
part of the modulation coding used to perform error prom IC404.
correction. The Viterbi algorithm is used in the decoder
to improve the system performance. 4.1.9.1 Bit error rate monitor:
The realized 8- state Viterbi-decoder, with Viterbi- The error pulses from the trellis decoder CNF22A are
depth=15, gives a coding gain of approx. 4 dB at used to carryout the error measurements leading to the
BER=10-6 compared with uncoded 128 QAM generation of three programmable performance threshold
modulation. indicators:
EWBER(Early warning) :Integration time 128ms
LBER :Integration time 8ms
4.1.6 STM-1 & alignment switch: HBER :Integration time 1ms
The STM-1-processor is used to perform the system These indicators will be activated immediately when an
synchronization, descrambling, Section OverHead on-threshold violation is detected and stays active until
(SOH)-termination and alignment switching. an integration period without an off-threshold violation is
A burst-decoder is used to rearrange the STM-1 frame elapsed. An active out of frame alarm from the STM-1
to its original state before the signal is applied to the processor will also activate the indicators.
other functions in the unit.
The circuit rebuilds the STM-1 frame according to the
rules specified in CCITT Rec.G.707-709 and 4.1.9.2 Viterbi-hop-error-pulse
Rec.G.782-784. processing:
All extraction of Section OverHead (SOH)-bytes from Error pulses from Viterbi decoder CNF36A are proc-
the incoming STM-1-frame and insertion of new SOH- essed in order to get a viterbi-hop-error-pulse of approx.
information is done in this circuit. 1us duration and a frequency less than 32kHz at BER
Alignment and switch function for the N+1 radio < 1 x 10-2.
protection switching is built into this circuit. The switch
function is controlled from the Radio Protection Switch
(RPS)-unit. 4.1.9.3 B1/B2 block error processing:
B1 ,B2 and STM-1 frame pulses from the STM-1
processor CNF19D are processed in order to generate
4.1.7 C4 demapper:
B1 and B2 block error-pulses. One pulse is generated for
The C4-DEMAPPER (demux) is used to map out the each frame containing B1 or B2 error pulses.
139.264 kbit/s of the STM-1-frame. This function is
only used if the 140 Mb interface is selected. Traffic is
carried straight through this circuit if the STM-1- 4.1.9.4 ATPC logic:
interface is selected. The C4-demapping is done
The purpose of this function is to control the transmitted
according to CCITT Rec. G.707-709 and Rec. G.782-
power.
784.
From the demod , we present an output power control
This circuit also extracts the Path Overhead (POH) bytes
voltage to the transmitter in opposit direction.
from the incoming STM-1 frame.
This voltage is a function of control signals from the
supervisory system and two bits in the incomming SOH
to the demod.The two bits in SOH comes from the
4.1.8 CMI CODEC:
reciever on opposite side and are inserted in the corre-
The CMI CODEC (ECL-asic), performs the combining sponding modulator.
and CMI-encoding of the data coming from the C4- Within IC403 we have placed the control logic and
DEMUX. The CMI-data signal is then applied to a CMI- presents a 6bit word to a D/A converter, giving the
driver before it is made available on the front of the control voltage to the transmitter.
demodulator unit. A CMI test output for in-service A regulation cycle, max to min or min to max, will take
H2971
11
2DNF135A
place in min 300ms. The regulation speed varies over the 4.2.3 SOH Bus-Outputs:
total range in a manner to compensate for the logarithmic
Section OverHead is extracted from the STM-1-frame
behaviour of the power control in the transmitter.
and bus drivers are included to transport the SOH-bus to
the service rack where different optional adapters can
4.1.10 XPIC timing and control logic.
connect to the bus for access to the SOH-bytes.
(IC406). The configuration program is located in serial
prom IC405. 4.2.4 SOH BUS Input (Optional):
By use of adapters, it is possible to insert Section
4.1.10.1 Xpic timing:
Overhead into the STM-1 Frame out from the
To achieve right delay of I & Q data using AD9050BR demodulator.
A/D converters, data are delayed two clock cyckles.
4.1.10.2 Control logic: 4.2.5 POH BUS Output (Optional):

This circuit controls Reset, Sweep memory, Xpic alm, By use of adapters, it is possible to extract Path
IF inp alm , XADD (Xpic on/off) and blind threshold Overhead from the incoming STM-1 Frame when C4-
level Beta (for the ATDE). demapping is active (140Mb output).
4.2.6 RF_ID:
Comparison of the two RF_ID bits in the incoming
STM-1 frame with the two bits selected on S501, is
4.2 Other Functions: performed in the demodulator unit.
An RF_ID_Alm is given if there is any difference.
The demodulator also includes circuits for 2 Mb/s RF_IO_ALM can be disabled with S501.
wayside output, B1, B2 and B3 parity error output, See "Configuration" for details.
SOH-bus outputs, SOH-bus input, POH- bus output,
RF_ID identification and alarm outputs.
4.2.7 MS_RFAIL_DEM:
The Demodulator alarm MS_RFAIL_DEM report the
4.2.1 2Mb/s Wayside traffic: quality of the data comming out of the STM-1 ASIC.
HDB-3 coding and line driver circuits for 2.048Mb/s (IC 503):
wayside traffic is included in the demodulator. The
interface is 75ohm, unbalanced (G703). If regular channel is selected by RPS:
else
4.2.2 Parity Error if protection channel is selected by RPS:
B1, B2 and B3 parity error pulses are available out from MS_RFAIL_DEM = LOF2_DEM or MS_AIS_DEM
the demodulator .
B1_ERR_DEM and B2_ERR_DEM can be taken from
either B1_ ERR_STM1 / B2_ ERR_STM1
or
BLOCK_ERR_B1 / BLOCK_ER_B2 by means of the
Straps W606 / W607.
These outputs are routed to the Alarm Collection Unit
(ACU).See Configuration for details.
B1- and B2 parity error outputs are available from the

ACU at the top of the slimracks for each STM-1
channel.
12 H2971
2DNF135A
4.3 Alarm Outputs:

input is missing
RF_ID_ALM Alarm indicating that wrong connected to the ACU,

RF-id is received can be disabled on S501
HBER_HOP_ALM Alarm for BER > 5*10-4 Red LED

HBER_SEC_ALM OR-ed HBER_HOP_ALM connected to the ACU

LBER_HOP_IND Indicator for BER > 5*10-7, Yellow LED

LBER_SEC_IND OR-ed LBER_HOP_IND connected to the ACU and RPS

EWBER_HOP_IND Early warning BER indicator connected to the ACU

based on Viterbi pseudo errors
EWBER_SEC_IND OR-ed EWBER_HOP_IND connected to the RPS

XPIC_ALM Indicates that IF input is missing connected to the ACU

in to xpic demod OR that xpic is
turned off with XPIC switch on
front of the unit.


received traffic.
SYNCL_SEC_ALM OR-ed OOF1_DEM+ connected to the ACU

Alarm indicating sync. loss has


H2971
13
2DNF135A

traffic

received traffic

received traffic

received traffic
AIS_OUT_140 AIS detected on 140 Mb/s data outp. connected to the ACU
CMI_OUT_ALM_DEM Alarm indicating 311/280 PLL connected to the ACU

(VCXO) is out of lock,
or CMI-data output is missing

STM-1 is locked to a 2 MHz
external clock


is carrying AIS


+ SYNCL_SEC_ALM
+ SYNCL_VITERBI

MS_RFAIL_DEM Signal reporting the quality of data connected to the modulator

comming out of the demod.
14 H2971
8F264A
EQUALIZER, IF
8F264A
H2015 Rev. A
© Nera AS
H2015
1
8F264A
1.0 Technical Data:

Impedance at 7J1...7J4 : 75 ohms unbalanced
Return loss at 7J1...7J4 for 55 MHz...85 MH : >26 dB
IF response variations for 55 MHz...85 MHz : <0.5 dB
Delay approx. parabolic for 55 MHz...85 MHz : 15 nS
Variable absolute delay : 0...16 nS
Gain : 0 dB ±1 dB
2.0 General Description:

8F264A, Equalizer IF, contains the printed circuit board EFU286A. Simplified circuit diagram
shown in fig. 1.
The fourth order network between 7J4 and 7J3 compensates for the group delay in the RF filters
in the main channel, while the network between 7J2 and 7J1 compensates for group delay and
absolute delay in the space div. channel. The absolute delay is adjustable 0...16 ns in steps of 1ns
by four slide switches on EFU286A. If more absolute delay in the space div. channel is necessary
to get signal synchronization between the two channels, a coax cable of suitable length can be
inserted between 7J3 and the IF preamplifier.
Fig.1: Principle Diagrams of 8F264A
2 H2015
8F264A
TO
TO
TO
TO
Fig. 2 Schematic Diagrams of Equalizer, IF, 8F264A
H2015
3
8F267A/B
EQUALIZER, IF
8F267A/B
H2014 Rev. A
© Nera AS
H2014
1
8F267A/B
1.0 Technical Description:
Impedance at 7J3...7J4 : 75 ohms unbalanced

Return loss at 7J3...7J4 for 55 MHz...85 MHz : >26 dB
IF response variations for 55 MHz...85 MHz : <0.5 dB
Delay approx. parabolic for 55 MHz...85 MHz : 15 nS
Gain : 0 dB ±1 dB
2.0 General Description:

8F267A/B, Equalizer IF, contains the printed circuit board EFU286B/C.
Fig. 1 shows a simplified circuit diagram .
The fourth order network between 7J4 and 7J3 compensates for the group delay in the RF filters
in the main channel.
Fig. 1 Principle Schematic Diagram for Equalizer, IF, 8F267A/B
2 H2014
8F267A/B
TO
TO
TO
TO
7J3
COAX 7L1
7J3 1 2 CP8
1
IF OUT 2
ALS1042
7P1
10
9
8
7
6 EQUALIZER IF
5 EFU286
4
3
2
1
CA10
FL
CP7
7FL1
7CP1
7J4
7J4 COAX
1 CP1
IF INP 2
Fig.2 Schematic Diagrams for Equalizer, IF, 8F267A/B
H2014
3
IF Filter, 70MHz
8F312A
H3028 Rev. A
© Nera ASA
8F312A
1.0 DESCRIPTION
1.1 General
For innermost channels, the IF filter with code 8F312A is placed in the radio on top of the IF equalizers.
The purpose is to reduce signal leakage from the transmitter to the receiver and with that retain the threshold requirements.
1.2 Functional
The filter is an elliptic filter composed of a fifth order low pass and high pass section connected together.
Input impedance: 75 ohm. Output impedance: 75 ohm.

Poles Amplitude
Pole(MHz) Pole(MHz) Pole(MHz) Pole(MHz) f=58 MHz f=70 MHz f=82 MHz
Att. dB Att. dB Att. dB
30.5±2 42±1.5 106±2.0 145 ±2.5 1.3±0.2 1.0±0.15 1.3 ±0.2
EQUALIZER
33J4 NOTE! CONNECTOR MOUNTED ON CABLE

IF FILTER DURING INSTALLATION
Fig.1 IF Filter mounted on Equalizer's lid
2 H3028
CMI - SPLITTER
2G426A
H2789 Rev. A
© Nera AS
2G426A
1 Description
1.1 General 1.2.2 CMI Output ( J2, J3 )
The CMI-splitter unit is the user interface CMI IN- Impedance : 75 ohm unbalanced
PUT on NL29X and performs the following functions: Pulse amplitude (nominal) : 1 ± 0.2 Vpp
1. Input characteristics according to G703. 1.2.3 CMI Input Alarm

2. Splits the CMI signal into two equal outputs
3. Detects CMI input and generates an alarm if
Driver : NPN open collector ,
CMI input signal is missing.
emitter to ground.
Status : Grounded means No
1.2 Technical Data input alarm (the tran-
1.2.1 CMI Input ( J1) sistor is in ON state)
1.2.4 Power Consumption
Impedance : 75 ohm unbalanced
Returnloss (7 to 240 MHz) : >= 15 dB + 5V / 85 mA
Pulse amplitude (nominal) : 1 ± 0.1 Vpp - 5.2V / 75 mA
1.3 Block Schematic Diagram of

CMI-Splitter:
Driver CMI out 1
CMI IN Input buffer Splitter Driver CMI out 2
Driver Detector
CMI INP alm
2 H2789
RELAY UNIT, SDH
0S186A
H2858 Rev. A
© Nera AS
0S186A
TABLE OF CONTENTS
Page
1 Technical Data 3
2 Description 4
2.1 Mechanical 4
2.2 General 4
2.3 Functional 4
Schematic Drawings 5-7
2
H2858
0S186A
1 Technical Data:
Baseband Connections:
BB reg. chan. CMI, input

(From RGLR Chan) : 6J4
BB prot. chan. CMI, input

(From Prev. relay/prot) : 6J2
BB CMI output (CMI-out) : 6J1
BB prot. chan. CMI, output

(To next relay) : 6J3
Baseband Input:
BB format : CMI, 140Mb/s or 155Mb/s

BB input impedance : 75 ohm, unbalanced
Baseband Output:
BB format : CMI, 140Mb/s or 155Mb/s

BB output impedance : 75 ohm, unbalanced
Relay Control Signal:
Control signal : P1, pin 1 and/or 2

Control signal, return : P1, pin 3
Control signal, relay operate : +15V relative to "return"
Control signal, relay deoperated : 0V relative to "return"
Power Supply:
No power supply needed
GND : P1, pin 9 and 10
Data signal attenuation (70 MHz):
Relay deoperated : <0.5 dB

Relay operated : <1 dB
Data signal attenuation during a relay protectional (Chan. number of switched channel) should be
switching in a N + 1 system: expected. If a Relay Unit is implemented on the
protection channel, an additional 0.5dB must be
A data signal attenuation (70MHz) less than 0.5 dB x expected.
3
H2858
0S186A
2 Description:
2.1 Mechanical: 2.3 Functional :
The unit is built on a printed circuit board mounted Ref. circuit diagram, Fig.3.
in a solid box of dimensions 63 x 45 x 25mm.
To avoid any need of Power Supply voltages during
normal operation, a mechanical relay is used for the
2.2 General: data signal switching.
The Relay Unit is designed for use in a 140Mb/s A diode is connected across the relay coil to avoid
or 155Mb/s, 1+1/N+1 system. voltage spikes during relay deoperation.
The main purpose of the unit is to perform During normal operation (relay deoperated) J4-input
protectional switching when the Alignment Switch (FROM RGLR CHAN) is connected to J1-output
in the Demodulator Unit is unable to perform (CMI OUT) and the J2-input (FROM PREVIOUS
protectional switching. RELAY/PROT CHAN) is connected to J3-output
(TO NEXT RELAY).
The relay is controlled from the Central Unit of the
Protectional Switching system, which uses the During relay protectional switching (relay operated)
different alarm states for deciding when a relay J2-input (FROM PREVIOUS RELAY/PROT
operation is required. CHAN) is connected to J1-output (CMI OUT) and
J4-input (FROM RGLR CHAN) is not connected to
During normal system operation on a regular any signal output. The J4-signal is then terminated in
channel, the relay is deoperated. a high impedance.
To reduce Cross-Talk to a minimum, no test output/

test switching is implemented. Component numbering system:
There is no active components in the unit. Main unit (box) : 1-99 (+ prefix)
For Relay Unit Configuration, see Fig.1 and Fig.2. Printed circuit board : 101 - and up (+ prefix)
4
H2858
0S186A
75
6J3
RELAY UNIT DEMODULATOR CHAN. N
OS186A
*
TO 6J1 CMI OUT 7 5 6J4 4J2 CMI
MUX 6 4J3 DRIVER
CH-N 4 COD.
2
3
1 8 CMI TEST
6J2 RELAY
CONTROL
6J3
RELAY UNIT DEMODULATOR CHAN 1
OS186A
*
TO 6J1 CMI OUT 7 5 6J4 4J2
CMI
MUX 6 4J3 DRIVER
CH-1 COD.
2 4
3
1 8 CMI TEST
6J2 RELAY
CONTROL
6J3 From RCVR Distribution Unit
RELAY UNIT DEMODULATOR PROT CHAN.

OS186A
6J2 To RCVR Distribution Unit
** 4J2
6J1 5
OPTIONAL CMI OUT 7 6J4 CMI
6 4J3 DRIVER
TRAFFIC PROT. 4 COD.
2
3
1 8 CMI TEST
RELAY
CONTROL
* RELAY SHOWN DEOPERATED
** RELAY SHOWN DEOPERATED

RELAY OPERATED DURING NORMAL OPERATION
Fig.1 Relay Unit Configuration with Relay for Optional Traffic on Protection Channel.
5
H2858
0S186A
75
RELAY UNIT 6J3 DEMODULATOR CHAN. N

0S186A
* 6J4 4J2
6J1 CMI OUT 7 5
6 4J3 CMI
CH-N DRIVER
TO 4 COD.
2
MUX 3
1 8 CMI TEST
-
6J2 RELAY
CONTROL
RELAY UNIT 6J3 DEMODULATOR CHAN 1

0S186A
6J4
6J1 CMI OUT * 5 4J2
7 6 CMI
TO CH-1 4J3 DRIVER
4 COD.
MUX 2
3
1 8 CMI TEST
6J2 RELAY
CONTROL
From RCVR Distribution Unit
DEMODULATOR PROT CHAN.
To RCVR Distribution Unit
4J2 CMI
DRIVER
4J3 COD.
CMI TEST
Not
connected CONTROL
* RELAY SHOWN DEOPERATED
Fig.2 Relay Unit Configuration without Optional Traffic on Protection Channel.
6
H2858
0S186A
Fig.3 Circuit Diagram of Relay Unit, 0S186A

7
H2858
ALARM COLLECTION UNIT (ACU)
0JG161A
H2596 Rev.B
© Nera AS
0JG161A
TABLE OF CONTENTS
1 INTRODUCTION 3
2.1 Alarm Interface 3
2.2 Parity Error Signal Interface 3
2.3 Control Outputs 3
2.4 Control Inputs 3
2.5 Analog to Digital Converter 4
2.6 Internal Serial Communicational Interface 4
2.7 CPU - ROM - RAM 4
2.8 Address Decoding 4
2.9 Memory Map 5
2.10 Watchdog-Reset 5
2.11 DIL Switch S3 5
2 H2596
0JG161A
1 INTRODUCTION All parity input pulses are TTL compatible and have a
variable occurrence that is dependent on the quality of
The Alarm Collection Unit (ACU) is used to perform the RF channel. Pulse high level duration is 1.95 µs and
the following functions: minimum distance between pulses is 3.9 µs. All parity
pulses are counted in hardware counters and are used to
1) collect the internal alarms of the equipment. calculate the performance of the radio relay channel.
2) measure the internal voltages of the equipment.
3) count the parity error pulses of the equipment. PULSE NAME DESCRIPTION
B1_ ERR_ DEM Regenerator section errors from demod. reg. chan.
The ACU can be mounted in either the service rack or the B2_ ERR_ DEM_REG Multiplex section error from demod. reg. chan.
B2_ ERR_ DEM_ PROT Multiplex section error from demod. prot. chan.
radio rack, but in the service rack the pulse count option B3_ ERR_ DEM Path overhead error from demodulator
is not valid. The ACU uses an INTEL-compatible G1_ ERR_ DEM Path overhead remote error from demodulator
microcontroller of the 8031-type. VIT_ HOP_ ERR Viterbi hop error
VIT_ SEC_ ERR Viterbi section error
PJE_ DEM Pointer justification event from demodulator
The ACU has standard single European card size and
runs on a +5V supply and consumes about 200 mA of B1_ ERR_ MOD Regenerator section error from modulator
B2_ ERR_ MOD Multiplex section error from modulator
current. PJE_ MOD Pointer justification event from modulator
The B1_ERR_DEM and B2_ERR_DEM_REG

2 FUNCTIONAL DESCRIPTION signals are buffered on the ACU before they are
routed to the top of the RF-channel rack as
2.1 Alarm Interface:
B1_ERR_HOP_OUT and as B2_ERR_SEC_OUT.
These outputs can be selected individually with
The ACU can handle up to 56 internal alarm inputs from
the equipment rack it is placed in. The alarms are handled dilswitch S3 as either TTL-compatible or OPTO-
internally on the ACU in groups of 8 alarms. Some alarm COUPLER-compatible.
groups come as serial alarms, while others come as
parallel alarms. These serial alarms are converted to OUTPUT NAME DESCRIPTION
parallel alarms by shift-registers (74595). The shift
registers get their timing signals from the back plane in B1_ ERR_ HOP_ OUT Regenerator section errors to top of rack
which the ACU is plugged. The alarm inputs are read by B2_ ERR_ SEC_ OUT Multiplex section errors to top of rack
the CPU every 10 ms.
Alarm conditions must be latched in the ACU until the 2.3 Control Outputs:
ACU is polled by the SU. Alarm latching is a means of
insuring the reporting of one or more occurrences of an The control outputs are used as set/reset signals within
alarm condition when the SU is not polling the ACU. the equipment rack. There are 8 control ouputs which
When the ACU is polled by the SU the alarm status is are latched and buffered. The MAIN_OUT_ALM sig-
transferred. All alarm inputs are TTL compatible. nal will drive a relay and therefore the port must be able
to sink max. 40 mA of current.
2.2 Parity Error Signal Interface:
2.4 Control Inputs:
The Parity Error Signal Interface receives parity pulses The SU must be able to distinguish between the different
from the modulator and demodulator. There are 11 parity ACUs in the supervision system when communicating
input pulses on the ACU and 2 parity output pulses on the via the internal serial parity line. Therefore every ACU
ACU for each RF channel. The B2_ERR_DEM_REG in a system must have its own unique hardware address.
and the B2_ERR_DEM_PROT pulses are combined to The hardware address is set up by a DIL-switch on
backplane. 5 bits are used for address selection, giving
1 signal on the ACU. The CHAN_SEL signal determines the possibility of having up to 32 ACUs connected to
which of the 2 channels is counted, but the parity-counter the serial bus. During the initialization the prosessor
sees only 1 signal. In a service rack position no pulses are reads the unit address and stores this address for later
counted. use.
H2596
3
0JG161A
The REMOTE_RESET_ACU_AAU is a reset signal address decoding.

from the local SU which resets both the ACU and the A chosen programmable peripheral (PSD311) con-
AAU. On the ACU it is «or-ed» with the watchdog/reset tains:
signal.
a) 32k * 8 bits of EPROM
The CHAN_SEL signal is latched on the ACU by a D- b) 2k * 8bits of RAM
flip-flop. The latching signal is provided by the RPS- c) a PAL for the generation of chip select signals.
system and after reset of the ACU it latches the
CHAN_SEL signal by itself. Future requirements may exceed the present RAM
capacity of 2k bytes. In order to increase RAM capacity
to more than 2k bytes RAM, space is provided to use an
optional 8k *8 RAM, but the RAM circuit will not be
2.5 Analog to Digital Converter: mounted before software needs this extra capacity. The
PSD311 will be programmed for the first software
The Analog to Digital converter is to measure: releases with only 2k*8 of RAM memory, starting at
8000 (hex) until it is decided to insert the optional RAM
a) the main power supply voltages device.
b) the XMTR power supply
c) various voltage levels from the receiver
and the transmitter of the RF-channel. 2.8 Address Decoding:
When the ACU is used in a service rack position ,only the The programmable peripheral circuit (PSD311) will
main supply voltages are measured. latch the address on the address/databus when ALE goes
low. The peripheral will then decode the address and
The A/D converter has 16 analog inputs and the resolu- generate external I/O-chip-select signals. These I/O
tion is 8 bits (256 levels). Every analog input channel is chip-select signals have a resolution of 2kbytes. The
scaled down to 2.3 V with a resistive devider. Every PSD311 I/O port-A is used to latch the address LSB
channel has the possibility to measure overvoltage con- (AD0 - AD7) and distribute it to other peripherals.
ditions up to +10 %. The analog channels are converted
every 10 ms but they are read only every second. The address decoding assumes that there is only one
memory space. This means that both WR, RD and PSEN
are used together.
2.6 Internal Serial To increase resolution of the alarm inputs from 2k, a 3
Communicational Interface: to 8 decoder is used to decode the alarm input groups.
This decoder uses the lower 3 address bits (A0, A1 and
To communicate with the Supervisory Unit (SU), the A2), this gives a maximum of 8 alarm input groups. The
ACU shall have a high speed (187.5 kbit/s) point to decoder is selected with the CS-ALM signal from the
multipoint serial bus implemented, using the microcon- PSD311 whenever an address lies within the 2kbyte
trollers built in UART. The electrical interface shall be alarm block.
RS-485, which is a balanced interface. The ACU will
always be in the listening mode. Only the SU can initiate All 12 parity counters are mapped within a 2kbyte block.
communication. A 2 to 4 decoder is used to generate 4 chip select signals
with 8 byte resolution by using A3 and A4. The decoder
is selected with the CS-CNTRS signal from the PSD311
whenever an address lies within the 2kbytes counter
2.7 CPU - ROM - RAM: block.
The CPU is an Intel 80C31 compatible microcontroller All 16 analog channels are mapped within a 2kbyte
running at 12 MHz . Because of space requirements an block. A 2 to 4 decoder is used to generate 2 chip-select
integrated solution is chosen for the ROM, RAM and signals with 8 byte resolution, by using A3 and A4. The
decoder is selected with the CS-ANALOG signal from
the PSD311 whenever an address lies within the 2kbytes
analog channel block. (See MEMORY MAP, next
page).
4 H2596
0JG161A
2.9 Memory Map:
A15 A14 A13 A12 A11 ALE RD WR DESCRIPTION HEX ADDR.
0 0 0 0 X 1 Y N PSD311 internal ROM 32k 0000 - 7FFF

1 0 0 0 0 1 Y Y PSD311 internal RAM 2k 8000 - 87FF
1 0 1 0 1 1 Y N I/O PORTS PSD311 A800 - AFFF
1 0 1 1 0 1 Y N ALARM GROUPS 1-7 B000 - B7FF

1 0 1 1 1 1 Y Y ANALOG CHANNELS B800 - BFFF
1 1 0 0 0 1 N Y CONTROL OUTPUT C000 - C7FF
1 1 0 0 1 1 Y Y PARITY COUNTERS C800 - CFFF
N: no
Y: yes
X: dont care
2.10 Watchdog-Reset: 2.12 DIL Switch S3:

The Watchdog (WD) is a counter which outputs a reset
signal to the micro-controller unless it is reset by the SWITCH NO. NORMAL POS. FUNCTION
micro-controller. The micro-controller will reset the
watchdog under software command.
S1 ON Tells the uP that ROM is external
On power- up the watchdog will issue a reset signal to S2 ON Enables the WD & reset
the micro-controller until the supply voltage has risen S3 OPEN Not used
above 4.6 Volts. If the supply voltage drops below 4.6 S4 OPEN Not used
V, the watchdog will generate a reset signal to the micro-
controller. The watchdog will not react on overvoltages S5 OPEN Not used
(>5.5 V). A manually operated push-button can be used S6 OPEN Not used
to reset the microcontroller with the aid of the watchdog S7 OPEN Not used
circuitry. The reset signal from the watchdog circuit is S8 ON Enables the main program
called MAN/WD-RESET.
The MAN/WD-RESET signal is «or-ed» together with

a remote reset signal (RMT_RESET_ACU_AAU) from
the SU. The resulting reset signal is dubbed uP-RESET
and can be disabled with a DIL-switch (S3)
2.11 DIL Switch S1:
SWITCH NO. NORMAL POS. FUNCTION
S1 OPEN If closed, gives TTL-compatible signal (S2 must be open)
S2 ON If closed, gives OPTO-compatible signal (S1 must be open)
S3 OPEN If closed, gives TTL-compatible signal (S4 must be open)
S4 ON If closed, gives OPTO-compatible signal (S3 must be open)
H2596
5
ALARM & LOGIC, HOT STANDBY
3KS218A
H2801 Rev. B
© Nera AS
3KS218A
1.0 TECHNICAL DATA
Parallel alarm inputs: HCT-logic with 10kW pull-up resistor
Serial alarm inputs: 8 alarms per input with sampling speed of about 10msec.
NPN Optocoupler alarm outputs: VCEO max: 70VDC

IC max: 12mA
Isolation voltage: 2.5kV
VCE (SAT): £ 0.2V for IC = 1mA
ICEO: £ 1µA for VCE = 40V
Relay alarm outputs: Contacts: 2 form C.

Contact resistance: <60mW
Max. switching power: 0.3A, 100VDC
Power consumption: Supply voltage: +5V, ±0.25V

Current: nom. 125mA
max. 280mA
1.1 Functional Description
1.1.1 Alarm Part:
This board collects alarms from units located in the For the Power Supply Alarm, the Normally Open or
radio rack Channel 1 and combines these into Normally Closed contact is selected by strap W8.
external alarms with optocoupler or relay contact
W8 in pos. 1-2 gives Normally Open.
outputs.
W8 in pos. 2-3 gives Normally Closed.
The outputs are wired via Connection Panel, EW52A
to a 37-pins D-sub connector located at the top of the
radio rack. On this connector there are also some 1.1.2 HOT STANDBY Logic Part:
monitor voltages coming from the Tx and Rx groups.
Alarms from other equipment can be taken into the This board is located in radio Channel 1. For termi-
board to take part in the Hot Standby switching logic. nals, alarms from radio Channel 2 are led to this board
by a flat-cable via backplane EW52A. The double
HOT STANDBY input alarm 2 and 3 have to share
straps W2 and W3 have to be in pos. 1-3, 2-4. For
the positions in the D-sub connector with the RF-ID
repeaters, alarms between the four radio racks, Chan-
Alarm Out.
nel 1 and 2 direction 1 and Channel 1 and 2 direction
When strap W1 is in pos.1-2, Hot Standby input
2, are distributed by a more complex cable via back-
alarm can
Alarm Outbeisused. When strap W1 is in pos.2-3, the
in use.
plane EW52A. The double strap W2 has to be in the
RF-ID
If strap W4 and W5 are on, HBER HOP alarm and same pos. as for terminals, but strap W3 has to be
LBER HOP alarm will be part of the RCVR Group moved to pos. 1-2, 3-4.
alarm.
With strap W6 in pos.2-3, RF ID alarm will be part 1.1.3 HOT STANDBY Channel Priority:
of the Demodulator alarm. With W6 in pos.1-2,
it will not be part of the Demodulator alarm.
By strap W7 the channel priority can be selected:
Power Supply Alarm and Main Alarm outputs are
relay contacts. For Main Alarm, both the Normally Strap in pos. 1-6: No priority
Open- and the Normally Closed contacts are wired to Strap in pos. 2-3: Channel 2 has priority
the D-sub connector. Strap in pos. 3-4: Channel 1 has priority
2 H2801
3KS218A
Channel 1 or 2 can be given priority via the supervi- The control signal to the RF-switch 10S226A and the
sory system independent of the W7 position. position indicating signals back from the RF-switch
At last, the manual switch S1 will override all other are routed via backplane EW52A-plug P10. (RF-
priority settings and it will also extinguish the switch is part of the RF-branching!)
Remote Lock indicator.
1.2 37-pins D-sub Connector at top of Radio Rack:
Pin 1: XMTR_GROUP_ALM Collector

Pin 2: XMTR_GROUP_ALM Emitter
Pin 3: RCVR_GROUP_ALM Collector
Pin 4: RVCR_GROUP_ALM Emitter
Pin 5: MODULATOR_ALM Collector
Pin 6: MODULATOR_ALM Emitter
Pin 7: DEMODULATOR_ALM Collector
Pin 8: DEMODULATOR_ALM Emitter
Pin 9: RF_SWITCH_COMMON Relay contacts. Closed for CH1. Open for CH2.
Pin 10: RF_SWITCH_POSITION
Pin 11: HBER_SEC_ALM Collector

Pin 12: HBER_SEC_ALM Emitter
Pin 13: LBER_SEC_IND Collector
Pin 14: LBER_SEC_IND Emitter
Pin 15: RF_ID_ALM / ALM2_INPUT Collector/TTL-level
Pin 16: RF_ID_ALM /ALM3_INPUT Emitter/TTL-level
Pin 17: PWR_SPLY_ALM Centre
Pin 18: PWR_SPLY_ALM NO/NC
Pin 19: AIS_XMTR_ALM Collector
Pin 20: AIS_XMTR_ALM Emitter
Pin 21: AIS_RCVR_ALM Collector
Pin 22: AIS_RCVR_ALM Emitter
Pin 23: PROT_SW_STATUS Collector
Pin 24: PROT_SW_STATUS Emitter
Pin 25: 2M_WAY_ALM Collector
Pin 26: 2M_WAY_ALM Emitter
Pin 27: ALM1_INPUT TTL-level
Pin 28: GND
Pin 29: MAIN_RCVR_RF_INP_LEVEL 0-5V (ca. 3V at -35dBm Input)
Pin 30: GND
Pin 31: SP_DIV_RCVR_RF_INP_LEVEL 0-5V (ca. 3V at -35dBm Input)
Pin 32: GND
Pin 33: XMTR_PWR_OUT_LEVEL 2V at nom. output level
Pin 34: GND
Pin 35: MAIN_ALM NO
Pin 36: MAIN_ALM Centre
Pin 37: MAIN_ALM NC
H2801
NO= Normally Open, NC= Normally Closed 3
ALARM BOARD, RADIO RACK
EJ163A
H2697 Rev. A
© Nera AS
EJ163A
1.0 TECHNICAL DATA

IC max: 12mA


Current: nom. 75mA
max. 200mA
This board collects alarms from units located in the
radio rack and combines these into external alarms Alarm Out is in use.
with optocoupler or relay contact outputs. If strap W2 and W3 are on, HBER HOP alarm and
The outputs are wired via Connection Panel, EW52A LBER HOP alarm will be part of the RCVR Group
to a 37-pins D-sub Connector located at the top of the alarm. With strap W4 in pos.2-3, RF ID alarm will
radio rack. On this connector there are also some be part of the Demodulator alarm. With W4 in pos.1-
monitor voltages coming from other units. 2, it will not be part of the Demodulator
alarm.
The board is prepared for a Hot Standby system, and
alarms from other equipment can be taken into the Power Supply Alarm and Main Alarm outputs are
board to take part in the switching logic. relay contacts. For Main Alarm, both the Normally
Open and the Normally Closed contacts are wired to
HOT STANDBY input alarm 2 and 3 have to share the D-sub connector.
Alarm Out. For Power Supply Alarm the Normally Open or
When strap W1 is in pos.1-2, Hot Standby input Normally Closed contact is selected by strap W2.
alarm can be used. When strap W1 is in pos.2-3, the W2 in pos. 1-2 gives Normally Open.
RF-ID W2 in pos. 2-3 gives Normally Closed.
2 H2697
EJ163A

Pin 9: CMI_SPLIT_ALM Collector
Pin 10: CMI_SPLIT_ALM Emitter
Pin 28: GND
Pin 30: GND
Pin 32: GND
Pin 34: GND
Pin 35: MAIN_ALM NO
Pin 37: MAIN_ALM NC
NO= Normally Open, NC= Normally Closed
H2697 3
EJ163A
Fig. 1 Alarm Board, Radio Rack, EJ163A
4 H2697
ALARM BOARD, RADIO RACK
EJ163B
H2993 Rev. A
© Nera ASA
EJ163B
1.0 TECHNICAL DATA

IC max: 12mA


Current: nom. 75mA
max. 200mA
This board collects alarms from units located in the
radio rack and combines these into external alarms Alarm Out is in use.
with optocoupler or relay contact outputs. If strap W2 and W3 are on, HBER HOP alarm and
The outputs are wired via Connection Panel, EW52A LBER HOP alarm will be part of the RCVR Group
to a 37-pins D-sub Connector located at the top of the alarm. With strap W4 in pos.2-3, RF ID alarm will
radio rack. On this connector there are also some be part of the Demodulator alarm. With W4 in pos.1-
monitor voltages coming from other units. 2, it will not be part of the Demodulator
alarm.
The board is prepared for a Hot Standby system, and
alarms from other equipment can be taken into the Power Supply Alarm and Main Alarm outputs are
board to take part in the switching logic. relay contacts. For Main Alarm, both the Normally
Open and the Normally Closed contacts are wired to
HOT STANDBY input alarm 2 and 3 have to share the D-sub connector.
Alarm Out. For Power Supply Alarm the Normally Open or
When strap W1 is in pos.1-2, Hot Standby input Normally Closed contact is selected by strap W2.
alarm can be used. When strap W1 is in pos.2-3, the W2 in pos. 1-2 gives Normally Open.
RF-ID W2 in pos. 2-3 gives Normally Closed.
2 H2993
EJ163B

Pin 9: CMI_SPLIT_ALM Collector
Pin 10: CMI_SPLIT_ALM Emitter
Pin 28: GND
Pin 30: GND
Pin 32: GND
Pin 34: GND
Pin 35: MAIN_ALM NO
Pin 37: MAIN_ALM NC
NO= Normally Open, NC= Normally Closed
H2993 3
EJ163B
P1
Fig. 1 Alarm Board, Radio Rack, EJ163B
4 H2993
FILTER & CONNECTION
PANEL BOARD, 48V
EF280A
H2027 Rev. B
© Nera AS
EF280A
1.0 DESCRIPTION 1.2 Functional
1.1 General 1.2.1 Rack Alarms

Relay K1 is related to the rack alarm and is controlled
The board is located at the top of radio racks, and the
by an alarm output from the Alarm Collection Unit
main function is to connect and filter the incoming
(ACU). The relay is normally activated and when
primary supply voltage and distribute this to the
fallback occurs, the primary supply voltage will
power supply units.
provide alarm visualized by a LED at the top of the
All relevant signals and voltages to and from XMTR rack.
Group, Cable Equalizer and Relay Unit are also
routed via this board. 1.2 Section Error/Hop Error
The rack power ON/OFF switch and fuse which are For external supervisory equipment, pulses for sec-
mounted on a bracket are also part of this unit. tion error and hop error monitoring are available on
coaxial connectors at the top of this board.
Fig. 1 Filter & Connection Panel, Board, EF280A
2 H2027
1 C5 1 C8
47nF 47nF
2 2
TB1
1 01 02
+ 1 2 MR752
1 C4 L1
1 C7
48V 2 R1
- G7 50V 680nF 3.9mH 680nF
CON2 1 U 2 2
2 03 04
1 C6 1 C9
47nF 47nF
2 2
F1 1 1
1 1 2 2 CPP
CPP 3 CP2
CP1 5A
S1
SWITCH
SECONDARY PRIMARY
ALARMS XMTR GP. POWER POWER MAIN ALARM
P1 P4 P5 P6 P7
1 GND GND 1 1 1 48V+ 1
2 GND 2 2 2 2
3 RF PWR OUT ALM 21 3 3 1 3
4 GND 22 4 4 R2 4
5 IF INP ALM 23 5 5 1.5k 5
6 GND 24 6 - 15V 6 2 6
7 XMTR LO ALM 25 7 7 7
8 GND 26 8 8 48V- 8
9 XMTR LO VARACTOR VOLT. 27 9 9 9
11 RF PWR OUT LEVEL TO METER 29 11 11 CA10
12 RF PWR OUT LEVEL TO RECORDER 30 12 12
13 XMTR LO LEVEL 31 13 13
14 XMTR LO LEVEL 32 14 + 15V 14
15 - 5V (FET PWR SPLY) 33 15 3M14
16 + 9.4V (FET PWR SPLY) 34 16
17 3 17
18 4 18
19 + 15V TO RELAY (FROM SERVICE RACK) 5 19
21 RELAY CONTROL (NORMALY HIGH) 7 21
22 - 5,2V TO CABLE EQL. & SPLITTER (FROM SERVICE RACK) 1 1N5822 48V+ 8 22 1N916
23 - 5,2V TO CABLE EQL. & SPLITTER (FROM SERVICE RACK) 9 23 1 2
24 + 5V TO CABLE EQL. & SPLITTER (FROM SERVICE RACK) G4 10 24
2
25 DATA INP ALM (SIGN FROM MUX) 11 25 G8
26 RCVR LO-LEVEL 12 26 SMD1005
27 13 27
28
29
RF INP LEVEL, MAIN (TO METER)
RF INP LEVEL, MAIN (TO RECORDER)
1 1N5822 RELAY CABLE EQL. 48V- 14
15
28
29
- 5,2V 10 1 +5V
30 RCVR LO ALM G1 P2 P3 - 15V 16 30 7

2
31 GND 1 1 17 31 8
9
32 DIVERSITY ALM 2 2 + 15V 18 32 4
33 GND 3 3 19 33 3
34 LOW INP LEVEL MAIN, ALM 4 4 + 5V 20 34 2
35 GND 5 5 35 35
2 1N5822 K1
36 LOW INP LEVEL DIVERSITY, ALM 6 6 - 5,2V 36 36
37 GND G2 7 7 37 37
1
38 RF INP LEVEL, DIVERSITY (TO METER) 8 8 38 38
39 RF INP LEVEL, DIVERSITY (TO RECORDER) 9 9 39 39
40 RCVR LO VARACTOR VOLT 10 10 40 40
41 CA10 CA10 3M40 41
42 MAIN ALM OUT,RACK (NORMALY LOW) 42
1
43 43 1
C10 R3
44 44 470nF 1.5k
45 J1 45 2 2
46 SECTION ERROR,OUT COAX 46 + 5V
1
47 2 47
48 HOP ERROR,OUT 1 P6KE12CA 48
1 C1 1 C2 1 C3
49 49 48V+
50 GND G9 1.0uF 1.0uF 1.0uF 50
2 2 2 2
3M50 3M50
J2
COAX 1 1N5822 2 1N5822 2 1N5822
1
2
G3 G5 G6
1 P6KE12CA 2 1 1
G10 + 5V
2
- 5,2V
+ 15V
- 15V
48V+
48V-
MAIN ALM
Document responsible Approved Ref Additional Circuit

NRKO/KR NRKO/KR NL190 Diagrams:
Prepared Subject responsible Code Date Rev
8908 NRUP/EV NRUP/EV EF280A 95-12-20 E
Project Title
FILTER & CONNECTION PANEL BD
Dwg No
ABB ABB Nera AS 1911-S20721
FILTER & CONNECTION
PANEL BOARD, 24V
EF280B
H2075 Rev. A
© Nera AS
EF280B
1.0 DESCRIPTION 1.2 Functional
1.1 General 1.2.1 Rack Alarms

Relay K1 is related to the rack alarm and is controlled
The board is located at the top of radio racks, and the
by an alarm output from the Alarm Collection Unit
main function is to connect and filter the incoming
(ACU). The relay is normally activated and when
primary 24V supply voltage and distribute this to
fallback occurs, the primary supply voltage will
the power supply units.
provide alarm visualized by a LED at the top of the
All relevant signals and voltages to and from XMTR rack.
Group, Cable Equalizer and Relay Unit are also
routed via this board. 1.2 Section Error/Hop Error
The rack power ON/OFF switch and fuse which are For external supervisory equipment, pulses for sec-
mounted on a bracket are also part of this unit. tion error and hop error monitoring are available on
coaxial connectors at the top of this board.
C10
-24V
Fig. 1 Filter & Connection Panel, Board, 24V, EF280B
2 H2075
1 C5 1 C8
47nF 47nF
2 2
TB1
1 01 02
+ 1 2 MR752
1 C4 L1
1 C7
24V 2 R1
- G7 25V 680nF 2.7mH 680nF
CON2 1 U 2 2
2 03 04
1 C6 1 C9
47nF 47nF
2 2
F1 1 1
1 1 2 2 CPP
CPP 3 CP2
CP1 8A
S1
SWITCH
SECONDARY PRIMARY
P1 P4 P5 P6 P7
1 GND GND 1 1 1 24V+ 1
2 GND 2 2 2 2
4 GND 22 4 4 R2 4
5 IF INP ALM 23 5 5 680 5
6 GND 24 6 - 15V 6 2 6
8 GND 26 8 8 24V- 8
14 XMTR LO LEVEL 32 14 + 15V 14
15 - 5V (FET PWR SPLY) 33 15 3M14
16 + 9.4V (FET PWR SPLY) 34 16
17 3 17
18 4 18
21 RELAY CONTROL (NORMALY HIGH) 7 21
22 - 5,2V TO CABLE EQL. & SPLITTER (FROM SERVICE RACK) 1 1N5822 24V+ 8 22 1N916
23 - 5,2V TO CABLE EQL. & SPLITTER (FROM SERVICE RACK) 9 23 1 2
24 + 5V TO CABLE EQL. & SPLITTER (FROM SERVICE RACK) G4 10 24
2
25 DATA INP ALM (SIGN FROM MUX) 11 25 G8
26 RCVR LO-LEVEL 12 26 SMD1005
27 13 27
28
29
RF INP LEVEL, MAIN (TO METER)
RF INP LEVEL, MAIN (TO RECORDER)
1 1N5822 RELAY CABLE EQL. 24V- 14
15
28
29
- 5,2V 10 1 +5V
30 RCVR LO ALM G1 P2 P3 - 15V 16 30 7

2
31 GND 1 1 17 31 8
9
32 DIVERSITY ALM 2 2 + 15V 18 32 4
33 GND 3 3 19 33 3
34 LOW INP LEVEL MAIN, ALM 4 4 + 5V 20 34 2
35 GND 5 5 35 35
2 1N5822 K1
36 LOW INP LEVEL DIVERSITY, ALM 6 6 - 5,2V 36 36
37 GND G2 7 7 37 37
1
38 RF INP LEVEL, DIVERSITY (TO METER) 8 8 38 38
39 RF INP LEVEL, DIVERSITY (TO RECORDER) 9 9 39 39
40 RCVR LO VARACTOR VOLT 10 10 40 40
41 CA10 CA10 3M40 41
42 MAIN ALM OUT,RACK (NORMALY LOW) 42
1
43 43 1
C10 R3
44 44 470nF 680
45 J1 45 2 2
46 SECTION ERROR,OUT 1
COAX 46 + 5V
47 2 47
48 HOP ERROR,OUT 1 P6KE12CA 1 C1 1 C2 1 C3 48
49 49 24V+
50 GND G9 1.0uF 1.0uF 1.0uF 50
2 2 2 2
3M50 3M50
J2
1
COAX 1 1N5822 2 1N5822 2 1N5822
2
G3 G5 G6
1 P6KE12CA 2 1 1
G10 + 5V
2
- 5,2V
+ 15V
- 15V
24V+
24V-
MAIN ALM

NRKO/KR NL192 Diagrams:
9003 NRKO/BD NRUP/EV EF280B 95-01-16 B
Project Title
FILTER & CONNECTION PANEL BD
Dwg No
DISTRIBUTION BOARD
RADIO RACK
EW52A
H2695 Rev.D
© Nera AS
EW52A
1.0 FUNCTIONAL DESCRIPTION
This board is a connection and distribution panel for the 1.1 Setting of Straps and DIL-Switches
radio rack as well as backplane for Alarm Collection A number of straps and DIL-switches are necessary to
Unit and Alarm Board. configure the rack. Depending on terminal or repeater,-
Collection of alarms from Modulator and Demodulator one or two way transmission, 2.048MHz external Sync.
on serial form is controlled by an oscillator circuit or not, 2.048Mb/s wayside traffic or not, - the straps and
located on this board. DIL-switches have to be set as follows:
S1-1: XMTR POWER OUT ALM is disabled when closed

S1-2: XMTR IF INPUT ALM "
S1-3: XMTR LO ALM "
S1-4: CMI SPLITTER INPUT ALM "

S1-5: RCVR LO ALM "
S1-6: RCVR SPACE DIV. ALM "
S1-7: RCVR, MAIN, LOW INPUT ALM "

S1-8: RCVR, SPACE DIV., LOW INPUT ALM "
S2-1: MODULATOR ALM 1-8 "
S2-2: MODULATOR ALM 9-16 "

S2-3: DEMODULATOR ALM 1-8 "
S2-6: WAYSIDE TRAFFIC ALM, DEMOD. is disabled when open. (Open on channels without
wayside traffic).
S2-7: 2.048Mb/s SYNC, DEMOD. is disabled when open. (Sync signal can be tapped
from only two channels, the other channels to be
disabled).
S2-8: 2.048MHz SYNC ALM, MOD. is disabled when open. (All channels to be disabled if
external sync is not used).
S3-1: ADDRESS_1 ACU Setting, See Table

S3-2: ADDRESS_2 ACU "
S3-3: ADDRESS_3 ACU "
S3-4: ADDRESS_4 ACU Closed on TERM. and REP. dir. UP.
Open on REP. dir. DOWN.
CHANNEL
SWITCH
1 2 3 4 5 6 7 PROT.
S3-1 closed open closed open closed open closed open

S3-2 closed closed open open closed closed open open
S3-3 closed closed closed closed open open open open
2 H2695
EW52A
S3-5: WAYSIDE TRAFFIC ALM, MOD. is disabled when closed. (To be closed on channels where
no new wayside traffic shall be inserted.)
S3-6: ENABLE LOF2, DEMODULATOR when switch is open. (Switch to be closed on all channels
where demodulator has no signal input on 4J13).
S3-7: SERIAL COMMUNICATION between SU and ACUs has to be terminated on the last
channel (channel N) where switch has to be closed. (On all other
channels switch shall be open).
S3-8: SECTION ALARMS from Demod. to Modulator to be disabled when open.

S4-1: POWER SUPPLY ALM is disabled when closed.
S4-2: HOT STANDBY IND XMTR 1 is disabled when closed.( Open only in hot standby system).
S4-3: HOT STANDBY IND XMTR2 is disabled when closed. ( Open only in hot standby system).
S4-4: HOT STBY MAN SW LOCK ALM is disabled when closed. ( Open only in hot standby system).
S4-5: DATA OUT ALM is disabled when closed. This alarm occurs if there is a fault
on the cable or the loop connector between demodulator and
relay on rack-top.
S4-6 to 8: Not in use
W1: ATPC-HIGHER, ATPC-LOWER Straps in pos.1-2 and 3-4 on terminals. On repeaters the straps
have to be changed by a cable between DIR. UP and DIR.
DOWN.
W2: Select CMI-INPUT This strap selects CMI-data input (MOD) either on front
connector (J2) or on rear connector (J16). Strap to be removed
on terminal, prot. chan., else in pos. 1-2.
W3: ENABLE-REPEATER Strap to be removed on repeaters to change component values

in 311MHz PLL. Strap has to be in pos. 1-2 on terminals.
W4: SYNC-IND-BIT-DISABLE The sync. ind bit is used to pass sync. information from
Tx-side to Rx-side. This is only used when external sync. is
used. W4 is not used in RS-mode.
Strap in pos 1-2 on terminals to disable incoming sync. ind. bit.
Strap removed on Repeaters to let sync. ind. bit pass through.
W5: VIT-SEC-ERROR Strap in pos. 2-3 on terminals, and 1-2 on repeaters.

W6: Prepared for ATPC (Automatic Transmitter Power Control). Remove strap until
ATPC is implemented. When strap is removed, ATPC is
disabled and output power is fixed.
W7: B2-ERROR-DEMOD-PROT Strap in pos. 1-2 only on terminals, protection channel. On all
other channels, strap has to be removed.
W8: TERMINATION SYNC SIGNAL Strap in pos. 1-2 on the last channel (channel N) to terminate
the 2.048MHz Sync signal. On all other channels, strap has to
be removed.
W9: SYNC SIGNAL SELECTION On receiver side, the Sync signal can be tapped from two
demodulators. Set the double strap in pos. 1-8, 2-7 on one
channel, and pos. 3-6, 4-5 on the other. On all other
channels, strap has to be removed.
H2695 3
EW52A
SK3100728 Fig. 1 Distribution Board, Radio Rack
4 H2695
SPARE:
74HCT4060 74HCT132 74HCT132
R1 2 7 1 74HCT132 9
COMMON FOR MOD/DEMOD

1 2 Q12 Q3 3 9 8
INTERNAL VOLTAGE MON.

3 5 2 10
SERIAL COMMUNICATION
HOT STBY ALM/VOLTAGE

CONN. AT TOP OF RACK)
MAIN ALM&HOT STBY BD
ALARM COLLECTION BD
12k Q13 Q4 10 8
MAIN ALARM BD,RADIO/
(EXTENT.TO 37P D-SUB

10 4
EXT. ALARM/VOLTAGE
C1 RTC Q5 IC3 A 74HCT132 IC4 C
HOT STBY CONTROL

1 2 9 CTC Q6 6 IC3 C 1
14 74HCT132 2 3
Q7 4 74HCT132
POWER SUPPLY
82pF 13 6 12 HEF4066
Q8 C3 5 11 IC4 A
12 15 13 8 9
R2 MR Q9 1 2
11 1 IC3 B 6
1 2 RS Q11 470pF IC3 D 11 10
24k C4
1
74HCT132
IC2 R12 R10 12
1 2 4 1 2
SERVICE RACK XMTR & RCVR MODULATOR DEMODULATOR 560 6 5 IC5 CD
470pF 2 10k
P1 P2 P3 P4 P5 P6 J1 J2 P7 J3 P8 P10 P9 1
560 C5 R13 IC4 B C6
+15V TO RELAY 2 2 2 ALM_SEL_A 1 2 1 2
19,20 1 2 82pF
RELAY CONTROL (norm=H) 3 21 3 3 ALM_SEL_B 3 4 560 2
-5.2V TO CMI SPLITTER 4 4 4 ALM_SEL_C 5 6 470pF
22,23
+5V TO CMI SPLITTER 5 24
XMTRSW_ALM_MOD 7 14 17c 17c REG_CLOCK R4
+15V P1 P3 J1 J2 P7
EN_PROT_MOD 8 17 18a 18a SHIFT_CLOCK GND 1 GND 1 GND 1a GND 1a J2-22b 1
ATPC_ALM 14 29a 1 1
P1-2 2 P3-2 2 GND 1b GND 1b J2-28c 2
ATPC_DIS 29b R14 R15 R16 R17
1 2 1 2 P1-3 3 P3-3 3 GND 1c GND 1c J2-22c 3
ATPC_REFLVL 27 8b 10k 10k
10k 10k 2 2 P1-4 4 P3-4 4 +5.0V 2a +5.0V 2a J2-29a 4
FUSE_ALARM 44 29 HEF4066 P1-5 5 P3-5 5 2b J2-2b 2b J2-23a 5
ATPC_XMTR 10 W6
1 2 2 1 P1-6 6 P3-6 6 +5.0V 2c +5.0V 2c J2-29b 6
3
LBER_SEC_IND 9 19 13 STRAP2 13
3
P1-7 7 P3-7 7 -5.2V 3a -5.2V 3a J2-23b 7
2
EWBER_SEC_IND 10 18 14 1 25 RE_PU_CTRL 2
3 4 Q2 P1-8 8 GND 8 P2-15 3b 3b P7-8 8
RELAY_ALM_DEM 11 15 14 27 18b EN_PU_CTRL Q1
5 2N3904 P1-9 9 P3-9 9 -5.2V 3c -5.2V 3c J2-23c 9
2N3904 1
SYNCL_SEC_ALM/HBER_SEC_ALM/RF_ID_ALM 12 20 16 1
AB IC5 P1-10 10 P3-10 10 4a 4a P7-10 10
EN_PROT_DEM 13 5 20b 20b MOD_ALM 1-8_DIS +5V P1-11 11 P3-11 11 P2-16 4b J2-4b 4b J2-24a 11
CHAN_SEL (REG=L,PROT.=H) 14 17 20c 20c MOD_ALM 9-16_DIS
6 5 4 3 2
1
P1-12 12 GND 12 4c 4c J2-29c 12
R9
ALIGN_IND_DEM 15 18 21a 21a DEMOD__ALM 1-8_DIS P1-13 13 13 -15V 5a -15V 5a J2-24b 13
MS_AIS_INS_DEM 16 20 21b 21b DEMOD_ALM 9-16_DIS P1-14 14 P1-7 14 5b J2-5b 5b J2-30a 14
CMI_INP_SEL 7 W2 21c 21c DEMOD_ALM 17-24_DIS
1 2 P1-15 15 15 -15V 5c -15V 5c J2-24c 15
RMT_RESET_SU_MOD 18 2
10k
STRAP2 P1-16 16 P3-16 16 P2-11 6a J2-6a 6a J2-10b 16
RMT_RESET_SU_DEM 19 19 25c P1-17 17 P1-8 17 P2-28 6b J2-6b 6b J2-25a 17
RMT_RESET_ACU-AAU 22 26a DILSWITCH8 P1-18 18 P1-10 18 P2-38 6c J2-6c 6c GND 18
XMTR_PWR_OUT_ALM 3 10c 10c 1 16 P1-19 19 P1-9 19 P2-13 7a J2-7a 7a J2-25b 19
XMTR_IF_INP_ALM 5 11a 11a 2 15 GND 20 P1-12 20 P2-26 7b J2-7b 7b P2-29 20
XMTR_LO_ALM 7 11b 11b 3 14 P3-21 21 P2-9 7c GND 7c J2-25c 21
XMTR_PWR_OUT_LVL,TO RECORDER 12 28 (33) 7 4 13 3M20
GND 22 P2-40 8a J2-8a 8a GND 22
5 12 P3-23 23 P2-27 8b J2-8b 8b J2-26a 23
W1
ATPC_HIGHER 17 1 2 12 6 11 GND 24 8c J2-8c 8c P2-39 24
ATPC_LOWER 18 3 4 11 10b 16(27) EXT_ALM1_HOT-STBY 7 10 P3-25 25 9a J2-9a 9a J2-26b 25
EN_REP (OPEN ON REP) 16 12 W3 8 9
STRAP4 1 2 P2 GND 26 P6-11 9b J2-9b 9b GND 26
G1 STRAP2 G2 S1 GND 1 P3-27 27 P6-12 9c J2-9c 9c J2-26c 27
CMI SPLITTER_DATA_INP_ALM 6 1 2 25 2 1 11c 11c DILSWITCH8 GND 2 GND 28 P6-7 10a 10a P2-12 28
1 16
2
P2-3 3 P3-29 29 P6-8 10b J2-10b 10b J2-27a 29
2800
2800 2800
G4
RCVR_RF_INP_LVL_MAIN,TO RECORDER 29 20 (29) 3 2 15 GND 4 GND 30 P2-3 10c P2-3 10c GND 30
RCVR_LO_ALM 30 12a 12a 3 14 P2-5 5 P3-31 31 P2-5 11a P2-5 11a J2-27b 31
RCVR_SPACE DIV_ALM 32 12b 12b 4 13 GND 6 GND 32 P2-7 11b P2-7 11b J2-31a 32
1
RCVR_LOW_INP_LVL_ALM,MAIN 34 12c 12c 5 12 P2-7 7 P3-33 33 J1-11c 11c J1-11c 11c J2-27c 33
RCVR_LOW_INP_LVL_ALM,SPACE DIV. 36 13a 13a 6 11 GND 8 GND 34 P2-30 12a P2-30 12a J2-31b 34
RCVR_RF_INP_LVL_SPACE DIV.,TO RECORDER 39 24 (31) 5 7 10 P2-9 9 P2-32 12b P2-32 12b J2-28a 35
MAIN_ALM,RACK (norm.L) 42 27a R3 8 9 3M34
1 2 +5V P2-10 10 P2-34 12c P2-34 12c J2-31c 36
B2_ERR_SEC_OUT 46 26c S2 P2-11 11 P4 P2-36 13a P2-36 13a J2-28b 37
5 1 560
B1_ERR_HOP_OUT 48 26b 2 IC1 P2-12 12 GND 1 P3-5 13b P3-5 13b GND 38
ENABLE_LOF2_DEM 7 G3 P3-2 2
1N4761 MOC805 74HCT132 P2-13 13 P3-6 13c P3-6 13c GND 39
PROT. SW. STATUS (C) 8 (23) 1 12 P2-14 14 P3-3 3 P4-5 14a P4-5 14a GND 40
PROT. SW. STATUS (E) 10 (24) 4 6 2 11 P3-4 4
13 P2-15 15 P4-6 14b P4-6 14b 3M40
DILSWITCH8 P2-16 16 P4-5 5 P4-7 14c P4-7 14c
ADDR_1 ACU 29c IC4 D 1 16 P2-17 17 P4-6 6 J1-15a 15a J1-15a 15a
ADDR_2 ACU 30a 2 15 P2-18 18 P4-7 7 J1-15b 15b J1-15b 15b
ADDR_3 ACU 30b 3 14 P1-2 19 GND 8 J1-15c 15c J1-15c 15c J3
ADDR_4 ACU 30c 4 13 P1-2 20 P4-9 9 J1-16a 16a J1-16a 16a J3-1 1
ADDR_5 ACU 31a 5 12 P1-3 21 P4-10 10 J1-16b 16b J1-16b 16b J3-2 2
MOD ALARM 1-8 5 13b 13b 6 11 P1-4 22 P4-11 11 J1-16c 16c J1-16c 16c P2-29 3
MOD ALARM 9-16 6 13c 13c 7 10 P1-4 23 P3-16 12 J1-17a 17a J1-17a 17a J3-4 4
2M_SYNC_MOD+ 9 3 R5 8 9 P1-9 13 P2-39 5
1 2 P1-5 24 J1-17b 17b J1-17b 17b
2M-SYNC_MOD- 10 4 110 S3 P2-25 25 P1-10 14 J1-17c 17c J1-17c 17c J3-6 6
2M_SYNC_MOD_DIS 11 P2-26 26 P1-11 15 J1-18a 18a J1-18a 18a P2-12 7
B1_ERR_MOD 23 22b 1
W8
2 P2-27 27 P1-12 16 P5-14 18b J2-18b 18b P2-15 8
B2_ERR_MOD 25 22c P9 P1-14 17 P2-16 9
STRAP2 P2-28 28 18c J2-18c 18c
DIS_WAY_MOD 13 +5V GND 1 P1-15 18
GND 2 P2-29 29 19a 19a CA9
SEC_ALM_DIS 29 P1-19 19
6 5 4 3 2
1
3 P2-30 30 19b 19b
R6
DEMOD ALM 1-8 5 14a 14a GND 31 P1-16 20 19c 19c
DEMOD ALM 9-16 6 14b 14b 4 P4-21 21
5 P2-32 32 P3-21 20a 20a P8
10K
DEMOD ALM 17-24 7 14c 14c GND 33 GND 22 J1-20b 20b J1-20b 20b
2M_SYNC_DEMOD+ 9 -15V 6 P4-23 23 GND 1
GND 7 P2-34 34 J1-20c 20c J1-20c 20c J2-2b 2
2M_SYNC_DEMOD- 10 GND 35 GND 24 J1-21a 21a J1-21a 21a
2M_SYNC_DEM_DIS 11 GND 8 P4-25 25 J2-4b 3
9 P2-36 36 J1-21b 21b J1-21b 21b J2-5b 4
DIS_WAY_DEM 6 GND 37 GND 26 J1-21c 21c J1-21c 21c
RMT_RESET-DEM 8 27b 2b 2 +5V HOT_STBY 10 P3-27 27 J2-8a 5
11 P2-38 38 GND 22a GND 22a J2-8b 6
4
3
2
1
ATPC_CTRL1 10 27c 4b 3 +15V HOT_STBY P2-39 39 GND 28 P3-23 22b J2-22b 22b
STRAP8
W9
ATPC_CTRL2 9 28a 5b 4 -15V HOT_STBY 1 12 P4-29 29 J2-8c 7
R8 13 P2-40 40 P3-25 22c J2-22c 22c J2-9a 8
PJE_DEM 21 23a 8a 5 HOT_STBY_ALM1 P1-17 41 GND 30 P4-21 23a J2-23a 23a
B1_ERR_DEM 23 23b 8b 6 HOT_STBY_ALM2 110 +15V 14 P4-31 31 J2-9b 9
P2-42 42 P4-23 23b J2-23b 23b
5
6
7
8
2 GND 15 J2-9c 10
B2_ERR_DEM_REG 25 23c 8c 7 HOT_STBY_ALM3 GND 43 GND 32 P4-25 23c J2-23c 23c
B2_ERR_DEM_PROT W7 23 24a 9a 8 HOT_STBY_ALM4 P9-16 16 P4-33 33 11
1 2 P2-44 44 P6-23 24a J2-24a 24a
SYNC_IND_EN 31 W4 9b 9 HOT_STBY_ALM5 17 GND 34 12
1 2 STRAP2 GND 45 P3-27 24b J2-24b 24b
B3_ERR_DEM 27 27 24b 9c 10 HOT_STBY_ALM6 18 J2-18b 13
STRAP2 10K P2-46 46 3M34 P4-29 24c J2-24c 24c
G1_ERR_DEM 29 24c 1 MONITOR -15V 1 2 19 J2-18c 14
20 GND 47 P6 P4-31 25a J2-25a 25a
VIT_HOP_ERR 31 25a 2 MONITOR +15V 3 4 P2-48 48 P4-33 25b J2-25b 25b 3M14
VIT_SEC_ERR 33 W5 33 25b 4 MONITOR -5.2V 5 6 21 GND 1
2 1 GND 49 P1-14 25c J2-25c 25c
6 MONITOR +5V 7 8 22 GND 2
3 GND 50 P6-22 26a J2-26a 26a
SERIES COMM ACU RXD+ 11 9b 18b 13 HOT_STBY_ALM7 9 10 23 P3-9 3
STRAP3 P2-48 26b J2-26b 26b P10
SERIES COMM ACU RXD- 12 9c 18c 14 HOT_STBY_ALM8 24 3M50 P3-10 4
R7 25 GND 5 P2-46 26c J2-26c 26c J2-6a 1
SERIES COMM ACU TXD+ 7 10a P2-42 27a J2-27a 27a J2-6b 2
SERIES COMM ACU TXD- 8 10b 26 GND 6
27 P6-7 7 P5-8 27b J2-27b 27b J2-6c 3
2M_SYNC_DEM_CHAN A+ 15 P5-10 27c J2-27c 27c GND 4
2M_SYNC_DEM_CHAN A- 16 -5.2V 28 P6-8 8
GND 29 P5 GND 9 P5-9 28a J2-28a 28a J2-7a 5
2M_SYNC_DEM_CHAN B+ 19 P5-1 1 J1-28b 28b J2-28b 28b J2-7b 6
2M_SYNC_DEM_CHAN B- 20 GND 30 GND 10
J1-15a 31 P1-18 2 P6-11 11 J1-28c 28c J2-28c 28c 7
POWER SUPPLY -15V 5a,c 5a,c 3-6 3 P2-14 29a J2-29a 29a 8
POWER SUPPLY +15V 4a,c 4a,c 9-14 32 P6-12 12
33 4 GND 13 J1-29b 29b J2-29b 29b 9
POWER SUPPLY -5.2V 3a,c 3a,c 17-28 P1-13 5 J1-29c 29c J2-29c 29c 10
POWER SUPPLY +5.0V GND (SEE CONNECTOR SYMB) 2a,c 2a,c 33-46 34 GND 14
35 P5-6 6 P6-15 15 J1-30a 30a J2-30a 30a 3M10
RMT_CTRL1_HOT-STBY 28b 30b 16 ATPC_XMTR P5-7 7 J1-30b 30b J1-28b 30b
RMT_CTRL2_HOT-STBY 28c 30c 36 P6-16 16
DILSWITCH8 P5-8 8 J1-30c 30c J1-28c 30c
PWR_SPLY_ALM 15a 15a 31 1 16 +5.0V 37 GND 17
38 P5-9 9 GND 18 GND 31a J2-31a 31a
HOT_STBY_IND_XMTR1 15b 15b 2 15 P5-10 10 31b J2-31b 31b
1 39 P6-19 19
HOT_STBY_IND_XMTR2 15c 15c 3 14 L1 P5-11 11 31c J2-31c 31c
HOT_STBY_MAN_SW_LOCK_ALM 16a 16a 4 13 40 P6-20 20
4.7 41 P5-12 12 GND 21 GND 32a GND 32a
RELAY DATA_OUT_ALM 17 41 2 1 16b 16b 5 12 uH P5-13 13 GND 32b GND 32b
SPARE, ALM G5 2800 16c 16c 6 11 42 P6-22 22
2 P5-14 14 GND 32c GND 32c
SPARE, ALM 17a 17a 7 10 +5V 43 P6-23 23
SPARE, ALM 17b 17b 8 9 44 3M14 GND 24 EU96 EU96
PJE_MOD 21 20a 1 45 P5-1 25
S4 + C2
XMTR_LO_VARACTOR_VOLT 9 7c 46 GND 26
220uF GND 47 P5-14 27
XMTR_PWR_OUT_LVL,TO METER 11 6a 6a 1 HOT_STBY,RF-SWITCH_CTRL_CH1 2
XMTR_LO_LVL 13 7a 6b 2 HOT_STBY,RF-SWITCH_CTRL_CH2 GND 48 GND 28
XMTR_PWR_SPLY -5V 15 3b 8 GND 49 P2-44 29
XMTR_PWR_SPLY +9,4V 16 4b 9 GND 50 GND 30
RCVR_LO_LVL 26 7b 6c 3 HOT_STBY,RF-SWITCH_COM -15V 3M50 3M30
RCVR_RF_INP_LVL_MAIN,TO METER 28 6b 7a 5 HOT_STBY,RF-SWITCH_IND_CH1
RCVR_RF_INP_LVL_SPACE DIV.,TO METER 38 6c 7b 6 HOT_STBY,RF-SWITCH_IND_CH2
RCVR_LO_VARACTOR_VOLT 40 8a 7c 4 HOT_STBY,RF-SWITCH_IND_COM(GND)
EXTERNAL, XMTR GROUP ALM (C;E) 22b;22c 1;3 (1;2)
EXTERNAL, RCVR GROUP ALM (C;E) 23a;23b 5;7 (3;4) +5V +15V Document responsible Approved Ref Additional Circuit
EXTERNAL, MOD_ALM (C;E) 23c;24a 9;11 (5;6) 16 14 14 14 NRKO/KR Diagrams:
EXTERNAL, DEMOD_ALM (C;E) 24b;24c 13;15 (7;8) 1 1 1 1
IC2 C7 IC3 C8 IC4 C9 IC5 C10 Prepared Subject responsible Code Date Rev
EXTERNAL, CMI SPLIT_ALM (C;E) 25a;25b 17;19 (9;10)
EXTERNAL, HBER_SEC_ALM (C;E) 25c;26a 21;23 (11;12) 2
10nF
2
10nF
2
10nF
2
10nF
9501 RRS/EV RRS/EV EW52A 95.02.15 B
EXTERNAL, LBER_SEC_IND (C;E) 26b;26c 25;27 (13;14) 8 7 GND 7 7
EXTERNAL, RF_ID_ALM (C;E)/HOT_STBY (EXT_ALM2;EXT_ALM3) 27a;27b 29;31 (15;16)
Project Title
EXTERNAL, PWR_SPLY_ALM (CENTRE;NO/NC) 27c;28a 33;35 (17;18) BOTTOM VIEW
EXTERNAL, AIS_XMTR_ALM (C;E) 28b;28c 37;2 (19;20) 6 4 14 8 16 9 SDH-RADIO DISTRIBUTION BD RADIO RACK
3 C
EXTERNAL, AIS_RCVR_ALM (C;E) 29a;29b 4;6 (21;22) E
EXTERNAL, 2M_WAY_ALM (C;E) 29c;30a 12;14 (25;26) B B
EXTERNAL, MAIN RACK ALM (NORMALY OPEN) 31a 32 (35) 2 1 3 1 7 1 8
C Dwg No
EXTERNAL, MAIN RACK ALM (CENTRE)
EXTERNAL, MAIN RACK ALM (NORMALY CLOSED)
31b
31c
34 (36)
36 (37)
1 E
2N3904
MOC805 74HCT132
HEF4066
HCT4060
XMTR SWITCH UNIT
2SN218A
H2788 Rev. A
© Nera AS
2SN218A
TABLE OF CONTENTS
Page
1 General 3
1.1 Block Schematic Diagram 3
2 Data in and out 4
2.1 Inputs from modulators 4

2.2 Inputs from CMI-splitters 4
2.3 CMI output to protection channel 4
3 Control of the XSU 4
3.1 Control signals from RPS 4

3.2 Power-on configuration 4
3.3 Status control 5
4 The different functions 6
4.1 Xmtr relay switch 6

4.2 Cable equalizer and splitter 6
4.3 140 Mb/s to STM-1 converter 6
4.4 Xmtr hitless switch 6
4.5 Xmtr switch status ind. 6
5 Xmtrsw UNIT ALARM 6
6 AIS insertion 6
2 H2788
2SN218A
1 General
The Xmtr Switch Unit (XSU) executes the orders Signals to be transmitted can be selected from one of
from Radio Protection Switching (RPS) according to the modulators (hitless switching) or from one of the
which signal being transmitted on protection chan- CMI-splitter units (relay switching).
nel.
Fig.1.1 Block Schematic Diagram of the

XSU:
8J11 to 8J17
ch1
CMI in ch2 CMI driver 8J18
(ECL from
modulators) 8-1 MUX CMI OUT
(to protection
ch7
OUT alm modulator)
ch0
Channel
HITless 3 on prot. 3
SWitch
Status
8J1 to 8J8
chp ch0
ch1 CABLE 2/1
CMI in EQUAL MUX
8
(from CMI splitter) & 140/155
RELAYS
SPLIT. CONVERTER
ch7
SEL 140 XSU
3 Converter Alm
Channel
RElay 3 3 on relay
SWich
Status
STATUS LATCHING AND

STATUS READBACK
UNIT ALM
(red)
3 3
SEL 140 MB/s

(yellow)
Control signals from RPS
Status readback to RPS
AIS INP
(yellow)
H2788
3
2SN218A
2 Data in and out 3 Control of the XSU
2.1 Inputs from modulators 3.1 Control signals from RPS

The inputs from the modulators are located on the The control signals from the RPS are latched through
back of the unit (8J11 to 8J17). a standard interface so that the XSU keep its status if
the RPS is removed or reset.
Data rate :155.52 Mb/s (STM-1) The actual status of the XSU can be read from the
Line Code : CMI RPS through the same interface.
Data format : ECL, 0.9 ±0.2Vpp
Impedance : 75 ohm, termin. to -2V 3.2 Power-on configuration
At power on, the XSU choses the following
2.2 Inputs from CMI-splitters default configuration:
The inputs from the CMI-splitters are located on
the front of the unit (8J1 to 8J8). Hitless switch on ch1
Relay switch on ch0
Date rate : 155.52 Mb/s(STM-1) or This means that ch1 is hitless on protection
140 Mb/s (PDH) channel.
Line code : CMI In addition, there is a possibility to chose power on
Impedance : 75 ohm unbalanced configuration for the 140 to 155 converter.
Return loss : >15dB, 7 to 240 MHz
Pulse amplit. (nom) : 1V ±0.1V
Max. attn. of inp.sign. : 12.7dB at 78 MHz S701.1 S701.2 Power ON configuration
(STM-1) or 12dB at
70 MHz (PDH) CLOSED OPEN Converter activated
OPEN CLOSED Converter deactivated
2.3 CMI output to protection channel CLOSED CLOSED Undefined
The output to the chp modulator is located on the OPEN OPEN Undefined
back of the unit (8J18).
Data rate : 155.52 Mb/s (STM-1)

Line code : CMI
Impedance : 75 ohm unbalanced
Pulse amplitude : 1V pp ±0.2V
4 H2788
2SN218A
3.3 Status control
The XSU status depends on control signals from

the RPS.
Table 3.3.1 gives an overview of the control
possibilities.
H = High, L= Low, X= no significance
REL A REL B REL C SW A SW B SWC Status

X X X H L L CH1 hitless on prot
X X X L H L CH2 hitless on prot
X X X H H L CH3 hitless on prot
X X X L L H CH4 hitless on prot

X X X H L H CH5 hitless on prot
X X X L H H CH6 hitless on prot
X X X H H H CH7 hitless on prot

L L L L L L Occasional traffic on prot
H L L L L L CH1 relay on prot
L H L L L L CH2 relay on prot

H H L L L L CH3 relay on prot
L L H L L L CH4 relay on prot
H L H L L L CH5 relay on prot

L H H L L L CH6 relay on prot
H H H L L L CH7 relay on prot
Table 3.3.1: The different XSU states.

In addition, the control signal SEL_140 = high, activates the converter from 140 (PDH) to 155 (STM-1) for
signals coming through the relays. Similarly, SEL_140 = low deactivates the converter.
H2788
5
2SN218A
4 The different functions if the converter is activated.

A yellow LED labelled "AIS INP" illuminates if the
Reference is made to the Block Schematic converter is active and there is AIS in incoming
Diagram. 140 Mb data.
A red LED labelled "UNIT ALM" illuminates when
4.1 Xmtr relay switch there is unit alm (see chapter 5).
The xmtr relay switch consists of eight solid state
relays in a "star" coupling where only one relay is
active at a time. The unused signals are grounded. 5 Xmtr sw Unit Alarm
This unit has only one alarm, "UNIT ALM".
4.2 Cable equalizer and splitter If the converter is not activated:
Performs equalization to compensate for cable losses UNIT ALM = CMI OUT ALM.
according to specifications. If the converter is activated:
It also splits the signal to "2 to 1 multiplexer" and to UNIT ALM = CMI OUT ALM + INP ALM CONV
the "140 / 150" converter. + PLL ALM CONV.
4.3 140 Mb/s to STM-1 converter

6 AIS insertion
When the control signal "SEL_140" goes high, the
power to the 311 MHz vcxo is turned on and the If the converter is active and an inp alm to the
converter becomes active. converter is detected, AIS data is inserted in the
140Mb data mapped into the STM-1 frame in IC406.
The rcvr part in IC405 "CMI CODEC", recovers data
and clk from the incoming 140 Mb/s CMI signal. It
also splits data into four times 35 Mb/s.
In IC406 "C4-MUX", STM-1 frame is generated and
maps 140 Mb data into it.
IC407 "STM-1" is used for scrambling and freq.
control of 311 MHz vcxo.
Finally, the transmit part of IC405 "CMI CODEC"
multiplexes four times 39 Mb/s to 155 Mb/s and
performs CMI coding.
4.4 Xmtr hitless switch

This is an ECL 8 to 1 MUX that either choses one of
the signals from the modulators in ch1 to ch7, or the
signal from the relays.
It also contains a CMI driver (with an output alarm),
sending the chosen signal to chp modulator.
4.5 Xmtr switch status ind.

Two seven-segment LED indicators, indicates the
positions on xmtr hitless switch and xmtr relay switch.
A yellow LED, labelled "SEL 140 Mb/s", illuminates
6 H2788
RCVR DATA DISTRIBUTION
2GN395A
H2806 Rev. A
© Nera AS
2GN395A
TABLE OF CONTENTS
Page:
1 TECHNICAL DATA 3
1.1 Data Connections 3
1.2 Indicators 3
2 GENERAL DESCRIPTION 4
H2806
2
2GN395A
1 TECHNICAL DATA
1.1 General:
Inputs:
DATA INPut (CMI) (J2) : Data 155.520 Mb/s CMI/1V, 75ohm (G.703)
From prot - demodulator.
DATA INPut (CMI-ECL) (J11) : Data 155.520 Mb/s CMI_ECL, 75ohm /-2V.
From prot - demodulator.
Outputs:
DATA OUTput (CMI) (J1) : Data 139.264 or 155.520 Mb/s CMI/1V,
75ohm, G.703. (Unprio traffic).
DATA OUTputs (CMI-ECL) (J12-J18) : Data 155.520 Mb/s CMI-ECL, 75ohm /-2V
(Split data from J11)
For Prot Input on regular Demodulators.
1.2 Indicators:
Name: Descriptions: Comments:

UNIT_ALM DATA_INP_ALM+CONV_ALM Red LED on unit front
(CONV_ALM= LOF1
+C4 LOP
+278M_PLL_ALM)
AIS 140 Mb/s Indicates AIS on 140 Mb/s output Yellow LED on unit front
SEL 140 Mb/s Indicates that the STM-1 to 140 Mb/s

converter is active Yellow LED on unit front

+5.0V / 310mA
-5.2V / 700mA
+15.0V / 50mA
H2806
3
2GN395A
The RCVR Data Distribution (RDU) located on the At regular intervals the RPS reads the status of the
receiver side, distributes the protection channel to all RDU to ensure correct output.
7 regular channels and protection channel for occa-
sional traffic. The RPS can via control signals select A block diagram of the main functions of the unit is
if the protection channel output shall be 140 Mb/s or shown in Fig.1.
155 Mb/s and in addition disable the output. The unit is built on one circuit board and mounted in
a box as shown in Fig.2.
INP
Data inp alm
DET
CH 1
CH 2 DATA OUT
DATA INP 155 Mb/s
CH 3
155 Mb/s, CMI-ECL SPLITTER CMI-ECL
& CH 4
To PROT INPUTS
CH 5
FROM PROT-DEMOD LINE on DEMODULATORS
CH 6
DRIVERS CH 7
Relay-1 Relay-2
DATA INP
UNPRIO
155 Mb/s, CMI, G.703
TRAFFIC
CMI/, G.703
FROM PROT-DEMOD 140/155 Mb/
DIS. UNPRIO. RDU SEL_140_RDU

( FROM RPS ) ( FROM RPS )
STM-1 TO 140 Mb/s CONVERTER
C4- CMI- CMI-

STM-1
DEMUX CODEC DRIVER
PROC
G.703
PLL ALM CONVERTER

278M CKTS ALARM
Figure 1: Main Functions of the RCVR Data Distribution Unit
H2806
4
2GN395A
INPUT DETECTOR
SPLITTER & LINE DRIVERS 9J11
9J12
9J1
RELAY - 2 9J13
9J14
RELAY - 1
9J15
CMI - DRIVER 9J16
9J2
9J17
CMI CODEC
9J18
PLL w/ VCXO 278MHz 9P1
STM-1 PROCESSING
C4 - DEMUX
STM-1 TO 140Mb/s
CONVERTER
9H1 9P1
ALARM CIRCUITS
9H3
9H2
RPS INTERFACE
Figure 2: Unit Board Diagram
H2806
5
2GN395A
3.1 Main Functions: 3.2 Other Functions:
A brief description of the main functions of the

The RCVR Data Distribution also includes
RCVR Data Distribution is given here:
different control and alarm circuits.
· SPLITTER & LINE DRIVERS:
· RPS STATUS LATCH & READ:
The CMI-ECL input data signal from the Protection
This is the interface circuits for the RPS-control
channel Demodulator is here split and distributed to 7
signals.
CMI-ECL outputs and to the STM-1 TO 140 Mb/s
EN_PU_CTRL : Latch-enable signal
CONVERTER.
RD_PU_CTRL : Read back signal
DIS-UNPRIO-RDU : Relay-operation and
AIS-140 Mb/s insert.
· INPUT DETECTOR:
SEL_140_RDU : Selects 140 Mb/s or 155
Mb/s output.
This detector gives Data Input alarm by loss of CMI-
ECL input data.
· Distribution Unit Alarm:
· STM-1 TO 140 Mb/s CONVERTER:
DISTR UNIT ALM = DATA INP ALM +
CONVerter ALM
155 Mb/s CMI-ECL data from the SPLITTER-block
This is an external alarm with open collector
is fed to the CMI-CODEC, which main functions are
output. High impedance when power is off. The
CMI-data decoding, clock recovery, split and
CONV ALM is turned off when 140 Mb/s output is
converting of the data signal prepared for CMOS-
not selected.
technology.
The STM-1 PROCESSOR performs frame
synchronization and descrambling.
· Converter Alarm:
The C4-DEMUX is used to map out the 139.264
Mb/s of the STM-1-frame.
CON_ALM= LOF 1 (Loss of frame,STM-1)
A PLL with a 278 Mhz VCXO generates the clock for
+C4_LOP (Loss of pointer,
the 139.264 Mb/s outmapping.
C4-DEMUX)
The CMI-CODEC also provides combining and CMI- +278_PLL_ALM (PLL out of Lock)
encoding of the data coming from the C4-DEMUX.
The CMI-data signal is then applied to a CMI-driver
before the output relay. * AIS Insert Control 140 Mb/s:
AIS_INS= DATA INP ALM (INPUT DET.)

· RELAY-1 and RELAY 2: +MS_AIS_R (STM-1 PROC)
+C4_LOP (C4-DEMUX)
These relays are used to select CMI-output data 155 +C4_PATH_AIS (C4-DEMUX)
Mb/s or 140 Mb/s. +DIS_UNPRIO (RPS)
H2806
6
ADAPTER, 64Kb/s
2N507A
H2823 Rev. D
© Nera AS
2N507A
1 ADAPTER, 64kb/s, 2N507A:
This adapter is designed to access bytes in SOH or POH. 64kb/s CH1
The adapter may access two bytes, each presented as
one 64kb/s channel at connector J1 in front.
Reference is made to Chapter 4 -CONFIGURATION- V11 or
point 1.1.1 in the Operator's Manual for information G703
about access to SOH through 2.048Mb/s buses in CH2
NL290 equipment. 64kb/s
The 64kb/s interface may be configured as V11, G703
contradirectional or G703 codirectional. In G703 codi- 2N507A
rectional configuration, adjustment between internal
datarate and applied datarate will be done by
SOH - buses
"byteslips".
Figure 1 to/from
TABLE for J1: Modem units
Connector J1 Signal Connections: 2 CONFIGURATION OF 64kb/s

1 TxD- INTERFACE TIMESLOTS:
2 TxD+
3 TxC+ Setting of each 64kb/s interface can be done independ-
4 TxC- Ch 1, G703 ently. The only limitation is that both bytes have to be at
5 RxD+
the same bus and data line.
6 RxD- Configuration of the two 64kb/s channels is done by
7 RxC+ switch S301 (CH1) and S302 (CH2).
8 RxC-
9 TxD-
10 TxD+ Switches 1-5 select timeslot to access
Switch 6 enable/disable output to 2Mb/s bus
11 TxC+
12 TxC-
Switches 7-8 select 64kb/s interface G703 or V11
Ch 2, G703
13 RxD+
14 RxD- See Table 2 and Table 3 for setup.
15 RxC+
16 RxC- If the adapter is used to access data in only one direction,

17 TxD- S201 can be used to disable alarms.
18 TxD+
19 TxC-
20 TxC+ S201-1 OFF Alarm for XMTR data disabled
Ch 1, V11
S201-2 OFF Alarm for RCVR data disabled
21 RxD-
22 RxD+
S201 Normally closed.
23 RxC-
24 RxC+ For test purposes it is possible to loop back 64kb/s
25 TxD-
DATA.
26 TxD+
27 TxC- S303-1 ON Loopback of Ch1
28 TxC+
29 RxD- Ch 2, V11 S303-2 ON Loopback of Ch2
30 RxD+ S303 Normally open.
31 RxC- S30x no ON OFF

32 RxC+ 8 CONTRADIR CODIR
33 BYTE1-
34 BYTE1+ V11, Rx
7 V11 G703
35 BYTE- 6 ENABLE DISABLE
36 BYTE+ V11, Tx
37 GND Table 1 Table 2
2 H2823
2N507A
S 30x no SOH- bytes SVCH POH

TIMESLOT 5 4 3 2 1 data1 data2 bus bus
0 x)
1 OFF OFF OFF OFF ON C1 1-8 S1
2 OFF OFF OFF ON OFF MS2 1-9 Z1#2 C2
3 OFF OFF OFF ON ON E1 2-8 Z1#3 B3
4 OFF OFF ON OFF OFF 2-5 2-9 Z2#1

5 OFF OFF ON OFF ON 2-6 3-8 Z2#2
6 OFF OFF ON ON OFF F1 3-9 M1 G1
7 OFF OFF ON ON ON D1 5-5 E2 Z3

8 OFF ON OFF OFF OFF 3-3 5-6 E1
9 OFF ON OFF OFF ON D2 5-8 2-5 Z4
10 OFF ON OFF ON OFF 3-5 5-9 2-6

11 OFF ON OFF ON ON 3-6 6-2 F1
12 OFF ON ON OFF OFF D3 6-3 3-3 Z5
13 OFF ON ON OFF ON K1 6-5 3-5 J1

14 OFF ON ON ON OFF K2 6-6 3-6 F2
15 OFF ON ON ON ON D4 6-8
16 x)
17 ON OFF OFF OFF ON D5 6-9 S1
18 ON OFF OFF ON OFF D6 7-2 Z1#2
19 ON OFF OFF ON ON D7 7-3 Z1#3

20 ON OFF ON OFF OFF D8 7-5 Z2#1
21 ON OFF ON OFF ON D9 7-6 Z2#2
22 ON OFF ON ON OFF D10 7-8 M1 H4

23 ON OFF ON ON ON D11 7-9 E2
24 ON ON OFF OFF OFF D12 8-2 E1
25 ON ON OFF OFF ON S1 8-3 2-5

26 ON ON OFF ON OFF Z1#2 8-5 2-6
27 ON ON OFF ON ON Z1#3 8-6 F1
28 ON ON ON OFF OFF Z2#1 8-8 3-3

29 ON ON ON OFF ON Z2#2 8-9 3-5
30 ON ON ON ON OFF M1 9-8 3-6
31 ON ON ON ON ON E2 9-9
x) Timeslots 0 and 16 are not allowed.
At terminals, SVCH-bus timeslots 17-30 are normally used.

At repeaters, SVCH-bus timeslots 1-15 are used towards lower stations,
and timeslots 17-30 are used towards higher stations.
Table 3
H2823 3
2N507A
REPEATER DIRECTION UP
DEMODULATOR MODULATOR
IF IN IF OUT
BUS 3 Omni &

BUS 1
Express
telephone
SVCH BUS
64 kb/s MSOH RSOH
adapters adapter adapter
64 kb/s
adapters
BUS 3 BUS 1
IF IN
IF OUT
MODULATOR DEMODULATOR
REPEATER DIRECTION DOWN
Figure 2: Access to SOH by 2Mb/s buses at Repeater.
MODULATOR
STM1 IN POH IF OUT
BUS 3 Omni &

BUS 1 Express
telephone
SVCH BUS
64 kb/s MSOH RSOH
adapters adapter adapter
64 kb/s
adapters
BUS 3 BUS 2 BUS 1
ALIGNMENT IF IN
POH SWITCH
STM1 OUT
DEMODULATOR
FROM PROT. CH.
Figure 3: Access to SOH & POH by 2Mb/s buses at Terminal.
4 H2823
2N507A
3 SETUP FOR ACCESS TO SOH
BUSES:
When placed at Connection Panel Adapter UWB310, Each bus has two datalines.
access to SOH bytes is done directly to the SOH buses
for radio channel no.1. The adapter can access two of Selection between bus 1 and bus 2 is done at Connection
five buses available. Bus 1 and 3 to/from modulator and Panel Adapter UWB310.
bus 1, 2 and 3 to/from demodulator.
At repeater only bus 1 from demodulator and bus 3 to To select which buses and datalines to access, several
modulator in both directions are available. possible settings of W501 - W504 are available:
Ref. Figures 2 and 3. Ref. Figure 4.
Placing of straps W501-W504 ( 12 U-links)
is marked by shadows
W501 W502
W503 W504
Data 1 Data 2 Data 1 Data 2

Bus3 Dir UP Bus3 Dir UP Bus3 Dir DOWN Bus3 Dir DOWN
Bus1 Dir DOWN Bus1 Dir DOWN Bus1 Dir UP Bus1 Dir UP
Access to "upper" station at repeater Access to "lower" station at repeater

and "radio side" at terminal and "customer side" at terminal
Figure 4 Data 1 Data 2 Data 1 Data 2

Access to Direction UP at repeater Access to Direction DOWN at repeate
H2823 5
2N507A
4 SETUP FOR ACCESS TO

SVCH BUS:
When placed at Distribution Board EW53A next to the Therefore it is possible that the clockrate differs at two
RSOH-adapter, access to SOH bytes is done at SVCH- different stations. To compensate for this there will be
bus. "byte-slips" at 64kb/s data at the adapters.
W501-W504 must be placed according to Fig. 5.
Placing of straps (12 U-links)
Each 64kb/s channel will then have a 1+1 protection is marked by shadows
both on terminals and repeaters through the RSOH
adapter. W501 W502
Clock rate of this bus is normally controlled from bus1
at modulator CH1, but if this bus is missing, the clock
rate will be controlled by the next bus, as shown in the
table:
Priority Bus Channel Direction
1 BUS1 CH1 UP
2 BUS1 Protection UP
3 BUS3 CH1 UP
4 BUS3 Protection UP
CABLE
UWML2710
5 BUS1 CH1 DOWN

6 BUS1 Protection DOWN
7 BUS3 CH1 DOWN
8 BUS3 Protection DOWN
PRIORITY FOR CLOCKRATE AT SVCH-BUS
Table 4
W503 W504
Figure 5
6 H2823
2N507A
5 SETUP FOR ACCESS TO
POH:
At terminals with PDH setup (140Mb/s) it is possible to Placing of straps ( 12 U-links)

access POH through the adapter. This is done by chang- is marked by shadows
ing bus 1 from modulator and bus 3 to demodulator to
carry POH instead of SOH. By doing this, bus 1 with W501 W502
SOH-data from modulator will change to transmit
POH-data to modulator and bus 3 with SOH-data to
demodulator will change to transmit POH-data from
demodulator. To do this, it is necessary to change setup
at several units and W501-W504 must be placed accord-
ing to Fig.6.
The adapters are placed at Connection Panel Adapter,
UWB310.
Setup for POH access:
Modulator 8MNF83A W403-W406 pos. 1-2

Demodulator 2DNF129A W701, W702 pos. 2-3
W704, W705 pos. 1-2
Dist.board EW53A W1-W4 off
Conn.panel UWB310 W1 off
W4 on W503 W504
Setup for SOH access: Figure 6
Modulator 8MNF83A W403-W406 pos. 2-3

Bytes B3 and G1 are always generated internally in the
Demodulator 2DNF129A W701, W702 pos. 1-2
W704, W705 pos. 2-3 modulator, and are only readable through the adapter.
Dist.board EW53A W1-W4 off
Conn.panel UWB310 W1 on To be able to insert byte C2, switch S501-2 at
W4 off modulator 8MNF83A must be set correctly.
Table 5
H2823 7
ADAPTER, RSOH
2N506A
H2606 Rev. B
© Nera AS
2N506A
At a repeater station, ADAPTER RSOH will take

1 ADAPTER RSOH, 2N506A care of traffic in both directions. At a terminal, data
to the radio (modulator) is always sent in direction
This unit interfaces the SOH traffic between radio "UP", and data from the radio (demodulator) received
modems and SVCH, RPS and SU units. in direction "DOWN".
SOH bytes are sent to/from modems by a Data to/from SerVice CHannel (SVCH) are trans-
2.048Mb/s timeslot bus that has 30 x 64kb/s chan- ferred by a similar 2.048Mb/s bus as SOH-data to/
nels available. 128kb/s is used for internal signal- from modems. By setup of the SVCH-board, the
ling. One bus is used to receive data from modula- bytes E1, F2 and E2 are available for SVCH traffic.
tor channel 1. One bus is used to transmit data to Only these bytes will transfer the E&M signalling
demodulator channel 1. The same number of buses between the SVCH boards.
are used for protection channel, making a total of
four buses for each direction. Since the adapter is Also SOH-byte 2-5, 2-6, 3-3, 3-5, 3-6, 3xZ1 and
able to handle traffic in two directions, a total of 3xZ2 are transferred at this bus. It is possible to use
eight buses are used towards radio modems. these bytes for SVCH traffic if the corresponding
timeslots are selected at SVCH board. These bytes
SOH-data from RSOH adapter to modulator is sent can also be used as 64kb/s channels with 1+1
at both channel 1 and protection. Both channels are protection by using 64kb/s adapters with setup for
received at RSOH adapter at demodulator side. the correct timeslots.
The RSOH adapter selects data from one of the
channels, depending on channel priority and alarm Selecting SOH-bytes that should be used to SVCH
status. and 64kb/s channels need special attention. Some
Channel priority is controlled by S1, S2 or by the of these bytes may be used for 2Mb/s wayside or
RPS unit. S1/S2 in upper position selects channel will not be available at "regenerator terminals".
one as default, and S1/S2 in lower position selects
protection channel as default. S1 is for direction Data to/from RPS and SU are sent by one 64kb/s
"UP" and S2 for direction "DOWN". and one 192kb/s channel. Byte MS2 (2-3) is used
for RPS and byte D1 (3-1), D2 (3-4) and D3 (3-7)
If S1 or S2 is in middle position, priority between are used for SU.
CH1 and protection is controlled by the RPS unit
and will follow switching of demodulator for CH1. RSOH-ADAPTER has eight LEDs in front which
If an alarm is detected at the selected channel, the indicates if one of eight buses to/from radio mo-
RSOH adapter will automatically switch to the dems is missing clock or sync signal. Alarm for
other channel regardless of S1, S2 or the RPS unit. each bus can be disabled by switch S401.
The LEDs are indicating (from top):
No.1 Alarm for received data from Channel 1 -direction "UP"

No.2 Alarm for received data from Prot. channel -direction "UP"
No.3 Alarm for transmitted data to Channel 1 -direction "UP"
No.4 Alarm for transmitted data to Prot.channel -direction "UP"
No.5 Alarm for received data from Channel 1 -direction "DOWN"

No.6 Alarm for received data from Prot.channel -direction "DOWN"
No.7 Alarm for transmitted data to Channel 1 -direction "DOWN"
No.8 Alarm for transmitted data to Prot.Channel -direction "DOWN"
2 H2606
2N506A
Normal setup in a N+1 and N+0 system is:

- terminal S401 -switch 3,4,5,6 closed. 1,2,7,8 open. S1 and S2 in neutral (middle) position.
- repeater S401 -all switches closed. S1 and S2 in neutral position.
Normal setup in a 1+0 system is:

- terminal S401 -switch 3,5 closed. 1,2,4,6,7,8 open. S1 and S2 in neutral position.
- repeater S401 -switch 1,3,5,7 closed. 2,4,6,8 open. S1 and S2 in neutral position.
To generate necessary clock rates, two PLL with 18MHz VCO are used. One for direction "UP", and one
for direction "DOWN". This is to enable operation with different 155Mb/s rates in each direction. Each PLL
has a PLL_ALARM which is activated if the PLL doesnt lock.
Unit alarm is activated if one of the PLL alarms or selected input alarms is active.
All processing of data to/from buses and SU/RPS is done by one custom designed VLSI circuit (IC401).
BYTE Radio bus SVCH bus

timeslot timeslot
E1 2 8 + 24
Byte 2-5 4 9 + 25
Byte 2-6 5 10 + 26
F1 6 11 + 27
Byte 3-3 8 12 + 28
Byte 3-5 10 13 + 29
Byte 3-6 11 14 + 30
Z1 #1 25 1 + 17
Z1 #2 26 2 + 18
Z1 #3 27 3 + 19
Z2 #1 28 4 + 20
Z2 #2 29 5 + 21
Z3 #3 30 6 + 22
E2 31 7 + 23
Table 1 Timeslots for SOH-bytes
At SVCH, bus timeslots 1-14 are used towards lower stations, and timeslots 17-30 towards higher sta-
tions.
H2606 3
ADAPTER, MSOH
2N505A
H2605 Rev. B
© Nera AS
2N505A
1 ADAPTER, MSOH, 2N505A: K1, K2 and DCCm are inserted at the modulator, and
are -as all MSOH traffic- protected together with the
The unit interfaces the SOH traffic between radio main traffic for that channel.
modems and external equipment that needs access to
K1, K2 and DCCm (D4-D12). K1, K2 and DCCm are available at D-connector in
front.
SOH bytes are sent to/from modems by a 2.048Mb/s K1 and K2 as NRZ, CMOS level with 64kHz clock and
bus that has 30 x 64kb/s channels available. 128kb/s are 8kHz load and strobe signals. Timing between data,
used for internal signalling. One bus is used to transmit clock, load and strobe signal is designed to interface to
data to the modulator. One bus is used to receive data 74xx166 P/S and 74xx4094 S/P converter to get parallel
from the demodulator. interface to K1, K2.
Fig. 1: Timing K1/K2
CLOCK
LOAD
DATA IN LSB MSB LSB
CLOCK
STROBE
DATA OUT LSB MSB LSB
DCCm as one serial NRZ datastream, Msb D4 transmitted first and Lsb D12 last, with 572kHz clock RS422
level.
Fig.2: TIMING DCCm (D4-D12)
CLOCK
DATA IN LSB MSB LSB MSB

D12 D4 D12 D4
CLOCK
DATA OUT LSB MSB LSB MSB

D12 D4 D12 D4
2
H2605
2N505A
MSOH-ADAPTER has two LEDs in front that indi- Normal setup:
cates if one of the two buses to/from radio modems is
missing clock or sync signal. Alarm for each bus can be S501 all switches closed
disabled by switch S501. S601 backward position
The LEDs are indicating (from top):
To generate necessary clock rates, two PLL with 18Mhz
No.1 Alarm for transmitted data bus Disabled S501-3 open VCO is used. One for transmitted data and one for
No.2 Alarm for received data bus Disabled S501-4 open received data. This to be able to operate with different
S501-1 open insert of K1 and K2 disabled
155Mb/s rates in both directions. Each PLL has a
S501-2 open insert of DCCm disabled PLL_ALARM that is activated if the PLL doesnt lock.
With S601 it is possible to select whether the adapter Unit alarm is activated if one of the PLL alarms or
shall interface K1, K2 and DCCm at radio side or selected input alarms are active.
"customer side".
"Forward" position- (customer side) K1, K2 and DCCm All processing of data is done by one custom designed
received in modulator and transmitted from demodula- VLSI circuit (IC 401).
tor. "Backward" position - data transmitted from mod-
ulator and received at demodulator.
Table 1:
P101 In/ P101 In/
Signal Signal
pin Out pin Out
1 K1 data TX IN 14 GND
2 K2 data TX IN 15 GND
3 K clock TX OUT 16 GND
4 K load TX OUT 17 GND
5 K1 data RX OUT 18 GND
6 K2 data RX OUT 19 GND
7 K clock RX OUT 20 GND
8 K strobe RX OUT 21 GND
9 GND 22 DCC data RX - OUT
10 DCC data RX+ OUT 23 DCC clk RX - OUT
11 DCC clk RX+ OUT 24 DCC clk TX - OUT
12 DCC clk TX+ OUT 25 DCC data TX - IN
13 DCC data TX+ IN
3
H2605
ADAPTER, PABX
2N504A
H2904 Rev. B
© Nera AS
2N504A
1 DESCRIPTION 1.2 Technical Data:

1.1 General: PABX Interface : 2W, 600W real
Line current : 20 .... 100mA
This board is a double unit which will give
Voltage drop over
adaptation between a PABX and Nera SDH-radio-
adapter for line current : 20mA, 5.5V ± 0.4V
relay omnibus - and express telephone.
: 50mA, 9.0V ±1.0V
Maximum 10 adapters can be connected : 100mA, 14.4V ±2.0V
(addressed) to each communication channel.
Voice circuit band : 300 ....3400Hz
Signalling : DTMF-CCITT, Q23
Power consumption : +5V, 120mA
3$%;$'$37(5%2$5'
3$%; RING
DETECTOR
)
RELAY
J1 - 8
J1-34
J1 - 7
3 3 gnd ADAPTER ADDRESS

20a TIP 20a
DIODE
20c RING 20c BRIDGE
LINE
25a 25a
1 2 3 4 5 6 7 8 9 0
25c VOICE FREQ 25c UNIVERSAL
23c 23c SPEECH
CIRCUIT
24a VOICE FREQ 24a
24c 24c DTMF FROM PARTY LINE LOGIC & DTMF Tx/Rx
6(59 23a 23a DTMF TO PARTY LINE
&+$1 17c 17c CONTROL SIGNAL
%'
)P1- for Adapter 1

P2- for Adapter 2
Fig.1 BLOCK SCHEMATIC DIAGRAM
2
H2904
2N504A
1.3 Operating: 1.3.3 Incoming Call from 2W PABX
1.3.1 PABX-ADAPTER 2N504A. Connection:
The unit is intended for use together with the When a subscriber is calling the radio-relay, the
Service Telephone Board, 2NF468A to give the party line will act like an ordinary subscriber. If no
radio-relay party line telephone access to the public other city line is connected to the party line, the
network and vice versa. This unit is a double one, adapter will start to send:
capable of serving two service telephone boards.
# #
(Omnibus - and express telephone). To connect/ *
1 sec
*
1 sec 3 sec
*
3 sec
disconnect the PABX, a control signal activated by
detected # plus off hook is used. Fig.3
The buzzer will now be activated on all stations in
periods of 1 : 3 seconds until any handset is lifted.
1.3.2 A Call from Radio-relay Equipment Detected # and off hook will cause the control
through a PABX-connection. signal to start. If the system is properly strapped,
To get the dialling tone from the PABX, it is the control signal will be transferred back to the
necessary to dial # as a prefix plus the Adapter Adapter, and connection is made. When the call is
address. This address is selected by setting a 10 over, always remember to put the handset back on
pos. DIL-switch on the Adapter Board. the hook to disconnect the PABX.
The address figure must follow # within 2.5 secs. For the SDH-radio, only 3 bytes are carrying the
to be valid. (#0.....#9). control signal. If a PABX-adapter is connected,
When the dialling tone is received, the handset bytes E1, F1 or E2 must be used for service
must be used as an ordinary subscriber. telephone communication. Normally omnibus
telephone is using E1 and express telephone is
Only one city-line can be connected at the same using F1.
time.
1.4 INSTALLATION and STRAPPING:
BACKPANEL UWB309 1.4.1 Location:

PABX ADAPTER is located in the upper cassette
in the service rack. Connection between PABX and
ADAPTER is shown on the main Block Schematic
AAU1 Diagram, Fig. 1.
AAU2
SERV TELEPH 1
ADAPTER 1 (Adapter 1 is connected to
SERV TELEPH 2 SERV TELEPH. 1 via backpanel)
PABX ADAPTER
ADAPTER 2 (Adapter 2 is connected to

SERV TELEPH. 2 via backpanel)
ALARM SW (W hen PABX Adapter is installed,

Alarms must be enabled by
open SW no.5 (ADAPTER 1) and
SW No.6 (ADAPTER 2)
Fig.2 Service Channel Cassette
3
H2904
2N504A
1.4.2 Strapping of PABX ADAPTER:
Check that strapping on PABX Adapter is correct
before installing the board.
675$3326&200(176
W100/W200 1-2 pos 2-3 used for factory testing

W101/W201 1-2 pos 2-3 used for factory testing
W102/W202 1-2 pos 2-3 for future use when
one common alarm output will be
used for Adapter 1 and Adapter 2
W103/W203 ON Removed only during factory testing
*W104A/W204A 1-2 When negative BATTERY voltage

*W104B/W204B 4-5 is grounded on station
*W104A/W204A 2-3 When positive BATTERY voltage

*W104B/W204B 5-6 is grounded on station
*Only on 2N504A, Rev. 2A and higher.
Table 1
Also select the calling number (address) for Adapter Connect 2W to J1 - pin 7 and pin 8 (37pins D-sub).
1 /Adapter 2 by setting one switch on the 10 pos. DIL- Set strap W101 and W102 in pos 2-3, 5-6 and 8-9 to
Switch (S100/S200). route the actual signals between 2NF468A and
The figures from 0 - 9 is marked on the PCB. 2N504A via Backpanel, UWB309.
I.e., if 8 is chosen, #8 have to be dialled to get Set strap W210 ON. This strap simulates an off hook
connected to the PABX. Off hook and detected # will situation for the voice band and leads to a full D/A -
start a necessary control signal to connect a PABX, A/D covertion constantly. This is necessary whenever
and when 8 is detected on the Adapter, the correct any analogue connection is made to J1.
PABX is connected to the party line.
The voice frequency signal connection between the
Service telephone board and the Adapter board is 4W
1.5 Strapping of Service Telephone, to obtain galvanic isolation between PABX and the
2NF468A: Radio equipment. If the line loss is high, it is possible
to compensate for the loss in signal level by adjusting
attenuators on the Service Channel board.
2W from PABX is connected via the actual Service DIL-Switch S601 is for signals from PABX, while
Telephone Board and Backpanel UWB309 to the S602 is for signals to PABX. (See handbook unit
Adapter. description for 2NF468A).
The strap W604 must be ON to route the 4W INPUT
See Block Schematic Diagram, Fig.1. internally on 2N468A.
4
H2904
2N504A
1.6 SYSTEM Strapping of Control
Signal:
1.6.1 Principle Schematic diagram for
distribution of Control signal:
2NF468A
TO RADIO DIR 1
J1
CTRL 1
33 TO RADIO DIR 2
OFF HOOK
FROM RADIO DIR 1
DET # FROM RADIO DIR 2
CTRL 2
34
SERVICE CHANNEL BOARD
Fig. 4 2N504A +5V

PABX
ADAPTER
BOARD
1.6.2 Definition of transmission

directions ref to Fig. 4:
DIR 1
DIR 2
Fig. 5
1.6.3 Strapping of Control signal:
1. On repeaters the control signal is

internally distributed.
2. Between terminals the control signal
must be distributed by wiring Ctrl2
(out) to Ctrl1 (inp) Depending on positive BATTERY (NEGATIVE
STATION GROUND) or negative BATTERY
Ctrl2 (out): J1-34
(POSITIVE STATION GROUND) Ctrl Signal
Ctrl1 (inp): J1-33 must be strapped on 2NF468A:
5
H2904
2N504A
POSITIVE BATTERY:
+5V +5V
+ VBAT
Ctrl2- strap W206 in pos 1-2, 4-5 LOGIC
Ctrl1- strap W208 in pos 1-2, 4-5 CIRCUIT
CTRL 2
CTRL 1
J1-34
Fig.6 J1-33
+5V +5V
NEGATIVE BATTERY:
LOGIC
Ctrl2- strap W206 in pos 2-3, 5-6 CIRCUIT
Ctrl1- strap W208 in pos 2-3, 5-6
CTRL 2
CTRL 1
VBAT
Fig. 7 J1-33 J1-34
1.7 CTRL 2 INTERFACE

1.7.1 2N504A, Rev. 1A:
NOTE: CTRL 2
On the Service Channel Board, which is connected

to the PABX-Adapter, Ctrl2 must always be
hooked up for POSITIVE BATTERY (W206 in pos. +5V
1-2, 4-5) and Ctrl2 must NOT be connected with a SERV. CHAN. BD PABX ADAPT. BD
Ctrl1-signal to avoid that the battery voltage
enters the PABX-Adapter.
Fig. 8a
6
H2904
2N504A
1.7.2 2N504A, Rev. 2A and higher:
Ctrl2 signal on 2N504A can be strapped to either

positive or negative battery by strap W104/W204
(See Table 1). Then Ctrl2 and Ctrll signal can be
wired together.
+VBAT
+5V
CTRL 2
SERV. CHAN. BD PABX ADAPT. BD
1 2 3
W 104A/204A
W 104B/204B
4 5 6
CTRL 2
+5V
-VBAT
SERV. CHAN. BD
PABX ADAPT. BD
1 2 3
W 104A/204A
W 104B/204B
4 5 6
Fig. 8b
7
H2904
2N504A
When Ctrl1 and Ctrl2 is looped on one station,
there must not be any looping in any of the
branches to avoid hang-up. See examples.
PABX PABX
ADAPT ADAPT
Example 1, Fig. 9:
PABX PABX
ADAPT ADAPT
Example 2, Fig. 10:
PABX
ADAPT
Example 3, Fig. 11:
8
H2904
2N504A
PABX
ADAPT
Example 4, Fig. 12:
PABX
ADAPT
PABX
ADAPT
Example 5, Fig. 13:
When only one Adapter is used, or when Adapters If it is difficult to place the Adapters in an extensive
are placed at the branching termination out from an "party line", this can be divided into control
intersection, there will be no risk of hang-up of the sections. In that case, only the Adapter within the
control signal. section can be controlled/used.
9
H2904
ALARM BOARD, SERVICE RACK
EJ164A
H2698 Rev. A
© Nera AS
EJ164A
1.0 TECHNICAL DATA
Parallel alarm inputs: HCT-logic with 10kohm pull-up resistor

IC max: 12mA
Relay alarm outputs: Contacts: 2 form C. Contact resistance: <60mW.

Current: nom. 60mA
max. 160mA
1.1 Functional Description 1.1.1 25-pins D-Sub Connector J14 on

This board collects alarms from units located in EW53A:
the service rack and combines these into external Pin 1: 64kb/s ADAPTER_ALM Collector
alarms with optocoupler or relay contact outputs. Pin 2: 64kb/s ADAPTER_ALM Emitter
Pin 3: XMTR_SW_ALM Collector
The alarm outputs are wired to a 25-pin D-sub Pin 4: XMTR_SW_ALM Emitter
connector, J14, on Connection Board, EW53A, Pin 5: SUPERVISORY_UNIT-ALM Collector
located in the middle of the Service Rack. Pin 6: SUPERVISORY_UNIT_ALARM Emitter
One of the alarm outputs can be selected either as Pin 7: PWR_SPLY_ALM Centre
Sync Unit Alarm or Test Mode Alarm. If Sync Pin 8: PWR_SPLY_ALM NO/NC
Pin 9: RCVR_DISTR_ALM Collector
Unit Alarm is selected, the strap W1 has to be in
pos. 2-3. If Test Mode Alarm is selected, Sync Pin 10: RCVR_DISTR_ALM Emitter
Pin 11: RSOH_ADAPTER_ALM Collector
Unit Alarm inputs are disabled in the backplane
Pin 12: RSOH_ADAPTER_ALM Emitter
and W1 has to be in pos. 1-2.
Pin 13: MSOH-ADAPTER_ALM Collector
Power Supply Alarm and Main Alarm outputs are Pin 14: MSOH_ADAPTER_ALM Emitter
relay contacts. For Main Alarm, both the Normally Pin 15: SERVICE_TEL_ALM Collector
Open and the Normally Closed contacts are wired Pin 16: SERVICE_TEL_ALM Emitter
to the D-sub connector. For Power Supply Alarm, Pin 17: AAU_ALM Collector
Normally Open or Normally closed contact is Pin 18: AAU_ALM Emitter
selected by strap W2. W2 in pos.1-2 gives Pin 19: RPS_UNIT_ALM Collector
Normally Open, and in pos.2-3 Normally Closed. Pin 20: RPS_UNIT_ALM Emitter
Pin 21: SYNC_UNIT/TEST_MOD_ALM Collector
Pin 22: SYNC-UNIT/TEST_MOD_ALM Emitter
Pin 23: MAIN_ALM NO
Pin 25: MAIN_ALM NC
NO= Normally Open, NC= Normally Closed.
2
H2698
EJ164A
Fig.1 Alarm Board, Service Rack, EJ164A

3
H2698
0JG164A
ALARM ADAPTER UNIT (AAU)

0JG164A
H2767 Rev. B
© Nera AS
H2767
1
0JG164A
TABLE OF CONTENTS
Page
1.0 ALARM ADAPTER UNIT (AAU) 3
1.1 Introduction 3
1.2 Alarm Interface 4
1.3 Remote Control Interface 4
1.4 AAU Address 4
1.5 V.11 - Serial Communication Interface 4
1.6 CPU - ROM - RAM 4
1.7 Watchdog/Remote Reset 4
1.8 Strap-Configuration 5
2 H2767
0JG164A
1.0 ALARM ADAPTER UNIT

(AAU)
1.1 Introduction:
The Alarm Adapter Unit (AAU) is a micro- The AAU communicates with the Supervisory
controller-based subsystem of the SDH Unit (SU) via a serial bus interface, V.11. The SU
Supervisory System, which collects external polls the AAUs at regular intervals to update the
equipment alarms and performs remote control alarm status. Each AAU has a fixed address
functions. The AAU is located in the service rack. which is set by a dil-switch in the backplane, one
dil-switch for each AAU.
The alarm input function is used for collection of Alarm inputs are connected through a 37 pin delta
external alarms as fire alarms, oil level alarms connector (P201).
etc. There are 32 alarm inputs available on each Remote control outputs are connected through a
AAU. 25 pin delta connector (P401).
A red LED located on the front indicates watchdog
The remote control function is used for external rundown.
outputs available for the user. There are 8 remote
control outputs on each AAU.
Alarm Adapter Unit:
V.11 SERIAL
V.11
COMM. INT. I/F
ADDRESS CHIP
CLK SEL
GEN
CPU
8032
ADDR/DATA ADDR
WD LATCH
EPROM RAM ALM_IN ALM_IN REMOTE

CS CS CS CS CS
32K x 8 8K x 8 GR_1 GR_4 CTRL
ALM_IN ALM_IN REMOTE

1-8 25 - 32 1 -8
The AAU is divided into 7 main functions:
1) - Alarm Input Interface 5) - CPU - ROM - RAM

2) - Remote Control Interface 6) - Watchdog/Remote Reset
3) - AAU Address 7) - Strap Configuration
4) - V.11 Serial Communication
Interface
H2767
3
0JG164A
1.2 Alarm Interface
The AAU can handle up to 32 external alarm During the initialization, the u-processor reads
inputs, which are galvanically isolated from the the unit address.
main +5V supply. AAU1 - AA8 have address 10(HEX) - 17(HEX).
The transient protection on each input can handle

a nonrepetitive pulse (duration <10 m.sec. and 1.5 V.11 - Serial Communication
an amplitude <250V). The 32 alarm inputs are Interface
configured for TTL or Current Loop and are
To communicate with the SU, a high speed
selectable in groups of 4 by straps W201-208 and
(375kb/s) party line, V.11, is implemented. The
W301-308. See strap configuration. The alarm
RS-485 is a balanced interface. The AAU is
input mask, i.e. HIGH or LOW, is set via the SU.
polled periodically by the SU to update the alarm
See SU Operator Commands. The alarm inputs
inputs and remote control.
are located at P201.
1.6 CPU ROM - RAM
1.3 Remote Control Interface
The Remote Control function can handle up to The CPU is the Intel 80C31 Microcontroller.
8 outputs implemented by using latched relays The ROM is the Intel 27C256 (32K * 8) Erasable
which are individually overvoltage protected. PROM. The RAM is the Toshiba 5565 (8K * 8)
Each output is also equipped with a VDR spark Static RAM (optional, depending on software
suppressor. The transient protection on each release).
relay output can handle a nonrepetitive pulse, i.e.
duration <10 m.sec. and an amplitude <100V. 1.7 Watchdog/Remote Reset
Each remote control output can be configured as The Watchdog Reset (WD), outputs a reset signal
a Latched output or as a Pulsed output. The to the u-controller unless WD - timer is reset by
latched control is a bistable ON - OFF output. a software.
The pulsed output is selectable from 0.5 to 63.5
sec in steps of 0.5 sec. The remote outputs are On "power-up", the u-controller is reset by the
located at P401. WD with a 10m pulse.
Manual reset is performed by the RESET
1.4 AAU ADDRESS SWITCH, S101, which will reset the WD timer
generating a reset signal to the u-controller. At
Each AAU has a fixed address to distinguish watchdog rundown, a red LED on the front of the
the different Peripheral Units (PU), AAU-ACU AAU illuminates.
when communicating via the party line serial The AAU can also be reset remotely from any
bus. This is realized by giving each PU a unique SU. This function can be disabled/enabled by the
address located in the backplane of each PU. Dilswitch S102-2.
4 H2767
0JG164A
1.8 Strap - Configuration
The following diagram gives the strap configuration of the AAU:
STRAP NAME PIN NO DESCRIPTION
W101 WDOG 1-2 WD - Disable

W101 WDOG 2-3 WD - Enable (NORM)
W201 * ALM 1-2 Alarm inputs in Current Loop mode

W201 ALM 2-3 Alarm inputs in TTL mode (NORM)
W202 * ALM 1-2 Alarm inputs in Current Loop mode
W202 ALM 2-3 Alarm inputs in TTL mode (NORM)
* W201 - W202, W203 - W204, W205 - W206, W207 - W208,

W301 - W302, W303 - W304, W305 - W306, W307 - W308
are alarms strapped in groups of 4.
1.9 DIL Switch S102
SWITCH NO. FUNCTION POSITION
1 HW TEST OFF
2 Remote Reset ON
3 NOT USED OFF
4 NOT USED OFF
H2767
5
MAIN ALARM DISPLAY
EK50A
H2030 Rev. A
© Nera AS
EK50A
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2 H2030
DISPLAY UNIT
0JK165A
H2726 Rev. B
© Nera AS
0JK165A
TABLE OF CONTENTS
1.0 DISPLAY UNIT ......................................................................................................... 3
1.1 General ............................................................................................................... 3
1.2 Display Unit ........................................................................................................ 4
1.3 Display ................................................................................................................ 4
1.4 Keyboard ............................................................................................................ 4
1.5 LED Status ......................................................................................................... 4
2 H2726
0JK165A
1.0 DISPLAY UNIT
1.1 General:
The Display Unit (DU) is part of the SDH radio Supervisory System and is mounted in the service rack
of the radio equipment. The DU consists of a graphical display, a membrane keyboard and a row of
LEDs for status display.
The Display Unit is shown in Fig. 1:
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H2726 3
0JK165A
1.2 Display Unit

The Display Unit, 0JK165A, contains control logic LCD, a 6 key membrane keyboard is included on the
for the keyboard, LEDs, power filter and necessary front panel of the DU. The keyboard is scanned by a
logic for interfacing to the u-processor bus. An keyboard and display controller chip on the Display
external chip selects logic. Wait state generator logic Unit Board. The controller automatically interrupts
is also provided on the display board. the u-processor when a depressed key is detected.
A resistor network provides the LCD with voltage
for adjustment of the display contrast. The LCD The different keys have the following functions:
illumination is turned ON and OFF by control logic.
* The arrows are used to move the cursor
and increase/decrease numbers.
1.3 Display * F1 button is used to return to previous
The LCD is a graphical display with 16 lines x 16 menu.
characters. * F2 button is used to turn the display
Display illumination is switched on by pressing the illumination ON and OFF.
F2 button and is automatically switched off 2 minutes * EXE button is used to execute the selected
after any key has been pressed. command.
The LCD contrast can be adjusted by varying the 1.5 LED Status
resistor R1 on the Display Unit Board.
On the DU there are located 9 LEDs which are
See Figure 2. displaying the alarm status for each radio channel
and for the service rack. When the LED is turned on,
this indicates that an alarm is detected in that
1.4 Keyboard channel. When the LED is blinking, this indicates
For entering commands and selecting menus on the that a manual operation is performed ( f.ex.
maintenance).
1 2
CAT W3
C9
H1 W2
P3
1 2 R7
R5
R4
R6
CAT.
C6
R3
H2
IC6
CAT.
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RESIST OR R1
Fig. 2 Display Unit Board
4 H2726
SUPERVISORY UNIT (SU)
2KZ198A
H2576 Rev. A
© Nera AS
2KZ198A
TABLE OF CONTENTS
1. TECHNICAL DATA ...................................................................................... 4
2. FUNCTIONAL DESCRIPTION ..................................................................... 5

2.1.INTRODUCTION ............................................................................ 5
2.2.CENTRAL PROCESSING UNIT (CPU) ........................................... 6
2.3.INTEGRATED SYSTEM PERIPHERAL (ISP) .................................. 6
2.3.1.Programmable interval timers (PIT) ........................................................... 6
2.3.2.DMA control unit (DMA) ............................................................................. 6
2.3.3.Interrupt control unit (PIC) .......................................................................... 7
2.3.4.Wait state control unit (WS ctrl) .................................................................. 7
2.4.CLOCK, RESET AND CONTROL UNIT .......................................... 7
2.4.1.Clock oscillator and clock signals ............................................................... 7
2.4.2.Reset and alarm circuit .............................................................................. 7
2.4.3.System control unit .................................................................................... 8
2.4.4.Real Time Clock unit (RTC) ....................................................................... 8
2.5.MEMORY ....................................................................................... 8
2.6.SERIAL INTERFACES .................................................................... 8
2.6.1.Data Communication channels (DCC) ........................................................ 8
2.6.2.Network Interface (NI) ................................................................................ 8
2.6.3.SCADA or Qx serial channel ...................................................................... 9
2.6.4.ACU/AAU serial bus ................................................................................... 9
2.6.5.VDU port for diagnostics or testing ............................................................. 9
2.6.6.Human Computer Interface (HCI) ............................................................... 9
2.7.PARALLEL INTERFACE ................................................................. 9
2.8.MISCELLANEOUS INPUTS/OUTPUTS (MISC I/O) ......................... 9
2.8.1.Display Unit (DU) interface ......................................................................... 10
2.8.2.RPS direct control I/O ports ........................................................................ 10
2.8.3.Radiolink station ID input port ..................................................................... 10
2.8.4.Control of the Radiolink Synchronisation Unit ............................................. 10
2.8.5.Local and remote reset functions ................................................................ 10
3. BOARD INTERFACE ................................................................................... 10
4. HARDWARE CONFIGURATION .................................................................. 15
5. CONNECTING A VDU TO THE SU .............................................................. 17
2 H2576
2KZ198A
1 TECHNICAL DATA
MICROPROCESSOR: Intel 80376 (supported by the Intel 82370 ISP).
MEMORY: -256 Kbytes for code (OTPROM)

-128 Kbytes for data (RAM)
-16 Kbytes for nonvolatile data (EEPROM).
WAITSTATE GENERATOR: -of type "normal ready"

-handles six independent waitstate request sources
-software controlled number of waitstates for each source.
TIMING SYSTEM: -31.9488 MHz crystal oscillator for CPU clock

-programmable system timebase ("tick")
-three general-purpose interval timers with interrupts
-Real Time Clock device with battery backup.
WATCHDOG TIMER: RTC built-in watchdog facility with programmable timeout.
INTERRUPTS: Handles interrupts from parallel and serial interfaces, timers and Display
Unit. Two spare interrupt inputs available at backplane connectors.
PARALLEL INTERFACE: Two interrupt-driven 8-bit bidirectional FIFO interfaces.
SERIAL INTERFACE: -two DCC, 192 kbit/s, CMOS

-one sync/async RS-485 channel, 1.2 to 124.8 kbit/s
-one sync/async channel, 1.2 to 124.8 kbit/s, configurable as RS-485 or
RS-232C
-µLAN RS-485 serial bus, 187.5 kbit/s
-two RS-232C channels, 1.2 to 19.2 kbit/s.
DMA CHANNELS: -four channels available for DCC

-two channels available for the sync/async RS-485 interface
-one channel available for the configurable RS-485/RS-232C interface
-one channel available for the µLAN serial bus.
ALARM OUTPUT: SU Main Alarm, active high, open-collector (activated by reset, watchdog
timeout or low-voltage detection ).
POWER SUPPLY: +5V ±0.25V, max 1.5A

+15V ±0.5V, max 0.1A
H2576 3
2KZ198A
2 FUNCTIONAL DESCRIPTION of the front panel of the radiolink station Service Rack.
For further information refer to the hardware documen-
2.1 Introduction: tation for the DU.
The 2KZ198A CPU board acts as the Supervisory Unit The main tasks for the Supervisory Unit is to
(SU) in the NL29x family of Digital Radio Relay · Meet the high speed serial interface requirements
Systems. It is based on the 2KZ149B/2SK184B Super- of SDH
visory & Switching Unit (SSU), but all functions · Support the needs of modern TMN systems
dedicated to the Radio Protection Switching system is · Support local and remote data aquisition through
now implemented on a separate board; the RPS the ACUs and AAUs
(2SK220A). The SU handles the alarm and meter data · Relieve the Protection Switching system from
storage and presentations, the operator interface, the demanding communications and user interface
SCADA (or optionally Qx) interface and the DCC tasks
interface for SDH.
The hardware is realised by surface mounted devices
A local operator interface based on the Display Unit (SMD) where possible, and CMOS type of integrated
(DU), 0JK165A, will provide the operator with access circuits is preferred to minimise power consumption.
to alarm status, meter readings and control of system Programmable circuits (PAL, EPROM) and RTC de-
configuration. Through the parallel interface with the vice are mounted in sockets.
RPS the operator will have control over configuration
and status of the Protection Switching system. Fig. 1 shows a functional block diagram of the SU. The
SU hardware is based upon powerful microcomputer
The Display Unit is equipped with LEDs indicating and peripheral circuits, and is designed to meet the
main alarms for each channel, a graphics LCD display requirements of a large number of communication
and a keyboard for command entering. The SU is interfaces.
connected to the DU through the back plane connectors
(data bus and control signals). The DU will act as part
.
Figure 1: Functional block diagram.
4 H2576
2KZ198A
The following sections contain brief descriptions of the CPU will act as bus controller and the ISP will be in
functional blocks of fig. 1. slave mode. During DMA transfers the ISP will be
working in master mode and act as bus controller. In
master mode the ISP behaves like the CPU to the rest of
2.2 Central Processing Unit (CPU): the system.
The 32-bit Intel 80376 embedded microprocessor will
act as the CPU. It is nearly equivalent to the 80386
microprocessor, but has a 24-bit address bus and a 16-
2.3.1 Programmable interval timers (PIT):
bit data bus.
The PIT included in the ISP is similar to the 8254 PIT
used on the 2KZ149B CPU board, except that in the ISP
The surrounding functions are designed to run with a 16
all timers run with a common clock input, and the
MHz CPU version. This requires that the 80376 is
number of timers is four. The common clock input
supplied with a 32 MHz clock signal. The minimum
signal is set to 1024 Hz so that a 16-bit timer can
instruction cycle (or bus cycle) length is two CPU clock
measure time intervals from 1 ms to 64 s.
cycles (125 ns). One CPU clock cycle is defined as a bus
state (i.e. 62.5 ns).
Timer 0 will run in mode 2 (rate generator) and be used
for the software system timebase, also called the Sys-
The 80376 Address Pipelining technique results in a
tem tick. It will generate a periodic interrupt to provide
system capable of running without waitstates while
a software task scheduler with some timing informa-
using memory and peripheral devices with access times
tion. The tick interrupt is generated by timer 0 at
of approx. 100 ns (or faster). Slower devices will need
terminal count, the counter will then reload itself and
one waitstate less compared to the case where the CPU
start a new countdown sequence. The length of this
is running non-pipelined bus cycles.
cycle (the tick interval) is software configurable and
will typically be in the order of 10 ms. Minimum
The 80376 has separate memory and I/O address space
interval is approx. 2 ms.
selected by the M/IO# control output. The 24-bit mem-
ory address range is handled by the 23-bit address bus
Timers 1, 2 and 3 will be available to the SU software
(A23 - A1) and the BHE# (byte high enable) and BLE#
for general timing purposes. An example is generation
(byte low enable) control outputs. This allows linear
of hardware timeout interrupts for software tasks which
addressing of 16 Mbytes of memory. When the CPU is
need a safe way of limiting the execution time of a
reset it will start executing instructions near the top of
process.
physical memory, at location 0FFFFF0H. It will need
some code memory in this area, and some data memory
starting at physical location 0 (at least 256 bytes).
2.3.2 DMA control unit (DMA):
The DMA controller included in the ISP replaces the
When addressing I/O the upper eight bits of the address
two 8237 DMA controllers used on the 2KZ149B CPU
bus are all zeroes, so I/O address space is limited to 64
board. It contains eight independent channels, each with
kbytes accessed by A15 - A1, BHE# and BLE#. For
its own hardware request signal (DREQ1 - DREQ8).
simplicity all 8-bit I/O devices in the SU are connected
The SU hardware is prepared for use of all DMA
to the lower half of the databus and are accessible only
channels for data transfers between memory and the
at even I/O-addresses (BLE# = 0).
most demanding serial channels.
For hardware allocation of DMA channels , see Table

2.3 Integrated System Peripheral (ISP): 1, page 7.
The Intel 82370 Integrated System Peripheral acts as a
support chip for the 16 MHz CPU. By supplying the ISP The two-cycle transfer mode will be used since the
with the same clock signal as for the CPU these devices peripherals are eight-bit devices while memory is or-
will run synchronously. ganised as 16-bit devices. In this mode there is no need
for hardware acknowledge signals from the DMA
The ISP will take care of DMA transfers, timer func- controller to the requester. Address and control signals
tions, wait state generator functions and interrupt con- are generated by the ISP in accordance with the contents
trol functions. Under normal program execution the
H2576 5
2KZ198A
of the programmable DMA registers for target and software configurable (up to a maximum of 16) through
requester. Each requester controls one hardware re- six programmable registers in the wait state control unit
quest input to the DMA controller. of the 82370 (three for memory and three for I/O).
DMA ch. Direction Comm.channel: Wait state requests are made by placing a code on the 2-
no: bit wait state select input bus (WSC1, WSC0) of the ISP.
This code is based on chip select signals from the
0 From memory DCC1 Tx data address decoding logic. The wait state generator logic is
1 To memory DCC1 Rx data of the normal ready type: Normally, [WSC1, WSC0]
2 From memory DCC2 Tx data
= [1, 1] which means that the wait state generator is
3 To memory DCC2 Rx data disabled and the READYO# output from the ISP is
4 From memory NI Tx data LOW. Waitstate requests are made by pulling one or
5 To memory NI Rx data both of the wait state select bus lines to GND.
6 To/From mem. SCADA/Qx Rx/Tx data
7 To/From mem. ACU/AAU serial bus Rx/Tx 2.4 Clock, Reset and Control Unit:
2.4.1 Clock oscillator and clock signals:
Table 1: Allocation of DMA channels. The basic timing signals for the SU are derived from a
31.9488 MHz crystal oscillator. This particular fre-
quency is chosen because it minimises the frequency
errors for the on-board programmable baud-rate gener-
2.3.3 Interrupt control unit (PIC): ators, when compared to standard baud-rates. The
The Programmable Interrupt Controller (PIC) of the oscillator output is used directly as clock input signal for
ISP offer nearly the same number of interrupt levels as the CPU and the ISP. It is also used to derive various
the three cascaded 8259 devices used in the 2KZ149B/ lower frequency clock signals.
2SK184B system. This PIC provides 15 external inter-
rupt request inputs and five interrupt requests internally A 15.9744 MHz clock signal is generated by a divide-
in the 82370. All external request inputs are active LOW by-2 circuit. This signal is used for peripheral devices
with a weak internal pullup. which are capable of operating at 16 MHz or higher.
When the PIC detects an interrupt request it issues an Some of the I/O devices require lower clock speed; a
interrupt signal to the microprocessor which then will clock signal of 3.9936 MHz is generated by further
service the interrupt by executing an interrupt acknowl- division of the 15.9744 MHz clock.
edge bus cycle and calling an interrupt service routine.
All the interrupt vectors (one for each IRQ) are fully Finally, a slow clock signal of 1024 Hz for the Program-
programmable. mable Interval Timers of the ISP is taken from the
square-wave output of the RTC module.
2.3.4 Wait state control unit (WS ctrl):

Memory or peripheral circuits may not match the 125 ns 2.4.2 Reset and alarm circuit:
bus cycle timing requirements, hence wait states need to The reset circuit will generate a properly timed reset
be inserted. One wait state equals one bus state (62.5 ns). signal to the ISP based on input signals from a voltage
In order not to insert more wait states than strictly supervision circuit, a watchdog circuit, remote-reset
necessary, it is possible for three separate memory- inputs and a manual reset switch, and turn on a red LED
mapped devices (or blocks of devices) and three sepa- indicator. The manual reset switch and the indicator are
rate I/O-mapped devices to individually request a spe- placed next to each other at the front edge of the board.
cific number of wait states. In addition, the SU_UNIT_ALM output (active high,
open collector) and the bypass control signals for DCC1
The number of wait states generated on a request is and DCC2 will be activated. These signals are latched
and require a CPU write cycle at a dedicated I/O a d -
dress to be cleared.
6 H2576
2KZ198A
The watchdog circuit detects abnormal behaviour of the 2.5 Memory:
microprocessor by starting a time-out cycle which the The SU contains OTPROM devices for program stor-
microprocessor will have to interrupt before it runs out. age, static RAM devices for volatile data storage and
If not interrupted it will activate the reset circuit. EEPROM devices for non-volatile data storage. All
types of memory are configured as 16-bit words by
The watchdog time-out length is configurable over the using byte-wide memory devices in parallel. The
range from 0.01 to 99.99 seconds. This function is amount of memory is 256 kbytes OTPROM (IC301 and
realised by a built-in programmable watchdog timer of IC302), 128 kbytes RAM and 16 kbytes EEPROM.
the RTC module. OTPROMs are 32-pin PLCC devices mounted in sock-
ets to allow for easy software upgrading
The voltage supervision circuit detects if the supply
voltage on the board is sufficient for safe operation of
the microprocessor and surrounding logic and memory
circuits. If the voltage supervisor detects insufficient 2.6 Serial Interfaces:
supply voltage it will activate the reset circuit. The SU contains several types of serial interfaces. Most
of these will be handled by Am85C30 Serial Commu-
The remote reset inputs are four external reset signals nication Controller (SCC) circuits (Advanced Micro
coming from demodulator units and are initiated by an Devices), or compatibles, running with a 16 MHz clock
SU in a remote location. They are combined into one (one interface is handled by an Intel 82510 async.
signal which may activate the reset circuit. controller). These circuits provide very flexible and
programmable interfaces, and covers a large range of
data rates. For most of the serial channels the hardware
2.4.3 System control unit: includes the necessary handshaking signals for use of
The System control unit is a group of logic functions DMA-transfer of data.
which handles address and control signal decoding and
latching, and the generation of various access control
signals like Chip-Enable, Output-Enable and Write- 2.6.1 Data Communication chan. (DCC):
Enable for memory and peripherals. The two Data Communication Channels (DCC1, DCC2)
are 192 kb/s (D1-D3 of SOH) or 576 kb/s (D4-D12 of
The basic function of the System control unit is the Bus SOH) CMOS synchronous serial channels connected to
Cycle Tracker (BCT) which is a state machine capable an RSOH Adapter, and will be used for communication
of tracing the bus cycles of the CPU or the ISP. This with SUs at remote stations. The baud rate is determined
function is necessary for the control unit to be able to by external clock signals. Each channel may employ
generate properly timed access control signals which two DMA channels for full-duplex data transfer be-
lets the CPU access the various devices with a minimum tween memory and Rx-/Tx-machine.
number of wait states. Most of the system control
functions are realised by an EEPLD device (IC110). Two control signal outputs are available from the SU to
set the adapter in bypass mode, so that bypass of each
DCC can be controlled individually by the software. If
2.4.4 Real Time Clock unit (RTC): the SU for any reason is reset, these signals go active
The RTC is a CMOS clock IC with battery backup (HIGH) until they are cleared by the software.
encapsulated in one package (IC113). It has an approx-
imate battery lifetime (without supply voltage) of ten 2.6.2 Network Interface (NI):
years. It is mounted in a socket. The date and time One Network Interface channel (NI) is available for
information is readable and writeable through CPU communication between two SUs located at the same
access to the I/O-mapped registers of the RTC. radio-relay station. This interface may be synchronous
or asynchronous with a data rate of from 1.2 kb/s to
This module also contains the watchdog timer unit and 124.8 kb/s. Through an on-board switch it can share one
a 1024 Hz square wave generator. of the clock signals for the DCC and thereby provide a
synchronous 192 kb/s or 576 kb/s interface. Electrical
specification is RS-485.
H2576 7
2KZ198A
This channel may employ two of the 82370 DMA 2.7 Parallel Interface:
channels for full-duplex information transfers between The SU is equipped with two parallel, interrupt driven
memory and Rx-/Tx-machine. The serial lines are interfaces of FIFO type called FIFO1 and FIFO2. One
available at a connector on the back plane . is for communication between the SU and the RPS. The
other is available for future system extensions (possibly
a Message Communications Function extension han-
2.6.3 SCADA or Qx serial channel: dling layered communication protocols). Both of these
A programmable serial interface, 1.2 kb/s to 124.8 kb/ interfaces communicate through the back plane con-
s asynchronous or 1.2 kb/s to 1.9 Mb/s synchronous, is nectors.
available for communication with SCADA/SIC-1 (or
SIC-2) equipment. Alternatively, this may be used as a Each FIFO register has its own parallel output (trans-
Qx interface. The data transfers to/from memory for mit) data bus of eight bits. The external units may read
this channel may be handled by the CPU or by half- the contents of the FIFO registers by activating read
duplex DMA transfers through DMA channel 6. signals. The SU will indicate parallel transmit opera-
tions by activating Message available flags (or inter-
The serial lines are available at a connector on the back rupts) to the external units after writing to the FIFO
plane. Electrical interface is RS-232C or RS-485, con- registers.
figurable through on-board switches. (Ref. fig.2 and
fig. 3). Parallel data is received through a common 8-bits
external data bus interface. The external units parallel
drivers need to have 3-state capability controlled by the
2.6.4 ACU/AAU serial bus: SU through read signals. Two interrupt request inputs
The actual alarm and meter data capture and the remote are to be controlled by the external units. These will
control functions for the supervisory system will be function as Message available interrupts to the SU.
performed by several peripheral units called Alarm
Collection Units (ACU) and Alarm Adapter Units
(AAU). Communication between the SU and these
peripherals is provided by a µLAN 187.5 kbit/s RS-485 2.8 Miscell. Inputs/Outputs (Misc I/O):
asynchronous serial bus distributed through the back
plane connector. This is a collection of several control/status functions
handled by discrete I/O signals. The output signals will
The ACU/AAU serial bus may also utilize one DMA control harware functions on the SU board and also on
channel for half-duplex data transfers. some external units by signals through the back plane
connector. The DU interface signals are also described
here.
2.6.5 VDU port for diagnostics or testing:
One RS-232C port is intended for use as a diagnostics The hardware I/O-registers for these signals are named
output port. It is also used for unit testing during Output-register-1, Output-register-2, Input-reg-
fabrication. This port is available through a connector ister-1 and Input-register-2.
at the front edge of the SU board. (Ref. chapt.5).
Control outputs are stored in the addressable output
registers, and status inputs are polled by the CPU by
2.6.6 Human Computer Interface (HCI): latching the inputs into the addressable input registers
An RS-232C serial interface (V.24 compatible), 1.2 kb/ and read its contents. The output registers are cleared by
s to 19.2 kb/s asynchronous, is available for use as a HCI the system reset signal.
for communication with Personal Computer (PC), ordi-
nary alphanumeric terminal or telephone modem. The
serial lines are available at a connector on the back
plane. The interface is implemented by an 82510 ASC A list of the control/status functions is shown in
(Asynchronous Serial Controller). Table 2, page 10
8 H2576
2KZ198A
Function: Accessed by: An 8-bit input port for radio-relay station identification
is provided at the back plane connector P2 (ADDR_SU,
DU interface Address, control and 19a - 22c). This input port is programmed by a DIL-
low data bus switch located in the back plane to set the local station
RPS direct ctrl outputs (4bits) Output-register-1 number. The information is accessed by a I/O-read
RPS direct ctrl inputs (8bits) Input-register-1 operation from the 8-bits Input-register-2.
RPS reset Output-register-2
ACU/AAU reset Output-register-2
Remote SU reset output Output-register-2 2.8.4 Control of the Radio-relay
Synchronisation Unit:
SU main alarm output Output-register-2 Two output signals are available at the back plane
Sync Unit ctrl 1 & 2 Output-register-2 connectors for control of the optional Radio-relay 2MHz
Radio-Relay Station ID (8bits) Input-register-2
Synchronisation Unit, and are accessed through I/O-
Table 2: Overview of I/O functions write operations to the 8-bits Output-register-2. These
will provide software control of the selection of external
synchronisation signal input and the distribution of
2.8.1 Display Unit (DU) interface: synchronisation output signals, in addition to the auto-
The DU interface is hardware compatible with that of matic control in the Synchronisation Unit.
2KZ149B, except for the physical connection. The
connection is now made through the back plane connec-
tor P1 (9a - 15c), ref. table 11. Access to the DU is 2.8.5 Local and remote reset functions:
controlled by chip-select, I/O-select and read/write Three software controlled external reset signals (active
signals. A 4 MHz clock is available as system clock, and HIGH) are generated by the SU:
some address bits are available for local address decod-
ing. Data is transferred to and from the DU over the · Reset of RPS unit
external databus on P1 (16a - 19c). The DU will use · Reset of ACU and AAU units
input IR11 on P1 (12a) to generate keyboard interrupt · Reset of SU units on remote stations
requests.
The remote SU reset function makes use of one bit in the

2.8.2 RPS direct control I/O ports: SOH to transmit the reset signal to other stations. The
In a 1+1 protection switching system it may be desirable remote reset output signal is connected to modulator
to replace the microprocessor-based RPS unit by a few units for channel 1 and Protection channel, which will
logic circuits which will not require any software. To insert a reset bit in the data traffic. On each station the
take care of switching status display and manual switch- demodulators will extract these bit streams and present
ing control functions in this case, the SU provides four them to the local SU (i.e. on a repeater the SU will
programmable output signals and eight readable input receive four such signals; two from each direction). In
signals at the back plane connectors. the SU these input signals are passed through filters and
combined with the rest of the reset logic. The remote
The RPS direct control outputs are accessed through I/ reset inputs may be disabled by on-board switches.
O-write operations to the 8-bits Output-register-1; only
the low nibble of the data byte is used. 3 BOARD INTERFACE
The RPS direct control inputs (status inputs) are ac- The board is equipped with two back plane connectors
cessed through I/O-read operations from the 8-bits of 64 pins each. Table 3 lists the signals present on the
Input-register-1. The inputs of this register may be upper connector (P1). Signal level Balanced refers to
driven by the simplified RPS logic unit with status signals with configurable line driver types. These sig-
information to the SU. nals conform to either RS-232C or RS-485 electrical
interface standard. A # suffix in the signal name
indicates active low logic.
2.8.3 Radio-relay station ID input port:
H2576 9
2KZ198A
Table 3: Signals on connector P1.
Pin # I/O Level: Row a signals: Function: Active:
1a GND
2a O Balanced SCADA TXD+ SCADA/SIC-1 (optionally Qx TMN) Tx data
3a I Balanced SCADA RXD+ SCADA/SIC-1 (optionally Qx TMN) Rx data
4a I Balanced SCADA RXC+ Optional Rx clock for synchr. TMN protocol

5a O Balanced NI TXD+ Network Interface Tx data
6a O Balanced NI TXC+ Network Interface Tx clock
7a I Balanced NI RXD+ Network Interface Rx data

8a I Balanced NI RXC+ Network Interface Rx clock
9a O CMOS A0 SU external address bit 0

12a I TTL IR11 Keyboard interrupt request HIGH
13a O CMOS IO/M I/O - Memory select signal (HIGH = I/O)

14a O CMOS IORD# I/O Read enable LOW
15a O CMOS RESET Hardware reset (SU and external units) HIGH
16a I/O TTL EXT_SU_DATA_0 External data bus bit 0


20a O CMOS FIFO_SU_0 Parallel port 1 output bus, bit 0

24a O CMOS MAVA1_SU Parallel port 1 Tx Message-Available HIGH
25a O CMOS READ1_SU# Parallel port 1 Rx read enable LOW

26a O CMOS CTRL_RPS_1 RPS directcontrol signal no.1
27a O CMOS CTRL_RPS_3 RPS direct control signal no.3
28a O CMOS RESET_RPS_SU Reset of RPS HIGH

29a I TTL DCC1_CLK DCC no.1 Rx/Tx clock
30a O CMOS DCC1_TXD DCC no.1 Tx data
31a I TTL DCC2_RXD DCC no.2 Rx data

32a GND
10 H2576
2KZ198A
(Table 3 continued: Connector P1)
Pin # I/O Level: Row c signals: Function: Active:
1c GND
2c O Balanced SCADA TXD- SCADA/SIC-1 (optionally Qx TMN) Tx data
3c I Balanced SCADA RXD- SCADA/SIC-1 (optionally Qx TMN) Rx data
4c I Balanced SCADA RXC- Optional Rx clock for synchr. TMN protocol

5c O Balanced NI_TXD- Network Interface Tx data
6c O Balanced NI_TXC- Network Interface Tx clock
7c I Balanced NI_RXD- Network Interface Rx data

8c I Balanced NI_RXC- Network Interface Rx clock
9c O CMOS A1 External address bit 1

12c O CMOS PCLK 4 MHz peripheral clock (CLK4)
13c O CMOS IOWR# I/O Write enable LOW

14c I TTL WSRQ1 Display Unit wait state request HIGH
15c O CMOS CS15# Display Unit select LOW
16c I/O TTL EXT_SU_DATA_1 External data bus bit 1


20c O CMOS FIFO_SU_1 Parallel port 1 output bus, bit 1

24c I TTL MAVA_RPS Parallel port 1 Rx Message-Available HIGH
25c I TTL READ_RPS# Parallel port 1 Tx read enable LOW

26c O CMOS CTRL_RPS_2 RPS direct control signal no.2
27c O CMOS CTRL_RPS_4 RPS direct control signal no.4
28c Not used

29c I TTL DCC1_RXD DCC no.1 Rx data
30c I TTL DCC2_CLK DCC no.2 Rx/Tx clock
31c O CMOS DCC2_TXD DCC no.2 Tx data

32c GND
H2576 11
2KZ198A
Table 4 lists the signals present on the lower connector (P2). Level specified as O.C. indicates an
open-collector output.
Table 4: Signals on connector P2.
Pin # I/O Level: Row a signals: Function: Active:
1a GND
2a +5V
3a - 5.2 V
4a + 15 V
5a - 15 V
6a O O.C. DCC1_BYP DCC no.1 Bypass enable HIGH
7a I CMOS IRQ_INP_12# Spare interrupt request input LOW

8a I CMOS IRQ_INP_13# Spare interrupt request input LOW
9a I RS-485 ACU/AAU RXD+ Internal serial bus (ACU/AAU) Rx data
10a O RS-485 ACU/AAU TXD+ Internal serial bus (ACU/AAU) Tx data

11a Not used
12a O CMOS FIFO2_SU_0 Parallel port 2 output bus, bit 0

16a O CMOS MAVA2_SU Parallel port 2 Tx Message-Available HIGH

17a O CMOS READ2_SU# Parallel port 2 Rx Read enable LOW
18a O TTL UNIT_ALM_SU SU unit alarm (open-collector output) HIGH-Z
19a I TTL ADDR_SU_0 RL-Station address bit 0


23a O CMOS SYN_CTRL_1 Sync. unit control signal no. 1
24a Not used
25a O RS-232 HCI_TXD HCI serial Tx data HIGH

26a I RS-232 HCI_RTS# HCI Request-to-send LOW
27a O RS-232 HCI_DSR# HCI Data-Set-Ready LOW
28a I RS-232 HCI_DTR# HCI Data-Terminal-Ready LOW

29a I TTL RMT_RES_SU_C1_D2 Remote reset input no. 1 HIGH
30a I TTL RMT_RES_SU_C1_D1 Remote reset input no. 3 HIGH
31a I TTL RMT_RES_SU_CP_D1 Remote reset input no. 4 HIGH

32a GND
12 H2576
2KZ198A
Pin # I/O Level Row c signals: Function: Active:
1c GND
2c +5V
3c - 5.2 V
4c + 15 V
5c - 15 V
6c O O.C. DCC2_BYP DCC no.2 Bypass enable HIGH
7c Not used
8c Not used
9c I RS-485 ACU/AAU RXD- Internal serial bus Rx data
10c O RS-485 ACU/AAU TXD- Internal serial bus Tx data

11c Not used
12c O CMOS FIFO2_SU_1 Parallel port 2 output bus, bit 1

16c I TTL MAVA_MCF Parallel port 2 Rx Message-Available HIGH

17c I TTL READ_MCF# Parallel port 2 Tx Read enable LOW
18c O CMOS TEST_MODE Test mode indicator HIGH
19c I TTL ADDR_SU_1 RL-Station address bit 1


23c O CMOS SYN_CTRL_2 Sync. unit control signal no. 2
24c Not used
25c I RS-232 HCI_RXD HCI serial Rx data HIGH

26c O RS-232 HCI_CTS# HCI Clear-to-send LOW
27c O RS-232 HCI_DCD# HCI Data-Carrier-Detect LOW
28c O CMOS RESET_ACU_AAU Reset of ACU and AAU units HIGH

29c I TTL RMT_RES_SU_CP_D2 Remote reset input no. 2 HIGH
30c O CMOS RMT_RES_SU_MOD Remote reset output (to modulator) HIGH

31c Not used
32c GND
H2576 13
2KZ198A
4 HARDWARE CONFIGURATION
Fig. 2 shows the board layout.
SMD switches S102, S201, S202 and S203 are used to configure the hardware and are described below.
Firm ware is located in IC110, IC301 and IC302.
CPU
IC101
EEPLD
ISP IC110
IC102
P1
IC309
IC301
IC310 1
ON
2
S102
1
3
4
IC302
2
1
2
S201
3
3
IC312 4
4
IC305 1 IC202
2
S202 3
4
IC313 IC306 1
S203 2
H101 3
4
ALARM LED
IC207
IC204
RESET
SWITCH IC206
S101
P2
IC208
IC113
P201
IC209
RTC
Fig.2 Printed Board Layout
14 H2576
2KZ198A
FACTORY SETTING
S102
off 1 - reserved for future use
off 3 - remote reset dir-2: ON = enabled/OFF =disabled
off 4 - remote reset dir-1: ON = enabled/OFF =disabled
SCADA/Qx Electrical Interface:

S201 RS-485 RS-232C
on 1 on off
off 2 off on
on 3 on off
off 4 off on
S202
on 1 on off
off 2 off on
off 3 - NI interface: ON= 192 kb/s synchronous/OFF= asynchr.
SCADA/Qx Interface Characteristics:

S203 SU as clock master SU as clock slave
off 1 on off
off 2 on off
Fig. 3 Factory Setting of SMD- Switches S102, S201, S202 and S203.
H2576 15
2KZ198A
5 CONNECTING A VDU TO THE SU
Connector P201 is located at the front edge of the SU board, below the reset switch.
The SU software may utilize this for printing diagnostic messages at an VT100 compatible alphanumeric
terminal (VDU). The P201 pin functions are as follows:
1 1 = SU Tx-data
2 2 = SU Rx-data
P201
3 3 = DCD #
4 4 = ground
Fig. 4 P201 Pin Functions
Note that connecting a VDU to P201 may influence the behaviour of the SU software concerning time-critical
tasks.
16 H2576
SUPERVISORY UNIT
2KZ198B
H3026 Rev. B
© Nera ASA
2KZ198B
2 H3026
2KZ198B
List of Revisions
Rev. Date What is changed
B 00-01-04 Correction in chapter 2.5.3
H3026
3
2KZ198B
Table of contents
List of Revisions ........................................................................................... 3
1.0 Technical Data Summary ............................................................................. 5
2.0 Functional Description ................................................................................. 6

2.1 Introduction......................................................................................... 6
2.2 Microcomputer Module ....................................................................... 7
2.3 Clock, Reset and Control Unit ............................................................ 7
2.4 Memory .............................................................................................. 7
2.5 Serial Interfaces ................................................................................. 7
2.5.1 DCC Interface Ports ........................................................................... 7
2.5.2 Radio Network Interface Port (NI) ...................................................... 7
2.5.3 Scada/Qx Serial Port ......................................................................... 8
2.5.4 ACU/AAU Serial Bus........................................................................... 8
2.5.5 Human Computer Interface Port (HCI) ............................................... 8
2.6 Parallel Interface ................................................................................ 8
2.7 Miscellaneous Inputs and Outputs (Misc. I/O) .................................... 8
2.7.1 Display Unit (DU) Interface ................................................................. 8
2.7.2 Radio Relay Station ID Input Port....................................................... 8
3.0 Board Interface ............................................................................................. 9
4.0 Board Layout ............................................................................................... 12
4 H3026
2KZ198B
1.0 Technical Data Summary

· CPU board for supervisory functions located in the NL29x SVCE rack
· Based on Motorola PowerQUICC microcontroller
· Flash memory for code storage
· DRAM for volatile data storage
· NV-RAM for configuration storage (battery backup)
· DMA support assures high performance for all synchronous serial ports
· Watchdog timer, RTC and programmable timers assure reliable RTOS performance
· Interrupt support for all communication ports
· Two full-duplex parallel ports provide high speed communication with RPS and MCF
· Two DCC ports
· One Scada/Qx serial port: Synchronous or asynchronous, RS-485 or RS-232C
· One NI port: Synchronous or asynchronous. RS-485, optional TP-Ethernet LAN
· One uLAN serial bus for internal communication
· Two UART serial ports, RS-232C
· Power supply: +5 V ± 0.25 V, max 1.5 A
H3026
5
2KZ198B

2.1 Introduction
The 2KZ198B CPU board acts as the Supervisory Unit (SU) in the NL29x family of Digital Radio Relay Systems.
It is based on the 2KZ198A but has some new features and improved performance; it is completely software
configurable and contains no switches or jumpers. Details on configuration of its resources are found in the User
Manual (B1055).
The SU handles the alarm and meter data storage and presentations, the operator interface (local LCD), the Scada
(or optionally Qx) interface and the DCC interface (for SDH element management).
The local operators interface is based on the Display Unit (DU), 0JK165A, and provides access to alarm status,
meter readings, general configuration and control, and Protection Switching status and control. The DU is
equipped with LEDs indicating main alarms for each channel, a graphics LCD and a keyboard for command
entering. The SU is connected to the DU through the back panel connectors.
The main tasks for the Supervisory Unit is to

· Meet the high speed serial interface requirements of SDH
· Support the needs of modern TMN systems
· Support local and remote data acquisition through the ACUs and AAUs
· Relieve the Protection Switching system from demanding communication and user interface tasks
Fig. 1 shows a functional block diagram of the SU.
Micro computer
DCC1
module
(powerQUICC) DCC2
Serial NI
Clock and interface Scada/Qx
reset
HCI
ACU/AAU
TP-LAN Ethernet
RJ45 XCVR
(option)
Parallel FIFO1
Memory interface
FIFO2
5V Power DU
RTC
distr. &
Misc. I/O
filtering Station ID
Euro connectors
Fig. 1 Supervisory Unit Block Diagram
6 H3026
2KZ198B
2.2 Microcomputer Module

The Microcomputer module is based on a PowerQUICC microcontroller which contains CPU, interrupt
controller, DMA controller, memory controller, bus interface unit, timers/counters, parallel I/O, UARTs and serial
communication controllers.
2.3 Clock, Reset and Control Unit

A 4 MHz clock source drives the clock synthesizer in the PowerQUICC. The CPU clock speed is software
programmable and will typically be around 40 MHz. System reset is a combination of power-on reset, manual
hardware reset (push-button S101 at the front edge of the board) and watchdog timer reset.
The 4 MHz clock signal is also used as peripheral clock for the DU interface. A separate crystal oscillator supplies
the uLAN UART with the appropriate clock signal for its baud rate generator. Various glue logic is implemented
in a JTAG-programmable CPLD.
2.4 Memory
Memory consists of DRAM for data storage, Flash for code storage and NV-RAM (battery-backed SRAM) for
configuration data storage. The Flash memory is divided into a boot code store and an application code store.
The Flash memory supports software download via a serial interface.
The backup battery is a standard 3V Lithium type placed in a socket (P8400).
2.5 Serial Interfaces

All the serial interfaces except the ACU/AAU serial bus are handled by PowerQUICC built-in serial
communication controllers. DCC, NI and Scada/Qx serial ports all have DMA support by the PowerQUICC built-
in DMA controller.
2.5.1 DCC Interface Ports

The two Data Communication Channels (DCC1, DCC2) are 192 kb/s (D1-D3 of SOH) or 576 kb/s (D4-D12
of SOH) synchronous serial channels connected to an RSOH Adapter within the Service rack (the physical
connections are established via the back panel, electrical interface is TTL). They are used for communication
with SUs at remote stations. The baud rate is determined by the RSOH Adapter. Each channel employs DMA
channels for full-duplex data transfer between memory and Rx-/Tx-machine.
The DCC interface includes two control signals which may set the RSOH Adapter in bypass mode. Bypass of
each DCC can be controlled individually by software. If the SU is reset these signals go active until they are cleared
by the software.
2.5.2 Radio Network Interface Port (NI)

One radio Network Interface port (NI) is available for communication between two SUs located at the same radio
relay site. This interface may be asynchronous with data rates up to 115 kb/s, or synchronous with data rates
up to approx. 8 Mb/s. It employs DMA channels for full-duplex data transfers between memory and Rx-/Tx-
machine. The physical attachment is a 15 pin Dsub connector in the back panel. Electrical interface is RS-485.
Optionally this port can be configured as a Twisted-pair Ethernet (10-BASE-T) LAN port providing the necessary
hardware resources for employment of layered communication protocol software. For this option the physical
attachment is the RJ-45 connector (P8317) at the front edge of the board, made available through a cutout in
the cassette cover (ref. Operators Guide for configuration details).
H3026
7
2KZ198B
2.5.3 Scada/Qx Serial Port

One Scada/Qx serial port is available for communication with SCADA/SIC equipment or other proprietary (Qx)
element management systems. This interface may be asynchronous with data rates up to 115 kb/s, or synchronous
with data rates up to approx. 8 Mb/s. In synchronous mode an external serial clock is required. It employs DMA
channels for full-duplex data transfers between memory and Rx-/Tx-machine.
The physical attachment is a 9 pin Dsub connector in the back panel. Electrical interface is RS-232C or
RS-485 (ref. Operators Guide for configuration details).
2.5.4 ACU/AAU Serial Bus

The alarm and meter data capture and the remote control functions for the supervisory system is handled by
several peripheral units called Alarm Collection Units (ACU) and Alarm Adapter Units (AAU). Communication
between the SU and these peripherals is provided by an asynchronous serial bus distributed through the back
panel connector.
2.5.5 Human Computer Interface Port (HCI)

An RS-232C serial port is available for use as a HCI (for console I/O via a PC, an alphanumeric terminal or a
telephone modem). The serial lines are available on a 9 pin Dsub in the back panel.
2.6 Parallel Interface

The SU is equipped with two high speed parallel interfaces with FIFOs. These are used for communication with
the RPS board and the optional Q-Adapter board (MCF). The physical connections are established via the back
panel. Electrical interface is TTL.
2.7 Miscellaneous Inputs and Outputs (Misc. I/O)

2.7.1 Display Unit (DU) Interface
The DU bus interface physical connection is made through the back panel connector.
2.7.2 Radio Relay Station ID Input Port

An 8-bit input port for Radio Relay station identification is provided via the back panel connector. This input
port is programmed bit-by-bit on a DIP-switch located in the back panel to set the local station number. The
resulting 8-bit pattern is read by the software.
8 H3026
2KZ198B
3.0 Board Interface

The board is equipped with two back panel connectors of 64 pins each which carries the signals listed in the
following tables. Signal level O.C is of type open collector, signal level Balanced refers to signals with
configurable line driver types. These signals conform to either RS-232C or RS-485 electrical interface standard.
A # suffix in the signal name indicate active low logic. Unconnected pins are marked n.c..
Table 1: Signals on connector P1

Pin # I/O Level: Signal: Function:
1a GND Ground
1c GND Ground
2a O Balanced SCADA TXD+ SCADA/Qx Tx data
2c O Balanced SCADA TXD SCADA/Qx Tx data
3a I Balanced SCADA RXD+ SCADA/Qx Rx data
3c I Balanced SCADA RXD SCADA/Qx Rx data
4a I Balanced SCADA RXC+ Optional Rx clock for synchr. protocol
4c I Balanced SCADA RXC Optional Rx clock for synchr. protocol
5a O RS-485 NI TXD+ Network Interface Tx data
5c O RS-485 NI TXD Network Interface Tx data
6a O RS-485 NI TXC+ Network Interface Tx clock
6c O RS-485 NI TXC Network Interface Tx clock
7a I RS-485 NI RXD+ Network Interface Rx data
7c I RS-485 NI RXD Network Interface Rx data
8a I RS-485 NI RXC+ Network Interface Rx clock
8c I RS-485 NI RXC Network Interface Rx clock
9a O CMOS A0 DU bus interface
9c O CMOS A1 DU bus interface
12a I TTL IR11 DU bus interface
12c O CMOS PCLK DU bus interface
13a O CMOS IO/M DU bus interface
13c O CMOS IOWR# DU bus interface
14a O CMOS IORD# DU bus interface
14c I TTL WSRQ1 DU bus interface
15a O CMOS RESET DU bus interface
15c O CMOS CS15# DU bus interface
H3026
9
2KZ198B
Table 1 continued : Signals on connector P1

24a O CMOS MAVA1_SU Parallel port 1 Tx Message-Available
24c I TTL MAVA_RPS Parallel port 1 Rx Message-Available
25a O CMOS READ1_SU# Parallel port 1 Rx read enable
25c I TTL READ_RPS# Parallel port 1 Tx read enable
26a O CMOS CTRL_RPS_1 RPS direct control signal no. 1
26c O CMOS CTRL_RPS_2 RPS direct control signal no. 2
27a O CMOS CTRL_RPS_3 RPS direct control signal no. 3
27c O CMOS CTRL_RPS_4 RPS direct control signal no. 4
28a O CMOS RESET_RPS_SU Reset of RPS
28c n.c. unused
29a I TTL DCC1_CLK DCC no.1 Rx/Tx clock
29c I TTL DCC1_RXD DCC no.1 Rx data
30a O CMOS DCC1_TXD DCC no.1 Tx data
30c I TTL DCC2_CLK DCC no.2 Rx/Tx clock
31a I TTL DCC2_RXD DCC no.2 Rx data
31c O CMOS DCC2_TXD DCC no.2 Tx data
32a GND Ground
32c GND Ground
Table 2: Signals on connector P2

1a GND Ground
1c GND Ground
2a + 5 V DC Supply voltage
2c + 5 V DC Supply voltage
3a n.c. unused
3c n.c. unused
4a n.c. unused
4c n.c. unused
5a n.c. unused
5c n.c. unused
6a O CMOS DCC1_BYP DCC no.1 Bypass enable
6c O CMOS DCC2_BYP DCC no.2 Bypass enable
7a I CMOS n.c. unused
7c n.c. unused
8a I CMOS n.c. unused
8c n.c. unused
9a I RS-485 ACU/AAU RXD+ Internal serial bus (ACU/AAU) Rx data
9c I RS-485 ACU/AAU RXD Internal serial bus (ACU/AAU) Rx data
10a O RS-485 ACU/AAU TXD+ Internal serial bus (ACU/AAU) Tx data
10c O RS-485 ACU/AAU TXD Internal serial bus (ACU/AAU) Tx data
11a n.c. unused
11c n.c. unused
10 H3026
2KZ198B
Table 2 continued: Signals on connector P2

16a O CMOS MAVA2_SU Parallel port 2 Tx Message-Available
16c I TTL MAVA_MCF Parallel port 2 Rx Message-Available
17a O CMOS READ2_SU# Parallel port 2 Rx Read enable
17c I TTL READ_MCF# Parallel port 2 Tx Read enable
18a O O.C. UNIT_ALM_SU SU unit alarm
18c O CMOS TEST_MODE Board test mode indicator
19a I TTL ADDR_SU_0 RR Station address bit 0
19c I TTL ADDR_SU_1 RR Station address bit 1
23a O CMOS SYN_CTRL_1 Sync. unit control signal no. 1
23c O CMOS SYN_CTRL_2 Sync. unit control signal no. 2
24a n.c. unused
24c n.c. unused
25a I RS-232 HCI_RXD HCI serial Rx data
25c O RS-232 HCI_TXD HCI serial Tx data
26a I RS-232 HCI_RTS# HCI Request-to-send
26c O RS-232 HCI_CTS# HCI Clear-to-send
27a O RS-232 HCI_DSR# HCI Data-Set-Ready
27c O RS-232 HCI_DCD# HCI Data-Carrier-Detect
28a I RS-232 HCI_DTR# HCI Data-Terminal-Ready
28c O CMOS RESET_ACU_AAU Reset of ACU and AAU units
29a I TTL RMT_RES_SU_C1_D2 Remote reset input no. 1
29c I TTL RMT_RES_SU_CP_D2 Remote reset input no. 2
30a I TTL RMT_RES_SU_C1_D1 Remote reset input no. 3
30c O CMOS RMT_RES_SU_MOD Remote reset output (to modulator)
31a I TTL RMT_RES_SU_CP_D1 Remote reset input no. 4
31c n.c. unused
32a GND Ground
32c GND Ground
H3026
11
2KZ198B
4.0 Board Layout

Fig. 2 shows the board layout.
3
3
3
+
6
3
Fig. 2 2KZ198B board layout
12 H3026
Q-ADAPTER
2KZ223A
H2988 Rev. B
© Nera ASA
2KZ223A
2 H2988
2KZ223A
TABLE OF CONTENTS
Page:
1. INTRODUCTION 4
1.1 SUMMARY
1.2 Add-on package for Q3 based management 4
1.3 Notes on installation in existing NL290 equipment 4
2. HARDWARE FUNCTIONAL DESCRIPTION 6
2.1 Microprocessor 7
2.2 Bus Control Unit 7
2.3 DRAM Control Unit 7
2.4 JTAG/PLD 7
2.5 Clocks 7
2.6 Reset circuitry 7
2.7 Boot FLASH/boot PROM 7
2.8 FLASH PROM 7
2.9 Dynamic RAM module 8
2.10 Ethernet Controller 8
2.11 Attachment Unit Interface (AUI) 8
2.12 Parallel input 8
2.13 Parallel output 8
2.14 Asynchronous serial communication 8
2.15 First-In First-Out 8
2.16 External I/O 8
2.17 Power supply 8
3. BOARD INTERFACE 9
3.1 Connectors, LEDs and switches 9
3.2 DIL switch settings 9
3.3 Back panel interface 11
4. SOFTWARE UPGRADE PROCEDURES 13
4.1 Updating the Q-Adapter boot PROMs 13
4.2 Loading a new Agent s.w. version 13
5. PINNING OF SERIAL PORTS COM1/COM2 14
H2988
3
2KZ223A
1. INTRODUCTION
1.1 Summary 1.2 Add-on package for Q3 based

management
The 2KZ223A Q-Adapter is an optional board designed
to fit in the same cassette as the Supervision Unit (SU) The NL290 family of RR Terminal stations may
board within the Auxiliary shelf (SVCE rack) of an support Q3 Management communication by adding
NL290 family RR station. It provides an Ethernet LAN the following optional hardware:
based Q3 Management interface for these systems. This
board together with an embedded software package ● 2KZ223A Q-Adapter card
(consisting mainly of an RTOS and a Q3-B3 protocol ● UWMK2881 AUI cable
machine, ref CCITT recommendation G.773) serves as ● Off-the-shelf IEEE 802.3 Ethernet
a general Agent platform. The type and extent of network Transceiver (AUI-to-BNC or AUI-to-TP)
element information flowing across the Q3 port is ● For NL290 systems with Supervision Unit
specified by an Information Model which serves as a (SU) firmware releases lower than R15D,
common interface specification between the NL290 a set of PROMS for upgrading the SU will
Network Element and an Element Management System be required
(EMS). The Q-Adapter may support a number of different
Information Models, each tailored to fit the requirements Figure 1.1 shows how this is physically installed in
of one specific EMS, by loading it with the appropriate the Auxiliary shelf (SVCE rack) of the NL290
type of Agent SW. equipment. The installation can easily be performed
on existing equipment in the field, even when carrying
Basically the Q-Adapter performs information mapping live traffic, provided that a temporary inhibition of the
from the proprietary Q1 protocol supported by the built- Protection Switching system is acceptable.
in Supervision Unit (SU), to the standardised Q3-B3
protocol. This information mapping is defined by the
Information Model for the RR Network Elements, and 1.3 Notes on installation in existing NL290
implemented by the NL290 Agent Software equipment
(SW2KZ223A-<version_id>) running on the 2KZ223A
Q-Adapter board. The Q3 interface uses IEEE 802.3 The Nera proprietary multi-RR-sections Supervisory
Ethernet as its physical layer. communication based on the NI ports controlled by
the SU will not be available in Terminal stations that
The board is delivered with the firmware components is equipped with a Q-Adapter. If the Nera NEW PC-
and with a preinstalled globally unique Ethernet MAC based supervision facility is to be used in locations
address from the Nera address range 00-60-C0-xx-xx- with clusters of RR stations of which some are
xx. This 6 bytes MAC address forms a part of the 20 equipped with Q-Adapters, these stations will have to
bytes NSAP address for the Agent. The remaining 14 be interconnected by using the Qx port of the SU.
bytes of the NSAP will in most systems remain fixed and
hardcoded in the Agent SW, but this may change in the
future.
4 H2988
2KZ223A
The LAN port of the Q-Adapter will use the J16 on the built-in Operators Panel:
connector in the Auxiliary shelf back panel, which • Enter the “Configuration - Network setup -
might already be in use by the local SU (this is the Ni setup” menu
“NI” port). If this is the case, the Q-Adapter LAN • Select the “No Ni” option and push <EXE>
port signals will be disturbed by the SU and will not followed by <HOME>
function properly. To assure safe and reliable
operation of the LAN port via an AUI cable This will disconnect the SU “Ni” communication port
connected to J16, one should take the following steps from the J16 connector, making it available for use as
a LAN port.
Transceiver
AUI Cable
J16 D-sub Distr. Board

female EW53A
RPS
Supervision Unit (SU)
Q-Adapter
RSOH Adapter
ACU
Fig.1.1: Q-Adapter in NL290 SVCE rack
H2988 5
2KZ223A
2. HARDWARE FUNCTIONAL DESCRIPTION
Figure 2.1 illustrates the hardware architecture of the board. The following sections contain brief descriptions
of the functional blocks.
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Fig.2.1: Q-Adapter block diagram
6 H2988
2KZ223A
2.1 Microprocessor
The 386EX embedded microprocessor runs at 25 A clock divider circuit generates a 20 MHz clock
Mhz. It has a 16 bit wide data bus and may address up from the 40 MHz reference, which then is used as the
to 64 Mbytes of memory and/or I/O. All of the timing reference for the Ethernet physical interface
386EX controlled chip-select signals and I/O and implemented through the Dual Serial Transceiver
memory addresses are latched and all data lines are (DST) device. The accuracy required (0.01 %
buffered. The address latches and data buffers serve as deviation) is achieved by selecting a 100 ppm device
3-state buffers towards the I/O and memory address for the 40 MHz reference oscillator.
and data buses.
A 11.0592 MHz clock is used for the baud rate
2.2 Bus Control Unit generation of the asynchronous serial ports (COM1,
COM2).
The Bus Control Unit (BCU) is a PLD which
implements most of the glue logic required to 2.6 Reset circuitry
interface the bus masters (CPU, SONIC) to the
system buses and to the memories and peripherals The reset control circuitry covers power-up reset,
available. manual reset, and watchdog reset. Power-up reset is
provided by a voltage supervision device.
2.3 DRAM Control Unit A DIL-switch (S501.2) is available for hardware
enable/disable of the watchdog timeout reset (external
The DRAM Control Unit (DCU) is a PLD which fixed interval ORed with 386EX internal watchdog).
implements the specific control signals required to See Table 3-3 for switch setting information.
read, write and refresh a standard 16 MB DRAM
Single-in-line Memory Module (SIMM). 2.7 Boot FLASH/boot PROM
2.4 JTAG/PLD Two PLCC PROM or FLASH devices are mounted

in sockets. These are 8-bit wide devices (e.g.
The JTAG connector is used for in-circuit 27C040), thus odd and even bytes have to be
programming of the PLDs. programmed separately when preparing a set of
PROMS. Maximum size supported is 1 MB. These
2.5 Clocks are used for boot (startup) code storage.
The main system clock source is a 50 MHz crystal 2.8 FLASH PROM
oscillator. This is the timing reference for the 386EX
as well as the BCU and DCU. Further it is used as The FLASH PROM contains 4 devices of type
input to a clock divider circuitry for generation of a 29F016 (2Mx8) totalling 8 MB. This is used as
25 MHz clock used as the bus clock input to the application code storage.
SONIC.
H2988
7
2KZ223A
2.9 Dynamic RAM module 2.12 Parallel input

The DRAM SIMM interface is based on a 72-pin This module contains bus transceivers and termination
horizontal SIMM socket. The SIMM must satisfy the circuitry for four input ports which may be read by the
following requirements: CPU:
- +5V supply · Unit Address (16 bit wide), for switch
- 4x32Mbit configuration (16 MB) setting see Section 3.2
- Single sided component placement (to · Miscellaneous Control & Status (16 bit
allow mounting in horizontal socket) wide)
- Access time 70 ns or lower · Memory configuration 0 (16 bit wide)
- RAS-only refresh · Memory configuration 1 (8 bit wide)
- Fast page mode
2.13 Parallel output
2.10 Ethernet Controller This module contains one 16-bits output register used
The Ethernet Controller chip is the 25 MHz National to hold various control output states as set by the
Semiconductor SONIC device (DP83932B or CPU.
DP83932C). This device has built-in DMA channels
for transferring Ethernet packets to/from system 2.14 Asynchronous serial communication
memory. The SONIC device is connected directly to The RS-232C (DCE) serial ports COM1 and COM2
the CPU buses since it will act as a second bus master have on-board connectors (9-pin D-sub and 8-pin
when accessing system RAM. Bus arbitration is to be Modular respectively). COM1 is used for SW
controlled by the BCU. The SONIC is using an download, while COM2 is used for console I/O.
external ENDEC device and supports various types of
s.w. controlled loopback testing. A miniature LED 2.15 First-In First-Out
will indicate when the SONIC is running ENDEC This module contains a FIFO device for parallel
loopback testing (LBK). communication with the SU.
2.11 Attachment Unit Interface (AUI) 2.16 External I/O

This module contains the Ethernet Attachment Unit This part contains the bus transceivers and
Interface (AUI). The main function of this module is termination circuitry needed for interfacing the
covered by the Dual Serial Transceiver device (DST, external 8-bit SU data bus to the system I/O data bus:
Intel 82503), which implements the Manchester
encoder/decoder (ENDEC) function together with 2.17 Power supply
balanced drivers/receivers for AUI. This device The 2KZ223A gets its power from the back panel
supports ENDEC loopback control and provides through one of the two EURO connectors (P2) and
LED driver outputs for status indications. Outputs for utilises soft power-on functionality to avoid power
the following status signals are connected to on-board surge spikes on the main supply lines during board
miniature LEDs: insertion. Required supply current is approx. 1 A on
the 5 V supply and 0.1 A on the 15 V supply.
- Tx Activity
- Rx Activity The +5V power supply distribution is divided into
- Collision Detect several separate supply lines all originated at the rear
- Link Integrity Test edge connectors but with individual power supply
- Polarity Reversed Detect filtering circuitry. This will limit the propagation of
supply noise from one device to another, and lower
In order to work properly, the switches S203 and the overall supply noise level. All ICs have supply
S401 must be set correctly. filtering/decoupling capacitors.
see Table 3-1 and Table 3-2.
8 H2988
2KZ223A
3. Board Interface
3.1 Connectors, LEDs and switches · LAN STATUS: LAN diagnostic LEDs:
· -LBK: Encoder/decoder loopback (test
Figure 3.1 illustrates some noticeable facilities mode)
located at the front edge of the board: · -LNK: Link integrity monitored bad
· -POL: Polarity inversion detected
· COM1 serial port, 9-pin D-sub connector · -COL: Collision activity detected
(RS- 232C), transmitting on pin 2, · -RX: Receive activity detected
receiving on pin 3. · -TX: Transmit activity detected
· COM2 serial port: ISDN connector (RS- · DIAGNOSTICS: Test and diagnostic LEDs
232C), transmitting on pin 2, receiving on
pin 3. 3.2 DIL switch settings
· JTAG port: 10-pin connector. Used for in- Factory setting of the DIL switches is as folllows:
circuit PLD programming.
· RESET: Hardware reset push-button. · S201: All OFF
· UNIT ALARM: Board alarm LED (if lit, · S202: All OFF
it indicates that the unit did not initialise · S203: See Table 3-1.
properly and may be damaged) · S401: See Table 3-2.
· S501: See Table 3-3.
1 2 3 4 5 6 7 8
OFF ON OFF OFF OFF OFF OFF OFF
Table 3-1: S203 switch settings.
1 2 3 4 5 6 7 8
ON OFF ON OFF ON OFF ON OFF
1 2 3 4
OFF ON OFF OFF
H2988
9
2KZ223A
LBK H401 S401

LNK H402 ON
POL H403
COL H404 T402 OFF
RX H405 IC409 12345678
TX H406
T401
IC501
IC410
COM2 J502
P1
IC508
JTAG P501
IC505
IC507
X501
IC104 8
IC510
OFF S202
COM1 J501
1
ON
IC105 8
IC509
S501
S201
1
ON OFF
Reset S502 IC304 IC303
Alarm
H202
IC502
IC311 IC310
IC313 IC312
H205
H204
P2
Diag. IC118
H203
IC213
H202
IC119 S203
DRAM MODULE ON OFF
Fig. 3.1 2KZ223A Board Layout
10 H2988
2KZ223A
3.3 Back Panel Interface
The board is equipped with two 64 pins back panel connectors which are described in the following tables.
The symbols used in the signal type column are as follows:
I - input sup - power supply

O - output b - balanced signal
T - output with 3-state capability oc - open collector output
A # indicates active LOW signal.
Pin Type Function Pin Type Function
1a sup GND 1c sup GND

2a not used 2c not used
5a O(b) Network AUI/TP TXD+ (DO-A, p3) 5c O(b) Network AUI/TP TXD- (DO-B, p10)
6a sup Network AUI +12V (not standard) 6c sup Network AUI GND (not standard)
7a I(b) Network AUI/TP RXD+ (DI-A, p5) 7c I(b) Network AUI/TP RXD- (DI-B, p12)
8a I(b) Network AUI CI+ (CI-A, p2) 8c I(b) Network AUI CI- (CI-B, p9)

16a T(I) Parallel port Tx D0 (SU extern. data) 16c T(I) Parallel port Tx D1 (SU extern. data)



Table 3-4 Signals on connector P1 (upper connector).

H2988
11
2KZ223A
Pin Type Function Pin Type Function

2a sup + 5 V ± 0.25 V 2c sup + 5 V ± 0.25 V
3a not used (- 5.2 V) 3c not used (- 5.2 V)
4a sup + 15 V ± 0.5 V 4c sup + 15 V ± 0.5 V
5a not used (- 15 V) 5c not used (- 15 V)


12a I Parallel port Rx D0 12c I Parallel port Rx D1
16a I Msg. avail. irq from SU 16c O Msg. avail. irq to SU

17a I FIFO RD# input from SU 17c O FIFO RD# output to SU
18a oc Unit Alarm 18c not used



12 H2988
2KZ223A
4. SOFTWARE UPGRADE
PROCEDURES
4.1 Updating the Q-Adapter boot PROMs
The board contains two socketed firmware board. Note that the Agent functionality will NOT
components (PROMs), IC303 and IC304 in Figure stay operational during s.w. download. The Agent
3.1, which hold the boot software. If upgrades to this SW will be available as a data file on diskettes or as a
firmware components should be required, Nera will file to be transferred via Internet (email or ftp).
provide new sets of devices. Replacement of the
devices requires use of a specific extraction tool (Nera Serial cable specification:
ref. VS-92H1A-1). Note also that the two devices are
different in their contents and will not function if · One 9-pin to 9-pin cable, Nera part no.
mounted in the wrong socket. During this kind of UWMK2808
operation one should take precautions to protect the · One 9-pin to ISDN cable, Nera part no.
equipment against static electricity. 87W46-5
IC303 and IC304 boot firmware components PC serial port requirements: 16450/16550 compatible
delivered by Nera will be marked 223A-303-Rxx UARTs supporting 115 kbaud transfer rate.
and 223A-304-Rxx respectively, where xx is the
boot s.w. release number. The download feature running from the boot s.w. in
the Q-Adapter will need to interact with a VT-100
compatible terminal emulator running under Windows
4.2 Loading a new Agent s.w. version 3.11 on the PC. The terminal emulator should be set
up to communicate via a COM-port connected to the
By installing a Nera proprietary download program Q-Adapter COM2 port.
on a 486 or Pentium PC (with DOS6.x and Windows
3.11 installed) and connecting it to the 2KZ223A For detailed description of the download procedure
board by two serial cables, new software versions may please refer to the documentation accompanying the
be downloaded to the Flash memory devices of the DOS-based download utility.
H2988
13
2KZ223A
5. Pinning of serial ports COM1/COM2
Pinning for the serial ports COM1 and COM2 for the Q-adapter is previously not described in the user manual
for NL 290-family STM-1 Radio-Relay Equipment.
COM1
The Q-adapter COM1 port (9 pin female D-SUB connector) looks like a DCE.
COM1 is used for software download from a PC.
Pinning for COM1:
Pin # Signal name Comments
1 DCD Q-adapter drives this signal

2 RXD Q-adapter transmits on pin 2
3 TXD Q-adapter receives on pin 3
4 DTR
5 GND
6 DSR Q-adapter drives this signal
7 RTS PC
8 CTS Q-adapter drives this signal
9 RI Q-adapter drives this signal
COM2
The Q-adapter COM2 port (8 pin RJ45 connector) looks like a DCE.
COM2 is used to communicate with a VT-100 terminal or a compatible terminal emulator on a PC.
Pinning for COM2:
Pin # Signal name Comments
1 GND
2 RXD Q-adapter transmits on pin 2
3 TXD Q-adapter receives on pin 3
14 H2988
RADIO PROTECTION
SWITCHING UNIT
2SK220A
H2577 Rev. B
© Nera AS
2SK220A
TABLE OF CONTENTS
1. INTRODUCTION: ..................................................................................................... 4
2. TECHNICAL DATA .................................................................................................. 4
3. DESCRIPTION ......................................................................................................... 5
3.1 General ........................................................................................................ 5
3.2 Microcomputer System ................................................................................ 5
3.2.1 Clock Generator........................................................................................... 5
3.2.2 Watchdog and Voltage Supervision ............................................................ 5
3.2.3 Timing System ............................................................................................. 5
3.2.4 Interrupt System........................................................................................... 5
3.2.5 Microprocessor and Bus Interface ............................................................... 5
3.2.6 Flash VPP (Optional) ................................................................................... 7
3.2.7 Memory and I/O Address Decoding.................... ......................................... 7
3.2.8 Memory........................................................................................................ 7
3.2.9 Wait State Generator....................................................................................7
4. MISCELLANEOUS CONTROL AND COMMUNICATION ...................................... 7

4.1 Miscellaneous Control ................................................................................. 7
4.2 Parallel Interface .......................................................................................... 7
4.3 Synchronous Serial Interface....................................................................... 7
4.4 Asynchronous Serial Interface ..................................................................... 8
5. ALARM INTERFACE ............................................................................................... 8
6. BOARD INTERFACE .............................................................................................. 9
7. SYSTEM CONFIGURATION ................................................................................. 17
2 H2577
2SK220A
1 INTRODUCTION
RPS is an abbrevation for radio protection switching.
The RPS unit handles all functions concerning radio protection switching of the SDH radio link system.
Operator interface will be through a parallel interface with the Supervisory Unit (SU).
2 TECHNICAL DATA
Microprocessor: 8088 compatible 8MHz version (20 bit address, 8 bit data)
Crystal Frequency: 24.0000 MHz
Wait State Generator 0 to 4 wait states (switch select)
Watchdog Timer 1.6 seconds time-out, or disabled.

Watchdog rundown LED indicator
Interrupt Levels: 16
Timing System: Operating system time-base

One programmable interval timer
Memory Capacity Memory size configurable through EPLD
128Kbytes (- 512Kbytes) of EPROM
512Kbytes of FLASH (Optional)
32Kbytes (- 128Kbytes) of RAM
8Kbytes (- 64Kbytes) of EEPROM
Serial Communication: Two channels, synchronous 64 Kbit/s, CMOS
One channel, asynchronous RS-232
Parallel Interface: One interrupt driven 8-bit bi-directional FIFO interface
Alarm Output: Watchdog/Low voltage alarm
Alarm Inputs: 64 alarm inputs with open collector interfaces

for handling digital alarm signals.
Reset & Power Down Protection: CPU and peripherals are reset and non-volatile memory
(EEPROM and FLASH) is write protected during
power up/down.
Ambient Operating Temperature 0ºC to +70ºC
Storage Temperature -40ºC to +70ºC
H2577
3
2SK220A
The following conditions will result in a CPU reset:

3 DESCRIPTION
• Power up / power drop
3.1 General: • External reset from SU.
The RPS unit is divided into the following main
functional blocks: • Manually reset by push button operation.
- MICROCOMPUTER SYSTEM • Reset when there is program execution failure.

(The watch dog must receive refresh pulses
- MISCELLANEOUS CONTROL AND generated by the running program to prevent reset
under normal operation.)
COMMUNICATION
3.2.3 Timing system:
- ALARM INTERFACE
The Timing control block consists of a Programmable
- BOARD INTERFACE Interval Timer (PIT) . This chip contains three individual
timers:
3.2 Microcomputer System:
• Timer-A: Input is PCLK=1/2*CLK(processor clock)
The microcomputer system contains the following func-
The timer is used as an intermediate clock.
tional blocks:
• Timer-B: Input is the intermediate clock. The timer
1. Clock generator
is used as the operational systems time base.
2. Watchdog and voltage supervision
• Timer-C: Input is the intermediate clock. The timer
3. Timing system is used as a programmable hardware delay timer.
4. Interrupt system 3.2.4 Interrupt system:

Interrupt control is taken care of by two Programma-
5. Microprocessor and bus interface(CPU) ble Interrrupt Controllers in a master and slave
6. Flash VPP supply (Optional)
configuration.
3.2.5 Microprocessor and bus interface:
7. Memory and I/O address decoder
The 8088 microprocessor and the surrounding
8. Memory functions are designed to run with 8 MHz CPU clock
frequency.
9. Wait state generator
• Data bus transceiver:
The 8088 microprocessor have multiplexed address

3.2.1 Clock Generator:
and data AD0..AD7 and requires an external bus
transceiver to interface the RPS data-bus.
A clock generator/driver and a xtal of 24. 0000MHz will
provide the system clock of 8MHz and a peripheral clock • Address latch low / high:
of 4MHz in addition to the synchronised ready and reset
signals. Interfacing the microprocessors multiplexed address/
data bus and the RPS address bus, requires latches on
3.2.2 Watchdog and voltage supervision: address bits AD0..AD7 and A16..A19. Two octal
The security block contains an integrated voltage super- latches provide the function. The ALE (address
vision and watchdog circuit. latch enable) and HLDA (hold acknowledge) output
from the 8088 control the latch enable and 3-state
The watchdog circuit will provide a 200ms reset pulse, and function of latches.
the refresh interval required is less than 1.6 sec.
4 H2577
2SK220A
MICRO COMPUTER SYSTEM
AD0..7 DB.TRANS ADRESS BUS
CPU
A8..19 DATABUS
8088 ADR. LATCH
CONTROLBUS
compa- DMA -
tible ADR.LATCH
WAIT- MEMORY
CLOCK
STATE- & I/0 EEPROM
GEN
GEN ADR.DEC
W.DOG &
RAM
POWER -
SUPERV.
TIMING
EPROM
SYSTEM
PIC FLASH-
MASTER MEMORY
(OPTIONAL)
FLASH
PIC
VPP-
SLAVE
SUPPLY
(OPTIONAL)
MISCELLANEOUS CONTROL ALARM INTERFACE

&
COMMUNICATION. SCC
ALARM
INTERFACE
PPI_0
DMA
ACC &
PPI_1
RS232
PU C TR LBU S
U N P R IO B U S
ALM BU S
D EM BU S
R D U BU S
XSU BU S
BOARD INTERFACE
CONN P1
PARALLEL-
FIFO-
CONN P2
INTERFACE
CONN P3
SUBUS-
TESTBUS
MS2BUS
Figure 1: RPS Block Schematic Diagram

H2577
5
2SK220A
• DMA address latches:
The DMA requires a page address latch for address 4 MISCELLANEOUS CONTROL
bits A16..A19, and an address latch for address bits
A8..A15. The page address latch inputs are program- AND COMMUNICATION
mable through an output portconnected to the 4 least The miscellaneous control and communication sys-
significant bits of the latched data bus. tems contain the following functional blocks:
• Read/ Write select: 1. Miscellaneous control
The following four signals from the 8088 chip: 2. Asynchronous serial interface
RD (read), WR (write), IO/M (IO/memory access), 3. Parallel interface
HLDA (hold acknowledge) are inputs to a quad 2-
input multiplexer with 3-state outputs in a manner to 4. Synchronous serial interface
generate individual IO and memory read/write sig-
nals. HLDA is controlling the 3-state function.
3.2.6 Flash VPP (Optional): 4.1 Miscellaneous control:
A +12V ± 5% voltage regulator provides FLASH Two programmable peripheral interface chips (PPI),
Vpp (programming supply voltage). in addition to some general purpose control pins on
SCC/ACC chips, are used as drivers and receivers of
3.2.7 Memory and I/O address decoding: different control signals. Each PPI contains three 8
Memory and I/O addresses are decoded by means bits ports which can be configured as inputs or
of an EPLD(erasable programmable logic device), outputs, and provides the system with a maximum of
giving a flexible memory map. 48 control lines.
4.2 Parallel interface:

3.2.8 Memory:
The memory consists of 4 different chips: A 512 byte FIFO provides a parallel interface for
communication with the SU unit.
The outgoing data-bus is driven by the FIFO chip.

Memory type: Capacity and comments: Socket: The incoming data-bus is input to an octal D-type
RAM 32Kbytes (-128Kbytes) for data latch interfacing the local databus.
FLASH MEMORY 512Kbytes.(Optional) Internal control signals are provided by the address
decoder chip.
EEPROM 8Kbytes (- 64Kbytes) for
parameter storing
EPROM 128Kbytes (- 512Kbytes) for 4.3 Synchronous serial interface

main program X The serial interface consists of two synchronous
communication channels intended to interface the
Table 1 : Memory capacity and comments Adapter RSOH (direction UP and DOWN) used to
Program code is stored in EPROM. access the MS2 byte of the STM1 frame. The MS2
A FLASH memory is Optional. byte represents a 64Kb/s channel used for communi-
cation between the RPS units in the switching
3.2.9 Wait state generator: section.
Some of the peripheral IC’s do not match the 8MHz
speed requirement, hence wait state generator logic The interface is DMA driven and consists of one
is implemented. The number of wait states generated dual serial communication controller(SCC) and one
(0, 1, 2, 3,4) can be selected by switches. The wait DMA controller.
state generation logic is of the “normal ready” type.
6 H2577
2SK220A
Tx /Rx clock is provided by the Adapter RSOH. group with an interrupt.

(Only one clock is input to the interface pr.channel).
For each group :
Considering the short signal path to the Adapter
RSOH, the format is CMOS. A change in alarm state (alarm on / alarm off) will
trigger the interrupt generator logic. The interrupt
Two general output pins on the SCC are used to active state is latched until acknowledged by soft-
control the bypass function of the order communica- ware.
tion channels at the RSOH adapter. The bypass
function is software controlled in addition to auto- The Alarm Acknowledge pulse will latch the current
matic enabling of bypass when reset of the RPS alarm status into the Alarm Register, clear the inter-
rupt signal and enable the interrupt logic.
4.4 Asynchronous serial interface:
The alarm status is now available for software to
One asynchronous communication channel leads to
perform an I/O read at address of the alarm status
a 4 pin connector P3 intended for connection of an
latch. The I/O read operation will put the content of
alphanumeric terminal for test purposes. The inter-
the latches on the data bus.
face consists of an asynchronous communication
controller (ACC) and a RS-232 driver/receiver. The alarm inputs interface an open collector inter-
face and are equipped with a 10kΩ pull-up resistor
The connector is located at the front of the PCB. and a 100Ω series resistor.
Electrically the interface is according to RS 232.
All alarms are collected through the back plane
connector P2.
5 ALARM INTERFACE
Alarm acknowledge and alarm read signals are gen-
The alarm input block is able to monitor 8 groups of erated by the EPLD.
8 individual alarms and act upon changes in each
H2577
7
2SK220A
6 BOARD INTERFACE
The board will be equipped with two back plane connectors of 96 pins each.
Table 2 : PIN DESCRIPTION OF P1:

Pin # Name Dir Type Function
1a GND
1b GND
1c GND
2a spare
2b spare
2c spare
3a spare
3b spare
3c spare
4a spare
4b spare
4c UNIT_ALM_XSU inp. o.c main alarm xmtr switch unit
5a MAN_IND_XSU reserved for future use
5b SEL_140_XSU bidir. cmos selects 140 Mb/s or 155Mb/s on relay in XSU
5c REL_A_XSU bidir. cmos bit A used to select chn. on relay in XSU
6a REL_B_XSU bidir. cmos bit B used to select chn. on relay in XSU
6b REL_C_XSU bidir. cmos bit C used to select chn. on relay in XSU
6c SW_A_XSU bidir. cmos bit A used to select chn. on prot. in XSU
7a SW_B_XSU bidir. cmos bit B used to select chn. on prot. in XSU
7b SW_C_XSU bidir. cmos bit C used to select chn. on prot. in XSU
7c spare
8a DIS_UNPRI_RDU bidir. cmos selects insertion of AIS on chn prot. on rcvr.distr
8b SEL_140_RDU bidir. cmos selects 140 Mb/s or 155Mb/s on rcvr. distr
8c EXT_CTRL bidir. cmos optional control signal
9a spare
9b spare
9c spare
8 H2577
2SK220A
(Table 2 continued)
10a MS2_1_CLK inp cmos tx and rx clock from over_head_adapt dir UP
10b MS2_1_RXD inp. cmos MS2 byte from over_head_adapter dir. UP
10c MS2_1_TXD outp. cmos MS2 byte to over_head_adapter dir. UP
11a MS2_1_BYP outp. cmos control bypass of MS2 byte dir. UP
11b MS2_2_CLK inp cmos tx and rx clock from over_head_adapt dir. DOWN
11c MS2_2_RXD inp. cmos MS2 byte from over_head_adapter dir. DOWN
12a MS2_2_TXD outp. cmos MS2 byte to over_head_adapter dir. DOWN
12b MS2_2_BYP outp. cmos Control bypass of MS2 byte dir. DOWN
12c UNIT_ALM_RPS outp. o.c.
13a EXT_SU_DATA_0 outp. cmos tx data bit 0 of fifo interface with SU
13b spare
13c EXT_SU_DATA_1 outp. cmos tx data bit 1 of fifo interface with SU
14a EXT_SU_DATA2 outp. cmos tx data bit 2 of fifo interface with SU
14b spare
14c EXT_SU_DATA3 outp. cmos tx data bit 3 of fifo interface with SU
15b spare

16b spare
17a FIFO_SU_0 inp. cmos rx data bit 0 of fifo interface with SU
17b spare
17c FIFO_SU_1 inp. cmos rx data bit 1 of fifo interface with SU
18b spare
19b spare

H2577
9
2SK220A
(Table 2 continued)
20b spare
21a MAVA1_SU inp. cmos msg. available signal from SU
21b MAVA_RPS outp. cmos msg. available signal to SU
21c READ1_SU/ inp. cmos fifo read signal from SU
22a READ_RPS/ outp. cmos fifo read signal to SU
22b spare reserved for future use.
22c spare reserved for future use.
23a spare reserved for future use.
23b spare reserved for future use.
23c RESET_RPS_SU inp. cmos rest signal from SU
24a ALIGN_IND_DEM_07 inp. o.c. idicates alignment of reg. and prot. ok on chn. 7
24b ALIGN_IND_DEM_06 inp. o.c. idicates alignment of reg. and prot. ok on chn. 6
24c ALIGN_IND_DEM_05 inp. o.c. idicates alignment of reg. and prot. ok on chn. 5
25b ALIGN_IND_DEM_03 inp. o.c. idicates alignment of reg. and prot. ok on chn. 3
25c ALIGN_IND_DEM_02 inp. o.c. idicates alignment of reg. and prot. ok on chn. 2
26b ALIGN_IND_DEM_0P inp. o.c. idicates alignment of reg. and prot. ok on chn. P
26c ALIGN_CHN_SEL_07 bidir. cmos 0 :reg. 1:prot. on chn. 7
27a ALIGN_CHN_SEL_06 bidir. cmos 0 :reg. 1:prot. on chn. 6
27b ALIGN_CHN_SEL_05 bidir. cmos 0 :reg. 1:prot. on chn. 5
28a ALIGN_CHN_SEL_03 bidir. cmos 0 :reg. 1:prot. on chn. 3
28b ALIGN_CHN_SEL_02 bidir. cmos 0 :reg. 1:prot. on chn. 2
29a ALIGN_CHN_SEL_0P bidir. cmos 0:reg. 1:prot. on chn. P
29b MS_AIS_INS_DEM_07 bidir. cmos selects insertion of ais on chn. 7
29c MS_AIS_INS_DEM_06 bidir. cmos selects insertion of ais on chn. 6

10 H2577
2SK220A
(Table 2 continued)
30a MS_AIS_INS_DEM_05 bidir. cmos selects insertion of ais on chn. 5
30c MS_AIS_INS_DEM_03 bidir. cmos selects insertion of ais on chn. 3
31a MS_AIS_INS_DEM_02 bidir. cmos selects insertion of ais on chn. 2
31c MS_AIS_INS_DEM_0P bidir. cmos selects insertion of ais on chn. P
32a GND
32b GND
32c GND
H2577
11
2SK220A
Table 3 : PIN DESCRIPTION OF CONNECTOR P2:
Pin # Name Dir Type Function
1a GND
1b GND
1c GND
2a +5V
2b spare
2c +5V
3a -5.2V not in use
3b spare
3c -5.2V not in use
4a +15V
4b spare
4c +15V
5a -15V
5b spare
5c -15V
6a ALM77 inp. o.c.
6b ALM76 inp. o.c.
6c ALM75 inp. o.c.
7a ALM74 inp. o.c.
7b ALM73 inp. o.c.
7c ALM72 inp. o.c.
8a ALM71 inp. o.c.
8b ALM70 inp. o.c.
8c ALM67 inp. o.c.
9a ALM66 inp. o.c.
9b ALM65 inp. o.c.
9c ALM64 inp. o.c.
12 H2577
2SK220A
(Table 3 continued)
10a ALM63 inp. o.c.
10b ALM62 inp. o.c.
10c ALM61 inp. o.c.
11a ALM60 inp. o.c.
11b ALM57 inp. o.c.
11c ALM56 inp. o.c.
12a ALM55 inp. o.c.
12b ALM54 inp. o.c.
12c ALM53 inp. o.c.
13a ALM52 inp. o.c.
13b ALM51 inp. o.c.
13c ALM50 inp. o.c.
14a ALM47 inp. o.c.
14b ALM46 inp. o.c.
14c ALM45 inp. o.c.
15a ALM44 inp. o.c.
15b ALM43 inp. o.c.
15c ALM42 inp. o.c.
16a ALM41 inp. o.c.
16b ALM40 inp. o.c.
16c ALM37 inp. o.c.
17a ALM36 inp. o.c.
17b ALM35 inp. o.c.
17c ALM34 inp. o.c.
18a ALM33 inp. o.c.
18b ALM32 inp. o.c.
18c ALM31 inp. o.c.
19a ALM30 inp. o.c.
19b ALM27 inp. o.c.
19c ALM26 inp. o.c.

H2577
13
2SK220A
(Table 3 continued)
20a ALM25 inp. o.c.
20b ALM24 inp. o.c.
20c ALM23 inp. o.c.
21a ALM22 inp. o.c.
21b ALM21 inp. o.c.
21c ALM20 inp. o.c.
22a ALM17 inp. o.c.
22b ALM16 inp. o.c.
22c ALM15 inp. o.c.
23a ALM14 inp. o.c.
23b ALM13 inp. o.c.
23c ALM12 inp. o.c.
24a ALM11 inp. o.c.
24b ALM10 inp. o.c.
24c ALMP7 inp. o.c.
25a ALMP6 inp. o.c.
25b ALMP5 inp. o.c.
25c ALMP4 inp. o.c.
26a ALMP3 inp. o.c.
26b ALMP2 inp. o.c.
26c ALMP1 inp. o.c.
27a ALMP0 inp. o.c.
27b RELAY_CTRL_7 outp. cmos control signal to rcvr relay chan 7
27c RELAY_CTRL_6 outp. cmos control signal to rcvr relay chan 6
28a RELAY_CTRL_5 outp. cmos control signal to rcvr relay chan 5
28b REALY_CTRL_4 outp. cmos control signal to rcvr relay chan 4
28c RELAY_CTRL_3 outp. cmos control signal to rcvr relay chan 3
29a REALY_CTRL_2 outp. cmos control signal to rcvr relay chan 2
29b REALY_CTRL_1 outp. cmos control signal to rcvr relay chan 1
29c RELAY_CTRL_P outp. cmos control signal to rcvr relay chan 30a spare
14 H2577
2SK220A
(Table 3 continued)
30b spare
30c RD_PU_CTRL/ outp. cmos read signal to registers in peripheral units
31a EN_PU_CTRL outp. cmos latch enable signal to registers in peripheral units
31b UNPRIO_MOD_CHP/ bidir. cmos Prot. chan. mod. set up : unprio. / reg. traffic
31c UNPRIO_DEM_CHP/ bidir. cmos Prot. chan. dem. set up : unprio. / reg. traffic
32a GND
32b GND
32c GND
Table 4 : PIN DESCRIPTION OF CONNECTOR P3:
Pin Name Dir Type Function
1 TOUT outp. RS232 Transmitted data
2 TIN inp. RS232 Received data
3 TEN/ inp. cmos Enable signal for test message display function.
(The connected cable must have signals 3 and 4
tied together to pull down the test output
enable pin.)
4 GND
H2577
15
2SK220A
7 SYSTEM CONFIGURATION
The RPS unit can be configured in different modes. The configuration is done with the use of 3 switches
S1, S2 and S3.
The different modes are described in Table 5 below.
The default mode and configuration switch locations are shown in Figure 2.
S1:1 Flash Boot-Block Programming:
off Disable Boot-Block Programming Option
on Enable Boot-Block Programming
S1:2 Watchdog:
off Disable Watchdog
on Enable Watchdog
S1:4 S1:3 Not in Use
S2:3 S2:2 S2:1 Software Configuration Switches
S3:4 S3:3 S3:2 S3:1 S2:4 Waitstate Selection:
off off off off on 0 Waitstate
off off off on off 1 Waitstate
off off on off off 2 Waitstate
off on off off off 3 Waitstate
on off off off off 4 Waitstate
Table 5: S1, S2 and S3 Modes.
16 H2577
2SK220A
S3 S2 S1 S101 H101
P3
RESET BU TTO N
P2 P1
S3 S2 S1
ON ON ON
1 2 3 4 1 2 3 4 1 2 3 4
DEFAULT CONFIGURATION SWITCH SETTING
Figure 2: Connectors and Switches
H2577
17
SYNCHRONIZING UNIT, 2MHz
2SF219A
H2857 Rev. B
© Nera AS
2SF219A
TABLE OF CONTENTS
1 General Information 3
1.1 Overview 3
1.2 Functional 3
1.3 Font 4
1.4 Back 5
2 Circuit Description 6
2.1 Transmitter 6
2.2 Receiver 6
2.3 Strapping Table 6
2 H2857
2SF219A
1 General Description:
1.1 Overview:
Fig. 1 shows overview of the transmitter and receiv-

er side. In addition to manual switches, each input
also has a detector from which the select decision is
taken. They also control the LEDs.
G703 receiver
INPUT 1
RS422 driver
XMTR
G703 receiver
INPUT 2
RS422 receiver
RCVRA
G703 driver
OUTPUT 1
PLL
RS422 receiver OUTPUT 2
OUTPUT 3
RCVRB
OUTPUT 4
Fig.1
1.2 Functional:
The unit can receive up to 2 separate sync inputs with selection, the frequency is smoothed by a PLL to
G703 format. The default selection here is Input1. remove jitter and noise.
If this is not detected, Input2 is selected. If no signal is This PLL has 2 modes: One fast mode when searching
present, an AIS frequency is inserted. The inputs are for an input to lock onto, and one slow mode when an
manually disabled by setting switches internally on the input is present.
unit. If both channels are disabled, an AIS frequency is
inserted. This can be disabled manually. The 2 selection switches are also remotely controlled
from the supervisory system by the CTRL signals from
On the other side, 2 separate sync signals with the the rear connector. These can also be manually
RS422 format are received. The default selection here disabled. In addition, the RCVR selection switch is
is RCVRA. If this is not detected, RCVRB is selected. manually operated from the front. Operation of this
If no signal is present, the output is clamped. The inputs switch overrides the alarm and remote signals. A LED
are disabled manually with internal switches. After the is lit when this is operated.
H2857 3
2SF219A
1.3 Front:
The coaxial connectors and alarm LEDs for the

external 2MHz sync signals and LEDs are placed at
the front, as shown in Fig.2:
SYNC 2MHz
INP OUT
J1 J2 Sync. 2.048MHz input/output 1
J3 J4 S ync. 2.048M H z input/output 2
J5 Sync. 2.048MHz output 3
J6 S ync. 2.04 8M H z output 4
SYNC 2MHz
unit 26
Man Alm Manual switch operated alarm
Sel
RcvrA
Select source from RCVR A
Sel
RcvrB
Select source from RCVR B
Unit alm Sync. unit combined alarm
Fig.2
The unit alarm is a combination of XMTR2_ALM, The selection LEDs indicate which of the RCVRA
XMTR1_ALM, RCVRA_ALM, RCVRB_ALM and or RCVRB is selected. This can be manually overrid-
PLL_ALM. den by the switch to the right.
4 H2857
2SF219A
1.4 Back:
At the rear side of the unit there is a 64-pin EURO-
connector (a+c) with the following signal assignment:
Pin No. Name: Description:
1a,1c,4a,4c,15a,15c,
24a,24c,25a,25c,32c GND Common ground
17c,18a,18c,19a,19c,20a,
20c,21a,21c,22a,22c,23a +5V Primary positive supply
5a,5c,6a,6c,7a,7c +15V Secondary positive supply
26a CTRL1_ SU Supevisory control signal 1
26c CTRL2_SU Supervisory control signal 2
27a XMTR- Negative transmit sync. signal
27c XMTR+ Positive transmit sync. signal
28a XMTR2_ALM Transmit alarm external sync. signal 2
28c XMTR1_ALM Transmit alarm external sync. signal 1
29a RCVRA- Negative receiver sync. signal A
29c RCVRA+ Positive receiver sync. signal A
30a RCVRA_ALM Receiver alarm sync. signal A
30c RCVRB_ALM Receiver alarm sync. signal B
31a RCVRB- Negative receiver sync. signal B
31c RCVRB+ Positive receiver sync. signal B
32c PLL_ALM Phase-Locked-Loop Alarm
The RCVRA, RCVRB and the XMTR signal follow the GND. The CONTROL signals are controlled from an
RS422 standard. The ALARM signals are all of the OC type signal with pull-up resistors of 10kΩ +5V.
open-collector (OC) type and are able to sink 10mA into
H2857 5
2SF219A
2 Circuit Description:
2.1 Transmitter: 2.2 Receiver:
One or two external 2.048MHz synchronisation signals The two inputs, RCVRA and RCVRB, are routed to the
can be connected to J1 and J3 on the front. The signals unit from one or two DEMODULATORs. Here they
are converted from G.703 level to CMOS. The source are converted from RS422 level to CMOS .The source
is firstly selected from the input alarms and secondly is selected firstly from the front switch, secondly from
from the CTRL1_SU signal, if enabled. Either or both the input alarms, and thirdly from the CTRL2_SU, if
inputs can be manually enabled from the internal DIL- enabled. Either or both inputs can be manually enabled
switch. from the internal DIL-switch.
If no external source is enabled or detected, an internal The signal is now passed through a PLL with a lowpass
AIS signal is selected. This signal can vary slightly with filter for smoothing eventual jitter or noise before being
temperature, but will be within specifications. converted to G.703 level. Thereafter it is split into 4
The signal can also be disabled from the DIL-switch. separate outputs for use in external equipment.
If the PLL is enabled, and no source is enabled or
The resulting signal is now converted to RS422 levels detected, the output is clamped. This is done to ensure
and distributed to all MODULATORs in the terminal. that no false frequencies leave the unit. If the PLL is
They will in turn synchronise the 155.52MHz main disabled , there will be a direct output from the selected
bitstream to this signal. DEMODULATOR in case an input is detected.
2.3 Strapping Table:
S2 ON OFF DEFAULT
1 DISABLE CTRL1 ENABLE CTRL1 ON

2 DISABLE CTRL2 ENABLE CTRL2 ON
3 DISABLE INP1 ENABLE INP1 ON
5 DISABLE RCVRA ENABLE RCVRA OFF

6 DISABLE RCVRB ENABLE RCVRB OFF
7 DISABLE PLL ENABLE PLL OFF
8 DISABLE AIS ENABLE AIS OFF
1: Enables/disdables external selection of INP1/INP2

2: Enables/disables external selection of RCVRA/RCVRB
3: Enables/disables INP1 on the transmitter side
4: Enables/disables INP2 on the transmitter side
5: Enables/disables RCVRA on the receiver side
6: Enables/disables RCVRB on the receiver side
7: Enables/disables PLL on the reiver side
8: Enables/disables AIS insertion on the transmitter side
6 H2857
SYNCHRONIZING UNIT, 2MHz
2SF219B
H2990 Rev. A
© Nera ASA
2SF219B
TABLE OF CONTENTS
1. GENERAL INFORMATION ........................................................................................... 3

1.1 REFERENCES ...................................................................................................... 3
1.2 OVERVIEW ......................................................................................................... 3
1.3 DESCRIPTION ...................................................................................................... 3
2. CONNECTIONS ............................................................................................................ 4
2.1 FRONT .............................................................................................................. 4
2.2 BACK ............................................................................................................... 5
3. SOFTWARE ................................................................................................................. 7
3.1 SYNC. SIGNALS ................................................................................................... 7
3.2 ALARM SIGNALS ................................................................................................... 7
3.3 CONTROL SIGNALS ............................................................................................... 7
3.4 LEDS .............................................................................................................. 8
3.5 SWITCHES ......................................................................................................... 8
3.6 S1-BYTE ........................................................................................................... 8
3.7 HOLDOVER ........................................................................................................ 9
3.8 SELF-TEST ......................................................................................................... 9
3.9 SERIAL PORT ...................................................................................................... 9
4. SETUP...................................................................................................................................10
4.1 HARDWARE REQUIREMENTS..........................................................................................10
4.1.1 SYSTEM OVERVIEW..................................................................................................... 10
4.2 UNIT CONFIGURATION...................................................................................................11
4.2.1 SYNC UNIT.................................................................................................................11
4.2.2 MODULATORS.............................................................................................................12
4.2.3 DEMODULATOR...........................................................................................................12
4.2.4 DISTRIBUTION BOARD, RADIO RACK.................................................................................12
4.2.5 DISTRIBUTION BOARD, SERVICE RACK............................................................................. 13
4.2.6 64KB/S ADAPTER........................................................................................................13
4.3 SYSTEM CONFIGURATION..............................................................................................13
4.3.1 MS TERMINATION........................................................................................................13
4.3.2 RS TERMINATION........................................................................................................13
5. TEST ..................................................................................................................... 14
2
H2990
2SF219B
1. General Information
1.1 References
- Requirement Specification RTA-SDHR\13-2-3\0002

- ITU-T Recommendations G.813
1.2 Overview
Here is an overview of the transmitter and receiver side. Each input also has a detector from which the automatic select decision is
taken in addition to the manual switches. They also control the alarms.
G703 receiver
Input 1 Input1/ SOH S1-byte

Input 2 64kb/s interface RS422 driver
G703 receiver XMTR
Input 2
Xmtr/ Normal/
Rcvr Alarm
RS422 receiver PLL
RCVRA RcvrA/ G703 driver

Rcvr B
Output 1
RS422 receiver
Output 2
RCVRB G.813
clock Output 3
Output 4
1.3 Description
There are 4 possible synchronisation sources in the following priority order:

Input1, Input2, RCVRA, RCVRB. If no one is available, an internal G.813 clock is selected. The S1-byte in the Section OverHead
(SOH) in channel 1 of the STM-1 frame is modified, dependent on the selection. Each source is manually disabled from a DIL-
switch available at the front.
Before outputting to either link equipment or external units, the frequency is smoothed (ref. G.813) to avoid sudden frequency
changes and possible synchronisation loss. This PLL have 2 modes; one fast mode when powering up, and one slow mode when
an input is present.
The 2 input selection switches are remotely controlled from the supervisory system by the CTRL signals from the rear connector.
They can also be disabled manually. There is one input alarm for each source and one PLL lock alarm.
Normally the 2.048MHz output is present for all S1-byte codes, except Error. This is squelch mode 1. It is also possible to
squelch the output if the source is other than G.811. This is squelch mode 2. In this case the squelching also applies to all special
codes.
3
H2990
2SF219B
2. Connections
2.1 Front
The connectors for the external 2MHz sync signals, S1-byte interface, DIP switches and LEDs are placed at the front as shown:
6<1&0+]
,13 287
Sync. 2.048Mhz input/output 1

Sync 2.048Mhz input/output 2
Sync 2.048Mhz output 3

Sync 2.048Mhz output 4
6<1&0+]
AIS clock indicator

XQLW 0DQDOP
Source selection indicators

Manual switches
Sync. unit combined alarm

8QLWDOP
The unit alarm is a combination of XMTR2_ALM, XMTR1_ALM, RCVRA_ALM, RCVR_B_ALM and PLL_ALM.
The selection LEDs indicate which of Input1, Input2 , RcvrA or RcvrB that is selected.
4
H2990
2SF219B
2.2 Back
Upper P2 is partly connected to a 64kb/s ADAPTER J1 and partly to SU (Supervisory Unit) via connection panel EW53 - P6 by
cable UWMK2897.
Upper P2 J1 P6 Signal Name Signal Description

(64kb/s Adapter) (Conn. Pnl)
1a - GND NC
1c 37 GND Common Ground
2c, 2a 35, 36 TxB+, TxB- 8kHz transmitter byte strobe
3c, 3a 33,34 RxB+, RxB- 8kHz receiver byte strobe
4c, 4a 31, 32 RxC+, RxC- 64kHz receiver clock
5c, 5a 29, 30 RxD+, RxD- 64kb/s receiver data

6c, 6a 27, 28 TxC+, TxC- 64kHz transmitter clock
7c, 7a 25, 26 TxD+, TxD- 64kb/s transmitter data
21c, 21a 7, 8 Tx+, Tx- Com. from SU

22c, 22a 9, 10 GND Common Ground
23c, 23a 11, 12 Rx+, Rx- Com.. to SU
24c, 24a 13, 14 GND Common ground
26c, 26a 17, 18 GND Common ground

28c 21 GND Common ground
28a 22 RMT RES. RESET FROM SU
Connection between Sync Unit P2 and 64kb/s Adapter J1 is used for communication of a 64kb/s channel which transfers the S1-
byte in Radio channel 1.
In both Tx- and Rx directions the clock goes positive in the middle of the data bit, and goes negative as the data bit changes. The
byte signal is high during data bit 8 only.
Connection between Sync Unit P2 and Connection Panel P6 is used for communication between Sync Unit and Supervisory Unit.
5
H2990
2SF219B
Lower, P1 Name Description
1a,1c,4a,4c,15a,15c, GND Common ground

24a,24c,25a,25c,32c
17c,18a,18c,19a,19c,20a, +5V Primary positive supply
20c,21a,21c,22a,22c,23a
5a,5c,6a,6c,7a,7c +15V Secondary positive supply
26a CTRL1_SU Supervisory control signal 1

26c CTRL2_SU Supervisory control signal 2
27a XMTR- Negative transmitter sync. signal
27c XMTR+ Positive transmitter sync. signal

28a INP2_ALM Transmitter alarm external sync. signal 2
28c INP1_ALM Transmitter alarm external sync. signal 1
29a RCVRA- Negative receiver sync. signal A

29c RCVRA+ Positive receiver sync. signal A
30a RCVRA_ALM Receiver alarm sync. signal A
30c RCVRB_ALM Receiver alarm sync. signal B

31a RCVRB- Negative receiver sync. signal B
31c RCVRB+ Positive receiver sync. signal B
32c PLL_ALM Phase-Locked-Loop Alarm
The RCVRA, RCVRB and XMTR signals follow the RS422 standard. The ALARM signals are of open-collector (OC) type
and sink 10mA into GND. The CONTROL signals are controlled from a signal of OC type and are pull-up'ed with 10kohms
to +5V.
6
H2990
2SF219B
3. Software
To control routing of synchronisation, switching and S1-byte communication, a processor is used. It interacts with the sync. signals
through a field programmable gate array. Programs for the gate array and processor reside in the same PROM.
3.1 Sync. signals
The SYNC1- 4 output signals are always available, except when received S1-byte code demands the output to be squelched. This
does not apply to the XMTR output to the modulators on the transmitter side.
Each input has an ENABLE signal that indicates a possible sync. source. If the input is not enabled, alarm signals from this source
are inhibited.
Each input has a detection circuit to indicate signal presence. This is made in hardware. In software, there is an additional circuit that
prevents the output frequency to go out of range. This is done by limiting the adjustment pulses.
3.2 Alarm signals
Alarms from the circuits mentioned above are used to set external alarm outputs. There is one alarm for each source, plus one PLL
alarm. Alarm detection times are shown below:
Alarm Source Time
XMTR1_ALM Input1 <10uS

XMTR2_ALM Input2 <10uS
RCVRA_ALM RcvrA <10uS
RCVRB_ALM RcvrB <10uS
PLL_ALM PLL <1S
3.3 Control signals
There are 2 control signals received from the SU. The action is taken from the following table:
CTRL2 CTRL1 Action
HIGH HIGH Selects source automatically after priority (default).

HIGH LOW Selects source forced from INP2.
LOW HIGH Selects source forced from RCVRA.
LOW LOW Selects source forced from RCVRB.
In addition, there is a RMT_RES signal that is used to reset the processor. This signal is disabled by a switch.
7
H2990
2SF219B
3.4 LEDs
There are 4 LEDs , each indicating the selected source. If no source is selected, or if the output is squelched, all indicators are OFF.
A manual LED is ON if the source selection is forced. There is also a main alarm LED which is ON if any external
alarms are ON or if the selection is forced.
3.5 Switches
Onboard there is a DIL-switch that sets specific operating modes. The modes are:
No. OFF ON Default
1 Disable RESET Enable RESET/TEST OFF

2 Squelch mode 1 Squelch mode 2 OFF
3 Disable INP1 Enable INP1 ON
4 Disable INP2 Enable INP2 OFF
5 Disable RCVRA Enable RCVRA OFF
6 Disable RCVRB Enable RCVRB OFF
7 Disable PLL smoothing Enable PLL smoothing ON
8 Disable CTRL1-2 Enable CTRL1-2 OFF
3.6 S1-byte
In squelch mode 2, if input 1 or 2 is enabled and present, it is assumed to be a G.811 clock, and 0010 is transmitted in the S1-
byte.
The following applies to squelch mode 1:
If Input1 is enabled and present, it is assumed to be a G.812 transit clock, and 0100 is transmitted in the S1-byte.
If Input2 is enabled and present , it is assumed to be a G.812 local clock, and 1000 is transmitted.
If RcvrB, from which the S1-byte is not available, is enabled and present, it is assumed to be an Unknown source and 0000 is
transmitted.
If RcvrA, from which the S1-byte always is available, is enabled and present, the S1-byte is looped back. This also counts for all
undefined states, which can be used for local synchronisation purposes. The exception is when Error is received, the G.81s clock
is then inserted and 1011 is transmitted. If the source clock is missing , the G.813 clock is inserted. If this is not available, the
Error state is used. Bit 4-1 of the S1-byte is set to 0000 when not looped back.
Dependent on squelch mode and source availability, the transmitted S1-byte is selected accordingly.
Mode Source Code Value Description
2 Input1 G.811 0010 Primary reference clock

2 Input2 G.811 0010 Primary reference clock
1 Input1 G.812-T 0100 Transit station clock
1 Input2 G.812-L 1000 Local station clock
- RcvrA - - S1-byte is looped back

- RcvrB Unknown 0000 Quality unknown
- AIS G.813 1011 SETS clock
- - Error 1111 No quality
8
H2990
2SF219B
Dependent on selection and S1-byte information the output is squelched accordingly.
Code Mode 1 Mode 2
Unknown Squelch
G.811
G.812-T Squelch
G.812-L Squelch
G.813 Squelch
Error Squelch Squelch
Other Squelch
3.7 Holdover
Each sync. source is a counter that counts adjustment pulses and a flag that indicates adjustment direction. In addition there is a
common counter that should be read each time the adjustment pulse arrives. The time between pulses is thus measured.
Dependent on source selection, the output should be adjusted by this interval. If a source is suddenly lost, the output is still adjusted
with this value. When switching sources, there is a smooth transition by incrementing or decrementing the output pulse adjustment
interval until it fits the source.
3.8 Self-test
At power-up the processor performs a quick self-test. If anything wrong is detected, alarms are applied and outputs squelched.
3.9 Serial port
Together with the processor, a serial interface is included which communicates through a party-line bus with the SU. This bus is only
used for test purposes.
9
H2990
2SF219B
4. SETUP
4.1 Hardware requirements
To enable external synchronisation as described in ITU-T G.813 the following hardware units must be mounted in each NL29x
equipment terminal.
- 2SF219B 2MHz Sync. Unit

- UWMK2897 Cable Assy., Sync. Unit
- 2N507A Adapter 64kb/s
- UWMH2282-1 Cable 2MHz Coax
If the S1-byte information in the section overhead of the STM-1 frame is not needed, the cable and adapter can be omitted.
4.1.1 System overview
Below is a simplified layout of a terminal for use when mounting the sync. equipment.
SERVICE RACK RADIO RACK
TOP TOP
SHELF SHELF
SVCH.
SHELF XMTR
ADPT.
SHELF
64kb/s
RCVR
ADPT. RSOH
SHELF
ACU
XMTR SYNC.
SWITCH UNIT
DEMOD./
MODULATOR
RCVR
DISTR.
PSU PSU
10
H2990
2SF219B
4.1.2 Mounting instructions
Prepare the cable to the sync. unit by pulling P1 of the UWMK2897 cable down behind the XMTR. switch shelf in the service rack.
Mount the connector to the shelf with the attached screws in the upper rightmost position. Disconnect the cable connected to P6 on
the distribution board EW53A/EW53B. Connect P3 of the sync. cable to P6 and connect the loose cable to P2 of the sync. cable. Place
the sync. cable to the left and over the edge of the RSOH adapter shelf. The cable will now be hidden behind the side panel. If this is
not enough the distribution board EW53A/EW53B must be removed and remounted.
Configure the adapter and sync. unit according to section 4.2.
Insert the adapter in one of the two upper left positions next to the RSOH Adapter, and connect P4 on the sync. cable to it.
Insert the synch. unit in the upper right position next to the XMTR Switch. If external input or output is needed mount cables from
the front of the sync. unit and to the distribution board EF212A/EF213A on the top of the rack. These cables should follow the sync.
cable to the left/under the distribution board EW53A/EW53B.
4.2 Unit configuration
There are a number of straps and switches that need to be set on a number of units to make the synchronisation work.
4.2.1 Sync unit
S2 OFF ON SETTING
1 DISABLE RESET ENABLE RESET OFF

2 SQUELCH MODE1 SQUELCH MODE2 OFF
4 DISABLE INP2 ENABLE INP2 OFF
5 DISABLE RCVRA ENABLE RCVRA OFF
6 DISABLE RCVRB ENABLE RCVRB OFF
7 DISABLE PLL ENABLE PLL ON
8 DISABLE CTRL ENABLE CTRL OFF
The first strap is only used for enabling external reset to the processor. It is only used during unit test. The second indicates the clamping
mode. ON is for squelching all outputs except for those derived from an G.811 clock.
The next 2 straps enable INP1 and INP2 to the transmitter. This counts for the alarm inclusion as well as the signal itself. INP1 has
priority when both are applied. INP2 is then backup if INP1 disappears.
The next 2 straps enables RCVRA and RCVRB from the receiver. If both of these signals are not present when enabled the output
is clamped. RCVRA has priority when both are applied. RCVRB is then backup if RCVRA disappears.
Strap 7 enables a PLL circuit on the receiver side to reduce jitter and noise. This is highly recommended. If disabled the
unfiltered clock is fed back to the XMTR output.
Strap 8 enables external control of the unit after the following priority:
CTRL1 CTRL2 SOURCE
HIGH HIGH INP1(default)

LOW HIGH INP2
HIGH LOW RCVRA
LOW LOW RCVRB
11
H2990
2SF219B
4.2.2 Modulators
S503 ON OFF SETTING
4 MS Termination RS Termination ON
6 Ptr. Processing No processing ON
This setting applies to the modulators where synchronism is to be applied. In all other modulators, terminal or repeater, switch 4 and
6 must be OFF. For a more detailed explanation see User manual for NL-290 Family, Configuration section, Setup of Modulator.
4.2.3 Demodulator
W703 ON OFF SETTING
1-2 Always Enabled ON
If this strap is not mounted synchronism is output when the sync. indication bit in the STM-1 frame is TRUE, else sync is always output
if enabled from the back panel.
4.2.4 Distribution board, radio rack
S2 ON OFF SETTING
7 Enable Sync Demod Disable ON

8 Enable Sync Mod Alm Disable ON
These switches must be set on the terminal stations to enable sync. output from demodulators (only channels that are selected RcvrA
or RcvrB should be enabled), and enable sync. alarm from modulators.
W4 ON OFF SETTING
1-2 Disable Enable OFF
This strap must be set on the terminal stations, where sync. is applied, to reset the sync. indicator bit in the STM-1 frame from external
sources. This bit is only usable if W703 is removed on the demodulator.
W8 ON OFF SETTING
1-2 Line termination No termination OFF
This strap must be set on the uppermost channel on terminal stations to terminate the distributed sync. signal.
W9 ON OFF SETTING
3-6,4-5 RCVRA selected No selection OFF

1-8,2-7 RCVRB selected No selection OFF
These double straps route the sync. signals from the demodulator to the SYNC unit. RcvrA must select channel 1, and RcvrB must
select protection channel.
12
H2990
2SF219B
4.2.5 Distribution board, service rack
S4 ON OFF SETTING
1-5 Disable Sync alarms Enable OFF
These switches must be set on the terminal stations to enable sync. alarms to the ACU.
S5 ON OFF SETTING
4 Disable Sync alarms Enable OFF
This switch must be set to enable sync. alarms to the ACU.
4.2.6 64kb/s Adapter
S302 ON OFF SETTING
1 ON
2 OFF
3 Slot number 17 ( S1-byte ) OFF
4 OFF
5 ON
6 Enable Channel 2 Disable ON
7 V.11 G.703 ON
8 - - ANY
S302 ON OFF SETTING
6 Enable Channel 1 Disable OFF

1-5,7-8 - - ANY
In addition, the unit must be set up for communication on the SVCE bus. For a more detailed explanation, see User manual for the
NL290 - Family, Configuration section, Setup of 64kb/s Adapter.
4.3.1 MS Termination
The above settings are typical for MS terminals. One of the terminals are considered the master to which external sync. is applied.
INP1 or INP2 should be selected there. The other terminal is the slave where sync. is received from RCVRA or RCVRB.
4.3.2 RS Termination
Synchronisation can though be used on RS terminals by tapping a 2.048MHz clock from a STM-1 channel. The sync. unit is here
configured as a slave unit. Insertion of sync. on the modulators is not allowed hence disabling this by setting S2,8 to OFF position
on the distribution board. Channel 1 must be selected on the adapter instead of channel 17 if sync. is received from the other
direction.
13
H2990
2SF219B
5 Test
For testing the unit, a test card is made. This connects to the rear plug of the unit and emulates a connected link. Power is also
supplied here. When testing the unit, the XMTR is looped back to the RCVRA and RCVRB inputs on the unit. Switches on the
test unit emulate the remote supervisory signals, and LEDs indicate the external alarm status.
14
H2990
OPTICAL INTERFACE UNIT
7NYD576B
H3003 Rev. A
© Nera ASA
CLASS 1 LASER PRODUCT
IEC825-2: 1993
7NYD576B
TABLE OF CONTENTS
Page:
1. INTRODUCTION 3
2. TECHNICAL DATA 3
3. DESCRIPTION 4
3.1 General 4
4. CIRCUIT DESCRIPTION, OPTICAL TRANSCEIVER PART 6

4.1 General 6
4.1.1 CMI-coder and decoder 6
4.1.2 Regenerator 6
4.1.3 CMI splitter 6
4.1.4 Input signal detector 6
4.1.5 Relay Switch 6
4.1.6 CMI regular input signal detector 6
4.1.7 Control and alarm circuits 6
4.1.8 Transmit data retiming 7
4.1.9 Transmitter failure shutdown 7
5 CIRCUIT DESCRIPTION ACU PART 7
5.1 General 7
5.1.1 Micro controller 7
5.1.2 Analog to digital conversion 7
5.1.3 Watchdog/Reset 7
5.1.4 RS485 serial communication interface 7
5.1.5 DIL-switch 7
5.1.6 Alarm collection 8
5.1.7 Automatic Laser Shutdown and Restart (ALS) 9
6 CALCULATED MTBF 10
7 PLUGS AND CONNECTORS 11
2
H3003
7NYD576B
1. INTRODUCTION
This document describes the optional Optical Interface Unit 7NYD576B which enables multiplex equipment to be located
up to approximately 15 km away from the radio link equipment. The interface falls into the category; STM-1 S-1.1
Inter-office Short-haul, defined by ITU-T rec. G.957, specifying an attenuation range of 0-12 dB and giving a target
distance on the order of 15 km. The unit replaces the electrical interface based on CMI signaling format. The signal format
here is optical NRZ. The unit has a transmitter part and a receiver part and thus can be regarded as an optical transceiver.
The transceiver is a laser class 1 product (IEC825).
2. TECHNICAL DATA
Optical characteristics:
Application code S-1.1

(Table 1/ITU-T G.957)
Operating wavelength range nm 1261-1360
Transmitter at reference point S*
Source type MLM**

Spectral characteristics
-maximum RMS width (s) nm 7.7
Mean launched power
-maximum dBm -8
-minimum dBm -15
Minimum extinction ratio dB 8.2
Receiver at reference point R*
Minimum sensitivity (BER<1x10e-10) dBm -29

Minimum overload dBm -8
*: Ref. to ITU-T G.957.

**: Multi-Longitudinal Mode laser
Electrical characteristics:
Electrical input signals:

Data regular ch (J1): CMI/1V 75W
Data prev.relay (J3): CMI/1V 75W
Electrical output signals:

Data next relay (J2): CMI/1V 75W
Data output (J4): CMI/1V 75W
Data output (J5): CMI/1V 75W
Power requirements:
+5.0V/0.4A
-5.0V/0.96A
+14.8V/50mA
Total power consumption: 7.5W
H3003
3
7NYD576B
3. DESCRIPTION
3.1 General
The Optical Interface Unit 7NYD576B consists of a box containing 2 subfunctions; an optical transceiver and an ACU-
function.
The main functions of the optical transceiver are:
Transmit direction:
- CMI decoding.
- Transmit data retiming.
- Electrical to optical conversion.
- Perform protection switching.
- Electrical input signal detection.
- Transmitter failure shutdown.
Receive direction:
- Optical to electrical conversion.
- Data and timing regeneration.
- CMI coding.
- Splitting of CMI signal.
- Optical input signal detection.
The main functions of the ACU are:
- Perform ALS.
- Collect alarms and status signals.
- Communication with SU.
- Measure analog voltages (A/D conversion).
4
H3003
7NYD576B
INP. ALM. DET. CLK FREQ.

coax
XMTR DOUBLER
REGEN
switch stm-1
SM-fiber
CMI
TRANSCEIVER INCL. O/E AND E/O

stm-1
Mod. SPLITTER IN
CMI SC
coax
CODER
RETI MING
MICRO
DATA
CMI
CONTROLLER
DECODER
&
COMM.
coax coax
CTRL. & ALM.

ALM. DET.
CMI REG. INP.
Demod. stm-1
SWITCH
SM-fiber
RELAY
Prev. stm-1
relay OUT
SC
Next stm-1
coax
relay
Pwr, alarms, status, control, address
DESBLK3
Fig. 3.1 Functional Block Diagram
H3003
5
7NYD576B
4. CIRCUIT DESCRIPTION,
OPTICAL TRANSC. PART
4.1 General. 4.1.5 Relay switch.

See Fig.3.1 Functional Block Diagram.
This circuit receives an external signal when protection
This transceiver performs the o/e and e/o conversion switching is to be performed. For all channels in a system
function. It consists of a single unit including optical consisting of N+1 channels, the relay is not activated
connectors. Control of laser operation, alarms and status during normal transmission, except channel P (Protection
signals are given by interface signals. The optical channel). For all N the signal routing may be described as
connectors are of the type SC. follows:
4.1.1 CMI-coder and decoder. 4.1.5.1 Normal operation.
CMI coding in the receive direction and CMI decoding in The CMI-level STM-1 signal comes from the demodulator
the transmit direction is performed by these circuits, which in the same rack and enters the relay contacts before it
mainly consist of two ASICs with some interface circuitry. goes to the optical transmitter part (via CMI decoder). The
The circuits operate on ECL logic levels and therefore alternative signal for protection switching also enters the
dissipate some heat. The ASICs are mounted on a relative relay coming from previous relay and is fed to the next
massive heat sink. relay in a daisy-chain fashion.
4.1.5.2 After protection switching.

4.1.2 Regenerator.
The signal from the demodulator in the same rack is
Regeneration of data and retiming of clock at 155 Mhz are decoupled from the relay by relay-operation and the
done in this circuit block. The regenerated clock at 155 alternative signal from the previous relay is fed to the
Mhz is then fed to a circuit which perform, frequency optical transmitter.
doubling to 311 Mhz. This signal is needed for the CMI-
coder to be able to do CMI coding. The data retiming at For the P-channel the relay is normally operated and the
155 Mb/s is done using an integrated circuit which STM-1 signal from the RCVR DATA DISTRIBUTION
incorporates a PLL function. Loop parameters are set by UNIT, 2GN395A , will be fed to the optical transmitter.
external components. Upon protection switching, this signal will be routed to the
next relay and nothing fed to the optical transmitter on the
P-channel.
4.1.3 CMI splitter.
4.1.6 CMI regular input signal detector
Before the CMI coded signal is fed to the modulator, the
signal is split in two. One signal is fed to the modulator as
mentioned, the other is fed to the transmitter switch. The This circuit detects if the incoming signal to the relay is
two signal branches are electrically equivalent. absent. The alarm CMI Regular Input Alarm is given.
4.1.4 Input signal detector. 4.1.7 Control and alarm circuits.

This circuit detects alarm conditions and converts readings
In order for the transmitter switch to operate there is an of laser bias current and transmitter output power to
input signal detector which detects loss of transitions at the appropriate format. This circuit communicates with the
output of the the CMI splitter, before splitting. This alarm ACU part. A signal to detect that laser lifetime is
is logically ORed with the alarm Incoming Signal approaching its end is also incorporated. These signals will
Absent, which signifies that there is no optical input to the be described further in the next section.
unit. In this way a detection of signal loss includes errors
that may occur through the receiver chain.
6
H3003
7NYD576B
4.1.8 Transmit data retiming.
The CMI to NRZ decoded signal is reshaped in a retiming The first signal is the laser bias current and the second is
circuit, before electrical to optical conversion. the transmitter (laser) output power.
5.1.3 Watchdog/Reset.
4.1.9 Transmitter failure shutdown.
A watchdog function is implemented in order to reset the
In case of malfunction of the laser output power control microprocessor in case of program malfuntion. During
circuit, the laser will be automatically shut down locally. normal operation the watchdog timer is reset at regular
Restart trial of laser can be done by power up of the intervals by software. In case of an abnormal situation, the
equipment or by manual restart from the supervisory processors program will not be able to reset the watchdog
system. Either by PC or by the display on the supervisory and this will in turn give a reset signal to the processor.
rack. (This is implemented in hardware and must be
separated from the ALS function, described later). The watchdog also continously monitors the supplied
+5.0V and gives a reset signal (Watchdog Out- via the
watchdog circuit itself) to the processor if this voltage
5. CIRCUIT DESCRIPTION, drops below +4.5V.
ACU PART In case of failure of the watchdog circuit, a remote reset is
implemented. Reset can be performed via the supervisory
system. This function may be disabled, using DIL-switch
5.1 General. S200.
This function is placed on the same circuit board as the
transceiver. The ACU will monitor the transceiver for
proper functioning.
5.1.4 RS485 serial communication
interface.
5.1.1 Micro controller.
The microcontroller is a 80C32. This version of the 80C32 The RS485 interface circuit interfaces to the serial-bus.
controller has program memory (ROM) on the The serial bus is used by the SU and ACU to communicate
chip so that no external ROM/EPROM is needed. The with each other. All alarms, monitoring signals, control
oscillator frequency is 12 Mhz. and status signals are exchanged on this bus.
5.1.5 DIL-switch.
5.1.2 Analog to digital conversion. The DIL-switch S200 configures the optical transceiver
2 analog signals are monitored by the ACU. These are unit as follows:
digitized and transmitted to the SU (Supervisory Unit).
S200 Signal name Description
1-8 ALS_IMPL ALS implemented = OPEN (Normally OPEN)

2-7 HW_TEST ACU HW-test enabled = OPEN (Normally CLOSED)
3-6 WD_OUT Watchdog Out enabled (inv.) = CLOSED (Normally CLOSED)
4-5 RMT_ RES_ACU Remote reset enabled (inv.) = CLOSED (Normally CLOSED)
H3003
7
7NYD576B
5.1.6 Alarm collection.
The ACU will regularly poll the alarms to determine their

state. These alarm states are sent to the SU.
The following alarms interface to the ACU:
No. Signal Name Description
1 CMI REG INP ALM CMI Regular Input Alarm

2 DATA INP ALM Data Input Alarm
3 FUSE ALM Fuse Alarm
4 INCOMING SIGNAL ABSENT Incoming Signal Absent
5 OUT OF RANGE Output Power Out Of Range
6 LD FAIL Laser Failure Alarm
7 BIAS OUT OF LIMITS Laser Bias Out Of Limits (Warning)
Alarms 1 and 2 are described in previous chapter.
No.3 Fuse Alarm: Alarm is given from the rack top back panel if one of two fuses are blown.
No.4 Incoming Signal Absent: If received optical signal input power drops below -37 dBm
(typ.) an alarm is given.
No.5 Output Power Out Of Range: Alarm if transmitter optical output power exceeds +2 dB
from its normal value. The normal (absolute) value varies with unit.
No.6 LD Fail: This alarm is derived from the laser monitor voltage inside the transceiver
module. A certain deviation shows a fault inside the module. In case of this monitor
voltage being above or below certain threshold values, the laser is shut down
automatically and alarm is given to the ACU.
No.7 Laser Bias Out Of Limits (Warning): If laser bias current (which is approximately equal
to laser threshold current) over time increases by more than roughly 50% of the
value at day one because of laser aging, a warning is given to enable maintenace
personnel to replace the unit before malfunction occurs. (The laser bias current uses
automatic power control (APC) to stabilize output power. This warning circuit is
temperature compensated, since the threshold current strongly depends on temperature,
and because of APC, the bias current also has the same dependency).
8
H3003
7NYD576B
5.1.7 Automatic Laser Shutdown and Restart (ALS).
This is a function implemented in software. It complies with the ITU-T rec. G.958. (This should not be mistaken for the
Automatic Transmitter Failure Shutdown mechanism, described earlier).
The following diagram describes the operation:
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7[RQIRU 7[RQIRU 7[RQIRU

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Fig. 5.1 ALS Operation Block Diagram
H3003
9
7NYD576B
If a cable break occurs in a section of the optical fiber, the convenient during installation and maintenance. One might
consecutive loss of signal at the receiver is used to shut for instance want to permanently set the laser on and
down the adjacent transmitter in the opposite direction for disable ALS during installation to enable quick testing and
eye satefy purposes.This in turn leads to a loss of signal at verification. Later, after completion of the installation, ALS
the receiver in the other end which switches off the may be enabled.
transmitter and consequently the fibers in this section are
both dark. If ALS is enabled and laser is on, no response will be given
to a transmitter laser on signal from the supervisory
For test and monitoring purposes it is possible to override system, but the laser will be shut down in response to a
the shutdown mechanism by switching on the laser transmitter laser off signal.
manually (remote or local). See description below.
The delay time is programmable from 60s to 300s in 30s
The ALS function may be implemented or not. This is set steps.
up at the factory and information is given to the
supervisory system.
6. Calculated MTBF
When implemented, the ALS may be enabled or disabled,
locally from the display on the service rack, or remotely
from a PC. After receiving a control signal, the According to calculation method defined in Mil. HDBK
microcontroller performs the necessary action. Thereafter 217 E, mean time between failure in ambient temperature
the microcontroller sends a status signal to display current of 25 °C is calculated to be approx:
status. Likewise, the transmitter laser may be shut on or
off, remotely or locally, and a status signal is given back to MTBF=85.000 hrs for the unit
the supervisory system. These features are particularly (MTBF = 100.000 hrs. for the optical module only).
10
H3003
7NYD576B
7. PLUGS AND CONNECTORS
P100:
Pin no. Description
1 -5.0V
2 -5.0V
3 +5.0V
4 +5.0V
5 GND
6 GND
7 +14.8V
8 Relay control
9 CMI regular input alarm
10 Data input alarm
11 Address bit 1 (LSB)
12 Address bit 2
13 RXD+ (Serial comm.) *
14 RXD- (Serial comm.) *
15 Address bit 3
16 Address bit 4 (MSB)
17 TXD+ (Serial comm.) *
18 TXD- (Serial comm.) *
19 Fuse alarm
20 Remote reset (inv.)
*: With respect to the signals RXD+, RXD-, TXD+ and TXD-, the direction is as seen from the SU, towards the optical
transceiver.
Coaxial connectors:
No. Description
J1 155 Mb/s STM-1 regular channel (to transmit)

J2 155 Mb/s STM-1 to next relay
J3 155 Mb/s STM-1 from previous relay/protection
J4 155 Mb/s STM-1 received data (to Mod.)
J5 155 Mb/s STM-1 received data (to XMTR sw.)
Optical interface.
The optical interface is single-mode duplex SC. See figure 7.1
H3003
11
7NYD576B
J5 J4 J3 J2 J1
Optical output
Optical input
RCVR
XMTR
CONNECT2
Figure 7.1. Connection of SM duplex SC connectors.
12
H3003
SVCE CHANNEL
COLLECTIVE CALL
2NF467A
SVCE CHANNEL
SELECTIVE CALL
2NF468A, 2NF533A
H2143 Rev. I
© Nera AS
2NF467/2NF468/2NF533A
2 H2143
2NF467/2NF468/2NF533A
TABLE OF CONTENTS
1.0 TECHNICAL DATA 4
2.0 GENERAL DESCRIPTION 5
3.0 FUNCTINAL DESCRIPTION 5

3.1 SVCE Interface 2NF468A/2NF533A. 5
3.1.1 Set-Up / Strapping: 8
3.1.2 How to use the equipment. 11
3.1.2.1 External connections 12
3.2 Service Channel Interface, 2NF467A. 13
3.2.1 Set-Up / Strapping: 15
3.2.2 How to use the equipment 16
3.2.2.1 External connections: 17
4.0 PARTS LIST 18
5.0 DIAGRAMS 31
H2143 3
2NF467/2NF468/2NF533A
1.0 TECHNICAL DATA
Voice circuit band : 300-3400 Hz

Signalling (2NF468A/2NF533A) : DTMF-CCITT, Q23
Max. number of selective party
line numbers (2NF468A/2NF533A) : 100
Interface towards radio : 2Mbit/s bus containing:

64 kbit/s : Data, Clock, Byte Timing in two directions
2*500 bit/s : Data in two directions
Internal telephone (2NF468A/2NF533A)

Interface : 2W, 600 ohm
Inp./out levels : 0/-6 dBr
DC loop current Max/Min : 35/10 mA
DC feed : 40-60 Volt through 2*850 ohm
Ringing voltage : 25 Hz, 60-70 Vrms superimposed on neg.supply
External telephone (2NF468A/2NF533A)

Interface : 2W, 600 ohm
Input level : +2 - -5.5 dBr in 0.5 dB step
Output level : -8 - -0.5 dBr in 0.5 dB step
DC loop current Max/Min : 35/10 mA
DC feed : 40-60 Volt trough 2*500 ohm
Ringing voltage : 25 Hz, 60-70 Vrms superimposed on neg.supply
4W bal. connection (2NF468A/2NF533A)

Interface : 4W, 600 ohm balanced
Input level : -0.5 - -16 dBr in 0.5 dB step
Output level : +7 - -8.5 dBr in 0.5 dB step
E- and M-Wire
transmission channel : Earth/High impedance
Other equipment : 4W, bal/unbal, 600 ohm, -6 dBr

Loudspeaker output (2NF468A/2NF533A) : <0.25W, >8ohm (Volume control is not provided)
E.O.W : 4W, bal/unbal, 600 ohm, -6dBr
4-W Unbal. con. (2NF468A/2NF533A) : 4W, 600 ohm, unbalanced, -6 dBr
Collective Call inp. and outp. : Earth/High impedance
Control signals : Earth/High impedance
Supply voltages : +5V, +9-15V, 20-60V
4 H2143
2NF467/2NF468/2NF533A
2.0 GENERAL DESCRIPTION 3.0 FUNCTINAL DESCRIPTION
The 2NF467A/2NF468A/2NF533A Service 3.1 SVCE Interface 2NF468A/2NF533A.

Channel Interfaces are designed to meet the The Service Channel Interface (SCI) 2NF468A/
requirements for omnibus voice circuit on digital 2NF533A can be divided into four parts:
radio relays.
The Service Channel interface is available in -Bus Interface
three versions: -Signalling logic
-2NF468A/2NF533A Normal version -Audio circuit
-2NF467A Low Cost version -DC/DC convertion
The difference between 2NF468A and 2NF533A
is that 2NF468A has an additional connector, P1. SUBINSERT Figure 1 shows a block schematic of the SCI.
DATABUS
TO/FROM
SERIAL
CONTROL 1/2
INP/OUT
R232, R233, R235, R238, R240, R241
W IRE
E/M
SIGNAL-
LOGIC
INTER-
FACE
LING
BUS
IC20
VLSI
INP/OUT
CALL
R201, R203-207
SIGNALLING BUS
S 203
DEC
IC22
DEC
CO-
CO-
IC21
TELEPHONE SWITCH
TELEPHONE SWITCH
S201
S202
RCVR
DTMF
DIL
DTMF
DIL
GEN
IC23
SELECTIVE CALL
R272, C205, C206
PRESETS
IC67A
IC67B
IC60B
OTHER EQUIPMENT 1/2

W 604
EXT.
IC60A
500Hz
RING
IC66
IC61
IC53B
SIGNALLING BUS
W 604
IC45B
IC51B
IC60B
IC43A
IC46B
IC65B
IC65A
IC64B
dB
dB
S501
IC10D
S601
dB
IC43B
IC46A
S602
dB
IC51A
IC52
IC45A
IC49
IC47
IC10C
T61
T60
IC10A
DC 30 Hz
IC40
IC50
G
SLIC
SLIC
DC
SPEAKER
TELEPH.
TELEPH.
UNBAL.
W
O
LOUD
EXT.
BAL.
4W
INT.
4W
Fig. 1 : Block Schematic Diagram of the SCI

H2143 5
2NF467/2NF468/2NF533A
The Bus-interface is the interface towards the one of the telephones are off hook. It is kept active
Radio equipment. This is a 2 Mbit/s bus containing as long as off hook is present. Control 1 is the input
Serial Data send/receive, 2 MHz clock and 500 and Control 2 the output when Control signals is
Hz Multiframe sync from the Radio. On repeater to be transferred between SCIs (Control 1 J1
stations, both directions are transmitted on the pin33, Control 2 J1 pin34).
same bus. Direction 1 can use timeslots 1-5, and
Dir. 2, 17-21. Timeslot in Dir. 1 is set on the SCI The Audio-Circuits distributes the voice-signals
by DIL-switches (S204). Dir.2 is always a distance to the different interfaces. All the interfaces are
16 timeslots away from Dir. 1. internally connected with the following exeptions:
In each direction a total traffic of one 64 kbit/s and Internal telephone - Loudspeaker -
two 500 bit/s signalling channels can be transmitted EOW, are in parallell only and not
and received. internally connected.
The LED (H101)- and external alarm (output to Other equipment 1 - Other
P2, pin 20a/20c) is on, when the SCI is unable to equipment 2, are in parallell only and not
syncronize to the bus. The signalling logic as well internally connected.
as the bus-interface is contained in a VLSI-circuit
(IC20). The signalling logic is based on Dual To transfer the Audio signals to the bus there are
Tone Multi Frequency (DTMF) signalling. From two A-law CODECs with internal BP- Filters.
each service telephone it is possible to call all One Codec transmits in Direction 1 and receives
other stations collectively or any other station in Direction 2 and the other vice versa. The send/
selectively. The number selections are done by receive levels on both Codecs are adjustable
internal DIL-switches. Internal (S202)- and (IC21, IC22).
External (S201)- telephone number can be chosen
independently. The Other equipment 1 & 2 are ment for
interconnection between similar equipment, and
The collective call can be activated either by up to 3 SCI-boards can be connected this way.
pushing * on any telephone connected, or by These interfaces are not overvoltage protected
pushing the call button (S203) on the SCI. This and therefore not recomended for long lines or
will cause a continious call on all other stations as outdoor use. The other equipment can be selected
long as the * or button is held. It will also cause the either balanced or unbalanced by internal straps.
Call-out signal (J1, pin31) to go active. A The levels on the inputs are adjustable +0.5 dB to
collective call can also be performed by activating compensate for cable losses and component
the Call-inp signal (J1, pin29). variation.
Whenever the selective number is received, there The balanced 4W-connection is ment to interface
will be two ring-signals in the telephone. At the to various types of equipment. The levels are
same time a tone can be heard on the omnibus adjustable in 0.5 dB step by internal DIL-switches.
channel.
The unbalanced 4W-connection is an interface
The E/M-Wire is a 500 bit/s transmission channel reserved for adapter use (such as PABX- adap-
over one hop. This channel can be used together ter).
with the 4W-connection to fullfill a standard
multiplex channel (E-wire J1 pin25, M-wire J1 In the Internal Telephone Interface a Subscriber
pin27). Line Interface Circuit (SLIC) (IC40), is used to
supply the line with DC as well as to feed through
The other 500 bit/s channel (Control 1 / Control the 4w audio signals to the line. This connection
2) is occupied for adapter connection. The Control is ment for the service telephone. The Service
2 signal becomes active when a # is received, and Telephone 87A10- is suitable for this purpose.
6 H2143
2NF467/2NF468/2NF533A
If a connection to a distant telephone is required, should be a fault on one of them, the connection
the External Telephone interface can be used. The between the others might be broken. See Fig 2.
levels here can be set in 0.5 dB step by an internal
DIL-switch (S501). The same type of SLIC (IC50), The DC/DC-converter (S33081), is designed to
as on Internal Telephone is used, but the External supply the telephone lines with DC-voltage and
Telephone interface is designed to meet the Ring- voltage independent of battery voltage. The
requirements for a longer line. battery voltage can vary from 20-60 volt and be
positive or negative referred to earth. The Line feed
The Loudspeaker output (J1, pin35), is not equipped is protected against short cut in the SLICs whitch
with a volume control. If this is necessary, a limits the line current to 35 mA. The Ring current is
loudspeaker with volume control can be used limted in a PTC of 35 mA (R320).
If more than three SCIs shall be connected, the

EOW can be used. A ring coupling can connect the
SCIs in a way that connects all of them, but if there
J1, pin1 J1, pin17 J1, pin1

OEO1 J1, pin2 J1, pin18 EOWI OEO1 J1, pin2
SCI J1, pin11 J1, pin5 SCI J1, pin11
J1, pin18
J1, pin17
OEI1 J1, pin12 J1, pin6 EOWO OEI1 J1, pin12
J1, pin6
J1, pin5
EOWO EOWI
SCI*
OEI1 OEO1
J1, pin1
J1, pin2
J1, pin11
J1, pin12

OEO1 J1, pin2 J1, pin12 OEI1 EOWO J1, pin6
SCI J1, pin11 J1, pin1

SCI* J1, pin17
OEI1 J1, pin12 J1, pin2 OEO1 EOWI J1, pin18
SCI = Service channel interface

EOWI = EOW input
EOWO = EOW output
OEO1 = Other equipment 1 out
OEI1 = Other equipment 1 inp.
* = Not available for Internal telephone connection
Fig. 2 : Connection Diagram for more than 3 SCI's
H2143 7
2NF467/2NF468/2NF533A
3.1.1 Set-Up / Strapping:

Strapping of artificial load External telephone (S33083):
Artificial load W501
600 ohm 1-2, 4-5, 7-8
600 ohm + 1uF 2-3, 5-6, 8-9
Strapping of levels Other equipment 1 & 2 input (S33084):
Input Other eqpt 1 Other eqpt 2
Strap W603 W605
0 dB OFF OFF
+ 0.5 dB 2-3 2-3
- 0.5 dB 1-2 1-2
Strapping of balanced/unbalanced .interfaces (S33082 and S33084):
Interface EOW Other eqpt 1 Other eqpt2
Straps concerned W401 W601 W602
Strap
Balanced ON
Unbalanced OFF
Strapping of W604 (S33084):
This strap connects the Other eqpt 1 & 2 input When any adapter is connected to rear contact P1, the
and the 4w bal/unbal input to the SCI. When none straps W101 and W102 should be in position 2-3/4-
of these inputs are used, the strap should be off. 5/8-9, else in position 1-2/4-5/7-8.
Strapping of interface to Service Channel Adapters
(Such as PABX-adapter) (S33079):
8 H2143
2NF467/2NF468/2NF533A
Straping for positive or negative supply on E/M, Control and Call Wires (S33080):
Interface Straps conserned
E-Wire W204
M-Wire W209
Call-inp W207
Call-out W205
Control 1 W208
Control 2 W206
Strap
Positive 48V supply 1-2, 4-5
Negative 48V supply 2-3, 5-6
Setting of DIL-switches for attenuators (S33083 and S33084):
By means of the DIL-switches the attenuators can vary from 0 to 15.5 (7.5) in 0.5 dB step
Switch= "OFF" means 0 attenuation
Switch= "ON" means the following attenuations:
Att. Ext. tel inp Ext. tel out 4W bal inp 4W bal out
0.5 dB S501 sw5 S501 sw1 S601 sw1 S602 sw1
1.0 dB S501 sw6 S501 sw2 S601 sw2 S602 sw2
2.0 dB S501 sw7 S501 sw3 S601 sw3 S602 sw3
4.0 dB S501 sw8 S501 sw4 S601 sw4 S602 sw4
8.0 dB S601 sw5 S602 sw5
H2143 9
2NF467/2NF468/2NF533A
Setting of DIL-switches for selective calling (S33080):
Ext. tel 1. digit S201 sw4 S201 sw3 S201 sw2 S201 sw1
Ext. tel 2. digit S201 sw8 S201 sw7 S201 sw6 S201 sw5
Int. tel 1. digit S202 sw4 S202 sw3 S202 sw2 S202 sw1
Int. tel 2. digit S202 sw8 S202 sw7 S202 sw6 S202 sw5
1 ON ON ON OFF
2 ON ON OFF ON
3 ON ON OFF OFF
4 ON OFF ON ON
5 ON OFF ON OFF
6 ON OFF OFF ON
7 ON OFF OFF OFF
8 OFF ON ON ON
9 OFF ON ON OFF
0 OFF ON OFF ON
* OFF ON OFF OFF
# OFF OFF ON ON
* and # are normally not used for selective calling
10 H2143
2NF467/2NF468/2NF533A
Setting of DIL-switches for time-slot choice (S33080):
Time slot S204 sw2 S204 sw3 S204 sw4 S204 sw5
0 , 16 ON ON ON ON Not allowed
1 , 17 ON ON ON OFF Supervisory use
2 , 18 ON ON OFF ON
3 , 19 ON ON OFF OFF
4 , 20 ON OFF ON ON
5 , 21 ON OFF ON OFF
6 , 22 ON OFF OFF ON
7 , 23 ON OFF OFF OFF
8 , 24 OFF ON ON ON
9 , 25 OFF ON ON OFF
10,26 OFF ON OFF ON
11,27 OFF ON OFF OFF
12,28 OFF OFF ON ON
13,29 OFF OFF ON OFF
14,30 OFF OFF OFF ON
15,31 OFF OFF OFF OFF
Strapping of W210 "Constant off hook" (S33080)
This strap simulates an off hook situation and leads

to a full D/A - A/D convertion constantly. This
should normally be off, but whenever any analog
connections are made to J1, the strap should be on.
3.1.2 How to use the equipment.

The SCI is connected directly to the omnibus two periods of aprox. one second. If a telephone has
without switching. Therefore no signalling is been reached with the selective number, a tone can
necessary to be throughconnected. Once any be heared on the omnibus channel.
telephone is off hook, it is connected.
· Use of collective call · External Loudspeaker

-When *-button or "Call"-button (S203) i - The loudspeaker output is normally open on all
pushed on any station, there will be a ring in all stations. To mute all the speakers connected to the
telephones connected to the omnibus. The ring omnibus, lift off your telephone and press #. (This
will last as long as the button is held. will also activate the Control 2 signal).
· Use of selective call

-The two digits have to be sent within approx.
five seconds. If one of these digits is wrong, just
wait for five seconds and then send two correct
digits. The correct telephone will then ring in
H2143 11
2NF467/2NF468/2NF533A
3.1.2.1 External connections (S33079)
J1 SIGNALS
1 OTHER EQPT. 1 BAL/UNBAL OUT
2 OTHER EQPT. 1 BAL OUT
5 EOW_OUT_A BAL/UNBAL
6 EOW_OUT_B BAL
7 4W_OUT_A (BAL) / OPTIONAL EXT.
8 4W_OUT_B (BAL) / OPTIONAL EXT.
9 4W-UNBAL_OUT / OPTIONAL EXT.
11 OTHER EQPT. 1 BAL/UNBAL INP.
12 OTHER EQPT. 1 BAL INP
17 EOW_INP_A BAL/UNBAL
18 EOW_INP_B BAL/UNBAL
19 4W_INP_A (BAL) / OPTIONAL EXT.
20 4W_INP_B (BAL) / OPTIONAL EXT
21 4W_UNBAL_INP / OPTIONAL EXT.
23 2W_TEL_A
24 2W_TEL_B
25 E_WIRE
27 M_WIRE
29 CALL_INP
31 CALL_OUT
33 CONTROL1 (INP.)
34 CONTROL2 (OUT)
35 LOUDSPEAKER (OUT)
10,13,14,
22,26,28, GND
30,32,36
37
12 H2143
2NF467/2NF468/2NF533A
3.2 Service Channel Interface,

2NF467A.
The Service Channel Interface (SCI) 2NF467A

can be divided into three parts:
-Bus Interface
-Signalling logic
-Audio circuit
Figure 3 shows a Block schematic of the SCI.
SUBINSERT
DATABUS
TO/FROM
SERIAL
X701
BELL
CONTROL 1/2
INP/OUT
R201, R205, R207
R233, R238, R241
SIGNAL-
LOGIC
INTER-
LING
FACE
BUS
VLSI
IC20
INP/OUT
CALL
S 203
DEC
CO-
DEC
IC21
CO-
IC22
IC60A
W604
OTHER EQUIPMENT
IC61
IC43A
IC45B
IC48
LEVEL
DET.
IC10
IC41 LEVEL
DET.
IC45A
IC49
IC44
IC42
W
O
E
N
D
A
S
E
T
Fig. 3 : Block Schematic Diagram of the SCI

H2143 13
2NF467/2NF468/2NF533A
The Bus-interface is the interface towards the The Audio-Circuits distributes the voice-signals
Radio equipment. This is a 2 Mbit/s bus containing to the different interfaces. All the interfaces are
Serial Data send/receive, 2 MHz clock and 500 internally connected with the following exeption:
Hz Multiframe sync from Radio. On repeater
stations, both directions are transmitted on the Handset - EOW, are in parallell
same bus. Direction 1 can use timeslots 1-5, and only and not internally connected.
Dir. 2, 17-21. Timeslot in Dir. 1 is set on the SCI
by DIL-switches (S204). Dir.2 is always a distance To transfer the Audio signals to the bus there are
16 timeslots away from Dir. 1. two A-law CODECs with internal BP- Filters.
One Codec transmits in Direction 1 and receives
In each direction a total traffic of one 64 kbit/s and in Direction 2 and the other vice versa. The send/
two 500 bit/s signalling channels can be transmitted receive levels on both Codecs are adjustable
and received. (IC21 and IC22).
The LED (H101)- and external alarm is on (output The interface to the handset receptacle is equipped
to P2 pin20a and 20c), when the SCI is unable to with a speech controlled switch. This switch is
syncronize to the bus. opened once sound is detected in the microphone
and is kept open appr. 5 seconds after sound is
The signalling logic as well as the bus-interface detected in ether direction.
is contained in a VLSI-circuit (IC20). The signalling
is performed with a Call-button (S203) on the The Other equipment is ment for
front of the unit. This will cause a continious call interconnection between similar equipment, and
on every SCI connected as long as the Call 2 SCI- boards can be connected this way. This
button is held. It will also activate the Call-out interface is not overvoltage protected and the-
signal (J1, pin31). A call can also be performed refore not recomended for long lines or outdoor
by activating the Call-inp signal (J1, pin29). use. The other equipment can be selected
either balanced or unbalanced by internal straps.
One of the 500 bit/s transmission channel is The level on the input is adjustable +0.5 dB to
occupied for the Call-signals. compensate for cable losses and component
variation.
The other 500 bit/s channel (Control 1 / Control
2) is occupied for adapter connection. Control 1 If more than two SCIs shall be connected, the EOW
is the input and Control 2 the output when SCIs are can be used. A ring coupling can connect the SCIs
connected (Control 1 J1 pin33, Control2 J1 pin34). in a way that connects all of them, but if there should
be a fault on one of them, the connection between the
others might be broken. See Fig 4.

OEO J1, pin2 J1, pin18 EOWI OEO J1, pin2 SCI = Service channel interface
SCI J1, pin11 J1, pin5 SCI J1, pin11
EOWI = EOW input
J1, pin18
J1, pin17
OEI J1, pin12 J1, pin6 EOWO OEI J1, pin12
EOWO = EOW output

J1, pin6
J1, pin5
EOWO EOWI OEO = Other equipment out

SCI* OEI = Other equipment inp.
OEI OEO
J1, pin1
J1, pin2
J1, pin11
J1, pin12

* = Not available for Internal telephone
OEO J1, pin2 J1, pin12 OEI EOWO J1, pin6
connection
SCI J1, pin11 J1, pin1
SCI* J1, pin17
OEI J1, pin12 J1, pin2 OEO EOWI J1, pin18
Fig.4 Connection scheme for more than 2 SCIs
14 H2143
2NF467/2NF468/2NF533A
3.2.1 Set-Up / Strapping:
Strapping of levels "Other equipment input" (S33078)
Input Other eqpt 1
Strap W603
0 dB OFF
+0.5 dB 2-3
-0.5 dB 1-2
Strapping of balanced/unbalanced intrfaces (S33075 and S33078)
Interface EOW Other eqpt
Straps concerned W401 W601
Strap
Balanced ON
Unbalanced OFF
Strapping for positive or negative supply on Control and Call Wire (S33076)
Interface Straps conserned Strap
Call-inp W207 Positive 48V supply 1-2, 4-5
Call-out W205 Negative 48V supply 2-3, 5-6
Control 1 W208
Control 2 W206
Strapping of W604 (S33078):
This strap connects the Other eqpt input to the SCI. When this input is not used, the strap should be off.
H2143 15
2NF467/2NF468/2NF533A
Setting of DIL-switches for time-slot choise (S33076):
Time slot S204 sw2 S204 sw3 S204 sw4 S204 sw5
0,16 ON ON ON ON Not allowed

1,17 ON ON ON OFF Supervisory use
2,18 ON ON OFF ON
3,19 ON ON OFF OFF
4,20 ON OFF ON ON
5,21 ON OFF ON OFF
6,22 ON OFF OF ON
7,23 ON OFF OFF OFF
8,24 OFF ON ON ON
9,25 OFF ON ON OFF
10,26 OFF ON OFF ON
11,27 OFF ON OFF OFF
12,28 OFF OFF ON ON
13,29 OFF OFF ON OFF
14,30 OFF OFF OFF ON
15,31 OFF OFF OFF OFF
Strapping of W210 "Constant off hook" (S33076)
This strap simulates an off hook situation and leads should normally be off, but whenever any analog
to a full D/A - A/D convertion constantly. This connections are made to J1, the strap should be on.
3.2.2 How to use the equipment

The SCI is connected directly to the omnibus · Use of speech controlled switch.
without switching. Therefore no signalling is - When the handset receptacle is unused, it is
necessary to be throughconnected. switched off in both send and receive directions
by the speech controlled switch. To listen if there
· Use of collective call is any traffic going on the omnibus, one has to make
- When Call-button (S203) is pushed on any a sound to open the switch (IC10). Once the switch
station, there will be a ring on all SCIs connected is open it remains open appr. 10 seconds after
to the omnibus. The ring will last as long as the there has been any sound in either send or receive
button is held. direction.
16 H2143
2NF467/2NF468/2NF533A
3.2.2.1 External connections (S33077):
J1 SIGNALS
3 N. C.
4 N. C.
5 EOW_OUT_A BAL/UNBAL
6 EOW_OUT_B BAL
7 N. C.
8 N. C.
9 N. C.
15 N. C.
16 N. C.
17 EOW_INP_A BAL/UNBAL
18 EOW_INP_B BAL/UNBAL
19 N. C.
20 N. C.
21 N. C.
23 N. C.
24 N. C.
25 N. C.
27 N. C.
29 CALL_INP
31 CALL_OUT
33 CONTROL1 (INP.)
34 CONTROL2 (OUT)
35 N. C.
10,13,14,22
26,28,30,32 GND
36,37
H2143 17
SERVICE CHANNEL CONNECTION
EK66A
H2694 Rev. A
© Nera AS
EK66A
Item No. Code: Description:

1 MBB84 Bracket
2 87A10-H6 Connector, Chassis
3 87K86-5B Housing
4 87K86-1D Terminal, Wire
-
6 87J99-1R Lamp, Indicator
2 H2694
DISTRIBUTION BOARD
SERVICE RACK
EW53A
H2696 Rev. C
© Nera AS
EW53A

This board is a connection and distribution panel for the
service rack as well as backplane for 2 pcs 64kb/s
Adapters, Alarm Board, Alarm Collection Unit,
RSOH Adapter, Supervisory Unit and Radio Protec-
tion Switching Board.
To use the same Alarm Collection Unit as in the radio
rack, some of the alarms must be converted into serial
form. The circuits to convert the alarms from parallel to
serial form - as well as the oscillator which is controlling
this - are located on this board.
A number of straps and DIL-switches are necessary to
configure the rack. Depending on terminal or repeater-
2.048MHz external Sync or not, Protection Switching
or not, number of Adapters and number of Service
Telephones- the straps and DIL-switches have to be set
according to the table on the opposite page.
Fig.1, Distribution Board, Service Rack, EW53A

2
H2696
EW53A
DIL-SWITCH and STRAPS

S1-1: 64kb/s ADAPTER 1 ALM is disabled when closed.
S1-2: 64kb/s ADAPTER 2 ALM is disabled when closed.
S1-3: RSOH ADAPTER ALM is disabled when closed.
S1-4: MCF-BOARD ALM is disabled when closed.

S1-5: SU ALM is disabled when closed.
S1-6: RPS-BOARD ALM is disabled when closed.
S1-7: XMTR SW ALM is disabled when closed.

S1-8: XMTR SW SPACE ALM is disabled when closed.
S2-1: PWR SUPPLY ALM is disabled when closed.

S2-2: RCVR DIST. UNIT ALM is disabled when closed.
S2-3: SPARE ALM is disabled when closed.


S2-8: TEST MODE ALM is disabled when closed.
S3-1: ADDRESS_0
S3-2: ADDRESS_1
S3-3: ADDRESS_2
S3-4: ADDRESS_3 Supervisory Unit Address.

S3-5: ADDRESS_4 Open = High
S3-6: ADDRESS_5 Closed= Low
S3-7: ADDRESS_6
S3-8: ADDRESS_7
S4-1: XMTR1 INP ALM, SYNC UNIT is disabled when closed

S4-2: XMTR2 INP ALM, SYNC UNIT is disabled when closed
S4-3: RCVR-A ALM, SYNC UNIT is disabled when closed
S4-4: RCVR-B ALM, SYNC UNIT is disabled when closed

S4-5: PLL ALM, SYNC UNIT is disabled when closed
S4-6: SPARE ALM is disabled when closed

S5-1: ALM 9-16 Alarms from Service Channel Cassette to be disabled

when closed ( if no cassette is present).
S5-2: ALM 17-24 Alarms from Adapter Cassette to be disabled when
closed (if no cassette is present).
S5-3: ALM 25-32 Alarms from Additional Adapter Cassette to be disabled
when closed ( if no cassette is present).
S5-4: ALM 33-40 Not in use. To be closed.
W1:
W2:
W3: Straps to be present on Repeaters only.
W4:
W5: This strap is used to enable occasional traffic on Ch.P in a N+1 protect-
ed system. The strap shall be removed to enable occ. traffic to be controlled
by the Radio Protection Switching Board. In a system without RPS, the
position of W5 has no significance and is parked in the ON position.
3
H2696
2Mb BUS
P1 P8 J1 J3 J6 J9 J11 P15 P19 ADAPT ALM EXT. CHP CHP CH1 CH1 SVCE ADAPT OMNI-
GND 1 GND 1 GND 1a GND 1a GND 1a GND 1a GND 1a GND 1 +5V 1 SYNC XMTR SERIAL
VOLT. RCVR DIST UNIT SWITCH COMM. CH P CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 RPS SU MCF -RSOH ACU BORD ADAPT ADAPT PC ALM. SCADA DIR1 DIR2 DIR1 DIR2 DCC DISPLAY CHAN ALM BUS
GND 2 +15V 2 GND 1b GND 1c GND 1c GND 1b GND 1c GND 2 +5V 2
-15V 3 P8-3 3 GND 1c J3-2a 2a +5.0V 2a GND 1c +5.0V 2a P15-3 3 J3-15c 3 P1- P3- P4- P5- P6- P7- P8- P9- P10- P11- P12- P13- P14- J1- J2- J3- J4- J5- J6- J7- J8- J9- J10- J11- J12- J13- J14- J15- P15- P16- P17- P18- J16- P19- P20- P21- P22-
-15V 4 -5.2V 4 2a J3-2c 2c +5.0V 2c +5.0V 2a +5.0V 2c P15-4 4 J3-11c 4 GND (SEE CONNECTOR SYMBOLS)
-15V 5 +5.0V 5 2b J3-3a 3a -5.2V 3a 2b -5.2V 3a J8-27a 5 J3-11a 5 +5.0V 33-46 5 5 5 5 5 5 5 5 2a,2b,2c 2a,2c 2a,2c 2a,2c 2a,2c 2a,2c 2a,2c 2a,2c 28
-15V 6 P8-6 6 2c J3-3c 3c -5.2V 3c +5.0V 2c -5.2V 3c J8-27c 6 J3-10c 6 -5.2V 17-28 4 4 4 4 4 4 4 4 3a,3b,3c 3a,3c 3a,3c 3a,3c 3a,3c 3a,3c 3a,3c 3a,3c 18 2 OMNIBUS_CALL_IND
GND 7 P8-7 7 3a J3-4a 4a +15V 4a -5.2V 3a +15V 4a J8-28a 7 J3-10a 7 +15V 9-14 2 2 2 2 2 2 2 2 4a,4b,4c 4a,4c 4a,4c 4a,4c 4a,4c 4a,4c 4a,4c 4a,4c 19 3 OMNIBUS_TEL_B
GND 8 GND 8 3b J3-4c 4c +15V 4c 3b +15V 4c J8-28c 8 J3-15a 8 -15V 3-6 5a,5b,5c 5a,5c 5a,5c 5a,5c 5a,5c 5a,5c 5a,5c 5a,5c 36 20 4 OMNIBUS_TEL_A
+15V 9 P8-9 9 3c J3-5a 5a -15V 5a -5.2V 3c -15V 5a P15-9 9 J3-12c 9 XMTRSW_ALM_MOD_CH7 7 6c 2a;c 3;4 SCADA TXD+;TXD-
+15V 10 P8-10 10 4a J3-5c 5c -15V 5c +15V 4a -15V 5c P15-10 10 J3-12a 10 CMI_SPLIT_DATA_INP_ALM_CH7 6 7a 3a;c 7;8 SCADA RXD+;RXD-
+15V 11 P8-11 11 4b J3-6a 6a J4-6a 6a 4b 6a GND 11 J3-9a 11 EWBER_SEC_IND_CH7 10 7b 4a;c 5;6 SCADA RXC+;RXC-
+15V 12 P8-12 12 P5-4 4c J3-6c 6c J4-6c 6c +15V 4c 6c 12 J3-14a 12 RELAY_ALM_DEM_CH7 11 7c
+15V 13 GND 13 P5-5 5a J3-7a 7a 7a -15V 5a 7a 13 J3-13c 13 LBER_SEC_IND_CH7 9 8a
+15V 14 P8-14 14 P5-8 5b J3-7c 7c 7c 5b 7c 14 J3-14c 14 SYNCL_SEC_ALM_CH7 12 8b 25a 3 HCI_TXD
GND 15 P8-15 15 P3-7 5c J3-8a 8a 8a -15V 5c J7-5a 8a 15 J1-13a 15 XMTRSW_ALM_MOD_CH6 7 9b 25c 2 HCI_RXD
16 P8-16 16 P3-10 6a J3-8c 8c 8c 6a 8c 16 J1-13c 16 CMI_SPLIT_DATA_INP_ALM_CH6 6 9c 26a 7 HCI_RTS
-5.2V 17 17 P5-9 6b J3-9a 9a 9a 6b 9a 17 J1-14a 17 EWBER_SEC_IND_CH6 10 10a 26c 8 HCI_CTS
-5.2V 18 P7-18 18 P3-12 6c J3-9c 9c 9c 6c 9c 18 J1-14c 18 RELAY_ALM_DEM_CH6 11 10b 27a 6 HCI_DSR
-5.2V 19 P8-19 19 P3-11 7a J3-10a 10a 10a 7a J7-6a 10a 19 J1-15a 19 LBER_SEC_IND_CH6 9 10c 27c 1 HCI_DCD
-5.2V 20 GND 20 P5-13 7b J3-10c 10c 10c 7b 10c 20 J1-15c 20 SYNCL_SEC_ALM_CH6 12 11a 28a 4 HCI_DTR
-5.2V 21 7c J3-11a 11a 11a 7c 11a GND 21 J1-16a 21 XMTRSW_ALM_MOD_CH5 7 12a 22b;c 1;2 EXT_ALM1_OUT -64kb/s ADAPT (C;E)
3M20 CMI_SPLIT_DATA_INP_ALM_CH5 6 12b 23a;b 3;4 EXT_ALM2_OUT -XMTR SW (C;E)
-5.2V 22 P3-5 8a J3-11c 11c 11c 8a 11c GND 22 J1-16c 22
-5.2V 23 P3-8 8b J3-12a 12a J4-12a 12a 8b J7-7a 12a J8-29a 23 J3-13a 23 EWBER_SEC_IND_CH5 10 12c 23c;24a 5;6 EXT_ALM3_OUT -SU&MCF (C;E)
-5.2V 24 8c J3-12c 12c J4-12c 12c 8c 12c J8-29c 24 J3-9c 24 RELAY_ALM_DEM_CH5 11 13a 24b;c 7;8 EXT_ALM4_OUT -PWR SPLY (CENTRE;NO/NC)
P9 LBER_SEC_IND_CH5 9 13b 25a;b 9;10 EXT_ALM5_OUT -RCVR DIST (C;E)
-5.2V 25 GND 1 9a J3-13a 13a J4-13a 13a 9a 13a J8-30a 25 25
-5.2V 26 9b J3-13c 13c J4-13c 13c P6-11 9b 13c J8-30c 26 26 SYNCL_SEC_ALM_CH5 12 13c 25c;26a 11;12 EXT_ALM6-OUT -RSOH ADAPT (C;E)
+15V 2 XMTRSW_ALM_MOD_CH4 7 14c 26b;c 13;14 EXT_ALM7_OUT -MSOH ADAPT (C;E)
-5.2V 27 P9-3 3 9c J3-14a 14a J4-14a 14a P6-12 9c 14a J8-31a 27 27
-5.2V 28 J1-10a 10a J3-14c 14c J4-14c 14c P6-7 10a 14c J8-31c 28 28 CMI_SPLIT_DATA_INP_ALM_CH4 6 15a 27a;b 15;16 EXT_ALM8-OUT -SERV TEL (C;E)
-5.2V 4 EWBER_SEC_IND_CH4 10 15b 27c;28a 17;18 EXT_ALM9-OUT -AAU (C;E)
GND 29 +5.0V 5 J1-10b 10b J3-15a 15a J4-15a 15a P6-8 10b 15a 29 29
GND 30 J1-10c 10c J3-15c 15c J4-15c 15c J9-10c 10c 15c 30 30 RELAY_ALM_DEM_CH4 11 15c 28b;c 19;20 EXT-ALM10-OUT -RPS (C;E)
P9-6 6 LBER_SEC_IND_CH4 9 16a 29a;b 21;22 EXT_ALM11_OUT -SYNC UNIT/TEST MODE (C;E)
P1-31 31 P9-7 7 J1-11a 11a J1-13a 16a J4-16a 16a J9-11a 11a 16a 3M30 31
32 J1-11b 11b J1-13c 16c J4-16c 16c J8-19a 11b 16c 32 SYNCL_SEC_ALM_CH4 12 16b 31a 23 EXT_MAIN_ALM_OUT (NO)
GND 8 XMTRSW_ALM_MOD_CH3 7 17b 31b 24 EXT_MAIN_ALM_OUT (CENTRE)
+5.0V 33 P9-9 9 J1-11c 11c J1-14a 17a J4-17a 17a J6-18a 11c 17a 33
+5.0V 34 J1-12a 12a J1-14c 17c J4-17c 17c J4-18a 12a 17c P16 34 CMI_SPLIT_DATA_INP_ALM_CH3 6 17c 31c 25 EXT_MAIN_ALM_OUT (NC)
P9-10 10 GND 1 EWBER_SEC_IND_CH3 10 18a 5a 8a 8a 2 RXD 2MB INT BUS
+5.0V 35 P9-11 11 J1-12b 12b J1-15a 18a J6-18a 18a J1-12c 12b J7-5c 18a 35
+5.0V 36 J1-12c 12c J1-15c 18c 18c P5-2 12c 18c GND 2 -15V 36 RELAY_ALM_DEM_CH3 11 18b 5c 18a 18a 4 TXD 2MB INT BUS C=COLLECTOR
P9-12 12 J8-20a 3 LBER_SEC_IND_CH3 9 18c 6a 10a,20a 10a,20a CLK1 2MB INT BUS E=EMITTER
+5.0V 37 GND 13 J1-13a 13a J1-16a 19a 19a P5-4 13a 19a GND 37
+5.0V 38 13b J1-16c 19c 19c J9-13b 13b 19c J8-20c 4 GND 38 SYNCL_SEC_ALM_CH3 12 19a 6c 6 CLK2 2MB INT BUS NO=NORMALY OPEN
P9-14 14 J8-21a 5 XMTRSW_ALM_MOD_CH2 7 20a 7a 12a,22a 12a,22a BYTE1 2MB INT BUS NC=NORMALY CLOSED
+5.0V 39 P9-15 15 J1-13c 13c J1-17a 20a 20a J9-13c 13c J7-6a 20a GND 39
+5.0V 40 J1-14a 14a J1-17c 20c 20c J9-14a 14a 20c J8-21c 6 GND 40 CMI_SPLIT_DATA_INP_ALM_CH2 6 20b 7c 8 BYTE2 2MB INT BUS
P9-16 16 J8-22a 7 EWBER_SEC_IND_CH2 10 20c 5a;c 5a;c 3;10 NI TXD+;TXD-
+5.0V 41 17 14b J1-18a 21a 21a J9-14b 14b 21a 3M40
+5.0V 42 J1-14c 14c J1-18c 21c 21c 14c 21c J8-22c 8 RELAY_ALM_DEM_CH2 11 21a 6a;c 6a;c 7;15 NI TXC+;TXC-
GND 18 P16-9 9 LBER_SEC_IND_CH2 9 21b 7a;c 7a;c 5;12 NI RXD+;RXD-
+5.0V 43 19 J1-15a 15a J1-19a 22a 22a P1-31 15a J7-7a 22a
+5.0V 44 15b J1-19c 22c 22c P3-1 15b 22c P16-10 10 SYNCL_SEC_ALM_CH2 12 21c 8a;c 8a;c 2;9 NI RXC+;RXC-
GND 20 GND 11 XMTRSW_ALM_MOD_CH1 7 22c 9a 11 A0
+5.0V 45 J1-15c 15c J1-20a 23a 23a P3-2 15c 23a
+5.0V 46 3M20 J1-16a 16a J1-20c 23c 23c P3-4 16a 23c 12 CMI_SPLIT_DATA_INP_ALM_CH1 6 23a 9c 24 A1
GND 47 16b J1-21a 24a 24a P3-9 16b 1 24a 13 EWBER_SEC_IND_CH1 10 23b 10a 7 A10
C1 14 RELAY_ALM_DEM_CH1 11 23c 10c 6 A11
GND 48 J1-16c 16c J1-21b 24c 24c P3-13 16c 100nF 24c
GND 49 P10 J1-17a 17a J1-21c 25a 25a P3-14 17a 25a 15 LBER_SEC_IND_CH1 9 24a 11a 5 A12
2
GND 50 GND 1 17b J1-22a 25c 25c J4-18c 17b 25c 16 SYNCL_SEC_ALM_CH1 12 24b 11c 4 A13
+15V 2 J1-17c 17c J1-22b 26a 26a J9-17c 17c 26a 17 XMTRSW_ALM_MOD_CHP 7 25b 12a 10 IR11
3M50 P10-3 3 18 CMI_SPLIT_DATA_INP_ALM_CHP 6 25c 12c 9 PCLK
J1-18a 18a J1-22c 26c 26c J9-18a 18a 26c
-5.2V 4 18b J1-23a 27a 27a 18b 27a 19 EWBER_SEC_IND_CHP 10 26a 13a 23 IO/M R5
+5.0V 5 20 RELAY_ALM_DEM_CHP 11 26b 13c 13 IOWR 1 2 +5V
J1-18c 18c J1-23b 27c 27c 18c 27c
P10-6 6 J1-19a 19a J1-23c 28a 28a 19a 28a GND 21 LBER_SEC_IND_CHP 9 26c 14a 12 IORD 10k
P10-7 7 19b 28c 28c 19b 28c GND 22 SYNCL_SEC_ALM_CHP 12 27a 14c 14 WSRQ1 R6
GND 8 P16-23 23 EN_PROT_RDU 5 8a 15a 8 RESET 2 1
J1-19c 19c J3-29a 29a 29a 19c 29a 3
P10-9 9 J1-20a 20a J3-29c 29c 29c 20a 29c P16-24 24 SEL_140_RDU 8 8b 15c 3 CS15
P10-10 10 J8-24a 25 13a 16a 16a 15 FIFO_RPS_0 4
20b J3-30a 30a 30a J9-20b 20b 30a 5
P10-11 11 J1-20c 20c J3-30c 30c 30c J9-20c 20c 30c J8-24c 26 2M_SYNC_MOD+ 3 3 13c 16c 16c 16 FIFO_RPS_1
P10-12 12 J8-25a 27 2M_SYNC_MOD- 4 4 14a 17a 17a 17 FIFO_RPS_2 6
J1-21a 21a J3-31a 31a 31a J9-21a 21a 31a 7
GND 13 J1-21b 21b J3-31c 31c 31c J9-21b 21b J9-10c 31c J8-25c 28 2M_SYNC_DEM_CH A+ 7 15 14c 17c 17c 18 FIFO_RPS_3
P10-14 14 29 2M_SYNC_DEM_CH A- 8 16 15a 18a 18a 19 FIFO_RPS_4 8
J1-21c 21c GND 32a GND 32a GND 21c GND 32a
P10-15 15 J1-22a 22a GND 32c GND 32c GND 22a GND 32c 30 2M_SYNC_DEM_CH B+ 11 19 15c 18c 18c 20 FIFO_RPS_5 10k
P10-16 16 J1-22b 22b 22b 3M30 2M_SYNC_DEM_CH B_ 12 20 16a 19a 19a 21 FIFO_RPS_6
17 EU64 EU64 EU64 16c 19c 19c 22 FIFO_RPS_7 74HCT373
J1-22c 22c 22c ULN2803A
GND 18 J1-23a 23a 23a RELAY7 1 18 RCVR_RELAY_CTRL_CH7 3 27b RELAY_CTRL_7 3 1D 1Q 2
19 J1-23b 23b J4 J7 23b RCVR_RELAY_CTRL_CH6 3 27c RELAY_CTRL_6 4 2D 2Q 5
GND 20 J12 RCVR_RELAY_CTRL_CH5 3 28a RELAY_CTRL_5 7 6
J1-23c 23c GND 1a GND 1a 23c GND 1a RELAY6 2 17 3D 3Q
3M20 P14-15 24a GND 1c GND 1c 24a RCVR_RELAY_CTRL_CH4 3 28b RELAY_CTRL_4 8 4D 4Q 9
GND 1c RCVR_RELAY_CTRL_CH3 3 28c RELAY_CTRL_3 13 12
P3 P13-15 24b +5.0V 2a 2a 24b +5.0V 2a RELAY5 3 16 5D 5Q
P12-15 24c +5.0V 2c 2c 24c RCVR_RELAY_CTRL_CH2 3 29a RELAY_CTRL_2 14 6D 6Q 15
P3-1 1 +5.0V 2c RCVR_RELAY_CTRL_CH1 3 29b RELAY_CTRL_1 17 16
P3-2 2 P11 P11-15 25a -5.2V 3a 3a 25a -5.2V 3a RELAY4 4 15 7D 7Q
GND 1 P10-15 25b -5.2V 3c 3c 25b RCVR_RELAY_CTRL_CHP 3 29c RELAY_CTRL_P 18 8D 8Q 19
P3-3 3 -5.2V 3c ALIGN_IND_DEM 07 15 24a 27a 27 MAIN ALM,RACK 1
P3-4 4 +15V 2 P9-15 25c +15V 4a 4a 25c +15V 4a RELAY3 5 14 CLR
P11-3 3 P8-15 26a +15V 4c 4c P6-22 26a ALIGN_IND_DEM 06 15 24b 6a 3 D1R12+ DEM/DIR2 11
P3-5 5 +15V 4c ALIGN_IND_DEM 05 15 24c 6c 4 D1R12- DEM/DIR2 IC9
P3-6 6 -5.2V 4 P7-15 26b -15V 5a J7-5a 5a 26b -15V 5a RELAY2 6 13
+5.0V 5 P14-14 26c -15V 5c J7-5c 5c 26c ALIGN_IND_DEM 04 15 25a 7a 5 CLKR12+ DEM/DIR2
P3-7 7 -15V 5c ALIGN_IND_DEM 03 15 25b 7c 6 CLKR12- DEM/DIR2
P3-8 8 P11-6 6 P13-14 27a J4-6a 6a J7-6a 6a J9-27a 27a 6a RELAY1 7 12
P11-7 7 P12-14 27b J4-6c 6c J7-6c 6c 27b ALIGN_IND_DEM 02 15 25c 8a 7 SYNCR12+ DEM/DIR2
P3-9 9 6c ALIGN_IND_DEM 01 15 26a 8c 8 SYNCR12- DEM/DIR2
P3-10 10 GND 8 P11-14 27c 7a J7-7a 7a 27c 7a RELAYP 8 11
P11-9 9 P10-14 28a 7c J7-7c 7c 28a ALIGN_IND_DEM 0P 15 26b STRAP2 W1
P3-11 11 7c CHAN_SEL 07 14 26c 9a 1 3 23 D1R32+ DEM/DIR2
P3-12 12 P11-10 10 P9-14 28b 8a 8a 28b J7-5a 8a 10
P11-11 11 P8-14 28c 8c 8c 28c CHAN_SEL 06 14 27a 9c 2 4 24 D1R32- DEM/DIR2 RELAY-BUS
P3-13 13 8c CHAN_SEL 05 14 27b 18c
P3-14 14 P11-12 12 P7-14 29a P6-11 9a J1-10a 9a 29a 9a IC1 RELAY7
GND 13 P14-16 29b P6-12 9c J1-10b 9c 29b CHAN_SEL 04 14 27c 10a 25 CLKR32+ DEM/DIR2
3M14 9c RELAY BUS P20 CHAN_SEL 03 14 28a 10c 26 CLKR32- DEM/DIR2 RELAY6
P11-14 14 P13-16 29c P6-7 10a J1-10c 10a 29c J7-6a 10a GND 1 RELAY5
P11-15 15 P12-16 30a P6-8 10c J1-11a 10c 30a CHAN_SEL 02 14 28b 11a 27 SYNCR32+ DEM/DIR2
10c J7-5a 2 CHAN_SEL 01 14 28c 18a RELAY4
P4 P11-16 16 P11-16 30b 11a J1-11b 11a 30b 11a P17 GND 3 RELAY3
P4-1 1 17 P10-16 30c 11c J1-11c 11c 30c CHAN_SEL 0P 14 29a 11c 28 SYNCR32- DEM/DIR2
11c GND 1 J7-5c 4 MS_AIS_INS_DEM 07 16 29b RELAY2
P4-2 2 GND 18 P9-16 31a J4-12a 12a J1-12a 12a 31a J7-7a 12a GND 2 GND 5 RELAY1
P4-3 3 P11-19 19 P8-16 31b J4-12c 12c J1-12b 12c 31b MS_AIS_INS_DEM 06 16 29c STRAP2 W2
12c P17-3 3 J7-6c 6 MS_AIS_INS_DEM 05 16 30a 12a 1 3 3 D1R11+ MOD/DIR1 RELAYP
P4-4 4 GND 20 P7-16 31c J4-13a 13a 13a 31c 13a P17-4 4 GND 7
P4-5 5 GND 32a J4-13c 13c 13c GND 32a MS_AIS_INS_DEM 04 16 30b 12c 2 4 4 D1R11- MOD/DIR1
3M20 13c J8-13a 5 J7-7c 8 MS_AIS_INS_DEM 03 16 30c 13a 5 CLKR11+ MOD/DIR1 1
P4-6 6 GND 32b J4-14a 14a 14a GND 32b 2 2
14a J8-13c 6 P6-7 9 MS_AIS_INS_DEM 02 16 31a 13c 6 CLKR11- MOD/DIR1 G1 G2 R9
P4-7 7 GND 32c J4-14c 14c 14c GND 32c 14c J8-14a 7 P6-8 10 2800 2800 100k
P4-8 8 J4-15a 15a 15a MS_AIS_INS_DEM 01 16 31b 14a 7 SYNCR11+ MOD/DIR1 1 1
P12 EU96 EU96 15a J8-14c 8 P6-11 11 2
P4-9 9 J4-15c 15c 15c MS_AIS_INS_DEM 0P 16 31c 14c 8 SYNCR11- MOD/DIR1
GND 1 15c 9 P6-12 12 RD_PU_CTRL 6 6 25 30c 1
R7 2
P4-10 10 +15V 2 J4-16a 16a 16a 16a 10 P20-13 13
P4-11 11 J4-16c 16c 16c STRAP2 W5 EN_PU_CTRL 3 3 27 31a 100k R10
P12-3 3 J2 J10 16c GND 11 P20-14 14 2 4 UNPRIO_MOD_CHP 8 31b 15a 23 D1R31+ MOD/DIR1 1 2
P4-12 12 -5.2V 4 GND 1a J4-17a 17a 17a GND 1a 17a 12 P20-15 15 R8
1 3 UNPRIO_DEM_CHP 13 31c 15c 24 D1R31- MOD/DIR1 1 2 10k
P4-13 13 +5.0V 5 GND 1b J4-17c 17c 17c GND 1b 17c 13 P20-16 16 RMT_RESET_SU-MOD_CHP&CH1 18 18 30c 16a 25 CLKR31+ MOD/DIR1 100k +5V 3
GND 14 P12-6 6 GND 1c J4-18a 18a 18a GND 1c J7-5c 18a 14 P20-17 17 RMT_RESET_SU_DEM_CHP-DIR1 19 31a 16c 26 CLKR31- MOD/DIR1 2
3M14 P12-7 7 +5.0V 2a J4-18c 18c 18c +5.0V 2a 18c 15 P20-22 18 Q1
J4-19a 19a 19a RMT_RESET_SU_DEM_CH1-DIR1 19 30a 17a 27 SYNCR31+ MOD/DIR1 1
GND 8 +5.0V 2b 2b 19a 16 P20-23 19 1 2N3904
RMT_RESET_SU_DEM_CHP-DIR2 19 29c 17c 28 SYNCR31- MOD/DIR1 R11 + C19 1
P12-9 9 +5.0V 2c J4-19c 19c 19c +5.0V 2c 19c 17 P20-24 20
P5 J4-20a 20a 20a RMT_RESET_SU_DEM_CH1-DIR2 19 29a 33k 100uF
GND 1 P12-10 10 -5.2V 3a -5.2V 3a J7-6a 20a 18 GND 21 2 2
P12-11 11 -5.2V 3b J4-20c 20c 20c 3b 20c 19 P6-22 22
P5-2 2 J4-21a 21a 21a 100
P3-3 3 P12-12 12 -5.2V 3c -5.2V 3c 21a 20 23 20a 3 D1P12+ DEM/DIR2 1
GND 13 +15V 4a J4-21c 21c 21c +15V 4a 21c GND 21 24
P5-4 4 J4-22a 22a 22a FIFO_SU_0;_SU_1 17a;17c 20a;20c 20c 4 D1P12- DEM/DIR2 2
P5-5 5 P12-14 14 +15V 4b 4b J7-7a 22a GND 22 25 FIFO_SU_2;_SU_3 18a;18c 21a;21c 21a 5 CLKP12+ DEM/DIR2 3
P12-15 15 +15V 4c J4-22c 22c 22c +15V 4c 22c J8-15a 23 26
P3-6 6 P4-2 23a 23a FIFO_SU_4;_SU_5 19a;19c 22a;22c 21c 6 CLKP12- DEM/DIR2 4
P3-7 7 P12-16 16 -15V 5a -15V 5a 23a J8-15c 24 J9-27a 27 FIFO_SU_6;_SU_7 20a;20c 23a;23c 22a 7 SYNCP12+ DEM/DIR2 5
17 -15V 5b P4-1 23c 23c 5b 23c J8-16a 25 +5.0V 28
P5-8 8 22c 8 SYNCP12- DEM/DIR2 6
RP5H2
GND 18 -15V 5c 24a 24a -15V 5c 1 24a J8-16c 26 P20-29 29
P5-9 9 24c 24c C2 MAVA1_SU 21a 24a 9 D2P12+ DEM/DIR2 7
P3-10 10 P12-19 19 6a 6a 100nF 24c J8-17a 27 GND 30 MAVA_RPS 21b 24c STRAP2 W3 10 D2P12- DEM/DIR2 8
GND 20 6b J4-25a 25a 25a 6b 25a J8-17c 28
P3-11 11 2 3M30 READ1_SU 21c 25a 23a 1 3 23 D1P32+ DEM/DIR2 9
P14-7 6c J4-25c 25c 25c 6c 25c 29
P3-12 12 3M20 J4-26a 26a 26a READ_RPS 22a 25c 23c 2 4 24 D1P32- DEM/DIR2 10
P5-13 13 P14-6 7a 7a 26a 30 CTRL_SIGN_SU_RPS_1 22b 26a 24a 25 CLKP32+ DEM/DIR2 11
P14-10 7b J4-26c 26c 26c 7b 26c P21
GND 14 J4-27a 27a 27a 3M30 P21-1 1 CTRL_SIGN_SU_RPS_2 22c 26c 24c 26 CLKP32- DEM/DIR2 12
P13 P14-11 7c 7c 27a CTRL_SIGN_SU_RPS_3 23a 27a 25a 27 SYNCP32+ DEM/DIR2
3M14 P14-9 8a J4-27c 27c 27c 8a 27c P21-2 2 R12
GND 1 J4-28a 28a J3-29a 28a P18 P21-3 3 CTRL_SIGN_SU_RPS_4 23b 27c 25c 28 SYNCP32- DEM/DIR2
+15V 2 P14-12 8b 8b 28a RESET_RPS_SU 23c 28a 29 D2P32+ DEM/DIR2
P6 8c P6-22 28c J3-29c 28c 8c 28c GND 1 P21-4 4
P13-3 3 P12-19 29a J3-30a 29a GND 2 P21-5 5 DCC1_CLK 29a 29a 28a 30 D2P32- DEM/DIR2
GND 1 -5.2V 4 9a 9a 29a DCC1_RXD 29c 29c 28c STRAP2 W4
GND 2 P13-7 9b P11-19 29c J4-6a 29c 9b 29c J8-6a 3 P21-6 6 100
+5.0V 5 P8-19 30a J3-30c 30a J8-6c 4 P21-7 7 DCC1_TXD 30a 30a 29a 26a 1 3 3 D1P11+ MOD/DIR1 1
P4-3 3 P13-6 6 P13-6 9c 9c 30a DCC1_BYP 6a 6a 29c 26c 2 4 4 D1P11- MOD/DIR1 2
P4-4 4 P13-10 10a P7-18 30c J3-31a 30c 10a 30c J8-7a 5 P21-8 8
P13-7 7 P7-19 31a J3-31c 31a J8-7c 6 P21-9 9 DCC2_CLK 30c 30c 30a 27a 5 CLKP11+ MOD/DIR1 3
GND 5 GND 8 P13-11 10b 10b 31a DCC2_RXD 31a 31a 30c 27c 6 CLKP11- MOD/DIR1 4
GND 6 P13-9 10c 31c J4-6c 31c J9-10c 10c J9-11a 31c J8-8a 7 P21-10 10
P13-9 9 GND 32a GND 32a J8-8c 8 P21-11 11 DCC2_TXD 31c 31c 31a 28a 7 SYNCP11+ MOD/DIR1 5
P6-7 7 P13-10 10 P13-12 11a J9-11a 11a GND 32a DCC2_BYP 6c 6c 31c 28c 8 SYNCP11- MOD/DIR1 6
RP5H2
P6-8 8 11b GND 32c GND 32c J8-19a 11b GND 32c 9 P21-12 12
P13-11 11 10 P21-13 13 FIFO2_SU_0 12a 12a 9 D2P11+ MOD/DIR1 7
GND 9 P13-12 12 11c EU64 EU64 J6-18a 11c EU64 FIFO2_SU_1 12c 12c 10 D2P11- MOD/DIR1 8
GND 10 P12-7 12a J4-18a 12a GND 11 GND 14
GND 13 12 FIFO2_SU_2 13a 13a 29a 23 D1P31+ MOD/DIR1 9
P6-11 11 P13-14 14 P12-6 12b J1-12c 12b 3M14 FIFO2_SU_3 13c 13c 29c 24 D1P31- MOD/DIR1 10
P6-12 12 P12-10 12c J5 J8 P5-2 12c 13
P13-15 15 J13 14 FIFO2_SU_4 14a 14a 30a 25 CLKP31+ MOD/DIR1 11
GND 13 P13-16 16 P12-11 13a GND 1a GND 1a P5-4 13a J4-27c 1 P22 FIFO2_SU_5 14c 14c 30c 26 CLKP31- MOD/DIR1 12
GND 14 P12-9 13b GND 1c GND 1c J9-13b 13b 15
17 J4-25c 2 16 GND 1 FIFO2_SU_6 15a 15a 31a 27 SYNCP31+ MOD/DIR1
P4-7 15 GND 18 P12-12 13c 2a +5.0V 2a J9-13c 13c J4-25a 3 P20-22 2 FIFO2_SU_7 15c 15c 31c 28 SYNCP31- MOD/DIR1 R13
P4-8 16 14a 2c +5.0V 2c J9-14a 14a 17
19 J4-28a 4 18 P20-23 3 MAVA2_SU 16a 16a 29 D2P31+ MOD/DIR1
GND 17 GND 20 14b 3a -5.2V 3a J9-14b 14b GND 5 P20-24 4 MAVA_MCF 16c 16c 30 D2P31- MOD/DIR1
GND 18 P11-7 14c 3c -5.2V 3c 14c 19
3M20 J4-27a 6 20 CON4 READ2_SU 17a 17a
P4-11 19 P11-6 15a 4a +15V 4a P1-31 15a J4-26a 7 READ_MCF 17c 17c 1,2 +5V
P4-12 20 P11-10 15b 4c +15V 4c P3-1 15b GND 21
J4-26c 8 GND 22 ACU/AAU_TXD+;TXD- 7;8 10a;c 10a;b 9;10
GND 21 P11-11 15c J3-5a 5a -15V 5a P3-2 15c 9 ACU/AAU_RXD+;RXD- 11;12 9a;c 9b;c 11;12
P6-22 22 P14 P11-9 16a J3-5c 5c -15V 5c P3-4 16a P18-23 23 C20
GND 1 CA9 P18-24 24 RESET ACU/AAU 22 28c 26a P6-22 22 1 2
23 P11-12 16b J3-6a 6a J8-6a 6a P3-9 16b MS2_1_CLK 10a 9a 29c ADDR_ACU_1
GND 24 +15V 2 16c J3-6c 6c J8-6c 6c P3-13 16c J8-10a 25 1uF
P14-3 3 J8-10c 26 MS2_1_TXD 10b 9c 30a ADDR_ACU_2
P3-6 25 17a J3-7a 7a J8-7a 7a P3-14 17a MS2_1_RXD 10c 10a 30b ADDR_ACU_3
GND 26 -5.2V 4 P10-7 17b J3-7c 7c J8-7c 7c J4-18c 17b J14 J8-11a 27
+5.0V 5 J10-22b 1 J8-11c 28 MS2_1_BYP 11a 10c 30c ADDR_ACU_4
P3-3 27 P10-6 17c J3-8a 8a J8-8a 8a J9-17c 17c MS2_2_CLK 11b 11a 31a ADDR_ACU_5
GND 28 P14-6 6 P10-10 18a J3-8c 8c J8-8c 8c J9-18a 18a J10-22c 2 29
P14-7 7 J10-23a 3 30 MS2_2_TXD 11c 11c 74HCT151 R14
29 P10-11 18b 9a J8-9a 9a 18b MS2_2_RXD 12a 12a 4 13 ALM9-INP AAU1 2 1 +5V
GND 30 GND 8 P10-9 18c 9c J8-9c 9c 18c J10-23b 4 3M30 D0
P14-9 9 J10-23c 5 S1 MS2_2_BYP 12b 12c 5 Y D1 3 14 ALM10_INP AAU2 3
3M30 P10-12 19a 10a J8-10a 10a 19a 1 16 ALM1_INP 64kb/s ADAPT1 10c 10c 31c 6 2 15 ALM11_INP SVCE TEL1 4
P14-10 10 19b 10c J8-10c 10c 19b J10-24a 6 W D2
P14-11 11 J10-24b 7 2 15 ALM2_INP 64kb/s ADAPT2 11a 11a 31c D3 1 16 ALM12_INP SVCE TEL2 5
19c 11a J8-11a 11a 19c J16 3 14 ALM3_INP RSOH ADAPT 19a 11b 11b 7 15 17 ALM13_INP PABX ADAPT1 6
P7 P14-12 12 P9-7 20a 11c J8-11c 11c 20a J10-24c 8 GND 1 S D4
GND 1 GND 13 J10-25a 9 4 13 ALM4_INP MCF 18a 11c 11c 11 A D5 14 29 ALM14_INP PABX ADAPT2 7
P9-6 20b 12a J8-12a 12a J9-20b 20b J3-8a 2 5 12 ALM5_INP SU 18a 12a 12a 10 13 74HCT151 8
+15V 2 P14-14 14 P9-10 20c 12c J8-12c 12c J9-20c 20c J10-25b 10 J3-5a 3 B D6
P7-3 3 P14-15 15 J10-25c 11 6 11 ALM6_INP RPS 12c 12b 12b 9 C D7 12 D0 4 1 ALM17_INP MSOH ADAPT1 9
P9-11 21a 13a J8-13a 13a J9-21a 21a GND 4 7 10 ALM7_INP XMTR SW 2 12c 12c 5 3 2 ALM18_INP 64kb/s ADAPT3 10
-5.2V 4 P14-16 16 P9-9 21b 13c J8-13c 13c J9-21b 21b J10-26a 12 J3-7a 5 Y D1
+5.0V 5 17 J10-26b 13 8 9 ALM8_INP XMTR SW 4 4c 13a 13a IC6 6 W D2 2 3 ALM19_INP 64kb/s ADAPT4
P9-12 21c 14a J8-14a 14a GND 21c GND 6 ALM9-16_ALM 13b 13b 1 4 ALM20_INP 64kb/s ADAPT5 4.7k
P7-6 6 GND 18 22a 14c J8-14c 14c GND 22a J10-26c 14 J3-6a 7 DILSW8 D3 R15
P7-7 7 19 J10-27a 15 S2 ALM17-24_ALM 13c 13c 7 S D4 15 5 ALM21_INP 64kb/s ADAPT6 2 1 +5V
22b 15a J8-15a 15a J10-22b 22b GND 8 1 16 ALM49_INP PWR SPLY 31 15a 15a 11 14
P7-8 8 GND 20 P8-7 22c 15c J8-15c 15c J10-22c 22c J10-27b 16 J3-8c 9 A D5 74HCT151 3
P7-9 9 J10-27c 17 2 15 ALM50_INP RCVR DIST 1 15b 15b 10 B D6 13 4 6 ALM25_INP MSOH ADAPT2 4
3M20 P8-6 23a J1-13a 16a J8-16a 16a J10-23a 23a J3-5c 10 3 14 ALM51_INP RCVR DIST 2 15c 15c 9 12 D0
P7-10 10 P8-10 23b J1-13c 16c J8-16c 16c J10-23b 23b J10-28a 18 GND 11 C D7 5 Y D1 3 7 ALM26_INP 64kb/s ADAPT7 5
P7-11 11 J10-28b 19 4 13 ALM52_INP RCVR DIST 4 16a 16a 6 2 8 ALM27_INP 64kb/s ADAPT8 6
P8-11 23c J1-14a 17a J8-17a 17a J10-23c 23c J3-7c 12 5 12 ALM53_INP SPARE 9 16b 16b IC7 W D2
P7-12 12 P8-9 24a J1-14c 17c J8-17c 17c J10-24a 24a J10-28c 20 13 D3 1 9 ALM28_INP 64kb/s ADAPT9 7
P7-13 13 J10-29a 21 6 11 ALM54_INP SPARE 13 16c 16c 7 15 10 ALM29_INP 64kb/s ADAPT10 8
P8-12 24b J1-15a 18a P8-14 18a J10-24b 24b GND 14 7 10 ALM55_INP SPARE 14 17a 17a S D4
P7-14 14 24c J1-15c 18c P12-14 18c J10-24c 24c J10-29b 22 J3-6c 15 11 A D5 14 11 ALM30_INP SPARE1 9
P7-15 15 J10-31a 23 8 9 ALM56_INP TEST MODE 18c 17b 17b 10 13 12 ALM31_INP SPARE2 10
25a J1-16a 19a J8-19a 19a J10-25a 25a CA15 ALM25-32_INP 14a 14a B D6
P7-16 16 P7-7 25b J1-16c 19c 19c J10-25b 25b J10-31b 24 DILSW8 9 C D7 12 13 ALM32_INP SPARE3
17 J10-31c 25 S3 ALM33-40_INP 14b 14b R16 4.7k +5V
P7-6 25c 20a J8-20a 20a J10-25c 25c 1 2
P7-18 18 1 16 ADDR_SU_0 19a IC8
P7-10 26a 20c J8-20c 20c J10-26a 26a CA25 2 15 ADDR_SU_1 19c 17c 17c REG_CLOCK 4.7k
P7-19 19 P7-11 26b 21a J8-21a 21a J10-26b 26b
GND 20 3 14 ADDR_SU_2 20a 18a 18a SHIFT_CLOCK S5
P7-9 26c 21c J8-21c 21c J10-26c 26c 4 13 ADDR_SU_3 20c 20b 20b ALM9-16_DISABLE 1 8
3M20 P7-12 27a 22a J8-22a 22a J10-27a 27a J15
GND 1 5 12 ADDR_SU_4 21a 20c 20c ALM17-24_DISABLE 2 7
14 8 J2-27b 27b 22c J8-22c 22c J10-27b 27b 6 11 ADDR_SU_5 21c 21a 21a ALM25-32_DISABLE 3 6
J2-27c 27c 23a J8-23a 23a J10-27c 27c GND 2
SPARE GATES J3-2a 3 7 10 ADDR_SU_6 22a 21b 21b ALM33-40_DISABLE 4 5
J2-28a 28a 23c J8-23c 23c J10-28a 28a 8 9 ADDR_SU_7 22c
74HCT132 J2-28b 28b 24a J8-24a 24a J10-28b 28b J3-2c 4 2 3 4 5 6 DILSWITCH4
1 7 9 J3-4a 5 MAN_IND_XSU 5 5a
8 J2-28c 28c 24c J8-24c 24c J10-28c 28c DILSW8
74HCT132 10 J3-4c 6 SEL_140_XSU 8 5b ALM_SEL_A 1 C18
J2-29a 29a 25a J8-25a 25a J10-29a 29a REL_A_XSU 7 7 5c ALM_SEL_B
J3-3a 7 1 C16 270pF
16 9 IC5 C J2-29b 29b 25c J8-25c 25c J10-29b 29b REL_B_XSU 10 10 6a ALM_SEL_C 2
74HCT132 J2-29c 29c 26a J8-26a 26a 29c J3-3c 8 2
270pF 1 R17 10k
12 GND 9 REL_C_XSU 9 6b 74HCT132 74HCT132 +5V
11 30a 26c J8-26c 26c 30a SW_A_XSU 12 12 6c 1 9
1 8 13 30b 27a J8-27a 27a 30b CA9 3 8
SW_B_XSU 11 11 7a 2 10
74HCT151 IC5 D P3-6 30c 27c J8-27c 27c 30c SW_C_XSU 13 7b 74HCT151 Document responsible Approved Ref Additional Circuit
HCT4060 P3-3 31a 28a J8-28a 28a J10-31a 31a S4 IC4 A IC4 C
1 16 ALM33_INP SYNC UNIT 5 4 D0 NRKO/KR NL290 Diagrams:
P7-8 31b 28c J8-28c 28c J10-31b 31b 2 15 ALM34_INP SYNC UNIT 6 3 5 HCT4060 74HCT132 74HCT132
18 10 P7-13 31c J3-29a 29a J8-29a 29a J10-31c 31c D1 Y 4 12
3 14 ALM35_INP SYNC UNIT 9 2 D2 W 6 2 Q3 7 5 6 13 11 Prepared Subject responsible Code Date Rev
GND
GND
32a
32b
J3-29c
J3-30a
29c
30a
J8-29c
J8-30a
29c
30a
GND
GND
32a
32b
4 13 ALM36_INP SYNC UNIT 10 1 D3 1
R2
2 3 Q12
Q13 Q4 5 9310 NRU/EV NRU/EV EW53A B
1 9 5 12 ALM37_INP SYNC UNIT 13 15 D4 S 7 12k 10 Q5 4 IC4 B IC4 D
GND 32c J3-30c 30c J8-30c 30c GND 32c 6 11 ALM38_INP SPARE 14 RTC Project Title
ULN2803A J3-31a 31a J8-31a 31a D5 A 11 C15 9
CTC Q6 6 74HCT132
1
EU96 EU96 7 10 ALM39_INP SPARE 13 D6 B 10 1 2 Q7 14 3
20 11
BOTTOM VIEW J3-31c 31c J8-31c 31c 8 9 ALM40_INP SPARE 12 9 13 74HCT132 2
3 C GND 32a GND 32a D7 C 82pF Q8 4
SDH-RADIO DISTRIBUTION BD SERVICE
+5V 12 15 1
E L1 MR Q9 6 IC5 A
10
DILSW8
2
3
4
5
6
7
8
9
B GND 32c GND 32c +5.0V 1 2 16 16 14 14 16 16 16 20 IC2 R3 11 1 5 R4

B 1 C14 1 2 RS Q11
1 10 2 EU64 EU64 1.0uH 1 C3 1 C5 1 C6 1 C7 1 C8 1 C9 1 C10 1 C11 1 C12 1 C13 10k
+ 270pF 24k IC5 B C17
4.7k
C IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 2

R1
Dwg No
74HCT373 1 E
2N3904
C4=OMITTED
P2=OMITTED +5V
2
220uF
9 8
2
100nF
8
2
100nF
7
2
100nF
7
2
100nF
8
2
100nF
8
2
100nF
8
2
100nF
10
2
100nF
2
100nF 2 IC3 1 2
1
82pF
CONNECTION PANEL
SERVICE CHANNEL
UWB309
H2699 Rev. B
© Nera AS
UWB309

1.1 General:
This board is backplane for two Alarm Adapter The single PABX-Adapter is connected to Service
Units, two Service Telephone Boards used for Telephone 1. IF strap W1 and W2 are in pos. 1-2,
express and omnibus, and one PABX-Adapter Service Telephone 1 is connected to the lower
Board, double or single. handset position and Service Telephone 2 to the
upper position. IF strap W1 and W2 are in pos. 2-
If any of the units is not present, the alarms can be
3, the routing is vice-versa.
disabled by a DIL-switch.
1.2 DIL-switch setting:
S1-1: Alarm Adapter Unit 1 ALM is disabled when closed

S1-2: Alarm Adapter Unit 2 ALM is disabled when closed
S1-3: Service Telephone 1 ALM is disabled when closed
S1-4: Service Telephone 2 ALM is disabled when closed
S1-5: PABX-Adapter 1 ALM is disabled when closed

S1-6: PABX-Adapter 2 ALM is disabled when closed
S1-7: Not used
S1-8: Not used
3

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Fig. 1 Connection Panel Board, UWB309.
2 H2699
J1 J3 J5 J7 J9 P1
1a GND 1a GND 1a GND 1a GND 1a GND 1 GND
1c GND 1c GND 1c GND 1c GND 1c GND 2 GND
2a 2a 2a 2a 2a 3 -15V
2c 2c 2c 2c 2c 4 -15V PABX ADAPTER EXPRESS TELEP. TO OPTICAL
3a 3a 3a 3a 3a 5 -15V AAU1 AAU2 SERVICE TELEP.1 SERVICE TELEP.2 NO.1 NO.2 VOLT. X-CONNECTION HANDSET INTERFACE
3c 3c 3c 3c 3c 6 -15V
4a 4a 4a 4a 4a 7 GND J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 P1 P2 P3 P4
4c 4c 4c 4c 4c 8 GND
5a 5a 5a 5a 5a 9 +15V +5V 2a,2c 2a,2c 2a,2c 2a,2c 2a,2c 33-46
5c 5c 5c 5c 5c 10 +15V G1
-5.2V 17-28 4-6,9,10,13 2 1
6a 6a 6a 6a 6a 11 +15V GND (SEE CONNECTOR SYMBOLS)
6c 6c 6c 6c 6c 12 +15V -5V 3a,3c 3a,3c 3a,3c 1N5822
7a 7a 7a 7a 7a 13 +15V +15V 4a,4c 4a,4c 4a,4c 9-14 2,3
7c 7c 7c 7c 7c 14 +15V -15V 5a,5c 5a,5c 5a,5c 3-6
8a 8a 8a 8a 8a 15 GND
8c 8c 8c 8c 8c 16 BAT+ (20-60V) 30a,30c 30a,30c 30a,30c 23,24
9a 9a 9a 9a 9a 17 -5.2V BAT- (20-60V) 31a,31c 31a,31c 31a,31c 25,26
9c 9c 9c 9c 9c 18 -5.2V
10a 10a 10a 10a 10a 19 -5.2V
10c 10c 10c 10c 10c 20 -5.2V CALL IND.,TELEP.1 27a
11a 11a 11a 11a 11a 21 -5.2V CALL IND.,OMNIBUS TELEP. 18 W1A 2 3
11c 11c 11c 11c 11c 22 -5.2V 1
STRAP3
12a 12a 12a 12a 12a 23 -5.2V TEL_B.,TELEP.1 26c
12c 12c 12c 12c 12c 24 -5.2V TEL_B.,OMNIBUS TELEP. 19 W1B 2 3
13a 13a 13a 13a 13a 25 -5.2V 1
STRAP3
13c 13c 13c 13c 13c 26 -5.2V TEL_A.,TELEP.1 26a
14a 14a 14a 14a 14a 27 -5.2V TEL_A.,OMNIBUS TELEP. 20 W1C 2 3
14c 14c 14c 14c 14c 28 -5.2V 1
STRAP3
15a 15a 15a 15a 15a 29 GND
15c 15c 15c 15c 15c 30 GND
16a 16a 16a 16a 16a 31 CALL IND.,TELEP.2 27a
16c 16c 16c 16c 16c 32 CALL IND.,EXPRESS TELEP. 2 W2A 2 3
17a 17a 17a J5-17a 17a J7-17a 17a J5-17a 33 +5V 1
STRAP3
17c 17c 17c J5-17c 17c J7-17c 17c J5-17c 34 +5V TEL_B.,TELEP.2 26c
18a 18a 18a 18a 18a 35 +5V TEL_B.,EXPRESS TELEP. 3 W2B 2 3
18c 18c 18c 18c 18c 36 +5V 1
STRAP3
19a 19a 19a 19a 19a 37 +5V TEL_A.,TELEP.2 26a
19c 19c 19c 19c 19c J9-19c 38 +5V TEL_A.,EXPRESS TELEP. 4 W2C 2 3
20a 20a 20a J5-20a 20a J7-20a 20a J5-20a 39 +5V 1
STRAP3
20c 20c 20c J5-20c 20c J7-20c 20c J5-20c 40 +5V
21a 21a 21a J5-21a 21a J7-21a 21a J5-21a 41 +5V
21c 21c 21c J5-21c 21c J7-21c 21c J5-21c 42 +5V
22a 22a 22a J5-22a 22a J7-22a 22a J5-22a 43 +5V PABX ADAPTER1 CONTROL1 17a 17a
22c 22c 22c J5-22c 22c J7-22c 22c J5-22c 44 +5V PABX ADAPTER1 CONTROL2 17c 17c
23a 23a 23a J5-23a 23a J7-23a 23a J5-23a 45 +5V PABX ADAPTER1 PABX TIP 20a 20a
23c 23c 23c 23c J7-23c 23c J5-23c 46 +5V PABX ADAPTER1 PABX RING 20c 20c
24a J1-24a 24a J1-24a 24a J5-24a 24a J7-24a 24a J5-24a 47 GND PABX ADAPTER1 SPARE 21a 21a
24c 24c 24c J5-24c 24c J7-24c 24c J5-24c 48 GND PABX ADAPTER1 SPARE 21c 21c
25a GND 25a 25a J5-25a 25a J7-25a 25a J5-25a 49 GND PABX ADAPTER1 SPARE 22a 22a
25c GND 25c GND 25c J5-25c 25c J7-25c 25c J5-25c 50 GND PABX ADAPTER1 SPARE 22c 22c
26a 26a 26a J5-26a 26a J7-26a 26a 3M50 PABX ADAPTER1 DTMF TO RADIO 23a 23a
26c 26c 26c J5-26c 26c J7-26c 26c PABX ADAPTER1 SPEECH TO RADIO 23c 23c
27a 27a 27a J5-27a 27a J7-27a 27a PABX ADAPTER1 SPEECH TO RADIO 24a 24a
27c 27c 27c 27c 27c P2 PABX ADAPTER1 DTMF FROM RADIO 24c 24c
28a 28a 28a 28a 28a 1 GND PABX ADAPTER1 SPEECH FROM RADIO 25a 25a
28c 28c 28c 28c 28c 2 J6-6c PABX ADAPTER1 SPEECH FROM RADIO 25c 25c
29a 29a 29a 29a 29a 3 GND
29c 29c 29c 29c 29c 4 J6-9c
30a 30a 30a 30a 30a 5 GND PABX ADAPTER2 CONTROL1 17a 17a
30c 30c 30c 30c 30c 6 J6-7c PABX ADAPTER2 CONTROL2 17c 17c
31a 31a 31a 31a 31a 7 GND PABX ADAPTER2 PABX TIP 20a 20a
31c 31c 31c 31c 31c 8 J6-8c PABX ADAPTER2 PABX RING 20c 20c
32a GND 32a GND 32a GND 32a GND 32a GND 9 J2-15a PABX ADAPTER2 SPARE 21a 21a
32c GND 32c GND 32c GND 32c GND 32c GND 10 J2-15c PABX ADAPTER2 SPARE 21c 21c
EU64 EU64 EU64 EU64 EU64 11 J2-16a PABX ADAPTER2 SPARE 22a 22a
12 J2-16c PABX ADAPTER2 SPARE 22c 22c
13 J2-19c PABX ADAPTER2 DTMF TO RADIO 23a 23a
14 J4-19c PABX ADAPTER2 SPEECH TO RADIO 23c 23c
J2 J4 J6 J8 J10 15 J6-20a PABX ADAPTER2 SPEECH TO RADIO 24a 24a
1a GND 1a GND 1a GND 1a GND 1a GND 16 J8-20a PABX ADAPTER2 DTMF FROM RADIO 24c 24c
1c GND 1c GND 1c GND 1c GND 1c GND 17 J9-19c PABX ADAPTER2 SPEECH FROM RADIO 25a 25a
2a +5V 2a +5V 2a +5V 2a +5V 2a +5V 18 P2-18 PABX ADAPTER2 SPEECH FROM RADIO 25c 25c
2c +5V 2c +5V 2c +5V 2c +5V 2c +5V 19 P2-19
3a 3a 3a -5V 3a -5V 3a -5V 20 P2-20 TXD+ 15a 15a 9 7
3c 3c 3c -5V 3c -5V 3c -5V 21 GND TXD- 15c 15c 10 8
4a 4a 4a +15V 4a +15V 4a +15V 22 J1-24a RXD+ 16a 16a 11 11
4c 4c 4c +15V 4c +15V 4c +15V 23 J6-30a RXD- 16c 16c 12 12
5a 5a 5a -15V 5a -15V 5a -15V 24 J6-30a
5c 5c 5c -15V 5c -15V 5c -15V 25 J6-31a RXD_2MB 6c 6c 2
6a 6a 6a 6a 6a 26 J6-31a TXD_2MB 9c 9c 4
6c 6c 6c J6-6c 6c J6-6c 6c 27 CLK_2MB 7c 7c 6
7a 7a 7a 7a 7a 28 BYTE_2MB 8c 8c 8
7c 7c 7c J6-7c 7c J6-7c 7c 29 J10-19c
8a 8a 8a 8a 8a 30
8c 8c 8c J6-8c 8c J6-8c 8c 3M30
9a 9a 9a 9a 9a
9c 9c 9c J6-9c 9c J6-9c 9c S1
10a 10a 10a 10a 10a P3 AAU1_ALM 19c 13 1 16
10c 10c 10c 10c 10c 1 GND AAU2_ALM 19c 14 2 15
11a 11a 11a 11a 11a 2 P3-2 SERV_TELEP1_ALM 20a,20c 15 3 14
11c 11c 11c 11c 11c 3 P3-3 SERV_TELEP2_ALM 20a,20c 16 4 13
12a 12a 12a 12a 12a 4 P3-4 PABX_ADAPTER1_ALM 19c 17 5 12
12c 12c 12c 12c 12c PABX_ADAPTER2_ALM 19c 29 6 11
13a 13a 13a 13a 13a CON4 7 10
13c 13c 13c 13c 13c ADDR_1 AAU 25a 25a 8 9
14a 14a 14a 14a 14a ADDR_2 AAU 25c 25c
DILSWITCH8
14c 14c 14c 14c 14c P4 ADDR_3 AAU 26a 26a
15a J2-15a 15a J2-15a 15a 15a 15a 1 GND ADDR_4 AAU 26c 26c
15c J2-15c 15c J2-15c 15c 15c 15c 2 +15V ADDR_5 AAU 27a 27a
16a J2-16a 16a J2-16a 16a 16a 16a 3 +15V
16c J2-16c 16c J2-16c 16c 16c 16c 4 -5.2V RESET_AAU 24a 24a 22 14
17a 17a 17a 17a 17a J7-17a 5 -5.2V
17c 17c 17c 17c 17c J7-17c 6 -5.2V
18a 18a 18a 18a 18a 7 J2-15a
18c 18c 18c 18c 18c 8 J2-15c
19a 19a 19a 19a 19a 9 -5.2V
19c J2-19c 19c J4-19c 19c 19c 19c J10-19c 10 -5.2V
20a 20a 20a J6-20a 20a J8-20a 20a J7-20a 11 J2-16a
20c 20c 20c J6-20a 20c J8-20a 20c J7-20c 12 J2-16c
21a 21a 21a 21a 21a J7-21a 13 -5.2V
21c 21c 21c 21c 21c J7-21c 14 J1-24a
22a 22a 22a 22a 22a J7-22a
22c 22c 22c 22c 22c J7-22c 3M14
23a 23a 23a 23a 23a J7-23a
23c 23c 23c 23c 23c J7-23c
24a 24a 24a 24a 24a J7-24a
24c 24c 24c 24c 24c J7-24c
25a 25a 25a 25a 25a J7-25a
25c 25c 25c 25c 25c J7-25c
26a 26a 26a 26a 26a
26c 26c 26c 26c 26c
27a 27a 27a 27a 27a
27c 27c 27c 27c 27c
28a 28a 28a 28a 28a
28c 28c 28c 28c 28c
29a 29a 29a 29a 29a
29c 29c 29c 29c 29c
30a 30a 30a J6-30a 30a J6-30a 30a J6-30a NRKO/KR Diagrams:
30c 30c 30c J6-30a 30c J6-30a 30c J6-30a
31a 31a 31a J6-31a 31a J6-31a 31a J6-31a
31c 31c 31c J6-31a 31c J6-31a 31c J6-31a 9512 RRS/EV RRS/EV UWB309 96-05-20 C
32a GND 32a GND 32a GND 32a GND 32a GND
Project Title
32c GND 32c GND 32c GND 32c GND 32c GND
EU64 EU64 EU64 EU64 EU64
SDH-RADIO CONNECTION PANEL SERVICE CHAN
Dwg No
NERA Nera AS 1911-S2100841
CONNECTION PANEL, ADAPTER
UWB310
H2700 Rev. A
© Nera AS
UWB310

1.1 Setting of DIL-switch and straps:
This board is backplane for five Adapters. The left W1: Strap in pos. 1-2 if main input signal is 155Mb/s.
position is reserved for MSOH-Adapter, the four Strap to be removed if main inp. signal is 139Mb/
others for 64kb/s Adapters. s.
To configure the system, DIL-switch and straps are
set as follows: W2: This strap is normally in pos. 1-2. If this databus is
not in use, either for RSOH-Adapter or any Adapt-
S1-1: MSOH ADAPTER ALM is disabled when closed ers in this cassette, remove the strap and the bus
S1-2: 64kb/s ADAPTER 1 ALM is disabled when closed signals are disabled.
S1-3: 64kb/s ADAPTER 2 ALM is disabled when closed
S1-4: 64kb/s ADAPTER 3 ALM is disabled when closed W3: This strap is normally in pos. 1-2 on terminals. On
repeaters, remove the strap and bus signals are dis-
S1-5: 64kb/s ADAPTER 4 ALM is disabled when closed abled.
S1-6: Closed if no extra Adapter cassette, else open W4: Strap in pos. 1-2 if main input signal is 139Mb/s.
S1-7: Same as S1-6 Strap to be removed if main input signal is 155Mb/
S1-8: Same as S1-6 s
W5,W6: Strap in pos. W5 on repeaters

Strap in pos. W6 on termninals..
Fig. 1 Connection Panel, Adapter, Board, UWB310
2 H2700
P1 J1 J3 J5
1 GND 1a GND 1a GND 1a GND 2Mb BUS 2Mb BUS
2 GND 1c GND 1c GND 1c GND MOD/DIR1 DEM/DIR2 ALM OUT ADAPTER 1 ADAPTER 2 ADAPTER 3 ADAPTER 4 ADAPTER 5 ALARM INP VOLTAGE
3 P1-3 2a +5.0V 2a +5.0V 2a +5.0V
4 P1-4 2c +5.0V 2c +5.0V 2c +5.0V P1 P2 P3 J1 J2 J3 J4 J5 P4 P5
5 P1-5 3a -5.2V 3a -5.2V 3a -5.2V
6 P1-6 3c -5.2V 3c -5.2V 3c -5.2V +5.0V 2a,c 2a,c 2a,c 2a,c 2a,c 33-46
7 P1-7 4a +15V 4a +15V 4a +15V -5.2V 3a,c 3a,c 3a,c 3a,c 3a,c 17-28
8 P1-8 4c +15V 4c +15V 4c +15V +15V 4a,c 4a,c 4a,c 4a,c 4a,c 9-14
9 P1-9 5a -15V 5a -15V 5a -15V -15V 5a,c 5a,c 5a,c 5a,c 5a,c 3-6
10 P1-10 5c -15V 5c -15V 5c -15V GND (SEE CONNECTOR SYMBOLS)
11 6a 6a 6a
12 6c 6c 6c D1R11+ MOD/DIR1 3 8a 8a 8a 8a 8a
13 7a 7a 7a D1R11- " 4 9a 9a 9a 9a 9a
14 7c 7c 7c CLKR11+ " 5 10a 10a 10a 10a 10a
15 8a P1-3 8a P1-3 8a P1-3 CLKR11- " 6 11a 11a 11a 11a 11a
16 8c P1-23 8c P1-23 8c P1-23 SYNCR11+ " 7 12a 12a 12a 12a 12a
17 9a P1-4 9a P1-4 9a P1-4 SYNCR11- " 8 13a 13a 13a 13a 13a
18 9c P1-24 9c P1-24 9c P1-24 D2R11+ " 9 14a 14a 14a 14a 14a
19 10a P1-5 10a P1-5 10a P1-5 D2R11- " 10 15a 15a 15a 15a 15a
20 10c P1-25 10c P1-25 10c P1-25
1
21 GND 11a P1-6 11a P1-6 11a P1-6 W1
22 GND 11c P1-26 11c P1-26 11c P1-26 STRAP2
23 P1-23 12a P1-7 12a P1-7 12a P1-7 2
24 P1-24 12c P1-27 12c P1-27 12c P1-27 100
25 P1-25 13a P1-8 13a P1-8 13a P1-8 1 2
26 P1-26 13c P1-28 13c P1-28 13c P1-28 3 4
27 P1-27 14a P1-9 14a P1-9 14a P1-9 5 6
28 P1-28 14c P1-29 14c P1-29 14c P1-29 7 8
29 P1-29 15a P1-10 15a P1-10 15a P1-10 9 10
30 P1-30 15c P1-30 15c P1-30 15c P1-30 R1
3M30 16a 16a 16a D1R31+ MOD/DIR1 23 8c 8c 8c 8c 8c
16c 16c 16c D1R31- " 24 9c 9c 9c 9c 9c
17a 17a 17a CLKR31+ " 25 10c 10c 10c 10c 10c
17c 17c 17c CLKR31- " 26 11c 11c 11c 11c 11c
P2 18a P2-23 18a P2-23 18a P2-23 SYNCR31+ " 27 12c 12c 12c 12c 12c
1 GND 18c J1-18c 18c J1-18c 18c J1-18c SYNCR31- " 28 13c 13c 13c 13c 13c
2 P2-2 19a P2-24 19a P2-24 19a P2-24 D2R31+ " 29 14c 14c 14c 14c 14c
3 P2-3 19c J1-19c 19c J1-19c 19c J1-19c D2R31- " 30 15c 15c 15c 15c 15c
4 P2-4 20a P2-25 20a P2-25 20a P2-25
5 P2-5 20c J1-20c 20c J1-20c 20c J1-20c
6 P2-6 21a P2-26 21a P2-26 21a P2-26 100
7 P2-7 1 2
21c 21c 21c 3 4
8 P2-8 22a P2-27 22a P2-27 22a P2-27
9 P2-9 5 6
22c 22c 22c 7 8
10 P2-10 23a P2-28 23a P2-28 23a P2-28
11 GND 9 10
23c 23c 23c
12 P2-12 24a P2-29 24a P2-29 24a P2-29 R2
13 P2-13 24c 24c 24c
14 P2-14 25a P2-30 25a P2-30 25a P2-30 DISABLE12 DEM/DIR2 2 W2 W5
1 2
15 P2-15 25c 25c 25c D1R12+ " 3 1 16 18c 18c 18c 18c 18c
STRAP2
16 P2-16 26a 26a 26a D1R12- " 4 2 15 19c 19c 19c 19c 19c
17 P2-17 26c 26c 26c CLKR12+ " 5 3 14 20c 20c 20c 20c 20c
18 P2-18 27a 27a 27a CLKR12- " 6 4 13 21c 21c 21c 21c 21c
19 P2-19 27c 27c 27c SYNCR12+ " 7 5 12 22c 22c 22c 22c 22c
20 P2-20 28a 28a 28a SYNCR12- " 8 6 11 23c 23c 23c 23c 23c
21 GND 28c 28c 28c D2R12+ " 9 7 10 24c 24c 24c 24c 24c
22 GND 29a 29a 29a D2R12- " 10 8 9 25c 25c 25c 25c 25c
23 P2-23 29c 29c 29c
24 P2-24 30a 30a 30a 100 STRAP16
25 P2-25 30c 30c 30c 1 2
26 P2-26 31a 31a 31a 3 4
27 P2-27 31c P3-1 31c P3-3 31c P3-5 5 6
28 P2-28 32a GND 32a GND 32a GND 7 8
29 P2-29 32c GND 32c GND 32c GND 9 10
30 P2-30
EU64 EU64 EU64 R3
3M30
J2 J4 P4 DISABLE22 DEM/DIR2 12 1
W3
2 W6
1a GND 1a GND 1 P3-6 D1R22+ " 13 STRAP2 1 16
P3 D1R22- " 14 2 15
1 P3-1 1c GND 1c GND 2 P3-7
2a +5.0V 2a +5.0V 3 P3-8 CLKR22+ " 15 3 14
2 P3-2 CLKR22- " 16 4 13
3 P3-3 2c +5.0V 2c +5.0V 4 P3-9
3a -5.2V 3a -5.2V 5 P3-10 SYNCR22+ " 17 5 12
4 P3-4 SYNCR22- " 18 6 11
5 P3-5 3c -5.2V 3c -5.2V 6 P3-11
4a +15V 4a +15V 7 P3-12 D2R22+ " 19 7 10
6 P3-6 D2R22- " 20 8 9
7 P3-7 4c +15V 4c +15V 8 P3-13
8 P3-8 5a -15V 5a -15V 9
5c -15V 5c -15V 10 100 STRAP16
9 P3-9 1 2
10 P3-10 6a 6a 11 3 4
11 P3-11 6c 6c 12 GND 5 6
12 P3-12 7a 7a 13 GND 7 8
13 P3-13 7c 7c 14 GND 9 10
14 GND 8a P1-3 8a P1-3 3M14
8c P1-23 8c P1-23 R4
3M14 9a P1-4 9a P1-4
9c P1-24 9c P1-24 P5
10a P1-5 10a P1-5 1 GND
10c P1-25 10c P1-25 D1R32+ DEM/DIR2 23 18a 18a 18a 18a 18a
2 GND D1R32- " 24 19a 19a 19a 19a 19a
11a P1-6 11a P1-6 3 -15V
11c P1-26 11c P1-26 CLKR32+ " 25 20a 20a 20a 20a 20a
4 -15V CLKR32- " 26 21a 21a 21a 21a 21a
12a P1-7 12a P1-7 5 -15V
12c P1-27 12c P1-27 SYNCR32+ " 27 22a 22a 22a 22a 22a
6 -15V SYNCR32- " 28 23a 23a 23a 23a 23a
13a P1-8 13a P1-8 7 GND
13c P1-28 13c P1-28 D2R32+ " 29 24a 24a 24a 24a 24a
8 GND D2R32- " 30 25a 25a 25a 25a 25a
14a P1-9 14a P1-9 9 +15V
14c P1-29 14c P1-29 10 +15V 1
15a P1-10 15a P1-10 11 +15V W4
15c P1-30 15c P1-30 12 +15V
STRAP2
16a 16a 13 +15V

2
16c 16c 100

14 +15V 1 2
17a 17a 15 GND 3 4
17c 17c 16 5 6
18a P2-23 18a P2-23 17 -5.2V 7 8
18c J1-18c 18c J1-18c 18 -5.2V 9 10
19a P2-24 19a P2-24 19 -5.2V
19c J1-19c 19c J1-19c 20 -5.2V R5
20a P2-25 20a P2-25 21 -5.2V S1
20c J1-20c 20c J1-20c ALARM ADAPTER1 1 31c 1 16
22 -5.2V ALARM ADAPTER2 2 31c 2 15
21a P2-26 21a P2-26 23 -5.2V
24 -5.2V ALARM ADAPTER4 4 31c 4 13
22a P2-27 22a P2-27 25 -5.2V
26 -5.2V ALARM ADAPTER6 6 1 6 11
23a P2-28 23a P2-28 27 -5.2V
23c J1-23c 23c J1-23c ALARM ADAPTER7 7 2 7 10
28 -5.2V ALARM ADAPTER8 8 3 8 9
24a P2-29 24a P2-29 29 GND
24c J1-24c 24c J1-24c ALARM ADAPTER9 9 4
30 GND ALARM ADAPTER10 10 5
DILSWITCH8
25a P2-30 25a P2-30 31
25c J1-25c 25c J1-25c ALARM SPARE1 11 6
32 ALARM SPARE2 12 7
26a 26a 33 +5.0V
26c 26c ALARM SPARE3 13 8
34 +5.0V
27a 27a 35 +5.0V
27c 27c 36 +5.0V
28a 28a 37 +5.0V
28c 28c 38 +5.0V
29a 29a 39 +5.0V
29c 29c Document responsible Approved Ref Additional Circuit
40 +5.0V
30a 30a 41 +5.0V NRKO/KR Diagrams:
30c 30c 42 +5.0V
31a 31a 43 +5.0V
31c P3-2 31c P3-4 44 +5.0V 9319 NRU/EV NRU/EV UWB310 A
32a GND 32a GND 45 +5.0V
32c GND 32c GND Project Title
46 +5.0V
EU64 EU64 47 GND
48 GND CONNECTION PANEL ADAPTER
SDH-RADIO
49 GND
50 GND
3M50 Dwg No
FILTER & CONNECTION
PANEL, 48V
EF312A
H2701 Rev. B
© Nera AS
EF312A

This board is a connection and filter panel for the The main switch and a slow blowing fuse (3A, 125V,
battery voltage and is located at the top of the service dim. 31.8x6.4 mm) is also part of this board.
rack. To protect the equipment against wrong battery
polarity, a protection diode is provided.
The connection terminal for the battery voltage is of
screw type for wire cross section 0.5 - 4.0 mm2. Battery operating voltage: 40 - 58V.
1 1 TB1
2 2 F1 1 2 - 48V PRIMARY VOLTAGE INPUT
CPP
3 CPP 1 +
CP1 3A
S1 SWITCH CP2 CON2
FILTERED PRIM ARY

VOLTAGE T O MAIN
POWER SUPP LY
P3
48V+
48V-
3M14
TO SERVICE CHANNEL CASSETTE

P1
48V+
48V-
MAIN ALARM, RACK
+5.0V
1N916
1 2
3M10 G2
1
R2 TF2-5V R3
1.5K
10 1 2 1.5K
MAIN ALARM, RACK 4
P2 3
2
7
8
9
5 6
K1
3M10
Fig.1, Filter & Connection Panel, 48V, EF312A

2 H2701
FILTER & CONNECTION
PANEL, 24V
EF313A
H2702 Rev. A
© Nera AS
EF313A
This board is a connection and filter panel for the The main switch and a slow blowing fuse (5A,
battery voltage, and is located at the top of the 125V, dim. 31.8x6.4 mm) is also part of this
service rack. board.
The connection terminal for battery voltage is of To protect the equipment against wrong battery
screw type for wire cross section 0.5 - 4.0 mm2. polarity, a protection diode is provided.
Battery operating voltage: 20 - 29V.
TB1
F1
&33
&33 24V PRIMARY VOLTAGE INPUT
&3 + 5A
&
7
&3
, CON2
:
66
FILTERED PRIMARY
VOLTAGE TO MAIN
POWER SUPPLY
P3
24V+
& &
5 & / &
* 9
& &
24V-
TO SERVICE CHANNEL CASSETTE
9
9
0 $,1$/$50 5$&.
9
G2
5 TF2-5V 5
MAIN ALARM, RACK

P2
K1
Fig.1 Filter & Connection Panel, EF313A
2 H2702
FILTER & CONNECTION
PANEL BOARD, RADIO, 48V
EF324A
H2995 Rev. A
© Nera ASA
EF324A
1.0 DESCRIPTION
1.1 General
This board is a special version for use together with c) To combine +15V and -5.2V from service
Optical Intercace Unit, 7NYD576A. rack and radio rack and to convert +15V to +5V.
The board is located at the top of each radio rack. A This combined voltages are used to supply the
terminal block for connection of the separate battery Optical Interface Unit which is a common unit for
circuits is provided. If only one circuit is used, regular and protection channel.
connect this to the upper terminals on the TB1 d) Relays K1 and K2 are related to fuse
(Fuse F1). Then remove strap W1 to disable the fuse alarm for F1 and F2. The relays are normally
alarm for F2. The rack power ON/OFF switch and activated, and a green LED located near the fuse
fuses, which are mounted on a bracket, are also part will light. If the fuse is blown, the relay will fall-
of this unit. back and give alarm to the Supervisory Unit. The
green LED will then extinguish.
1.2 Functional e) Relay K3 is related to the rack alarm and

is controlled by an alarm output from the Alarm
1.2.1 The different functions of the Collection Unit (ACU). The Relay is normally
board activated, and when fall-back occurs, the primary
a) Filtering of battery voltage (48VDC) and voltage will provide alarm visualized by a red LED
distribution of this to the main power supply via P6 at the top of the rack.
and to XMTR power supply via P4. c) Switch S2 is used to set address in the
b) Distribution of signals and secondary Optical Interface Unit depending on Radio
voltages to/from XMTR Group (P4) and Optical Channel.
Interface Unit (P3).
S2-4 S2-3 S2-2 S2-1 Radio Channel 1

OPEN
0 0 0 0 PROT. 2
0 0 0 1 1 3
4
0 0 1 0 2
0 0 1 1 3 OPEN =1
0 1 0 0 4 CLOSED = 0
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
Fig. 1, Switch S2 on EF324A
2 H2995
EF324A
Fig. 2 Filter & Connection Panel, Board, EF324A
H2995
3
1N916 1N916
1 2 1 2
G7 G10
SMD1005 SMD1005
1 C6 1 C9
10 1 10 1
47nF 47nF
7 7 2 2
1 1
R1 8 R2 8 2 01 02
9 9 1 1 C5 1 C8
L1
4.3K 4 4.3K 4 G11 R3
TB1 2 3 2 3 680nF 3.9mH 680nF
2 2 1 3 MBR20100CT U 50V 2 2
1
CPP
CPP
GND 6 03 04
2
CP4
CP7
BATTERY1+ 5 1 C7 1 C10
BATTERY1- 4 K1 1 K2
1 1 W1 47nF 47nF
GND 3 H1 H2 2 2
STRAP2
BATTERY2+ 2 GREEN GREEN 2
BATTERY2- 1 2 2
CON6
CP5
CP8
CPP
CPP
G12
1
F1 1 1
1 1 2 1 2 1 1 2 CPP
CPP CPP CPP 3 CP10
CP1 5A CP3 MBR10100 CP9
S1
F2 G13 SWITCH
1 1 2 1 2 1
CPP CPP
CP2 5A CP6 MBR10100
1
C4
470nF
2
SECONDARY PRIMARY
P1 P4 P5 P6 P7
1 GND 1 1 1 48V+ 1
2 GND 2 2 2 2
4 GND 22 4 4 R4 4
5 IF INP ALM 23 5 5 1.5k 5
6 GND 24 6 - 15V 6 2 6
8 GND 26 8 8 48V- 8
10 ATPC_XMTR 28 10 10 10
14 ATPC_ALM 32 14 + 15V 14
15 - 5V (FET PWR SPLY) 33 15 3M14
16 + 9.4V (FET PWR SPLY) 34 16
17 ATPC_HIGHER 3 17
18 ATPC_LOWER FROM SERV.RACK 4 18
19 + 15V TO OPTICAL INTERFACE (FROM SERVICE RACK) P2 5 19
20 + 15V TO OPTICAL INTERFACE (FROM SERVICE RACK) 1 6 20
21 RELAY CONTROL (NORMALY HIGH) 2 7 21
22 - 5,2V TO OPTICAL INTERFACE (FROM SERVICE RACK) 3 48V+ 8 22 1N916
23 - 5,2V TO OPTICAL INTERFACE (FROM SERVICE RACK) 4 9 23 1 2
24 +5V FROM SERVICE RACK 5 10 24
25 DATA INP ALM (SIGN FROM MUX) 6 11 25 G14
26 RCVR LO-LEVEL 7 12 26 SMD1005
27 ATPC_REFLVL 8 13 27
28 RF INP LEVEL, MAIN (TO METER) 9 48V- 14 28 - 5,2V 10 1 +5V
29 RF INP LEVEL, MAIN (TO RECORDER) 10 OPTICAL 15 29
30 RCVR LO ALM 11 - 15V 16 30 7
31 GND 12 INTERFACE 17 31 9
8
32 DIVERSITY ALM 13 P3 + 15V 18 32 4
33 GND 1N5822 1
14 -5V 1 19 33 3
34 LOW INP LEVEL MAIN, ALM G5 2 + 5V 20 34 2
2 3M14
35 GND +5V_REG 3 35 35
36 LOW INP LEVEL DIVERSITY, ALM 4 - 5,2V 36 36 K3
2 1N5822
37 GND 5 37 37
38 RF INP LEVEL, DIVERSITY (TO METER) G3 6 38 38
1
39 RF INP LEVEL, DIVERSITY (TO RECORDER) +15V 7 39 39
40 RCVR LO VARACTOR VOLT RELAY_CTRL 8 40 40
41 RELAY DATA_OUT_ALM DATA_OUT_ALM 9 3M40 41
42 MAIN ALM OUT,RACK (NORMALY LOW) DATA_INP_ALM 10 42
1
43 ADDR_1 11 43 1
C11 R5
44 FUSE_ALM ADDR_2 12 44 470nF 1.5k
45 J1 TXD+ 13 45 2 2
46 SECTION ERROR,OUT 1
COAX TXD- 14 46 + 5V
47 2 ADDR_3 15 47
48 HOP ERROR,OUT 1 P6KE12CA ADDR_4 16 48
49 RXD+ 17 49 48V+
50 GND G1 RXD- 18 50
2
3M50 FUSE_ALM 19 3M50
RMT_RESET_ACU 20
J2 1 C1 1 C2 CA20 + 5V
COAX 1 C18
1
8
7
6
5
2 1.0uF 1.0uF
2 2 1.0uF
DILSWITCH4
1 P6KE12CA 2
S2
G2 1N5822 1 2 1N5822
2
G4 G6
1
2
3
4
2 1
- 5,2V
+ 15V
- 15V
48V+
48V-
MAIN ALM
1 C14 1
+ C16
1.0uF 220uF
S2102275 Rev. B
2 2
MAX744A
R6 1 8
1 2 SHDN V+
2 7 L2
510k REF LX 1 4
3 SS GND 6 100uH
FILTER & CONNECTION PANEL, Radio, 48V

4 CC OUT 5
1 C12 C13 1
IC1 2 1N5822 1 C17
0.1uF 10nF C15 G15 470uF
2 2 1
1 2 2
EF324A
330pF
DC-DC CONVERTER
FILTER & CONNECTION
PANEL BOARD, RADIO, 48V/24V
EF324C/EF324D
H3025 Rev. A
© Nera ASA
EF324C/D
1.0 DESCRIPTION
1.1 General
These boards supersedes EF280A/B and EF324A/B c) To combine +15V and -5.2V from service rack
and can be used together with electrical as well as optical and radio rack and to convert +15V to +5V for
interface units. use in Optical Interface Unit and CMI Splitter Unit.
The board is located at the top of each radio rack. A These units are common units for regular- and
terminal block for connection of two separate battery protection channel.
circuits is provided. If only one circuit is used, connect d) Relays K1 and K2 are related to fuse alarm for F1
this to the circuit with Fuse F1. Then remove strap W1 and F2. The relays are normally activated, and a
to disable the alarm for fuse F2. The rack power ON/ green LED located near the fuse will light. If the
OFF switch and fuses, which are mounted on a bracket, fuse is blown, the relay will fallback and give
are also part of this unit. alarm to the Supervisory Unit (SU) (fuse alarm is
not connected to SU for electrical interface). The
green LED will then extinguish.
1.2 Functional
e) Relay K3 is related to the rack alarm and is
1.2.1 The different functions of the controlled by an alarm output from the Alarm
board Collection Unit (ACU). The Relay is normally
a) Filtering of battery voltage and distribution of this to activated, and when fallback occurs, the primary
the main power supply via P8 and to XMTR voltage will provide alarm visualized by a red LED
power supply via P6. at the top of the rack.
b) Distribution of secondary voltages and signals to/ f) Switch S2 is used for setting address in the Optical
from Optical Interface Unit via P5, CMI Splitter Interface Unit depending on Radio Channel.
via P4 and to CMI ouput Relay via P3.
S2-4 S2-3 S2-2 S2-1 Radio Channel 1

OPEN
0 0 0 0 PROT. 2
0 0 0 1 1 3
4
0 0 1 0 2
0 0 1 1 3 OPEN =1
0 1 0 0 4 CLOSED = 0
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
Fig. 1, Switch S2 on EF324C/D
2 H3025
EF324C/D
Connection point for F2 Fuse
Connection point for F1 Fuse
Fig. 2 Filter & Connection Panel, Board, EF324C/D
H3025
3
POWER SUPPLY, 48V
OPR171A
H2455 Rev. B
© Nera ASA
0PR171A
1. Technical Data:
Input voltage : 40 to 60 V, nom. 48 V
Output voltages : +5.0 V, ±0.1 V, 6.5A

-5.0 V, ±0.1 V, 3.5A
+15.0 V, ±0.4 V, 1.0A
-15.0 V, ±0.4 V, 0.5A
2. Main Power Supply Distribution:

(See Fig. 1)
An input filter dampens the "Common Mode" noise. In a transmitter/ receiver shelf there are 3 power
supplies: 0PR147B (1 pcs.) and 0PR171A (2 pcs.).
In a service rack there are 2 pcs. 0PR171A. 0PR147B is mounted together with a high freguency FET
amplifier on a heat sink. The 0PR171A power supplies are connected in parallel. (See fig. 1). One power
supply compensates for the loss of the other.
Each power supply incorporates an input filter and a fuse.
48V 48V 48V + 9 .4V

ON OFF INPUT
0PR147B
SWITCH FILTER -5V
+ FUSE
+1 5 V +1 5 V
-1 5V - 15 V
A
0PR171B + 5V + 5V
-5V
- 5V
+15 V
-1 5 V
A
0PR171B +5V
- 5V
Fig. 1 Main Power Supply Distribution
2 H2455
0PR171A
3. Basic Principles of Operation:

The power supply contains 3 converters, one for +5 V, one for -5 V and one for +15 V/-15 V
conversion.These 3 converters are synchronised with each other. Each converter is a "push-pull" converter
with a switching frequency of 100 kHz. Push-pull means that a transformer is used with a center tapped
primary winding. The input voltage is connected to the center-tap. The other 2 terminations are connected
through semiconductor switches to the return conductor of the input voltage.
The semiconductor switches are Field Effect Transistors (FET). Those 2 transistors should never be
switched on at the same time. If this occurs, a short circuit is put across the input voltage and destroys the
switches. It follows that they must be switched on one at a time.
When one transistor is switched off before the other one is switched on, a large transient could be expected
because of the energy which is stored in the primary inductance. This is not the case because the rectifying
diodes on the secondary side clamp the voltage. Unfortu-nately we do get a transient because of the leakage
inductance.
3.2 Regulating Principle:

In order to obtain a stable output voltage, regulation is needed. Feedback from the output voltage is needed
and this feedback signal must change something in order to correct for the observed output error.
This power supply uses Pulse Width Modulation (PWM). PWM means that the on-time of the
semiconductor switches is varied according to the feedback signal (see fig. 2). The system has a fixed
frequency.
ON OFF
Fig. 2 Timing and Modulation of 1 output of the IC
Every converter uses a PWM-IC. This IC has two outputs, each driving a FET. The IC uses an oscillator
that runs at 200 kHz. That means that every output is switching at 100 kHz. The transformer is being
switched with a 100 kHz frequency. The outputs have a 200 kHz ripple voltage, due to the split windings on
the transformer.
The feedback signal is generated by comparing the output voltage (in our case scaled down by a resistive
divider) with a reference voltage. If a deviation is detected, the error is compensated for by feedback,
either by increasing or decreasing the current that is sent through the LED of the optocoupler. This current is
converted to a voltage and fed to pin 2 on the PWM-IC. This voltage is compared with a triangular voltage.
When the triangular voltage overtakes the feedback voltage, the output is switched off (that means the FET
is switched off).
H2455 3
0PR171A
4.1 Input Filter:
The input filter attenuates the noise that is produced in the power supply. A part of the filter is incorporated
into each converter (L101, L201 and L301). L1 is a current compensated coil and reduces the common-
mode noise.
4.2 +5 V Converter:
The "heart" of the converter is the PWM, this is an integrated circuit. The IC contains all the building blocks
that are needed to construct a PWM-modulator (see fig. 3).
The voltage from the transformer is rectified. This pulsating voltage is smoothed out by a LC-filter. On the
+5 V converter the output coil has an extra winding. This winding produces about 15 V which is fed back to
the primary side as a supply voltage, (Vaux1) for the PWM-IC's and FET-drivers.
From the transformer another voltage (Vaux2) is generated through a multiplier circuit. This voltage is
needed to drive the feedback amplifier/comparator and the FET at the output. This FET replaces the usual
"oring diode" that is used when power supplies are connected in parallel.
Each FET contains a body-diode. This diode is short-circuited when the FET is switched on. The FET is
switched on by drivig its gate higher than 10 V (with reference to its source terminal). This switch-on signal
is generated by a separate IC (UC1903J, fig. 4).
Feedback signal is generated by an operation amplifier (CA3240). This op-amp uses localised feedback to
obtain an overall stable feedback system.
4.3 -5 V Converter:
This converter is the same as the one described above. The difference is that it does not generate a Vaux1
voltage that is fed back to the primary side.
4 H2455
0PR171A
4.4 +15 V/-15 V Converter:
This converter is slightly different from those above. It uses one coil to smooth out both the +15 V and the -
15 V outputs. Feedback is taken from the +15 V output. This means that the -15 V output is not properly
regulated. Its output voltage will vary according to the load on both outputs. To avoid problems in case one
of the outputs is unloaded, a constant power drain on each output voltage is included.
%/2&.',$*5$0
+5V
REGULATOR
U.V. Power to 12 CA
sense internal FLIP
circuitry FLOP
OSC 3 T 11 E
A
RT 6 CLOCK
OSC
CT 7
RAMP R
+ S
PW M 13 CB
COMP S
COMP 9 - LATCH
V-in
14 EB
INV INPUT 1 -
E/A 1K
+
V-in
200mV 10K
4 - 8
C.L. (-) SENSE 5 +
&211(&7,21',$*5$0
',/7239,(:
-RU13DFNDJH
RT 6 11 EMITTER A
CT 7 10 SHUTDOW N
Fig. 3A/B Integrated Circuit, UC1524AJ
H2455 5
0PR171A
BLOCK DIAGRAM
OUTPUT 16 +VIN
SUPPLY
INV. 18
UNDERVOLTAGE
+ GENERAL SENSE
N.I. 17 OVER-VOLTAGE
PURPOSE
OP-AMP
COMPARATOR
11 O.V. FAULT
SENSE 1 9 +
SENSE 2 8 + O.V. DELAY
SENSE 3 7 +
SENSE 4 6 +
SENSE 4 5 10 O.V.DELAY
INVERT
INPUT + UNDER-VOLTAGE 13 U.V.DELAY
COMPARATOR
12 U.V. FAULT
+VIN
1
U.V. DELAY
O.V.THRESH
VREF (2.5V) 2
U.V. THRESH
+ START
WINDOW 4
ADJUST LATCH
2.0 V
S Q
GROUND 3
R
14 POWER OK
LINE/ +
SWITCHER
15
SENSE
&211(&7,21',$*5$0
',/7239,(:
-RU13DFNDJH
+ VIN 1 18 G.P. OP. AMP INV.

V (2.5V) 2 17 G.P. OP. AMP N.I.
REF
GROUND 3 16 G.P. OP AMP OUT
WINDOW ADJUST 4 15 LINE/SWITCHER SENSE

SENSE 4 5 14 POWER OK
INVERT INP
SENSE 4 6 13 UV DELAY
SENSE 3 7 12 UV FAULT
SENSE 2 8 11 0V FAULT
SENSE 1 9 10 0V DELAY
Fig. 4A/B Integrated Circuit, UC1903J
6 H2455
POWER SUPPLY, 48V
OPR171B
H2989 Rev. B
© Nera ASA
0PR171B
1. Technical Data:
Input voltage : 40 to 60 V, nom. 48 V

-5.0 V, ±0.1 V, 3.5A
+15.0 V, ±0.4 V, 1.0A
-15.0 V, ±0.4 V, 0.5A
48V 48V 48V + 9 .4V

ON OFF INPUT
0PR147B
SWITCH FILTER -5V
+ FUSE
+1 5 V +1 5 V
-1 5V - 15 V
0PR171B + 5V + 5V
-5V
- 5V
+15 V
-1 5 V
0PR171B +5V
- 5V
2. Main Power Supply Distribution:

(See Fig. 1)
An input filter dampens the "Common Mode" noise. In a transmitter/ receiver shelf there are 3 power
supplies: 0PR147B (1 pcs.) and 0PR171B (2 pcs.).
In a service rack there are 2 pcs. 0PR171B. 0PR147B is mounted together with a high freguency FET
amplifier on a heat sink. The 0PR171B power supplies are connected in parallel. (See fig. 1). One power
supply compensates for the loss of the other.
Each power supply incorporates an input filter and a fuse.
2 H2989
0PR171B
3. Basic Principles of Operation:

The power supply contains 3 converters, one for +5 V, one for -5 V and one for +15 V/-15 V
conversion.These 3 converters are synchronised with each other. Each converter is a "push-pull"
converter with a switching frequency of 100 kHz. Push-pull means that a transformer is used with
a center tapped primary winding. The input voltage is connected to the center-tap. The other 2
terminations are connected through semiconductor switches to the return conductor of the input
voltage.
The semiconductor switches are Field Effect Transistors (FET). Those 2 transistors should never
be switched on at the same time. If this occurs, a short circuit is put across the input voltage and
destroys the switches. It follows that they must be switched on one at a time.
When one transistor is switched off before the other one is switched on, a large transient could be
expected because of the energy which is stored in the primary inductance. This is not the case
because the rectifying diodes on the secondary side clamp the voltage. Unfortu-nately we do get a
transient because of the leakage inductance.
3.2 Regulating Principle:

In order to obtain a stable output voltage, regulation is needed. Feedback from the output voltage is
needed and this feedback signal must change something in order to correct for the observed output
error.
This power supply uses Pulse Width Modulation (PWM). PWM means that the on-time of the
semiconductor switches is varied according to the feedback signal (see fig. 2). The system has a
fixed frequency.
Fig. 2 Timing and Modulation of 1 output of the IC:
ON OFF
Every converter uses a PWM-IC. This IC has two outputs, each driving a FET. The IC uses an
oscillator that runs at 200 kHz. That means that every output is switching at 100 kHz. The
transformer is being switched with a 100 kHz frequency. The outputs have a 200 kHz ripple
voltage, due to the split windings on the transformer.
The feedback signal is generated by comparing the output voltage (in our case scaled down by a
resistive divider) with a reference voltage. If a deviation is detected, the error is compensated for
by feedback, either by increasing or decreasing the current that is sent through the LED of the
optocoupler. This current is converted to a voltage and fed to pin 2 on the PWM-IC. This voltage
is compared with a triangular voltage. When the triangular voltage overtakes the feedback voltage,
the output is switched off (that means the FET is switched off).
H2989 3
0PR171B
4.1 Input Filter:
The input filter attenuates the noise that is produced in the power supply. A part of the filter is
incorporated into each converter (L101, L201 and L301). L1 is a current compensated coil and
reduces the common-mode noise.
4.2 +5 V Converter:
The "heart" of the converter is the PWM, this is an integrated circuit. The IC contains all the
building blocks that are needed to construct a PWM-modulator (see fig. 3).
The voltage from the transformer is rectified. This pulsating voltage is smoothed out by a LC-
filter. On the +5 V converter the output coil has an extra winding. This winding produces about 15
V which is fed back to the primary side as a supply voltage, (Vaux1) for the PWM-IC's and FET-
drivers.
From the transformer another voltage (Vaux2) is generated through a multiplier circuit. This
voltage is needed to drive the feedback amplifier/comparator.
Feedback signal is generated by an operation amplifier (CA3240). This op-amp uses localised
feedback to obtain an overall stable feedback system.
4.3 -5 V Converter:
This converter is the same as the one described above. The difference is that it does not generate a
Vaux1 voltage that is fed back to the primary side.
4 H2989
0PR171B
4.4 +15 V/-15 V Converter:
This converter is slightly different from those above. It uses one coil to smooth out both the +15
V and the -15 V outputs. Feedback is taken from the +15 V output. This means that the -15 V
output is not properly regulated. Its output voltage will vary according to the load on both
outputs. To avoid problems in case one of the outputs is unloaded, a constant power drain on
each output voltage is included.
%/2&.',$*5$0
+5V
REGULATOR
U.V. Power to 12 CA
sense internal FLIP
circuitry FLOP
OSC 3 T 11 E
A
RT 6 CLOCK
OSC
CT 7
RAMP R
+ S
PW M 13 CB
COMP S
COMP 9 - LATCH
V-in
14 EB
INV INPUT 1 -
E/A 1K
+
V-in
200mV 10K
4 - 8
C.L. (-) SENSE 5 +
&211(&7,21',$*5$0
',/7239,(:
-RU13DFNDJH
RT 6 11 EMITTER A
CT 7 10 SHUTDOW N
Fig. 3A/B Integrated Circuit, UC1524AJ
H2989 5
0PR171B
BLOCK DIAGRAM
OUTPUT 16 +VIN
SUPPLY
INV. 18
UNDERVOLTAGE
+ GENERAL SENSE
PURPOSE
OP-AMP
COMPARATOR
11 O.V. FAULT
SENSE 1 9 +
SENSE 3 7 +
SENSE 4 6 +
INVERT
COMPARATOR
12 U.V. FAULT
+VIN
1
U.V. DELAY
O.V.THRESH
VREF (2.5V) 2
U.V. THRESH
+ START
WINDOW 4
ADJUST LATCH
2.0 V
S Q
GROUND 3
R
14 POWER OK
LINE/ +
SWITCHER
15
SENSE
&211(&7,21',$*5$0
',/7239,(:
-RU13DFNDJH

V (2.5V) 2 17 G.P. OP. AMP N.I.
REF

INVERT INP
Fig. 4A/B Integrated Circuit, UC1903J
6 H2989
POWER SUPPLY, 24V
0PR172A
H2456 Rev.A
© Nera AS
0PR172A
1 Technical Data:
Input voltage : 20 to 30 V, nom.24 V

-5.0 V, ±0.1 V, 3.5A
+15.0 V, ±0.4 V, 1.0A
-15.0 V, ±0.4 V, 0.5A
24v ON/OFF 24v 24v +9.4V

INPUT 0PR159A
SWITCH
FILTER -5V
FUSE
+15V
+15V
-15V
-15V
0PR172A
+5V
+5V
-5V -5V
+15V
-15V
0PR172A +5V
-5V
2 Main Power Supply

Distribution:
(See Fig. 1)
An input filter dampens the Common Mode noise. amplifier on a heat sink. The 0PR172A power
In a transmitter/ receiver rack there are 3 power supplies are connected in parallel. (See fig. 1). One
supplies: 0PR159 (1 pcs.) and 0PR172A (2 pcs.). power supply compensates for the loss of the other.
In a service rack there are 2 pcs. 0PR172A. 0PR159A Each power supply incorporates an input filter and a
is mounted together with a high frequency FET fuse.
2 H2456
0PR172A
current that is sent through the LED of the
3. Basic Principles of optocoupler. This current is converted to a voltage
Operation: and fed to pin 2 on the PWM-IC. This voltage is
compared with a triangular voltage. When the
triangular voltage overtakes the feedback voltage,
3.1 Converting Principle: the output is switched off (that means the FET is
The power supply contains 3 converters, one for switched off).
+5V, one for -5V and one for +15V/-15V
conversion.These 3 converters are synchronised with
each other. Each converter is a push-pull converter
with a switching frequency of 100 kHz. Push-pull
means that a transformer is used with a center tapped
primary winding. The input voltage is connected to the 4.1 Input Filter:
center-tap. The other 2 terminations are connected The input filter attenuates the noise that is produced in
through semiconductor switches to the return conduc- the power supply. A part of the filter is incorporated
tor of the input voltage. into each converter (L101, L201 and L301). L1 is a
current compensated coil and reduces the common-
The semiconductor switches are Field Effect Transis- mode noise.
tors (FET). Those 2 transistors should never be The input filter also contains an inrush current lim-
switched on at the same time, otherwise a short circuit iter. This limiter consists of R20 ( a NTC resistor) and
is put across the input voltage and destroys the Q4. Q4 shorts out R20 after a certain delay.
switches. It follows that they must be switched on one
at a time.
4.2 +5 V Converter:
When one transistor is switched off before the other The heart of the converter is the PWM- IC. The IC
one is switched on, a large voltage transient will be contains all the building blocks that are needed to
generated because of the energy which is stored in the construct a PWM-modulator (see fig. 3).
primary leakage inductance.
The voltage from the transformer is rectified and the
3.2 Regulating Principle: square wave voltage is smoothed out by a LC-filter. On
In order to obtain a stable output voltage, regulation is the +5 V converter the output coil has an extra winding.
needed. Feedback from the output voltage is needed This winding produces about 15 V which is fed back
and this feedback signal must change something in to the primary side as a supply voltage for the PWM-
order to correct for the observed output error. ICs and FET-drivers.
This power supply uses Pulse Width Modulation From the transformer another voltage (Vaux2) is gen-
(PWM). PWM means that the on-time of the semicon- erated through a multiplier circuit. This voltage is
ductor switches is varied according to the feedback needed to drive the feedback amplifier/comparator.
signal (see fig. 2). The system has a fixed frequency. Feedback signal is generated by an operation ampli-
Every converter uses a PWM-IC. This IC has two fier (CA3240). This op-amp uses localised feedback
outputs, each driving a FET. The IC uses an oscillator to obtain an overall stable feedback system.
that runs at 200 kHz. That means that every output is In order to connect both power supplies in parallel, a
switching at 100 kHz. The transformer is being diode is needed at the output to prevent
switched with a 100 kHz frequency. The power supply a voltage drop in case of power failure.
outputs have a 200 kHz ripple voltage, due to the split
windings on the transformer. 4.3 -5 V Converter:
The feedback signal is generated by comparing the This converter is the same as the one described above.
output voltage (in our case scaled down by a The differences are that it does not generate a voltage
resistive divider) with a reference voltage. If there that is fed back to the primary side, and it does not use
is a deviation, the error is compensated for by the a multiplier to obtain a voltage needed to drive the
feedback by either increasing or decreasing the feedback op-amp.
H2456 3
0PR172A
4.4 +15 V/-15 V Converter: FET-transistors instead of diodes are used at the +15V
This converter is slightly different from those above. and -15V outputs. These FET-transistors
It uses one coil to smooth out both the +15V and the - contain a parasite diode between drain and source
15V outputs. Feedback is taken from the +15V output. which is used for paralleling the power supplies. By
This means that the -15V output is not properly regu- normal operation these diodes are shorted by driving
lated. Its output voltage will vary according to the load the gate terminal with a >5V voltage. This signal is
on both outputs. To avoid problems in case one of the generated by the UC2903N which monitors the output
outputs is unloaded, a constant power drain on each voltages on all outputs. The FET transistors also serve
output voltage is included. as balancing resistors for equal current charging under
normal operation.
ON OFF
4 H2456
0PR172A
%/2&.',$*5$0
+5V
REGULATOR
U.V. Power to 12 CA
sense internal FLIP
circuitry FLOP
OSC 3 T 11 E
A
RT 6 CLOCK
OSC
CT 7
RAMP R
+ S
PWM 13 CB
COMP S
COMP 9 - LATCH
V-in
14 EB
INV INPUT 1 -
E/A 1K
+
V-in
200mV 10K
4 - 8
5 +
C.L. (-) SENSE
&211(&7,21',$*5$0
',/7239,(:
-RU13DFNDJH
RT 6 11 EMITTER A
CT 7 10 SHUTDOW N
Fig. 3A/B Integrated Circuit, UC2524AN
H2456 5
0PR172A
%/2&.',$*5$0
OUTPUT 16 +VIN
SUPPLY
INV. 18
UNDERVOLTAGE
+ GENERAL SENSE
PURPOSE
OP-AMP COMPARATOR
11 O.V. FAULT
SENSE 1 9 +
SENSE 3 7 +
SENSE 4 6 +
INVERT
COMPARATOR
12 U.V. FAULT
+VIN
1 U.V. DELAY
O.V.THRESH
VREF (2.5V) 2
U.V. THRESH + START
WINDOW 4
ADJUST LATCH
2.0 V
GROUND 3 S Q
R
14 POWER OK
LINE/ +
SWITCHER
15
SENSE
&211(&7,21',$*5$0
',/7239,(:
-RU13DFNDJH

V (2.5V) 2 17 G.P. OP. AMP N.I.
REF

INVERT INP
Fig. 4A/B Integrated Circuit, UC2903N
6 H2456
APPENDIXES
to OPERATOR's MANUAL
NL290- Family
H2615 Rev. B
© Nera AS
Appendixes
Appendix A, List of Abbreviations
A/D Analog to Digital Converter

AAU Alarm Adapter Unit
ACU Alarm Collection Unit
AIS Alarm Indication Signal
AGC Automatic Gain Control
ALC Automatic Level Control

ASF Alignment Switch Function
ASIC Application Specific Integrated Circuit
ATDE Adaptive Time Domain Equalizer
ATT Attenuator
BER Bit Error Ratio

CA Controlled Attenuator
CB Control Board
CEPT European Conference of Postal and Telecommunications Administration
CLK Clock
CMI Coded Mark Inversion

CPU Central Processor Unit
DC Direct Current
DIP Dual In-line Package
DM Degraded Minutes
DRO Dielectric Resonator Oscillator

DTMF Dual Tone Multi-Frequency
ECL Emitter Coupled Logic
EMC Electromagnetic Compatibility
EOW Engineering Order Wire
EPROM Erasable Programmable Read-Only Memory

EQL Equalizer
ES Errored Seconds
FB Filter Bank
FEC Forward Error Correction
FET Field Effect Transistor

FM Frequency Modulation
GaAs Gallium Arsenide
HBER High Bit Error Ratio
HDB3 High Density Bipolar (Max. 3 "0")
I/O Input/Output
IF Intermediate Frequency
ITU-R International Telecom. Union (former CCIR)
ITU-T International Telecom. Union (former CCITT)
LBER Low Bit Error Ratio
2
H2615
Appendixes
LCD Liquid Crystal Display

LD Level Detector
LED Light Emitting Diode
LIF Line Interface
LMS Least Mean Square
LNA Low Noise Amplifier

LO Local Oscillator
LPF Low Pass Filter
MC Micro Controller
MGC Manual Gain Control
MIL-STD Military Standard

MLE Maximum Level Error
MOD Modulator
MSOH Multiplexer Section Overhead
MST Multiplexer Section Termination
NE Network Element
NRZ Non Return to Zero
OSC Oscillator
PABX Private Automatic Branch Exchange
PAL Programmable Array Logic
PLL Phase Locked Loop

PLO Phase Locked Oscillator
PROM Programmable Read-Only Memory
PROT CH Protection Channel
PSCU Protection Switching Control Unit
PSK Phase Shift Keying

PWM Pulse Width Modulation
QPSK Quadrature Phase Shift Keying
RAM Random Access Memory
RCVR Receiver
RDDU Receiver Data Distribution Unit

REG CH Regular Channel
RF Radio Frequency
RPS Radio Protection Switching
RSOH Regenerator Section Overhead
RST Regenerator Section Termination

RU Relay Unit
SAW Surface Acoustic Wave
SCADA Supervision, Control And Data Acquisition
SDH Synchronous Digital Hierarchy
3
H2615
Appendixes
SES Severely Errored Seconds

SIC Serial Interface Controller
SOH Section Overhead
SSB Single Side Band
SSS SDH Supervisory System
STM-1 Synchronous Transport Module (1 stands for 1 x 155Mb/s)

SU Supervisory Unit
TCM Trellis Coded Modulation
TMN Telecommunication Management Network
TTL Transistor-Transistor Logic
UAT Unavailable Time

VC Virtual Container
VCO Voltage Controlled Oscillator
VCXO Voltage Controlled X-tal Oscillator
VLSI Very Large Scale Integration
XMTR Transmitter
XSU XMTR Switch Unit
4
H2615
Appendixes
Appendix B, Customer Report Forms
Nera AS
RADIOLINK CUSTOMER SUPPORT Customer Return Note for faulty units or cards
In order to ensure a responsible, efficient and which is sent to Nera AS for repair.
traceable handling of customer complaints and The purpose of this form is to:
error reports on products and services delive-
red by Nera AS Radiolink Division, the following - Identify the owner of an item received at
forms should be used: (ref. page 6 & 7) Nera AS for repair.
- Secure correct return address of a

repaired item.
Customer System Report for Non-Conforman-
ce and/or Customer Dissatisfaction. - Reduce the turn-around-time for repair
by giving as much details of a failure
Non-Conformance is defined as the failure of a as available to the repair organization.
characteristic to conform to the requirements
specified in the contract, drawings, specificati- - Describe any external factors that could
ons or other approved product descriptions. contribute to such a failure.
Customer Dissatisfaction is defined as com- - Identify any attempts from the Customer
plaints that are due to misunderstandings, ex- to repair a unit, and to eliminate possible
pectations not met, or not appropriate handling consequences from such attempts.
of customer.
It is also appreciated that the Customer indica-
Also included are requests for improvements tes on the form - if so wanted - a Warranty Repair
etc. Claim.
5
H2615

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TECHNICAL MANUAL

Digital Radio-Relay System

Booklet No: Revision: Booklet No: Revision:

Transmitter Groups NL290 - Family H2600 2

Power Supply, Tx (48V) 0PR147B H2189 3

Modulator, 64/128TCM 8MNF83A, 83C, 89A H2805, 2972, 2970 4

Relay & Driver Unit OS186A H2858 5

Switch, XMTR 2SN218A H2788 6

Main Alarm Display EK50A H2030 7

Service Channel, Sel. Call 2NF468A H2143 8

This equipment contains components which are sensitive to "ESD"

It is therefore essential that whenever disassembling the equipment and/

These precautions include personnel grounding, grounding of work

Any unnecessary exposure is undesirable and should be avoided.

In Radio-Relay communication installations, orderly setup for normal operation, the

Dangerous radiation may be found in the neighbourhood of open waveguide flanges

To avoid dangerous radiation the following precautions must be taken:

r Before opening coaxial - or waveguide connectors carrying RF power, turn

r Consider any incidentally open RF connector as carrying power, until

r DO NOT remove or insert the Transmitter / Receiver

r To avoid traffic disturbance during maintenance on

PLEASE OBSERVE that mechanical switches should be

When handling Laser products the following precautions must be taken:

r Never look directly into an open connector or optical cable

r Before disconnecting an optical cable from the transmitter, the power

r When the cable is reconnected it must be connected to the

1 - NETWORK AND SYSTEM CONSIDERATIONS ..................................................................................................... 7

2 - EQUIPMENT MAIN CHARACTERISTICS ............................................................................................................. 9

1 - NETWORK AND SYSTEM CONSIDERATIONS

Z' E' A' B' C' D'

MAIN RECEIVER PATH

DIVERSITY RECEIVER PATH

(*) no filtering included

Figure 1.1: Principle block diagram for a NL290-family radio system

SVCE CHP CH1 CHN

MAIN MAIN MAIN

OPTION 64kb/s ADPT

IF- IF- IF-

OPTION SYNCH UNIT

Figure 1.2: Rack-layout for a N+1 terminal

2 - Equipment main characteristics

2.2 Frequency bands and channel arrangement

Equipment Freq Frequency ITU-R Centre Df channel Tx-Rx min.

NL294 4 GHz 3.6-4.2 GHz Rec. 635-2 3890 MHz 40 80

NL293 5GHz 4.4-5.0 GHz Rec. F.1099 4700 MHz 30 to 40 60

NL295 U6 GHz 6.4-7.1 GHz Rec. 384-5 6770 MHz 40 60

NL299 7 GHz 7.4-7.7 GHz Rec. 385-5 7575 MHz 28 42 (1)

NL291 11GHz 10.7-11.7 GHz Rec. 387-6 11200 MHz 40 90

NL296 13 GHz 12.7-13.3 GHz Rec. 497-4 12996 MHz 28 70

2.2.1. Frequency tolerance

2.3 System configuration

2.3.1 Radio terminal configurations

2.3.2 Radio repeater configurations

2.3.2.1 Standard repeater

2.3.2.1 Add/drop repeater

2.3.3 Radio channel identification

2.4 Modes of operation

2.5 Types of installation

2.5.1 Safety conditions

System gain CC (10-3) [dB]

4.2 IF input characteristics (point E)