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    SUFYAN Lab Report

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    Sufyan Asghar
    This document contains code for two lab tasks and their corresponding testbenches. Lab Task 1 code implements a module that performs addition, concatenation, or selection on two 3-bit inputs based on a 2-bit selection signal. The always block sums the result and previous total and tracks overflow. Lab Task 2 code implements an ALU module that performs addition, subtraction, AND, or OR on two 16-bit inputs based on a 2-bit selection signal. The testbench iterates through all input combinations for exhaustive testing.

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    Attribution Non-Commercial (BY-NC)
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    SUFYAN Lab Report

    Uploaded by

    Sufyan Asghar
    44 views5 pages
    This document contains code for two lab tasks and their corresponding testbenches. Lab Task 1 code implements a module that performs addition, concatenation, or selection on two 3-bit inputs based on a 2-bit selection signal. The always block sums the result and previous total and tracks overflow. Lab Task 2 code implements an ALU module that performs addition, subtraction, AND, or OR on two 16-bit inputs based on a 2-bit selection signal. The testbench iterates through all input combinations for exhaustive testing.

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    This document contains code for two lab tasks and their corresponding testbenches. Lab Task 1 code implements a module that performs addition, concatenation, or selection on two 3-bit inputs based on a 2-bit selection signal. The always block sums the result and previous total and tracks overflow. Lab Task 2 code implements an ALU module that performs addition, subtraction, AND, or OR on two 16-bit inputs based on a 2-bit selection signal. The testbench iterates through all input combinations for exhaustive testing.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    44 views5 pages

    SUFYAN Lab Report

    Uploaded by

    Sufyan Asghar
    This document contains code for two lab tasks and their corresponding testbenches. Lab Task 1 code implements a module that performs addition, concatenation, or selection on two 3-bit inputs based on a 2-bit selection signal. The always block sums the result and previous total and tracks overflow. Lab Task 2 code implements an ALU module that performs addition, subtraction, AND, or OR on two 16-bit inputs based on a 2-bit selection signal. The testbench iterates through all input combinations for exhaustive testing.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
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    You are on page 1of 5

    Submitted by: NS SUFYAN ASGHAR (067) NS AMBER GHOURI (011)

    LAB TASK #01


    Code:
    module labtask1 (a,b,sel,clk,rst,total,flow); input [2:0]a; input[2:0]b; input[1:0]sel; input clk,rst; wire [3:0]e,c,d; reg [3:0]r1; output reg [6:0]total; output reg flow; assign e=a+b; assign c={1'b0,a}; assign d={1'b0,b}; always@(*) begin case(sel) 2'b00: begin r1<=c; end 2'b01: begin r1<=e; end 2'b10:

    begin r1<=d; end default: r1<=d; endcase end

    always @ (posedge clk) begin if (rst===1) begin total<=0; flow<=0;

    end else begin

    total<=total[5:0]+r1; flow=(total[6]|flow); end end endmodule

    stimulus lab task #01:


    module stimlab1(); reg [2:0]A,B; reg [1:0]SEL;

    reg CLK,RST; wire [6:0]TOTAL; wire SUM; integer i;

    initial CLK=0;

    labtask1 stim(A,B,SEL,CLK,RST,TOTAL,SUM);

    always #5 CLK=~CLK;

    initial begin #5 RST=0; #2 RST=1; #12 RST=0; end initial begin #5 A=0;B=0;SEL=0; for(i=0;i<=10;i=i+1) begin #5 A=A+1;B=B+1;SEL=SEL+1; End end endmodule

    LAB TASK 02
    module alu(a,b,sel,out);

    input [15:0]a,b; input [1:0]sel; output reg [15:0]out; always@(*) begin case(sel) 2'b00: out<=a+b; 2'b01: out<=a-b; 2'b10: out<=a&b; 2'b11: out<=a|b; endcase

    end endmodule

    STIMULAS LABTASK 02
    module alu_stim(); reg [15:0]A,B; reg [1:0]SEL; wire [15:0]OUT; integer i,j,k; alu stim(A,B,SEL,OUT); initial begin #5 SEL=-1;A=0;B=0; for(i=0;i<4;i=i+1) begin SEL=SEL+1;

    for(j=0;j<16;j=j+1) begin A=A+1; for(k=0;k<16;k=k+1) #5 end end end endmodule B=B+1;

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