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8 Cmos Capacitance
8 Cmos Capacitance
CGB CGB
VDD
Gate Capacitance
ε OX WL
CGB = = COX WL
tOX
• Define Cpermicron = CoxL
– Typically about 2 fF/µm
• Therefore, CGB = Cpermicron X W
• Realistically, there are additional capacitances.
However, the above
relationship is a
polysilicon
good approximation gate
W
of the gate
t ox
capacitance. L SiO 2
gate oxide
n+ n+ (good insulator, εox = 3.9ε0)
p-type body
MOSFET Resistance
• The resistance of a MOSFET transistor must be
determined from the Shockley I-V relationships.
– However, Ids(Vds, Vgs).
RC Delay Model
• Use equivalent circuits for MOS transistors
– Ideal switch + capacitances and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
• The PMOS resistance should actually be (k’n/k’p)R
• Capacitance proportional to width
• Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
s
g k g kC
g k g
s kC kC
kC d
s
d
– Cpermicron = COX X L:
• COX – the oxide capacitance which depends on the type
of oxide used and is inversely dependent on the
thickness of the oxide layer.
– COX is typically in the range of ~700aF/µm2
» a stands for atto – 10-18.
• L – the length of the channel.
2 Y 2
A
1 1
2C
2C
2C
2 Y 2
A Y
1 1
C
R C
2C
2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C
2C
2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C
d = 6RC
VLSI Design Dr. Bassel Soudan – University of Sharjah 15
Delay Components
• Delay has two parts
– Parasitic delay – due to capacitances of the
driving gate itself.
• 3 RC in the inverter example above.
• Independent of load.
– Effort delay – due to capacitances of the load
gates.
• The other 3 RC in the inverter example above.
• Depends on the number and type of driven gates.
2 2 2
3
3
3
2 2 2
2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C
3C
3
3C
3C
3
3C
3C
3
3C
3C
Combining Capacitances
• Capacitors on source diffusions of transistors
connected to VDD or GND will be shorted out.
• The DC voltage on the second terminal of a
capacitor is irrelevant to delay calculation.
– Therefore, all capacitors will be estimated as
terminating to GND.
2 2 2
3 9C
5C
3 3C
5C
3 3C
5C
Elmore Delay
• ON transistors look like resistors
• Pullup or pulldown network modeled as RC
ladder
• Elmore delay of RC ladder
t pd ≈ ∑
nodes i
Ri −to − sourceCi
C1 C2 C3 CN
2 2 Y
h copies
A 2
B 2x
2 2 Y
A 2 6C 4hC h copies
B 2x 2C
2 2 Y
A 2 6C 4hC h copies
B 2x 2C
R
Y t pdr = ( 6 + 4h ) RC
(6+4h)C
2 2 Y
A 2 6C 4hC h copies
B 2x 2C
2 2 Y
A 2 6C 4hC h copies
B 2x 2C
= ( 7 + 4h ) RC
R/2 2C (6+4h)C
Diffusion Capacitance
• we assumed contacted diffusion on every s / d.
• Good layout minimizes diffusion area
• Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too
2C 2C
Shared
Contacted
Diffusion Isolated
Contacted 2 2 2
Merged Diffusion
Uncontacted 3 7C
Diffusion 3 3C
3C 3C 3C 3 3C
VDD VDD
A B A B
Y Y
GND GND
12 C
12 C
P: 2
N: 3
P: 2
N: 1
P: 2
N: 1
P: 2
N: 1
R 3C 4(4C)
d = 19RC
P: 2
N: 1
R 6C 3C
d = 9RC
P: 2
N: 1
R 3C 5C + 5C + 3C = 13C
d = 16RC
P: 2
N: 1
R/2
R/2 4C 6C 12C
P: 2
N: 1
P: 2
N: 1
P: 2
N: 1
R 3C 4(4C)
d = 19RC
P: 2
N: 1
R/2
R/2 2C 6C 3C
P: 2
N: 1
R 3C 5C + 5C + 3C = 13C
d = 16RC
P: 2
N: 1
R 6C 12C
d = 18RC
P: 2
N: 1