EEEE 482 Electronics II

Experiment #7: Propagation Delay in CMOS Circuits

Objective
The goal of this lab experiment is to introduce the student to the dynamic behavior of CMOS
circuits. This will complement understanding of static behavior acquired in previous laboratory
exercises. Propagation delay through a CMOS inverter will be calculated and simulated using
PSPICE. A CMOS ring oscillator will be analyzed by hand-calculation, simulated to confirm
calculations, then built and tested.

Introduction
This lab will explore the dynamic characteristics of several CMOS circuits. A discussion of the
switching properties of CMOS circuits can be found in Analysis and Design of Digital Integrated
Circuits, by Hodges, Jackson, and Saleh, 3rd ed., McGraw-Hill, Chapter 6.
When a change is applied to the input(s) of a digital gate, such as a CMOS inverter, the output
cannot respond instantaneously. In order for the voltage at the output node to change, capacitance
must be charged or discharged. However, we know from circuit theory that a capacitor cannot be
charged or discharged instantaneously it would require an infinite amount of energy to do so.
Instead, current flows into or out of a capacitor, and the instantaneous voltage across the capacitor is
related to the instantaneous current by this familiar relationship:
dv t
i t C C .
dt
The time that it takes to achieve a given voltage change across a capacitor can be approximated as
t

CV
I avg

where Iavg is the average of the currents flowing to/from the capacitor at the beginning and the end of
the voltage transition V.
The propagation delay tP through a logic gate, then, is determined by the magnitude of the
capacitance that must be charged/discharged, the required voltage swing, and the available current.
When the output is transitioning from its low state (VOL) to its high state (VOH), the low-to-high
propagation delay tPLH is taken to be the time required for Vout to rise from VOL to V50%, where V50% is
V VOH
the halfway point between VOL and VOH i.e., V 50% OL
. Likewise, when the output is
2
transitioning from VOH to VOL, the high-to-low propagation delay tPHL is taken to be the time required
for Vout to fall from VOH to V50%. These definitions assume rapidly rising or falling inputs, and must
be refined somewhat for more realistic input waveforms.
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The load capacitance that must be charged/discharged during the switching process is comprised of
many components, a detailed consideration of which is given in the text and in lecture. For purposes
of the hand calculations and simulations in this laboratory exercise, these capacitive elements are
lumped together into a single load capacitance. This greatly facilitates hand calculations, while
sacrificing some accuracy.
The PSPICE simulation software is capable of accounting for all the individual components of
capacitance, provided that all the requisite information is supplied to the appropriate .model and
Properties fields. This information includes parameters like junction areas and perimeters, as well as
doping levels and voltage-dependent capacitance model exponents. For the sake of efficiency
again, at the cost of some accuracy the load capacitance is treated in these exercises as a single,
lumped value. In the hardware measurements, of course, the various capacitances are inherently
operating, and the measurements will reflect their actual contributions.

Pre-Lab
Before coming to lab, do all of the following (Parts (1)(4)):
Part 1: Analysis of a CMOS Inverters Dynamic Behavior
Objective: Perform hand calculations of propagations delays through a CMOS inverter.
Consider a CMOS inverter such as the one shown in Figure 1. The propagation delay times, tPLH and
tPHL, will be determined by the current-driving capacities of the NMOS and PMOS transistors, as
well as the magnitude of the load capacitance CL.

Figure 1. CMOS Inverter

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In this lab, circuits will be built using the CD4007 chip. The pin-out diagram and specifications for
the CD4007 chip are shown in Figures 4(a), 4(b), and 4(c). For a supply voltage of 10 V and a load
capacitance of 50 pF, the expected propagation delays for a single CMOS inverter are tPLH = tPHL = 30
ns (see Figure 4(c)). Best-available transistor parameters for the CD4007 devices are as follows:
VTN0 = 1.3 V, kn = 20 A/V2, Wn = 200 m, and Ln = 10 m for the NMOS drivers; VTP0 = 1.1 V,
kp = 8 A/V2, Wp = 500 m, and Lp = 10 m for the PMOS loads. Note that the kn and kp values are
the same, thereby giving equal-strength NMOS and PMOS devices when equivalent bias conditions
are applied.
The propagation delay tPLH for a CMOS inverter can be calculated as:
t PLH

C L V
,
I DPavg

where I DPavg is the average of the PMOS currents at the beginning of the low-to-high transition
(Vout = 0 ) and at the 50% point (Vout = VDD /2). Likewise, the propagation delay tPHL for a CMOS
inverter can be calculated as:
t PHL

C L V
,
I DNavg

where I DNavg is the average of the NMOS currents at the beginning of the high-to-low transition
(Vout = VDD ) and at the 50% point (Vout = VDD /2).
Use the NMOS and PMOS transistor data given above and calculate the expected propagation
delays, tPLH and tPHL. Use a load capacitance value of 47 pF. Compare your calculated values to
the 30 ns value from the CD4007 data sheet. You shouldnt expect perfect agreement, but they
should agree to within a factor of two or three.
Calculate approximate propagation delays, tPHL and tPLH, using the text approach of treating the
NMOS device as an effective resistance of 12.5 k/ and the PMOS device as an effective
resistance of 30 k/, respectively. Use a load capacitance value of 47 pF, as well as the W and
L values given above for the CD4007 NMOS and PMOS devices. Compare your calculated
values to the 30 ns value from the CD4007 data sheet and to your calculated values from above.

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Part 2: Analysis of a CMOS Ring Oscillator

Objective: Relate measurable performance parameters of a ring oscillator to properties of individual
inverter stages.

Figure 2. Five-Stage Ring Oscillator

A five-stage ring oscillator is shown in Figure 2. Each stage is comprised of a CMOS inverter like
the one shown in Figure 1. The output node of every inverter stage has a number of internal
parasitic capacitances connected to it e.g., the drain-to-gate capacitance of both the NMOS and
the PMOS devices. Additionally, the output of a given inverter stage is driving the succeeding
inverter in the ring and all the capacitance associated with that input node, as well as interconnect
capacitance. The 25 pF capacitance attached to the output node of every inverter stage in Figure 2
represents the effective parasitic and load capacitance at that node, CLeff.
It would possible for a given inverter stage to drive more than just one succeeding stage (not shown
in Figure 2). The number of succeeding stages that an inverter drives is referred to as the fanout
(FO) of the gate. The capacitance being driven by a given inverter stage would scale proportionately
with the number of identical fan-out stages. (The internal parasitic capacitances associated with the
driving inverter itself would not scale with the fanout.)
In order to measure the effective load capacitance CLeff at the output of a single inverter stage,
additional external capacitance Cext can be added at each output, as shown in Figure 3. This
increases the total load capacitance at each driven output node by the same amount and has a direct
impact on the measured delay per gate. Comparison of the delay per gate with and without the
additional known external capacitance Cext leads directly to an estimate of the effective inherent
capacitance CLeff at the output of the inverter stage.

Figure 3. Five-Stage Ring Oscillator with Additional Load Capacitance Cext

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 Derive a simple equation that relates the propagation delay tP through a single inverter stage to
the period T of the measured ring oscillator signal, the fanout FO of a single stage, and the
number n of inverter stages. Ignore the internal parasitic capacitance of a single stage and
assume that the load capacitance driven by one stage is proportional to the fanout FO. Also,
assume that all stages have the same fanout.
Derive a simple equation that relates the effective load capacitance CLeff at the output of a single
inverter stage to all three of the following: (a) the delay per stage without external capacitive
load, tdelay(no load), (b) the delay per stage with external capacitive load, tdelay(load), and (c) the amount
of external capacitive load per stage, Cext.

Part 3: Simulation of a CMOS Ring Oscillator

Objective: Compare hand calculations from the analysis of a ring oscillator to PSPICE simulation.
Open Capture CIS and construct the circuit of Figure 2. Before running the simulation, establish the
transistor parameters for both the NMOS and PMOS devices. Remember that vto, kp, gamma, and
phi are set in the .model statements, whereas W and L should normally be set in Properties. In this
particular case, however, since all NMOS devices are specified to be the same size (see below), WN
and LN can be set in the .model statement; likewise, since all PMOS devices are specified to be the
same size (see below), WP and LP can be set in the .model statement.
Use VTN0 = 1.3 V, kn = 20 A/V2, Wn = 200 m, and Ln = 10 m for the NMOS drivers.
Use VTP0 = 1.1 V, kp = 8 A/V2, Wp = 500 m, and Lp = 10 m for the PMOS loads.
Make sure that all NMOS substrates are tied to the lowest system supply and that all PMOS
substrates are tied to the highest system supply.
Circuits having several capacitive components often have convergence problems in establishing an
initial state for the circuit. The ring oscillator presently under consideration offers a good example
of these problems. The easiest way to remedy these initial convergence problems is to use the IC1
(eyeseeone) component in PSPICE, as shown in Figure 2. The IC1 component is a singleterminal component whose value should be set to the system supply voltage in this case, 10 V. In
a real circuit implemented in hardware, thermal noise in the system would be sufficient to start the
circuit without external intervention, since a small noise signal would be amplified by the gain of
each inverter stage until the outputs of all stages would be swinging between ground and VDD. The
ideal components used in simulations have no associated noise.
Create a simulation profile, giving it a name of your choosing. Choose the analysis type to be Time
Domain (Transient), and chose the time increment to provide good resolution, with the duration of
the simulation chosen taking the calculations of Parts (1) and (2) into consideration.
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 Run the simulation (of the circuit in Figure 2) and view the results. Use your analysis from Part
(2) to relate your measured period T to the propagation delay per inverter stage, tP.
Make sure that you save/print any schematic diagrams and simulation results that are needed
before modifying your circuit!!
Re-run the simulation for two different VDD values: 5 V and 7.5 V. (Remember to set the IC1
component accordingly for each case.) From the simulated waveform, determine the delay per
stage and compare the three delay values that you have obtained thus far. Does the delay per
stage scale proportionately to VDD? Briefly explain why or why not.
Reset VDD (and IC1) to 10 V. Edit your circuit and add Cext = 47 pF to each output node. The
location of Cext is shown in Figure 3. Run the simulation and view the results. Using the analysis
done in Part (2), determine the value of the inherent effective load capacitance, CLeff. Compare
this result to the known value of 25 pF that was used for CLeff in the simulation to verify that the
relationship between Cext and CLeff was correctly derived.

Part 4: Preparation for Building and Testing a CMOS Ring Oscillator

Objective:
oscillator.

Determine in advance the wiring connections required for building a CMOS ring

The pin-out diagram and specifications for the CD4007 chip are shown in Figure 4(b). A larger,
more legible version of the pin-out diagram is shown in Figure 4(a). Study the pin-out diagram
carefully, making sure you understand the various substrate and source pin-out locations. Note that
the source and substrate for each of the leftmost NMOS and PMOS devices are hard-wired together.
Sketch the transistor-level schematic of the CMOS ring oscillator (as in Figure 2) and indicate on
your diagram the corresponding pins on the CD4007 chips. You will need to use two CD4007
chips. Take care to ensure that all NMOS substrate (body) connections are wired to the lowest
system supply voltage in this case, ground and that all PMOS substrate connections are
wired to the highest system supply voltage in this case, VDD.

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Lab Measurement of Ring Oscillator Dynamic Behavior

In this lab, we will build and measure certain characteristics of a CMOS ring oscillator using
CD4007 chips. Refer to Figures 4(a) and 4(b) for the CD4007 chip pin-out. There are three
NMOS and three PMOS devices on each chip. Pay particular attention to the substrate
connections for the NMOS and PMOS devices, pins 7 and 14, respectively. Note that the psubstrate connection (pin 7) is common to the three NMOS devices; also, the n-substrate
connection (pin 14) is common to the three PMOS devices.
Required Electronic Components:
2 CD4007 chips
5 47 pF capacitors

Figure 4(a). Enlarged CD4007 Pin-Out Diagram

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Figure 4(b). CD4007 Pin-Out and Specifications

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Figure 4(c). Additional CD4007 Data Sheet Specifications

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(Parts (1)(4) were done as part of the Pre-Lab preparation)

Part 5: CMOS Ring Oscillator

IMPORTANT:

Do not apply voltage to the gates (pins 3, 6, and 10) before the drains, sources, and
substrates are connected. The gates must be connected last to avoid damage from static discharge.
When disassembling your circuits, the gates must be disconnected first.
Build the CMOS ring oscillator shown in Figure 5 using two CD4007 chips. Refer to your
schematic diagram prepared in Part (4) of the pre-lab work, which shows appropriate pin
connections for constructing the circuit. N.B.: The 25 pF capacitances shown in Figure 2
represent parasitic and load capacitances for simulation purposes, and should not be included
in the assembled hardware circuit of Figure 5 since they are inherently part of the devices used
to build the circuit. Also, there is no need for the IC1 initial condition simulation component in
the hardware circuit, as discussed in Part (3) of the pre-lab preparations.

Figure 5. Five-Stage Ring Oscillator

Make sure that you have correctly wired the circuit before proceeding.
For three values of VDD 5 V, 7.5 V, and 10 V measure the period of the ring oscillator signal
and calculate the three corresponding per-gate delay values. Compare these values to your
expected values from hand calculations and simulations.
Set VDD = 10 V if it is not already. Add Cext = 47 pF capacitance to every inverter stages output
node, as shown in Figure 6. Measure the period of the ring oscillator and calculate the
corresponding delay per gate. Use this loaded delay value and the unloaded delay value from
your previous measurement at VDD = 10 V to determine the inherent effective load capacitance,
CLeff. (Use the relationship developed in Part (2) of the pre-lab work.)

Figure 6. Five-Stage Ring Oscillator with Additional Load Capacitance Cext

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Tech Memo
Summarize the hand calculations of propagation delays through the CMOS inverter. Compare the
CV

values obtained by (1) t I

analysis, and (2) effective resistance-based calculations to each
avg
other and to expected delay values.
Summarize the relationships derived for the ring oscillator circuit that allow the determination of
(1) the delay per inverter stage, and (2) the effective load capacitance, CLeff. Summarize the results of
your simulations with respect to (1) the effect of VDD on delay per stage, and (2) the impact of
additional load capacitance, Cext.
Include diagrams and calculations required in the pre-lab preparation. Summarize the results from
your experimental measurements of the CMOS ring oscillator circuit. All information detailed on
the check-off sheet should be included in a logical and professionally-organized fashion and should
be briefly discussed.

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Check-Off Sheet
A. Pre-Lab
Analysis of CMOS inverter dynamic behavior: (a) calculation of propagation delays tPLH and
CV

tPHL from t I
approach; (b) calculation of propagation delays tPLH and tPHL from
avg
effective resistance approach; (c) comparison of delay values obtained from the two methods
to expected values.
Analysis of CMOS ring oscillator: (a) relationship of propagation delay per gate to the
period T of the measured ring oscillator signal, the fanout FO of a single stage, and the
number n of inverter stages; (b) relationship of effective load capacitance CLeff at the output
of a single inverter stage to the delay per stage without external capacitive load, tdelay(no load),
the delay per stage with external capacitive load, tdelay(load), and the amount of external
capacitive load per stage, Cext.
Simulation of CMOS ring oscillator: (a) schematic; (b) output waveforms showing proper
operation of the circuit; (c) results from simulated VDD variations plot delay per gate vs.
VDD; (d) results from simulation of additional load capacitance, Cext calculate the effective
load capacitance CLeff at the output of each inverter stage and verify the proper derivation of
the CLeff relationship.
Preparation for CMOS ring oscillator construction: schematic diagram with CD4007 pin
numbers indicated for all transistor nodes.
B. Experimental
CMOS ring oscillator circuit: (a) output waveforms for VDD variations; (b) delay per inverter
stage for VDD variations; (c) output waveform for VDD = 10 V with additional 47 pF load
capacitance, Cext; (d) calculated value of inherent effective load capacitance, CLeff.

TA Signature: ____________________________ Date: ___________________________

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