TMS320C5x Users Guide

Literature Number: SPRU056D June 1998

Printed on Recycled Paper

IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (Critical Applications). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customers applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.

Copyright 1998, Texas Instruments Incorporated

Preface

Read This First

About This Manual
This users guide describes the architecture, hardware, assembly language instructions, and general operation of the TMS320C5x digital signal processors (DSPs). This manual can also be used as a reference guide for developing hardware and/or software applications.

How to Use This Manual

The following table summarizes the C5x information contained in this users guide:
If you are looking for information about: Addressing modes Assembly language instructions Boot loader Clock generator Control bits CPU Custom ROM from TI Development support information Features Host port interface Input/output ports Interrupts Memory configuration Memory interface On-chip peripherals Opcodes Part order information Turn to: Chapter 5, Addressing Modes Chapter 6, Assembly Language Instructions Chapter 8, Memory Chapter 9, On-Chip Peripherals Chapter 4, Program Control Chapter 3, Central Processing Unit (CPU) Appendix F, Submitting ROM Codes to TI Appendix G, Development Support and Part Order Information Chapter 1, Introduction Chapter 2, Architectural Overview Chapter 9, On-Chip Peripherals Chapter 8, Memory Chapter 4, Program Control Chapter 8, Memory Chapter 8, Memory Chapter 9, On-Chip Peripherals Chapter 6, Assembly Language Instructions Appendix G, Development Support and Part Order Information

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Notational Conventions / Notational Conventions How to Use This Manual

If you are looking for information about: Pinouts Pipeline operation Program control Serial ports Status registers Timer Upgrading from a C25 Wait-state generators XDS510 Emulator

Turn to: Appendix A, Pinouts and Signal Descriptions Chapter 7, Pipeline Chapter 4, Program Control Chapter 9, On-Chip Peripherals Chapter 4, Program Control Chapter 9, On-Chip Peripherals Appendix C, System Migration Chapter 9, On-Chip Peripherals Appendix D, Design Considerations for Using XDS510 Emulator

Notational Conventions
This document uses the following conventions.
- Program listings, program examples, and interactive displays are shown

in a special typeface similar to a typewriters. Examples use a bold version of the special typeface for emphasis; interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays (such as prompts, command output, error messages, etc.). Here is a sample program listing:
0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .even 1, 2 3, 4 6, 3

Here is an example of a system prompt and a command that you might enter:
C: csr a /user/ti/simuboard/utilities

- In syntax descriptions, the instruction, command, or directive is in a bold

typeface font and parameters are in an italic typeface. Portions of a syntax that are in bold should be entered as shown; portions of a syntax that are in italics describe the type of information that should be entered. Here is an example of a directive syntax: .asect section name, address .asect is the directive. This directive has two parameters, indicated by section name and address. When you use .asect, the first parameter must be
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Notational Conventions

an actual section name, enclosed in double quotes; the second parameter must be an address.
- Square brackets ( [ and ] ) identify an optional parameter. If you use an

optional parameter, you specify the information within the brackets; you dont enter the brackets themselves. Heres an example of an instruction that has an optional parameter: LALK 16bit constant [, shift] The LALK instruction has two parameters. The first parameter, 16-bit constant, is required. The second parameter, shift, is optional. As this syntax shows, if you use the optional second parameter, you must precede it with a comma. Square brackets are also used as part of the pathname specification for VMS pathnames; in this case, the brackets are actually part of the pathname (they are not optional).
- Braces ( { and } ) indicate a list. The symbol | (read as or) separates items

within the list. Heres an example of a list: { * | *+ | * } This provides three choices: *, *+, or *. Unless the list is enclosed in square brackets, you must choose one item from the list.
- Some directives can have a varying number of parameters. For example,

the .byte directive can have up to 100 parameters. The syntax for this directive is: .byte value1 [, ... , valuen ] This syntax shows that .byte must have at least one value parameter, but you have the option of supplying additional value parameters, separated by commas.

Read This First

Information About Cautions and Warnings / Related Documentaiton From Texas Instruments Information About Cautions and Warnings

Information About Cautions and Warnings

This book may contain cautions and warnings.

This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.

The information in a caution is provided for your protection. Please read each caution and warning carefully.

Related Documentation From Texas Instruments

The following books describe the C5x and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 4778924. When ordering, please identify the book by its title and literature number.

TMS320C5x General-Purpose Applications Users Guide (literature number SPRU164) serves as a reference book for developing hardware and/ or software applications for the C5x generation of devices. TMS320C5x, TMS320LC5x Digital Signal Processors (literature number SPRS030) data sheet contains the electrical and timing specifications for these devices, as well as signal descriptions and pinouts for all of the available packages. TMS320C1x/C2x/C2xx/C5x Code Generation Tools Getting Started Guide (literature number SPRU121) describes how to install the TMS320C1x, TMS320C2x, TMS320C2xx, and TMS320C5x assembly language tools and the C compiler for the C1x, C2x, C2xx, and C5x devices. The installation for MS-DOS, OS/2, SunOS, and Solaris systems is covered. TMS320C1x/C2x/C2xx/C5x Assembly Language Tools Users Guide (literature number SPRU018) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the C1x, C2x, C2xx, and C5x generations of devices.
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Related Documentation From Texas Instruments

TMS320C2x/C2xx/C5x Optimizing C Compiler Users Guide (literature number SPRU024) describes the C2x/C2xx/C5x C compiler. This C compiler accepts ANSI standard C source code and produces TMS320 assembly language source code for the C2x, C2xx, and C5x generations of devices. TMS320C5x C Source Debugger Users Guide (literature number SPRU055) tells you how to invoke the C5x emulator, evaluation module, and simulator versions of the C source debugger interface. This book discusses various aspects of the debugger interface, including window management, command entry, code execution, data management, and breakpoints. It also includes a tutorial that introduces basic debugger functionality. TMS320C5x Evaluation Module Technical Reference (literature number SPRU087) describes the C5x evaluation module, its features, design details and external interfaces. TMS320C5x Evaluation Module Getting Started Guide (literature number SPRU126) tells you how to install the MS-DOS, PC-DOS, and Windows versions of the C5x evaluation module. TMS320C54x Simulator Getting Started Guide (literature number SPRU137) describes how to install the TMS320C54x simulator and the C source debugger for the C54x. The installation for Windows 3.1, SunOS, and HP-UX systems is covered. XDS51x Emulator Installation Guide (literature number SPNU070) describes the installation of the XDS510, XDS510PP, and XDS510WS emulator controllers. The installation of the XDS511 emulator is also described. JTAG/MPSD Emulation Technical Reference (literature number SPDU079) provides the design requirements of the XDS510 emulator controller, discusses JTAG designs (based on the IEEE 1149.1 standard), and modular port scan device (MPSD) designs. TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over 100 third parties that provide various products that serve the family of TMS320 digital signal processors. A myriad of products and applications are offeredsoftware and hardware development tools, speech recognition, image processing, noise cancellation, modems, etc.
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Technical Articles Related Documentation From Texas Instruments / Technical Articles

TMS320 DSP Development Support Reference Guide (literature number SPRU011) describes the TMS320 family of digital signal processors and the tools that support these devices. Included are code-generation tools (compilers, assemblers, linkers, etc.) and system integration and debug tools (simulators, emulators, evaluation modules, etc.). Also covered are available documentation, seminars, the university program, and factory repair and exchange.
If you are an assembly language programmer and would like more information about C or C expressions, you may find this book useful:

The C Programming Language (second edition, 1988), by Brian W. Kernighan and Dennis M. Ritchie, published by Prentice-Hall, Englewood Cliffs, New Jersey.

Technical Articles
A wide variety of related documentation is available on digital signal processing. These references fall into one of the following application categories:
-

General-Purpose DSP Graphics/Imagery Speech/Voice Control Multimedia Military Telecommunications Automotive Consumer Medical Development Support

In the following list, references appear in alphabetical order according to author. The documents contain beneficial information regarding designs, operations, and applications for signal-processing systems; all of the documents provide additional references. Texas Instruments strongly suggests that you refer to these publications.

General-Purpose DSP:
1) Antoniou, A., Digital Filters: Analysis and Design, New York, NY: McGrawHill Company, Inc., 1979. 2) Brigham, E.O., The Fast Fourier Transform, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1974.
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Technical Articles

3) Burrus, C.S., and T.W. Parks, DFT/FFT and Convolution Algorithms, New York, NY: John Wiley and Sons, Inc., 1984. 4) Chassaing, R., Horning, D.W., Digital Signal Processing with Fixed and Floating-Point Processors. CoED, USA, Volume 1, Number 1, pages 14, March 1991. 5) Defatta, David J., Joseph G. Lucas, and William S. Hodgkiss, Digital Signal Processing: A System Design Approach, New York: John Wiley, 1988. 6) Erskine, C., and S. Magar, Architecture and Applications of a SecondGeneration Digital Signal Processor. Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, USA, 1985. 7) Essig, D., C. Erskine, E. Caudel, and S. Magar, A Second-Generation Digital Signal Processor. IEEE Journal of Solid-State Circuits, USA, Volume SC21, Number 1, pages 8691, February 1986. 8) Frantz, G., K. Lin, J. Reimer, and J. Bradley, The Texas Instruments TMS320C25 Digital Signal Microcomputer. IEEE Microelectronics, USA, Volume 6, Number 6, pages 1028, December 1986. 9) Gass, W., R. Tarrant, T. Richard, B. Pawate, M. Gammel, P. Rajasekaran, R. Wiggins, and C. Covington, Multiple Digital Signal Processor Environment for Intelligent Signal Processing. Proceedings of the IEEE, USA, Volume 75, Number 9, pages 12461259, September 1987. 10) Gold, Bernard, and C.M. Rader, Digital Processing of Signals, New York, NY: McGraw-Hill Company, Inc., 1969. 11) Hamming, R.W., Digital Filters, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1977. 12) IEEE ASSP DSP Committee (Editor), Programs for Digital Signal Processing, New York, NY: IEEE Press, 1979. 13) Jackson, Leland B., Digital Filters and Signal Processing, Hingham, MA: Kluwer Academic Publishers, 1986. 14) Jones, D.L., and T.W. Parks, A Digital Signal Processing Laboratory Using the TMS32010, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 15) Lim, Jae, and Alan V. Oppenheim, Advanced Topics in Signal Processing, Englewood Cliffs, NJ: Prentice- Hall, Inc., 1988. 16) Lin, K., G. Frantz, and R. Simar, Jr., The TMS320 Family of Digital Signal Processors. Proceedings of the IEEE, USA, Volume 75, Number 9, pages 11431159, September 1987.
Read This First
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Technical Articles

17) Lovrich, A., Reimer, J., An Advanced Audio Signal Processor. Digest of Technical Papers for 1991 International Conference on Consumer Electronics, June 1991. 18) Magar, S., D. Essig, E. Caudel, S. Marshall and R. Peters, An NMOS Digital Signal Processor with Multiprocessing Capability. Digest of IEEE International Solid-State Circuits Conference, USA, February 1985. 19) Morris, Robert L., Digital Signal Processing Software, Ottawa, Canada: Carleton University, 1983. 20) Oppenheim, Alan V. (Editor), Applications of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978. 21) Oppenheim, Alan V., and R.W. Schafer, Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975 and 1988. 22) Oppenheim, A.V., A.N. Willsky, and I.T. Young, Signals and Systems, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983. 23) Papamichalis, P.E., and C.S. Burrus, Conversion of Digit-Reversed to BitReversed Order in FFT Algorithms. Proceedings of ICASSP 89, USA, pages 984987, May 1989. 24) Papamichalis, P., and R. Simar, Jr., The TMS320C30 Floating-Point Digital Signal Processor. IEEE Micro Magazine, USA, pages 1329, December 1988. 25) Parks, T.W., and C.S. Burrus, Digital Filter Design, New York, NY: John Wiley and Sons, Inc., 1987. 26) Peterson, C., Zervakis, M., Shehadeh, N., Adaptive Filter Design and Implementation Using the TMS320C25 Microprocessor. Computers in Education Journal, USA, Volume 3, Number 3, pages 1216, July September 1993. 27) Prado, J., and R. Alcantara, A Fast Square-Rooting Algorithm Using a Digital Signal Processor. Proceedings of IEEE, USA, Volume 75, Number 2, pages 262264, February 1987. 28) Rabiner, L.R. and B. Gold, Theory and Applications of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975. 29) Simar, Jr., R., and A. Davis, The Application of High-Level Languages to Single-Chip Digital Signal Processors. Proceedings of ICASSP 88, USA, Volume D, page 1678, April 1988. 30) Simar, Jr., R., T. Leigh, P. Koeppen, J. Leach, J. Potts, and D. Blalock, A 40 MFLOPS Digital Signal Processor: the First Supercomputer on a Chip. Proceedings of ICASSP 87, USA, Catalog Number 87CH2396 0, Volume 1, pages 535538, April 1987.
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Technical Articles

31) Simar, Jr., R., and J. Reimer, The TMS320C25: a 100 ns CMOS VLSI Digital Signal Processor. 1986 Workshop on Applications of Signal Processing to Audio and Acoustics, September 1986. 32) Texas Instruments, Digital Signal Processing Applications with the TMS320 Family, 1986; Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 33) Treichler, J.R., C.R. Johnson, Jr., and M.G. Larimore, A Practical Guide to Adaptive Filter Design, New York, NY: John Wiley and Sons, Inc., 1987.

Graphics/Imagery:
1) Andrews, H.C., and B.R. Hunt, Digital Image Restoration, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1977. 2) Gonzales, Rafael C., and Paul Wintz, Digital Image Processing, Reading, MA: Addison-Wesley Publishing Company, Inc., 1977. 3) Papamichalis, P.E., FFT Implementation on the TMS320C30. Proceedings of ICASSP 88, USA, Volume D, page 1399, April 1988. 4) Pratt, William K., Digital Image Processing, New York, NY: John Wiley and Sons, 1978. 5) Reimer, J., and A. Lovrich, Graphics with the TMS32020. WESCON/85 Conference Record, USA, 1985.

Speech/Voice:
1) DellaMorte, J., and P. Papamichalis, Full-Duplex Real-Time Implementation of the FED-STD-1015 LPC-10e Standard V.52 on the TMS320C25. Proceedings of SPEECH TECH 89, pages 218221, May 1989. 2) Frantz, G.A., and K.S. Lin, A Low-Cost Speech System Using the TMS320C17. Proceedings of SPEECH TECH 87, pages 2529, April 1987. 3) Gray, A.H., and J.D. Markel, Linear Prediction of Speech, New York, NY: Springer-Verlag, 1976. 4) Jayant, N.S., and Peter Noll, Digital Coding of Waveforms, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984. 5) Papamichalis, Panos, Practical Approaches to Speech Coding, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 6) Papamichalis, P., and D. Lively, Implementation of the DOD Standard LPC10/52E on the TMS320C25. Proceedings of SPEECH TECH 87, pages 201204, April 1987. 7) Pawate, B.I., and G.R. Doddington, Implementation of a Hidden Markov Model-Based Layered Grammar Recognizer. Proceedings of ICASSP 89, USA, pages 801 804, May 1989.
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Technical Articles

8) Rabiner, L.R., and R.W. Schafer, Digital Processing of Speech Signals, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978. 9) Reimer, J.B. and K.S. Lin, TMS320 Digital Signal Processors in Speech Applications. Proceedings of SPEECH TECH 88, April 1988. 10) Reimer, J.B., M.L. McMahan, and W.W. Anderson, Speech Recognition for a Low-Cost System Using a DSP. Digest of Technical Papers for 1987 International Conference on Consumer Electronics, June 1987.

Control:
1) Ahmed, I., 16-Bit DSP Microcontroller Fits Motion Control System Application. PCIM, October 1988. 2) Ahmed, I., Implementation of Self Tuning Regulators with TMS320 Family of Digital Signal Processors. MOTORCON 88, pages 248262, September 1988. 3) Ahmed, I., and S. Lindquist, Digital Signal Processors: Simplifying HighPerformance Control. Machine Design, September 1987. 4) Ahmed, I., and S. Meshkat, Using DSPs in Control. Control Engineering, February 1988. 5) Allen, C. and P. Pillay, TMS320 Design for Vector and Current Control of AC Motor Drives. Electronics Letters, UK, Volume 28, Number 23, pages 21882190, November 1992. 6) Bose, B.K., and P.M. Szczesny, A Microcomputer-Based Control and Simulation of an Advanced IPM Synchronous Machine Drive System for Electric Vehicle Propulsion. Proceedings of IECON 87, Volume 1, pages 454463, November 1987. 7) Hanselman, H., LQG-Control of a Highly Resonant Disc Drive Head Positioning Actuator. IEEE Transactions on Industrial Electronics, USA, Volume 35, Number 1, pages 100104, February 1988. 8) Jacquot, R., Modern Digital Control Systems, New York, NY: Marcel Dekker, Inc., 1981. 9) Katz, P., Digital Control Using Microprocessors, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1981. 10) Kuo, B.C., Digital Control Systems, New York, NY: Holt, Reinholt, and Winston, Inc., 1980. 11) Lovrich, A., G. Troullinos, and R. Chirayil, An All-Digital Automatic Gain Control. Proceedings of ICASSP 88, USA, Volume D, page 1734, April 1988.
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12) Matsui, N. and M. Shigyo, Brushless DC Motor Control Without Position and Speed Sensors. IEEE Transactions on Industry Applications, USA, Volume 28, Number 1, Part 1, pages 120127, JanuaryFebruary 1992. 13) Meshkat, S., and I. Ahmed, Using DSPs in AC Induction Motor Drives. Control Engineering, February 1988. 14) Panahi, I. and R. Restle, DSPs Redefine Motion Control. Motion Control Magazine, December 1993. 15) Phillips, C., and H. Nagle, Digital Control System Analysis and Design, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984.

Multimedia:
1) Reimer, J., DSP-Based Multimedia Solutions Lead Way Enhancing Audio Compression Performance. Dr. Dobbs Journal, December 1993. 2) Reimer, J., G. Benbassat, and W. Bonneau Jr., Application Processors: Making PC Multimedia Happen. Silicon Valley PC Design Conference, July 1991.

Military:
1) Papamichalis, P., and J. Reimer, Implementation of the Data Encryption Standard Using the TMS32010. Digital Signal Processing Applications, 1986.

Telecommunications:
1) Ahmed, I., and A. Lovrich, Adaptive Line Enhancer Using the TMS320C25. Conference Records of Northcon/86, USA, 14/3/110, September/October 1986. 2) Casale, S., R. Russo, and G. Bellina, Optimal Architectural Solution Using DSP Processors for the Implementation of an ADPCM Transcoder. Proceedings of GLOBECOM 89, pages 12671273, November 1989. 3) Cole, C., A. Haoui, and P. Winship, A High-Performance Digital Voice Echo Canceller on a SINGLE TMS32020. Proceedings of ICASSP 86, USA, Catalog Number 86CH22434, Volume 1, pages 429432, April 1986. 4) Cole, C., A. Haoui, and P. Winship, A High-Performance Digital Voice Echo Canceller on a Single TMS32020. Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing, USA, 1986. 5) Lovrich, A., and J. Reimer, A Multi-Rate Transcoder. Transactions on Consumer Electronics, USA, November 1989.
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6) Lovrich, A. and J. Reimer, A Multi-Rate Transcoder. Digest of Technical Papers for 1989 International Conference on Consumer Electronics, June 79, 1989. 7) Lu, H., D. Hedberg, and B. Fraenkel, Implementation of High-Speed Voiceband Data Modems Using the TMS320C25. Proceedings of ICASSP 87, USA, Catalog Number 87CH23960, Volume 4, pages 19151918, April 1987. 8) Mock, P., Add DTMF Generation and Decoding to DSP P Designs. Electronic Design, USA, Volume 30, Number 6, pages 205213, March 1985. 9) Reimer, J., M. McMahan, and M. Arjmand, ADPCM on a TMS320 DSP Chip. Proceedings of SPEECH TECH 85, pages 246249, April 1985. 10) Troullinos, G., and J. Bradley, Split-Band Modem Implementation Using the TMS32010 Digital Signal Processor. Conference Records of Electro/86 and Mini/Micro Northeast, USA, 14/1/121, May 1986.

Automotive:
1) Lin, K., Trends of Digital Signal Processing in Automotive. International Congress on Transportation Electronic (CONVERGENCE 88), October 1988.

Consumer:
1) Frantz, G.A., J.B. Reimer, and R.A. Wotiz, Julie, The Application of DSP to a Product. Speech Tech Magazine, USA, September 1988. 2) Reimer, J.B., and G.A. Frantz, Customization of a DSP Integrated Circuit for a Customer Product. Transactions on Consumer Electronics, USA, August 1988. 3) Reimer, J.B., P.E. Nixon, E.B. Boles, and G.A. Frantz, Audio Customization of a DSP IC. Digest of Technical Papers for 1988 International Conference on Consumer Electronics, June 810 1988.

Medical:
1) Knapp and Townshend, A Real-Time Digital Signal Processing System for an Auditory Prosthesis. Proceedings of ICASSP 88, USA, Volume A, page 2493, April 1988. 2) Morris, L.R., and P.B. Barszczewski, Design and Evolution of a PocketSized DSP Speech Processing System for a Cochlear Implant and Other Hearing Prosthesis Applications. Proceedings of ICASSP 88, USA, Volume A, page 2516, April 1988.
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Technical Articles Technical Articles / Trademarks

Development Support:
1) Mersereau, R., R. Schafer, T. Barnwell, and D. Smith, A Digital Filter Design Package for PCs and TMS320. MIDCON/84 Electronic Show and Convention, USA, 1984. 2) Simar, Jr., R., and A. Davis, The Application of High-Level Languages to Single-Chip Digital Signal Processors. Proceedings of ICASSP 88, USA, Volume 3, pages 16781681, April 1988.

Trademarks
DuPont Electronics is a registered trademark of E.I. DuPont Corporation. HP-UX is a trademark of Hewlett-Packard Company. IBM, OS/2, and PC-DOS are trademarks of International Business Machines Corporation. MS and Windows are registered trademarks of Microsoft Corporation. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SPARC is a trademark of SPARC International, Inc., but licensed exclusively to Sun Microsystems, Inc. 320 Hotline On-line, TI, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated. VAX and VMS are trademarks of Digital Equipment Corp.

Read This First

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If You Need Assistance

If You Need Assistance . . .

-

World-Wide Web Sites

TI Online Semiconductor Product Information Center (PIC) DSP Solutions 320 Hotline On-linet http://www.ti.com http://www.ti.com/sc/docs/pic/home.htm http://www.ti.com/dsps http://www.ti.com/sc/docs/dsps/support.htm

North America, South America, Central America

Product Information Center (PIC) (972) 644-5580 TI Literature Response Center U.S.A. (800) 477-8924 Software Registration/Upgrades (214) 638-0333 Fax: (214) 638-7742 U.S.A. Factory Repair/Hardware Upgrades (281) 274-2285 U.S. Technical Training Organization (972) 644-5580 DSP Hotline (281) 274-2320 Fax: (281) 274-2324 DSP Modem BBS (281) 274-2323 DSP Internet BBS via anonymous ftp to ftp://ftp.ti.com/pub/tms320bbs

Email: dsph@ti.com

Europe, Middle East, Africa

European Product Information Center (EPIC) Hotlines: Multi-Language Support +33 1 30 70 11 69 Email: epic@ti.com Deutsch +49 8161 80 33 11 or +33 1 30 70 11 68 English +33 1 30 70 11 65 Francais +33 1 30 70 11 64 Italiano +33 1 30 70 11 67 EPIC Modem BBS +33 1 30 70 11 99 European Factory Repair +33 4 93 22 25 40 Europe Customer Training Helpline Fax: +33 1 30 70 10 32

Fax: +49 81 61 80 40 10

Asia-Pacific
Literature Response Center +852 2 956 7288 Fax: +852 2 956 2200 Hong Kong DSP Hotline +852 2 956 7268 Fax: +852 2 956 1002 Korea DSP Hotline +82 2 551 2804 Fax: +82 2 551 2828 Korea DSP Modem BBS +82 2 551 2914 Singapore DSP Hotline Fax: +65 390 7179 Taiwan DSP Hotline +886 2 377 1450 Fax: +886 2 377 2718 Taiwan DSP Modem BBS +886 2 376 2592 Taiwan DSP Internet BBS via anonymous ftp to ftp://dsp.ee.tit.edu.tw/pub/TI/

Japan
Product Information Center +0120-81-0026 (in Japan) +03-3457-0972 or (INTL) 813-3457-0972 DSP Hotline +03-3769-8735 or (INTL) 813-3769-8735 DSP BBS via Nifty-Serve Type Go TIASP Fax: +0120-81-0036 (in Japan) Fax: +03-3457-1259 or (INTL) 813-3457-1259 Fax: +03-3457-7071 or (INTL) 813-3457-7071

Documentation
When making suggestions or reporting errors in documentation, please include the following information that is on the title page: the full title of the book, the publication date, and the literature number. Mail: Texas Instruments Incorporated Email: dsph@ti.com Technical Documentation Services, MS 702 P.O. Box 1443 Houston, Texas 77251-1443

Note:

When calling a Literature Response Center to order documentation, please specify the literature number of the book.

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Contents

Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 Summarizes the features of the TMS320 family of products and presents typical applications. Describes the TMS320C5x DSP and lists its key features. 1.1 TMS320 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 History, Development, and Advantages of TMS320 DSPs . . . . . . . . . . . . . . . . . 1.1.2 TMS320 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C5x Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C5x Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 2 2 4 5 7

1.2 1.3 2

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 Summarizes the TMS320C5x architecture. Provides general information about the bus structure, CPU, internal memory organization, on-chip peripherals, and scanning logic. 2.1 2.2 Bus Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 2.2.1 Central Arithmetic Logic Unit (CALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 2.2.2 Parallel Logic Unit (PLU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 2.2.3 Auxiliary Register Arithmetic Unit (ARAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 2.2.4 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 2.2.5 Program Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2.3.1 Program ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2.3.2 Data/Program Dual-Access RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2.3.3 Data/Program Single-Access RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 2.3.4 On-Chip Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 2.4.1 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 2.4.2 Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 2.4.3 Software-Programmable Wait-State Generators . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 2.4.4 Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 2.4.5 Host Port Interface (HPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 2.4.6 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 10 2.4.7 Buffered Serial Port (BSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 10 2.4.8 TDM Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 10 2.4.9 User-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 10 Test/Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 11
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Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 Describes the TMS320C5x CPU operations. Includes information about the central arithmetic logic unit, the parallel logic unit, and the auxiliary register arithmetic unit. Also provides a summary of registers. 3.1 3.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Central Arithmetic Logic Unit (CALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 3.2.1 Multiplier, Product Register (PREG), and Temporary Register 0 (TREG0) . . . 3 7 3.2.2 Arithmetic Logic Unit (ALU) and Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . 3 11 3.2.3 Scaling Shifters and Temporary Register 1 (TREG1) . . . . . . . . . . . . . . . . . . . . 3 14 Parallel Logic Unit (PLU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 15 Auxiliary Register Arithmetic Unit (ARAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 17 Summary of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 21 3.5.1 Auxiliary Registers (AR0AR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 21 3.5.2 Auxiliary Register Compare Register (ARCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 3 21 3.5.3 Block Move Address Register (BMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 21 3.5.4 Block Repeat Registers (RPTC, BRCR, PASR, PAER) . . . . . . . . . . . . . . . . . . 3 21 3.5.5 Buffered Serial Port Registers (ARR, AXR, BKR, BKX, SPCE) . . . . . . . . . . . . 3 22 3.5.6 Circular Buffer Registers (CBSR1, CBER1, CBSR2, CBER2, CBCR) . . . . . . 3 22 3.5.7 Dynamic Bit Manipulation Register (DBMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 22 3.5.8 Global Memory Allocation Register (GREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 23 3.5.9 Host Port Interface Registers (HPIC, HPIA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 23 3.5.10 Index Register (INDX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 23 3.5.11 I/O Space (PA0PA15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 23 3.5.12 Instruction Register (IREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 23 3.5.13 Interrupt Registers (IMR, IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 23 3.5.14 Processor Mode Status Register (PMST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 24 3.5.15 Product Register (PREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 24 3.5.16 Serial Port Interface Registers (SPC, DRR, DXR, XSR, RSR) . . . . . . . . . . . . 3 24 3.5.17 Software-Programmable Wait-State Registers (PDWSR, IOWSR, CWSR) . 3 24 3.5.18 Status Registers (ST0, ST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 25 3.5.19 Temporary Registers (TREG0, TREG1, TREG2) . . . . . . . . . . . . . . . . . . . . . . . . 3 25 3.5.20 Timer Registers (TIM, PRD, TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 25 3.5.21 TDM Serial Port Registers (TRCV, TDXR, TSPC, TCSR, TRTA, TRAD, TRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 25

3.3 3.4 3.5

Program Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 Describes the TMS320C5x program control mechanisms. Includes information about the program counter, the hardware stack, address generation, status and control registers, interrupts, reset, and power-down modes. 4.1 4.2 4.3 4.4 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program-Memory Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Circular Buffer Control Register (CBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 4 4 4 2 4 5 6 6

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4.6 4.7

4.8

4.9 4.10

4.4.2 Processor Mode Status Register (PMST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 4.4.3 Status Registers (ST0 and ST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10 Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 17 4.5.1 Conditional Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 17 4.5.2 Conditional Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 18 4.5.3 Conditional Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 18 4.5.4 Multiconditional Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 18 4.5.5 Delayed Conditional Branches, Calls, and Returns . . . . . . . . . . . . . . . . . . . . . . 4 19 4.5.6 Conditional Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 20 Single Instruction Repeat Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 22 Block Repeat Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 31 4.7.1 Context Save and Restore Used With Block Repeat . . . . . . . . . . . . . . . . . . . . 4 32 4.7.2 Interrupt Operation in a Block Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 34 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 36 4.8.1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 36 4.8.2 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 38 4.8.3 Interrupt Flag Register (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 39 4.8.4 Interrupt Mask Register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 40 4.8.5 Interrupt Mode (INTM) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 40 4.8.6 Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 41 4.8.7 Software-Initiated Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 41 4.8.8 Interrupt Context Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 42 4.8.9 Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 43 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 45 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 50 4.10.1 IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 50 4.10.2 IDLE2 Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 50 4.10.3 Power Down Using HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 51

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 Describes the basic addressing modes of the TMS320C5x 5.1 5.2 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 5.2.1 Indirect Addressing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5.2.2 Indirect Addressing Opcode Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 5.2.3 Bit-Reversed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 12 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 14 5.3.1 Short Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 14 5.3.2 Long Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 15 Dedicated-Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 17 5.4.1 Using the Contents of the BMAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 17 5.4.2 Using the Contents of the DBMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 18 Memory-Mapped Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 19 Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 21
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Assembly Language Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 Lists and defines the symbols and abbreviations used in the instruction set summary and in the individual instruction descriptions. Provides a summary of the instruction set divided into seven basic types of operation. Also provides an example description of an instruction and describes the TMS320C5x assembly language instructions individually. 6.1 Instruction Set Symbols and Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 6.1.1 Symbols and Abbreviations Used in the Instruction Set Opcodes . . . . . . . . . . 6 2 6.1.2 Symbols and Abbreviations Used in the Instruction Set Descriptions . . . . . . . 6 4 6.1.3 Notations Used in the Instruction Set Descriptions . . . . . . . . . . . . . . . . . . . . . . . 6 6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Instruction Set Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 22

6.2 6.3 7

Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 Describes the TMS320C5x pipeline operation and lists the pipeline latency cycles for these types of latencies 7.1 7.2 Pipeline Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 7.2.1 Normal Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 7.2.2 Pipeline Operation on Branch and Subroutine Call . . . . . . . . . . . . . . . . . . . . . . . 7 6 7.2.3 Pipeline Operation on ARAU Memory-Mapped Registers . . . . . . . . . . . . . . . . 7 14 7.2.4 Pipeline Operation on External Memory Conflict . . . . . . . . . . . . . . . . . . . . . . . . 7 21 Pipeline Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 24

7.3 8

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 Describes the TMS320C5x memory configuration and operation. Includes memory maps and descriptions of program memory, data memory, and I/O space. Also includes descriptions of direct memory access (DMA), memory management, and available bootloader options. 8.1 8.2 Memory Space Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 8.2.1 Program Memory Configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 8.2.2 Program Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 11 8.2.3 Program Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 8.2.4 Program Memory Protection Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 14 Local Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 15 8.3.1 Local Data Memory Configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 15 8.3.2 Local Data Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 17 8.3.3 Local Data Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 19 Global Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 20 8.4.1 Global Data Memory Configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 20 8.4.2 Global Data Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 20 Input/Output (I/O) Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 22 8.5.1 Addressing I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 22 Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 23 8.6.1 DMA in a Master-Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 23

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8.9 8.10 9

8.6.2 External DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7.1 Memory-to-Memory Moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7.2 Memory Block Moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.1 HPI Boot Mode (C57 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.2 Serial Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.3 Parallel EPROM Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.4 Parallel I/O Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.5 Warm Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Parallel Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Wait-State Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 8 8 8 8 8 8 8 8 8 8 8

24 26 26 27 32 33 34 35 37 37 39 42

On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 Describes the TMS320C5x on-chip peripherals and how to control them. Includes information about the clock generator, timer, wait-state generators, general-purpose I/O pins, parallel I/O ports, standard serial port interface, buffered serial port interface, time-division multiplexed serial port interface, and host port interface. 9.1 Peripheral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 9.1.1 Memory-Mapped Peripheral Registers and I/O Ports . . . . . . . . . . . . . . . . . . . . . 9 2 9.1.2 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 9.1.3 Peripheral Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 9.2.1 Standard Clock Options (C50, C51, C52, C53, and C53S only) . . . . . . . . . . 9 7 9.2.2 PLL Clock Options (LC56, C57S, and LC57 only) . . . . . . . . . . . . . . . . . . . . . . 9 8 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 9.3.1 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 9.3.2 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 11 Software-Programmable Wait-State Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 9.4.1 Program/Data Wait-State Register (PDWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 9.4.2 I/O Wait-State Register (IOWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 16 9.4.3 Wait-State Control Register (CWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 17 9.4.4 Logic for External Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 19 General-Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 20 9.5.1 Branch Control Input (BIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 20 9.5.2 External Flag Output (XF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 21 Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 22 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 23 9.7.1 Serial Port Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 24 9.7.2 Serial Port Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 25 9.7.3 Setting the Serial Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 27 9.7.4 Burst Mode Transmit and Receive Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 9 37 9.7.5 Continuous Mode Transmit and Receive Operations . . . . . . . . . . . . . . . . . . . . 9 44 9.7.6 Serial Port Interface Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 46
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9.7.7 Example of Serial Port Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 50 Buffered Serial Port (BSP) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 53 9.8.1 BSP Operation in Standard Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 55 9.8.2 Autobuffering Unit (ABU) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 60 9.8.3 System Considerations of BSP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 69 9.8.4 BSP Operation in Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 73 Time-Division Multiplexed (TDM) Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 9 74 9.9.1 Basic Time-Division Multiplexed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 74 9.9.2 TDM Serial Port Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 74 9.9.3 TDM Serial Port Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 76 9.9.4 TDM Mode Transmit and Receive Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 9 80 9.9.5 TDM Serial Port Interface Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . 9 82 9.9.6 Examples of TDM Serial Port Interface Operation . . . . . . . . . . . . . . . . . . . . . . . 9 82 Host Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 87 9.10.1 Basic Host Port Interface Functional Description . . . . . . . . . . . . . . . . . . . . . . . . 9 88 9.10.2 Details of Host Port Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 91 9.10.3 Host Read/Write Access to HPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 97 9.10.4 DSPINT and HINT Function Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 101 9.10.5 Considerations in Changing HPI Memory Access Mode (SAM/HOM) and IDLE2 Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 102 9.10.6 Access of HPI Memory During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 103

Pinouts and Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 1 Provides pinouts and signal descriptions for the TMS320C5x devices A.1 A.2 A.3 A.4 A.5 A.6 A.7 100-Pin QFP Pinout (C52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 2 100-Pin TQFP Pinout (C51, C52, C53S, and LC56) . . . . . . . . . . . . . . . . . . . . . . . . . . . A 4 128-Pin TQFP Pinout (LC57) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 6 132-Pin BQFP Pinout (C50, C51, and C53) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 8 144-Pin TQFP Pinout (C57S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 10 100-Pin TQFP Device-Specific Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 12 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 13

Instruction Classes and Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B 1 Describes the classes and lists the cycles of the instruction set B.1 B.2 Cycle Class-to-Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B 2 Instruction Set-to-Cycle Class Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B 5

System Migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 1 Provides information that is necessary to upgrade a TMS320C2x system into a TMS320C5x system. Consists of a detailed list of the programming differences and hardware and timing differences between the two generations of TMS320 DSPs. C.1 C.2 Package and Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 8 C.2.1 Device Clock Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 8

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C.2.2 Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 8 C.2.3 External Memory Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 8 C.2.4 Execution Cycle Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 9 On-Chip Peripheral Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 11 C2x-to-C5x Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 12 C.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 12 C.4.2 Serial Port Control Bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 13 C.4.3 C2x-to-C5x Instruction Set Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 13

Design Considerations for Using XDS510 Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 1 Describes the JTAG emulator cable and how to construct a 14-pin connector on your target system and how to connect the target system to the emulator D.1 D.2 D.3 D.4 D.5 D.6 D.7 Cable Header and Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 2 Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 3 Emulator Cable Pod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 4 Emulator Cable Pod Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 6 Target System Test Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 7 Configuring Multiple Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 8 Connections Between the Emulator and the Target System . . . . . . . . . . . . . . . . . . . . . . D 9 D.7.1 Emulation Signals Not Buffered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 9 D.7.2 Emulation Signals Buffered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 10 Emulation Timing Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 11

D.8 E

Memories, Sockets, and Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E 1 Provides product information regarding memories and sockets that are manufactured by Texas Instruments and are compatible with the TMS320C5x E.1 E.2 E.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E 2 Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E 2 Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E 3

Submitting ROM Codes to TI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F 1 Provides information for submitting ROM codes to Texas Instruments F.1 F.2 F.3 Single-Chip Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F 2 TMS320 Development Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F 3 Submitting TMS320 ROM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F 4

Development Support and Part Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G 1 Provides device part numbers and support tool ordering information for the TMS320C5x and development support information available from TI and third-party vendors G.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.1.1 Software and Hardware Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.1.2 Third-Party Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.1.3 Technical Training Organization (TTO) TMS320 Workshops . . . . . . . . . . . . . . . G.1.4 Assistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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G.2

G.3

Part Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.2.1 Device and Development Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . G.2.2 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.2.3 Development Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hewlett-Packard E2442A Preprocessor C5x Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . G.3.1 Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.3.2 Logic Analyzers Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.3.3 Pods Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.3.4 Termination Adapters (TAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.3.5 Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G G G G G G G G G G

4 4 5 6 8 8 8 9 9 9

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H 1 Defines terms and abbreviations used throughout this book Summary of Updates in This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I 1 Provides a summary of the updates in this version of the document

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Figures
11 12 21 31 32 33 34 35 36 41 42 43 44 45 46 47 48 49 410 51 52 53 54 55 56 57 58 59 510 511 71 81 82 83 84 85 Evolution of the TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Typical Applications for the TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 C5x Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Block Diagram of C5x DSP Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . 3 3 Central Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Examples of Carry Bit Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 13 Parallel Logic Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 15 Indirect Auxiliary Register Addressing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 17 Auxiliary Register Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 18 Program Control Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Circular Buffer Control Register (CBCR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Processor Mode Status Register (PMST) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Status Register 0 (ST0) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 11 Status Register 1 (ST1) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 13 Interrupt Vector Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 38 Interrupt Flag Register (IFR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 39 Interrupt Mask Register (IMR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 40 Minimum Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 44 RS and HOLD Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 49 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Indirect Addressing Opcode Format Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Short Immediate Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 14 Long Immediate Addressing Mode No Data Memory Access . . . . . . . . . . . . . . . . . . . . 5 15 Long Immediate Addressing Mode Two Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 16 Dedicated-Register Addressing Using the BMAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 18 Dedicated-Register Addressing Using the DBMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 18 Memory-Mapped Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 19 Memory-Mapped Addressing in the Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . 5 20 Four Level Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 C50 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 C51 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 C52 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 C53 and C53S Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 LC56 and LC57 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6
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86 87 88 89 810 811 812 813 814 815 816 91 92 93 94 95 96 97 98 99 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930
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C57S Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Direct Memory Access Using a Master-Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . 8 23 Boot Routine Selection Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 33 16-Bit Word Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 34 8-Bit Word Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 35 16-Bit Source Address for Parallel EPROM Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 35 Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 37 16-Bit Entry Address for Warm Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 38 External Interface Operation for Read-Read-Write (Zero Wait States) . . . . . . . . . . . . . . . 8 40 External Interface Operation for Write-Write-Read (Zero Wait States) . . . . . . . . . . . . . . . 8 41 External Interface Operation for Read-Write (One Wait State) . . . . . . . . . . . . . . . . . . . . . . 8 41 External Interrupt Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 Timer Control Register (TCR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 Program/Data Wait-State Register (PDWSR) Diagram (C50, C51, and C52 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Program/Data Wait-State Register (PDWSR) Diagram (C53S, LC56, and C57 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 I/O Port Wait-State Register (IOWSR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 16 Wait-State Control Register (CWSR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 17 Software-Programmable Wait-State Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . 9 19 BIO Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 20 XF Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 21 I/O Port Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 22 One-Way Serial Port Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 26 Serial Port Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 27 Serial Port Control Register (SPC) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 28 Receiver Signal MUXes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 32 Burst Mode Serial Port Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 38 Serial Port Transmit With Long FSX Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 39 Burst Mode Serial Port Transmit Operation With Delayed Frame Sync in External Frame Sync Mode (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 40 Burst Mode Serial Port Transmit Operation With Delayed Frame Sync in External Frame Sync Mode (BSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 40 Burst Mode Serial Port Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 41 Burst Mode Serial Port Receive Overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 41 Serial Port Receive With Long FSR pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 42 Burst Mode Serial Port Transmit at Maximum Packet Frequency . . . . . . . . . . . . . . . . . . . 9 43 Burst Mode Serial Port Receive at Maximum Packet-Frequency . . . . . . . . . . . . . . . . . . . . 9 43 Continuous Mode Serial Port Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 45 Continuous Mode Serial Port Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 46 SP Receiver Functional Operation (Burst Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 47 BSP Receiver Functional Operation (Burst Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 47 SP/BSP Transmitter Functional Operation (Burst Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 48 SP/BSP Receiver Functional Operation (Continuous Mode) . . . . . . . . . . . . . . . . . . . . . . . 9 49

Figures

931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 A1 A2 A3 A4 A5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 D6 D7 F1 G1 G2

SP/BSP Transmitter Functional Operation (Continuous Mode) . . . . . . . . . . . . . . . . . . . . . 9 50 BSP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 54 BSP Control Extension Register (SPCE) Diagram Serial Port Control Bits . . . . . . . . . 9 57 Transmit Continuous Mode with External Frame and FIG = 1 (Format is 16 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 60 ABU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 62 BSP Control Extension Register (SPCE) Diagram ABU Control Bits . . . . . . . . . . . . . . 9 63 Circular Addressing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 67 Transmit Buffer and Receive Buffer Mapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 68 Standard Mode BSP Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 70 Autobuffering Mode Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 71 Time-Division Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 74 TDM 4-Wire Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 76 TDM Serial Port Registers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 78 Serial Port Timing (TDM Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 80 Host Port Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 87 Generic System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 89 Select Input Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 93 HPIC Diagram Host Reads from HPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 96 HPIC Diagram Host Writes to HPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 96 HPIC Diagram C5x Reads From HPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 96 HPIC Diagram C5x Writes to HPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 96 HPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 98 Pin/Signal Assignments for the C52 in 100-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 2 Pin/Signal Assignments for the C51, C52, C53S, and LC56 in 100-Pin TQFP . . . . . . . A 4 Pin/Signal Assignments for the LC57 in 128-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 6 Pin/Signal Assignments for the C50, C51, and C53 in 132-Pin BQFP . . . . . . . . . . . . . . . A 8 Pin/Signal Assignments for the C57S in 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . A 10 TMS320C25 in 68-Pin CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 2 TMS320C25 in 68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 3 TMS320C25-to-TMS320C5x Pin/Signal Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 5 TMS320C25 and TMS320C5x Clocking Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 6 TMS320C25 IACK Versus TMS320C5x IACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 7 Header Signals and Header Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 2 Emulator Cable Pod Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 5 Emulator Cable Pod Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 6 Target-System Generated Test Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 7 Multiprocessor Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 8 Emulator Connections Without Signal Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 9 Buffered Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 10 TMS320 ROM Code Submittal Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F 3 TMS320 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G 5 TMS320 Development Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G 6
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Tables

Tables
11 21 22 31 32 41 42 43 44 45 46 47 48 49 410 411 412 413 414 415 416 51 52 53 54 55 61 62 63 64 65 66 67 68 69
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Characteristics of the C5x DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 Number of Serial/Parallel Ports Available in Different C5x Package Types . . . . . . . . . . . . 2 9 IEEE Std.1149.1 (JTAG)/Boundary-Scan Interface Configurations for the C5x . . . . . . . 2 12 C5x CPU Internal Hardware Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Auxiliary Register Arithmetic Unit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 19 Address Loading Into the Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Circular Buffer Control Register (CBCR) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Processor Mode Status Register (PMST) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 On-Chip RAM Configuration Using OVLY and RAM Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10 Status Register 0 (ST0) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 11 Status Register 1 (ST1) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 13 Product Shifter Mode as Determined by PM Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 16 Conditions for Branch, Call, and Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 17 Groups for Multiconditional Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 19 Multi-cycle Instructions Transformed Into Single-Cycle Instructions by the Repeat Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 23 Repeatable Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 24 Instructions Not Meaningful to Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 27 Nonrepeatable Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 29 Interrupt Vector Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 37 CPU Registers Bit Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 46 Peripheral Registers Bit Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 47 Indirect Addressing Opcode Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Indirect Addressing Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Instruction Field Bit Values for Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Bit-Reversed Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 13 Instructions That Support Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 14 Instruction Set Opcode Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Instruction Set Descriptions Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Instruction Set Descriptions Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Accumulator Memory Reference Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 Auxiliary Registers and Data Memory Page Pointer Instructions . . . . . . . . . . . . . . . . . . . . 6 13 Parallel Logic Unit (PLU) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 14 TREG0, PREG, and Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 15 Branch and Call Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 17 I/O and Data Memory Operation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 19

Tables

610 611 71 72 73 74 75 76 77 78 79 710 81 82 83 84 85 86 87 88 89 810 811 812 813 814 815 816 91 92 93 94 95 96 97 98 99 910 911 912 913

Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 20 Address Blocks for On-Chip Single-Access RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 26 Pipeline Operation of 1-Word Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pipeline Operation of 2-Word Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Pipeline Operation with Branch Taken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Pipeline Operation with Branch Not Taken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 Pipeline Operation with Subroutine Call and Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 Pipeline Operation with ARx Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 15 Pipeline Operation with ARx Load and NOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 17 Pipeline Operation with ARx Load and NOP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 7 19 Pipeline Operation with External Bus Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 21 Latencies Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 24 C50 Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 C51 Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 C52 Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 C53 and C53S Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 LC56 and LC57 Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 C57S Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 11 C5x Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 C50 Local Data Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 16 C51 Local Data Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 16 C52 Local Data Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 16 C53 and C53S Local Data Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 16 LC56, LC57, and C57S Local Data Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . 8 17 Data Page 0 Address Map CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 18 Global Data Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 21 Address Ranges for On-Chip Single-Access RAM During External DMA . . . . . . . . . . . . 8 25 Number of CLKOUT1 Cycles Per Access for Various Numbers of Wait States . . . . . . . . 8 42 Data Page 0 Address Map Peripheral Registers and I/O Ports . . . . . . . . . . . . . . . . . . . . 9 2 Standard Clock Options (C50, C51, C52, C53, and C53S only) . . . . . . . . . . . . . . . . . . . 9 7 PLL Clock Options (LC56, C57S, and LC57 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Timer Control Register (TCR) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 Program/Data Wait-State Register (PDWSR) Address Ranges (C50, C51, and C52 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 Program/Data Wait-State Register (PDWSR) Address Ranges (C53S, LC56, and C57 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 Number of CLKOUT1 Cycles per Access for Various Numbers of Wait States . . . . . . . . 9 15 I/O Port Wait-State Register (IOWSR) Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 16 Wait-State Control Register (CWSR) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 17 Wait-State Field Values and Number of Wait States as a Function of CWSR Bits 03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 18 Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 24 Serial Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 26 Serial Port Control Register (SPC) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 28
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914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 C1 C2
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Serial Port Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 37 Buffered Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 55 Differences Between SP and BSP Operation in Standard Mode . . . . . . . . . . . . . . . . . . . 9 56 BSP Control Extension Register (SPCE) Bit Summary Serial Port Control Bits . . . . 9 58 Buffered Serial Port Word Length Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 59 Autobuffering Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 60 BSP Control Extension Register (SPCE) Bit Summary ABU Control Bits . . . . . . . . . 9 64 TDM Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 75 Interprocessor Communications Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 83 TDM Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 83 HPI Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 90 HPI Signal Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 91 HPI Input Control Signals Function Selection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 9 94 HPI Control Register (HPIC) Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 95 HPIC Host/C5x Read/Write Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 96 Wait-State Generation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 99 Initialization of BOB and HPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 100 Read Access to HPI with Autoincrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 100 Write Access to HPI with Auto-Increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 101 Sequence of Entering and Exiting IDLE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 103 HPI Operation During RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 104 Signal/Pin Assignments for the C52 in 100-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 3 Signal/Pin Assignments for the C51, C52, C53S, and LC56 in 100-Pin TQFP . . . . . . . A 5 Signal/Pin Assignments for the LC57 in 128-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 7 Signal/Pin Assignments for the C50, C51, and C53 in 132-Pin BQFP . . . . . . . . . . . . . . . A 9 Signal/Pin Assignments for the C57S in 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . A 11 Device-Specific Pin/Signal Assignments for the C51, C52, C53S, and LC56 in 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 12 Address and Data Bus Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 13 Memory Control Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 14 Multiprocessing Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 15 Initialization, Interrupt, and Reset Operations Signal Descriptions . . . . . . . . . . . . . . . . . . A 16 Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 16 Oscillator/Timer Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 17 Oscillator/Timer Standard Options (C50, C51, C52, C53, and C53S Only) . . . . . . . . . A 18 Oscillator/Timer Expanded Options (LC56, C57S, and LC57 Only) . . . . . . . . . . . . . . . . A 19 Serial Port Interface Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 20 Buffered Serial Port Interface Signal Descriptions (LC56 and C57 Only) . . . . . . . . . . . . A 21 Host Port Interface Signal Descriptions (C57 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 22 Emulation/Testing Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 24 Cycle Class-to-Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B 2 Instruction Set-to-Cycle Class Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B 5 TMS320C2x Versus TMS320C5x for the ADD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . C 12 TMS320C2x to TMS320C5x Serial Port Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 13

Tables

C3 C4 C5 C6 C7 C8 D1 D2 E1 G1

TMS320C2x-to-TMS320C5x Accumulator Memory Reference Instructions . . . . . . . . . . C 14 TMS320C2x-to-TMS320C5x Auxiliary Registers and Data Memory Page Pointer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 15 TMS320C2x-to-TMS320C5x TREG0, PREG, and Multiply Instructions . . . . . . . . . . . . . . C 16 TMS320C2x-to-TMS320C5x Branch and Call Instructions . . . . . . . . . . . . . . . . . . . . . . . . . C 17 TMS320C2x-to-TMS320C5x I/O and Data Memory Operation Instructions . . . . . . . . . . . C 18 TMS320C2x-to-TMS320C5x Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 19 XDS510 Header Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 2 Emulator Cable Pod Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 6 Commonly Used Crystal Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E 3 TMS320C5x Development Support Tools Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . G 7

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Examples

Examples
41 42 43 44 45 46 47 48 49 410 411 412 413 51 52 53 54 55 56 57 58 59 510 511 512 513 71 72 73 74 75 76 77 78 79 81
xxxii

Use of Conditional Returns (RETC Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 18 Use of Conditional Branch (BCND Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 19 Use of Delayed Conditional Branch (BCNDD Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . 4 20 Conditional Branch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 20 Use of Conditional Execution (XC Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 20 XC Execution with Unstable Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 21 XC Execution with Stable Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 21 Use of Block Repeat (RPTB Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 31 Context Save and Restore Used With Block Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 32 Block Repeat with Small Loop of Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 33 Interrupt Operation With a Single-Word Instruction at the End of an RPTB . . . . . . . . . . . 4 34 Interrupt Operation With a Single-Word Instruction Before the End of RPTB . . . . . . . . . 4 35 Modifying Register Values During Interrupt Context Save . . . . . . . . . . . . . . . . . . . . . . . . . . 4 43 Indirect Addressing With No Change to AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10 Indirect Addressing With Autodecrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10 Indirect Addressing With Autoincrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10 Indirect Addressing With Autoincrement and Change AR . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11 Indirect Addressing With INDX Subtracted from AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11 Indirect Addressing With INDX Added to AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11 Indirect Addressing With INDX Subtracted from AR With Reverse Carry . . . . . . . . . . . . . 5 11 Indirect Addressing With INDX Added to AR With Reverse Carry . . . . . . . . . . . . . . . . . . . 5 12 Indirect Addressing Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 12 Sequence of Auxiliary Register Modifications in Bit-Reversed Addressing . . . . . . . . . . . 5 13 Memory-Mapped Register Addressing in the Indirect Addressing Mode . . . . . . . . . . . . . 5 20 Memory-Mapped Register Addressing in the Direct Addressing Mode . . . . . . . . . . . . . . . 5 20 Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 22 Pipeline Operation of 1-Word Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pipeline Operation of 2-Word Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Pipeline Operation with Branch Taken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Pipeline Operation with Branch Not Taken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 Pipeline Operation with Subroutine Call and Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 Pipeline Operation with ARx Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 14 Pipeline Operation with ARx Load and NOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 16 Pipeline Operation with ARx Load and NOP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 7 18 Pipeline Operation with External Bus Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 21 Moving External Data to Internal Data Memory With the BLDD Instruction . . . . . . . . . . . 8 27

Examples

82 83 84 85 86 87 91 92 93 94 95 96 97 98

Moving External Data to Internal Program Memory With the BLDP Instruction . . . . . . . . Moving External Data to Internal Program Memory With the TBLW Instruction . . . . . . . Moving External Program to Internal Data Memory With the BLPD Instruction . . . . . . . . Moving External Program to Internal Data Memory With the TBLR Instruction . . . . . . . . Moving Data From Internal Data Memory to I/O Space With the LMMR Instruction . . . . Moving Data from I/O Space to Internal Data Memory With the SMMR Instruction . . . . Code Initialization for Generating a 50-kHz Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Service Routine for a 50-kHz Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device 0 Transmit Code (Serial Port Interface Operation) . . . . . . . . . . . . . . . . . . . . . . . . . Device 1 Receive Code (Serial Port Interface Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Initialization in Burst Mode with External Frame Sync and External Clock (Format is 10 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Initialization in Continuous Mode (Format is 16 bits) . . . . . . . . . . . . . . . . . . . . . . Device 0 Transmit Code (TDM Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device 1 Receive Code (TDM Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 8 8 8 8 8 9 9 9 9 9 9 9 9

28 29 30 30 31 31 12 12 51 52 72 73 85 86

Contents

xxxiii

Chapter 1

Introduction
This users guide discusses the TMS320C5x generation of fixed-point digital signal processors (DSPs) in the TMS320 family. The C5x DSP provides improved performance over earlier C1x and C2x generations while maintaining upward compatibility of source code between the devices. The C5x central processing unit (CPU) is based on the C25 CPU and incorporates additional architectural enhancements that allow the device to run twice as fast as C2x devices. Future expansion and enhancements are expected to heighten the performance and range of applications of the C5x DSPs. The C5x generation of static CMOS DSPs consists of the following devices:
Device TMS320C50/LC50 TMS320C51/LC51 TMS320C52/LC52 TMS320C53/LC53 TMS320C53S/LC53S TMS320LC56 TMS320LC57 TMS320C57S/LC57S On-Chip RAM 10K words 2K words 1K words 4K words 4K words 7K words 7K words 7K words On-Chip ROM 2K words 8K words 4K words 16K words 16K words 32K words 32K words 2K words

Topic
1.1 1.2 1.3

Page
TMS320 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 TMS320C5x Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 TMS320C5x Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Introduction

1-1

TMS320 Family Overview

1.1 TMS320 Family Overview

The TMS320 family consists of two types of single-chip DSPs: 16-bit fixedpoint and 32-bit floating-point. These DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. Combining these two qualities, the TMS320 processors are inexpensive alternatives to custom-fabricated VLSI and multichip bit-slice processors. Refer to subsection 1.1.2, TMS320 Typical Applications, for a detailed list of applications of the TMS320 family. The following characteristics make this family the ideal choice for a wide range of processing applications:
-

Very flexible instruction set Inherent operational flexibility High-speed performance Innovative, parallel architectural design Cost-effectiveness

1.1.1

History, Development, and Advantages of TMS320 DSPs

In 1982, Texas Instruments introduced the TMS32010 the first fixed-point DSP in the TMS320 family. Before the end of the year, the Electronic Products magazine awarded the TMS32010 the title Product of the Year. The TMS32010 became the model for future TMS320 generations. Today, the TMS320 family consists of eight generations: the C1x, C2x, C2xx, C5x, and C54x are fixed-point, the C3x and C4x are floating-point, and the C8x is a multiprocessor. Figure 11 illustrates the performance gains that the TMS320 family has made over time with successive generations. Source code is upward compatible from one fixed-point generation to the next fixed-point generation (except for the C54x), and from one floating-point generation to the next floating-point generation. Upward compatibility preserves the software generation of your investment, thereby providing a convenient and cost-efficient means to a higher-performance, more versatile DSP system. Each generation of TMS320 devices has a CPU and a variety of on-chip memory and peripheral configurations for developing spin-off devices. These spin-off devices satisfy a wide range of needs in the worldwide electronics market. When memory and peripherals are integrated into one processor, the overall system cost is greatly reduced, and circuit board space is saved.

1-2

TMS320 Family Overview

Figure 11. Evolution of the TMS320 Family

Introduction

1-3

TMS320 Family Overview

1.1.2

TMS320 Typical Applications

The TMS320 family of DSPs offers better, more adaptable approaches to traditional signal-processing problems, such as vocoding, filtering, and error coding. Furthermore, the TMS320 family supports complex applications that often require multiple operations to be performed simultaneously. Figure 12 shows many of the typical applications of the TMS320 family.

Figure 12. Typical Applications for the TMS320 Family

Automotive Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Global positioning Navigation Vibration analysis Voice commands General-Purpose Adaptive filtering Convolution Correlation Digital filtering Fast Fourier transforms Hilbert transforms Waveform generation Windowing Instrumentation Digital filtering Function generation Pattern matching Phase-locked loops Seismic processing Spectrum analysis Transient analysis Consumer Digital radios/TVs Educational toys Music synthesizers Power tools Radar detectors Solid-state answering machines Control Disk drive control Engine control Laser printer control Motor control Robotics control Servo control

Graphics/Imaging 3-D rotation Animation/digital map Homomorphic processing Pattern recognition Image enhancement Image compression/transmission Robot vision Workstations Medical Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment Telecommunications

Industrial Numeric control Power-line monitoring Robotics Security access

Military Image processing Missile guidance Navigation Radar processing Radio frequency modems Secure communications Sonar processing Voice/Speech Speech enhancement Speech recognition Speech synthesis Speaker verification Speech vocoding Voice mail Text-to-speech

1200- to 19200-bps modems Adaptive equalizers ADPCM transcoders Cellular telephones Channel multiplexing Data encryption Digital PBXs Digital speech interpolation (DSI) Personal digital assistants (PDA)

DTMF encoding/decoding Echo cancellation Fax Line repeaters Speaker phones Spread spectrum communications Video conferencing X.25 Packet Switching Personal communications systems (PCS)

1-4

TMS320C5x Overview

1.2 TMS320C5x Overview

The C5x generation consists of the C50, C51, C52, C53, C53S, C56, C57, and C57S DSPs, which are fabricated by CMOS integrated-circuit technology. Their architectural design is based on the C25. The operational flexibility and speed of the C5x are the result of combining an advanced Harvard architecture (which has separate buses for program memory and data memory), a CPU with application-specific hardware logic, on-chip peripherals, on-chip memory, and a highly specialized instruction set. The C5x is designed to execute up to 50 million instructions per second (MIPS). Spin-off devices that combine the C5x CPU with customized on-chip memory and peripheral configurations may be developed for special applications in the worldwide electronics market. The C5x devices offer these advantages:
- Enhanced TMS320 architectural design for increased performance and

versatility
- Modular architectural design for fast development of spin-off devices - Advanced integrated-circuit processing technology for increased per-

formance and low power consumption

- Source code compatibility with C1x, C2x, and C2xx DSPs for fast and

easy performance upgrades

- Enhanced instruction set for faster algorithms and for optimized high-level

language operation
- Reduced power consumption and increased radiation hardness because

of new static design techniques Table 11 lists the major characteristics of the C5x DSPs. The table shows the capacity of on-chip RAM and ROM, number of serial and parallel input/output (I/O) ports, power supply requirements, execution time of one machine cycle, and package types available with total pin count. Use Table 11 for guidance in choosing the best C5x DSP for your application.

Introduction

1-5

TMS320C5x Overview

Table 11. Characteristics of the C5x DSPs

On-Chip Memory (16-bit words) DARAM SARAM ROM 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 9K 9K 1K 1K 1K 1K 3K 3K 3K 3K 6K 6K 6K 6K 2K 2K 8K 8K 8K 8K 4K 4K 4K 4K 16K 16K 16K 16K 32K 2K 32K 2K I/O Ports Serial Parallel 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2# 2# 2# 2# 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64Kk 64Kk 64Kk Power Supply S pply (V) 5 3.3 5 5 3.3 3.3 5 5 3.3 3.3 5 5 3.3 3.3 3.3 5 3.3 3.3 Cycle Time (ns) 50/35/25 50/40/25

TMS320 Device ID C50 LC50 C51 C51 LC51 LC51 C52 C52 LC52 LC52 C53 C53S LC53 LC53S LC56 C57S LC57 LC57S PQ PQ PQ PZ PQ PZ PJ PZ PJ PZ PQ PZ PQ PZ PZ PGE PBK PGE

Package Type 132 pin BQFPd 132 pin BQFPd

50/35/25/20 132 pin BQFPd 50/35/25/20 100 pin TQFPk 50/40/25 50/40/25 132 pin BQFPd 100 pin TQFPk

50/35/25/20 100 pin QFPh 50/35/25/20 100 pin TQFPk 50/40/25 50/40/25 50/35/25 50/35/25 50/40/25 50/40/25 50/35/25 50/35/25 50/35/25 50/35 100 pin QFPh 100 pin TQFPk 132 pin BQFPd 100 pin TQFPk 132 pin BQFPd 100 pin TQFPk 100 pin TQFPk 144 pin TQFPD 128 pinTQFPk 144 pin TQFPD

Dual-access RAM (DARAM) Single-access RAM (SARAM) ROM bootloader available Includes time-division multiplexed (TDM) serial port # Includes buffered serial port (BSP) || Includes host port interface (HPI) d 20 20 3.8 mm bumpered quad flat-pack (BQFP) package k 14 14 1.4 mm thin quad flat-pack (TQFP) package h 14 20 2.7 mm quad flat-pack (QFP) package D 20 20 1.4 mm thin quad flat-pack (TQFP) package Sixteen of the 64K parallel I/O ports are memory mapped.

1-6

TMS320C5x Key Features

1.3 TMS320C5x Key Features

Key features of the C5x DSPs are listed below. Where a feature is exclusive to a particular device, the devices name is enclosed within parentheses and noted after that feature.
- Compatibility: - Speed:

Source-code compatible with C1x, C2x, and C2xx devices

20-/25-/35-/50-ns single-cycle fixed-point instruction execution time (50/40/28.6/20 MIPS)

- Power J J

3.3-V and 5-V static CMOS technology with two power-down modes Power consumption control with IDLE1 and IDLE2 instructions for power-down modes

- Memory J

224K-word 16-bit maximum addressable external memory space (64K-word program, 64K-word data, 64K-word I/O, and 32K-word global memory) 1056-word 16-bit dual-access on-chip data RAM 9K-word 16-bit single-access on-chip program/data RAM (C50) 2K-word 16-bit single-access on-chip boot ROM (C50, C57S) 1K-word 16-bit single-access on-chip program/data RAM (C51) 8K-word 16-bit single-access on-chip program ROM (C51) 4K-word 16-bit single-access on-chip program ROM (C52) 3K-word 16-bit single-access on-chip program/data RAM (C53, C53S) 16K-word 16-bit single-access on-chip program ROM (C53, C53S) 6K-word 16-bit single-access on-chip program/data RAM (LC56, C57S, LC57) 32K-word 16-bit single-access on-chip program ROM (LC56, LC57)

J J J J J J J J J J

Introduction

1-7

TMS320C5x Key Features

- Central processing unit (CPU) J

Central arithmetic logic unit (CALU) consisting of the following: H H H 32-bit arithmetic logic unit (ALU), 32-bit accumulator (ACC), and 32-bit accumulator buffer (ACCB) 16-bit 16-bit parallel multiplier with a 32-bit product capability 0- to 16-bit left and right data barrel-shifters and a 64-bit incremental data shifter

J J J

16-bit parallel logic unit (PLU) Dedicated auxiliary register arithmetic unit (ARAU) for indirect addressing Eight auxiliary registers

- Program control J J J J J

8-level hardware stack 4-deep pipelined operation for delayed branch, call, and return instructions Eleven shadow registers for storing strategic CPU-controlled registers during an interrupt service routine (ISR) Extended hold operation for concurrent external direct memory access (DMA) of external memory or on-chip RAM Two indirectly addressed circular buffers for circular addressing

- Instruction set J J J J J J J J J

Single-cycle multiply/accumulate instructions Single-instruction repeat and block repeat operations Block memory move instructions for better program and data management Memory-mapped register load and store instructions Conditional branch and call instructions Delayed execution of branch and call instructions Fast return from interrupt instructions Index-addressing mode Bit-reversed index-addressing mode for radix-2 fast-Fourier transforms (FFTs)

1-8

TMS320C5x Key Features

- On-chip peripherals J J J J J J J J J

64K parallel I/O ports (16 I/O ports are memory-mapped) Sixteen software-programmable wait-state generators for program, data, and I/O memory spaces Interval timer with period, control, and counter registers for software stop, start, and reset Phase-locked loop (PLL) clock generator with internal oscillator or external clock source Multiple PLL clocking option (x1, x2, x3, x4, x5, x9, depending on the device) Full-duplex synchronous serial port interface for direct communication between the C5x and another serial device Time-division multiplexed (TDM) serial port (C50, C51, C53) Buffered serial port (BSP) (LC56, C57S, LC57) 8-bit parallel host port interface (HPI) (C57, C57S)

- Test/Emulation J J

On-chip scan-based emulation logic IEEE JTAG Standard 1149.1 boundary scan logic (C50, C51, C53, C57S)

- Packages J J J J J

100-pin quad flat-pack (QFP) package (C52) 100-pin thin quad flat-pack (TQFP) package (C51, C52, C53S, LC56) 128-pin TQFP package (LC57) 132-pin bumpered quad flat-pack (BQFP) package (C50, C51, C53) 144-pin TQFP package (C57S)

Introduction

1-9

Chapter 2

Architectural Overview
This chapter provides an overview of the architectural structure of the C5x, which consists of the buses, on-chip memory, central processing unit (CPU), and on-chip peripherals. The C5x uses an advanced, modified Harvard-type architecture based on the C25 architecture and maximizes processing power with separate buses for program memory and data memory. The instruction set supports data transfers between the two memory spaces. Figure 21 shows a functional block diagram of the C5x. All C5x DSPs have the same CPU structure; however, they have different on-chip memory configurations and on-chip peripherals.

Topic
2.1 2.2 2.3 2.4 2.5

Page
Bus Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Test/Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Architectural Overview

2-1

C5x Functional Block Diagram

Figure 21. C5x Functional Block Diagram

Data bus

Memory Program ROM C50 C51 C52 C53 LC56 C57S LC57 2K 8K 4K 16K 32K 2K 32K Data/Program SARAM C50 C51 C52 C53 LC56 C57S LC57 9K 1K 3K 6K 6K 6K Peripherals 6 Serial port 1 Data DARAM Data/Program DARAM B0 (512 X 16) B2 (32 X 16) B1 (512 X 16) TDM serial port Program bus Buffered serial port 6 6 Serial port 2

1 Timer Program controller Memory control Multiprocessing Interrupts Initialization Oscillator/timer Program counter Status/control registers Hardware stack Address generation logic Instruction register Auxiliary register arithmetic unit (ARAU) Memorymapped registers Host port interface CALU D Multiplier D Accumulator D ACC Buffer D Shifters D Arithmetic logic unit (ALU) Parallel logic unit (PLU) 7 Test/emulation 18

CPU Data bus

2-2

Bus Structure

2.1 Bus Structure

Separate program and data buses allow simultaneous access to program instructions and data, providing a high degree of parallelism. For example, while data is multiplied, a previous product can be loaded into, added to, or subtracted from the accumulator and, at the same time, a new address can be generated. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the C5x includes the control mechanisms to manage interrupts, repeated operations, and function calling. The C5x architecture is built around four major buses:
-

Program bus (PB) Program address bus (PAB) Data read bus (DB) Data read address bus (DAB)

The PAB provides addresses to program memory space for both reads and writes. The PB also carries the instruction code and immediate operands from program memory space to the CPU. The DB interconnects various elements of the CPU to data memory space. The program and data buses can work together to transfer data from on-chip data memory and internal or external program memory to the multiplier for single-cycle multiply/accumulate operations.

Architectural Overview

2-3

Central Processing Unit (CPU)

2.2 Central Processing Unit (CPU)

The C5x CPU consists of these elements:
-

Central arithmetic logic unit (CALU) Parallel logic unit (PLU) Auxiliary register arithmetic unit (ARAU) Memory-mapped registers Program controller

The C5x CPU maintains source-code compatibility with the C1x and C2x generations while achieving high performance and greater versatility. Improvements include a 32-bit accumulator buffer, additional scaling capabilities, and a host of new instructions. The instruction set exploits the additional hardware features and is flexible in a wide range of applications. Data management has been improved through the use of new block move instructions and memory-mapped register instructions. See Chapter 3, Central Processing Unit (CPU).

2.2.1

Central Arithmetic Logic Unit (CALU)

The CPU uses the CALU to perform 2s-complement arithmetic. The CALU consists of these elements:
-

16-bit  16-bit multiplier 32-bit arithmetic logic unit (ALU) 32-bit accumulator (ACC) 32-bit accumulator buffer (ACCB) Additional shifters at the outputs of both the accumulator and the product register (PREG)

For information on the CALU, see Section 3.2, Central Arithmetic Logic Unit (CALU), on page 3-7.

2.2.2

Parallel Logic Unit (PLU)

The CPU includes an independent PLU, which operates separately from, but in parallel with, the ALU. The PLU performs Boolean operations or the bit manipulations required of high-speed controllers. The PLU can set, clear, test, or toggle bits in a status register, control register, or any data memory location. The PLU provides a direct logic operation path to data memory values without affecting the contents of the ACC or PREG. Results of a PLU function are written back to the original data memory location. For information on the PLU, see Section 3.3, Parallel Logic Unit (PLU), on page 3-15.

2-4

Central Processing Unit (CPU)

2.2.3

Auxiliary Register Arithmetic Unit (ARAU)

The CPU includes an unsigned 16-bit arithmetic logic unit that calculates indirect addresses by using inputs from the auxiliary registers (ARs), index register (INDX), and auxiliary register compare register (ARCR). The ARAU can autoindex the current AR while the data memory location is being addressed and can index either by 1 or by the contents of the INDX. As a result, accessing data does not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel. For information on the ARAU, see Section 3.4, Auxiliary Register Arithmetic Unit (ARAU), on page 3-17.

2.2.4

Memory-Mapped Registers
The C5x has 96 registers mapped into page 0 of the data memory space. All C5x DSPs have 28 CPU registers and 16 input/output (I/O) port registers but have different numbers of peripheral and reserved registers (see Chapter 4, Memory). Since the memory-mapped registers are a component of the data memory space, they can be written to and read from in the same way as any other data memory location. The memory-mapped registers are used for indirect data address pointers, temporary storage, CPU status and control, or integer arithmetic processing through the ARAU. For information on registers, see Section 3.5, Summary of Registers, on page 3-21.

2.2.5

Program Controller
The program controller contains logic circuitry that decodes the operational instructions, manages the CPU pipeline, stores the status of CPU operations, and decodes the conditional operations. Parallelism of architecture lets the C5x perform three concurrent memory operations in any given machine cycle: fetch an instruction, read an operand, and write an operand. See Chapter 4, Program Control, and Chapter 7, Pipeline. The program controller consists of these elements:
-

Program counter Status and control registers Hardware stack Address generation logic Instruction register

Architectural Overview

2-5

On-Chip Memory

2.3 On-Chip Memory

The C5x architecture contains a considerable amount of on-chip memory to aid in system performance and integration:
- Program read-only memory (ROM) - Data/program dual-access RAM (DARAM) - Data/program single-access RAM (SARAM)

The C5x has a total address range of 224K words  16 bits. The memory space is divided into four individually selectable memory segments: 64K-word program memory space, 64K-word local data memory space, 64K-word input/ output ports, and 32K-word global data memory space. For information on the memory organization, see Chapter 8, Memory.

2.3.1

Program ROM
All C5x DSPs carry a 16-bit on-chip maskable programmable ROM (see Table 11 for sizes). The C50 and C57S DSPs have boot loader code resident in the on-chip ROM, all other C5x DSPs offer the boot loader code as an option. This memory is used for booting program code from slower external ROM or EPROM to fast on-chip or external RAM. Once the custom program has been booted into RAM, the boot ROM space can be removed from program memory space by setting the MP/MC bit in the processor mode status register (PMST). The on-chip ROM is selected at reset by driving the MP/MC pin low. If the on-chip ROM is not selected, the C5x devices start execution from off-chip memory. For information on the program ROM, see Section 8.2, Program Memory, on page 8-7. The on-chip ROM may be configured with or without boot loader code. However, the on-chip ROM is intended for your specific program. Once the program is in its final form, you can submit the ROM code to Texas Instruments for implementation into your device. For details on how to submit code to Texas Instruments to program your ROM, see Appendix F, Submitting ROM Codes to TI.

2.3.2

Data/Program Dual-Access RAM

All C5x DSPs carry a 1056-word  16-bit on-chip dual-access RAM (DARAM). The DARAM is divided into three individually selectable memory blocks: 512-word data or program DARAM block B0, 512-word data DARAM block B1, and 32-word data DARAM block B2. The DARAM is primarily intended to store data values but, when needed, can be used to store programs as well. DARAM blocks B1 and B2 are always configured as data memory; however, DARAM

2-6

On-Chip Memory

block B0 can be configured by software as data or program memory. The DARAM can be configured in one of two ways:
- All 1056 words  16 bits configured as data memory - 544 words  16 bits configured as data memory and 512 words 16 bits

configured as program memory DARAM improves the operational speed of the C5x CPU. The CPU operates with a 4-deep pipeline. In this pipeline, the CPU reads data on the third stage and writes data on the fourth stage. Hence, for a given instruction sequence, the second instruction could be reading data at the same time the first instruction is writing data. The dual data buses (DB and DAB) allow the CPU to read from and write to DARAM in the same machine cycle. For information on DARAM, see Section 8.3, Local Data Memory, on page 8-15.

2.3.3

Data/Program Single-Access RAM

All C5x DSPs except the C52 carry a 16-bit on-chip single-access RAM (SARAM) of various sizes (see Table 11). Code can be booted from an offchip ROM and then executed at full speed, once it is loaded into the on-chip SARAM. The SARAM can be configured by software in one of three ways:
- All SARAM configured as data memory - All SARAM configured as program memory - SARAM configured as both data memory and program memory

The SARAM is divided into 1K- and/or 2K-word blocks contiguous in address memory space. All C5x CPUs support parallel accesses to these SARAM blocks. However, one SARAM block can be accessed only once per machine cycle. In other words, the CPU can read from or write to one SARAM block while accessing another SARAM block. When the CPU requests multiple accesses, the SARAM schedules the accesses by providing a not-ready condition to the CPU and executing the multiple accesses one cycle at a time. SARAM supports more flexible address mapping than DARAM because SARAM can be mapped to both program and data memory space simultaneously. However, because of simultaneous program and data mapping, an instruction fetch and data fetch that could be performed in one machine cycle with DARAM may take two machine cycles with SARAM. For information on SARAM, see Section 8.3, Local Data Memory, on page 8-15.

2.3.4

On-Chip Memory Protection

The C5x DSPs have a maskable option that protects the contents of on-chip memories. When the related bit is set, no externally originating instruction can access the on-chip memory spaces. For information on the protection feature, see subsection 8.2.4, Program Memory Protection Feature, on page 8-14.
Architectural Overview
2-7

On-Chip Peripherals

2.4 On-Chip Peripherals

All C5x DSPs have the same CPU structure; however, they have different onchip peripherals connected to their CPUs. The C5x DSP on-chip peripherals available are:
-

Clock generator Hardware timer Software-programmable wait-state generators Parallel I/O ports Host port interface (HPI) Serial port Buffered serial port (BSP) Time-division multiplexed (TDM) serial port User-maskable interrupts

2.4.1

Clock Generator
The clock generator consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator can be driven internally by a crystal resonator circuit or driven externally by a clock source. The PLL circuit can generate an internal CPU clock by multiplying the clock source by a specific factor, so you can use a clock source with a lower frequency than that of the CPU. For information, see Section 9.2, Clock Generator, on page 9-7.

2.4.2

Hardware Timer
A 16-bit hardware timer with a 4-bit prescaler is available. This programmable timer clocks at a rate that is between 1/2 and 1/32 of the machine cycle rate (CLKOUT1), depending upon the timers divide-down ratio. The timer can be stopped, restarted, reset, or disabled by specific status bits. For information, see Section 9.3, Timer, on page 9-9.

2.4.3

Software-Programmable Wait-State Generators

Software-programmable wait-state logic is incorporated in C5x DSPs allowing wait-state generation without any external hardware for interfacing with slower off-chip memory and I/O devices. This feature consists of multiple waitstate generating circuits. Each circuit is user-programmable to operate in different wait states for off-chip memory accesses. For information, see Section 9.4, Software-Programmable Wait-State Generators, on page 9-13.

2-8

On-Chip Peripherals

2.4.4

Parallel I/O Ports

A total of 64K I/O ports are available, sixteen of these ports are memory-mapped in data memory space. Each of the I/O ports can be addressed by the IN or the OUT instruction. The memory-mapped I/O ports can be accessed with any instruction that reads from or writes to data memory. The IS signal indicates a read or write operation through an I/O port. The C5x can easily interface with external I/O devices through the I/O ports while requiring minimal off-chip address decoding circuits. For information, see Section 9.6, Parallel I/O Ports, on page 9-22. Table 21 lists the number and type of parallel ports available in C5x DSPs with various package types.

2.4.5

Host Port Interface (HPI)

The HPI available on the C57S and LC57 is an 8-bit parallel I/O port that provides an interface to a host processor. Information is exchanged between the DSP and the host processor through on-chip memory that is accessible to both the host processor and the C57. For information, see Section 9.10, Host Port Interface, on page 9-87.

Table 21. Number of Serial/Parallel Ports Available in Different C5x Package Types

TMS320 Device Package ID PQ High-Speed Serial Port 1 1 1 1 2 1 1 1 TDM Serial Port 1 1 1 Buffered Serial Port 1 1 1 Host Port (Parallel) 1 1 C50/LC50 C51/LC51 C52/LC52 C53/LC53 PQ/PZ PJ/PZ PQ PZ PZ C53S/LC53S LC56 C57S/LC57S LC57 PGE PBK
PGE is a 20 20 1.4 mm thin quad flat-pack (TQFP) package PJ is a 14 20 2.7 mm quad flat-pack (QFP) package PQ is a 20 20 3.8 mm bumpered quad flat-pack (BQFP) package PZ and PBK are a 14 14 1.4 mm thin quad flat-pack (TQFP) package

Architectural Overview

2-9

On-Chip Peripherals

2.4.6

Serial Port
Three different kinds of serial ports are available: a general-purpose serial port, a time-division multiplexed (TDM) serial port, and a buffered serial port (BSP). Each C5x contains at least one general-purpose, high-speed synchronous, full-duplexed serial port interface that provides direct communication with serial devices such as codecs, serial analog-to-digital (A/D) converters, and other serial systems. The serial port is capable of operating at up to onefourth the machine cycle rate (CLKOUT1). The serial port transmitter and receiver are double-buffered and individually controlled by maskable external interrupt signals. Data is framed either as bytes or as words. Table 21 lists the number and type of serial ports available in C5x DSPs with various package types. For information on serial ports, see Section 9.7, Serial Port Interface, on page 9-23.

2.4.7

Buffered Serial Port (BSP)

The BSP available on the C56 and C57 devices is a full-duplexed, doublebuffered serial port and an autobuffering unit (ABU). The BSP provides flexibility on the data stream length. The ABU supports high-speed data transfer and reduces interrupt latencies. Table 21 lists the number and type of serial ports available in C5x DSPs with various package types. For information, see Section 9.8, Buffered Serial Port (BSP) Interface, on page 9-53.

2.4.8

TDM Serial Port

The TDM serial port available on the C50, C51, and C53 devices is a fullduplexed serial port that can be configured by software either for synchronous operations or for time-division multiplexed operations. The TDM serial port is commonly used in multiprocessor applications. Table 21 lists the number and type of serial ports available in C5x DSPs with various package types. For information, see Section 9.9, Time-Division Multiplexed (TDM) Serial Port Interface, on page 9-74.

2.4.9

User-Maskable Interrupts
Four external interrupt lines (INT1INT4) and five internal interrupts, a timer interrupt and four serial port interrupts, are user maskable. When an interrupt service routine (ISR) is executed, the contents of the program counter are saved on an 8-level hardware stack, and the contents of eleven specific CPU registers are automatically saved (shadowed) on a 1-level-deep stack. When a return from interrupt instruction is executed, the CPU registers contents are restored. For information, see Section 4.8, Interrupts, on page 4-36.

2-10

Test/Emulation

2.5 Test/Emulation
On the C50, LC50, C51, LC51, C53, LC53, C57S and LC57S, an IEEE standard 1149.1 (JTAG) interface with boundary scan capability is used for emulation and test. This logic provides the boundary scan to and from the interfacing devices. It can be used to test pin-to-pin continuity and to perform operational tests on devices that are peripheral to the C5x. On the C52, LC52, C53S, LC53S, LC56, and LC57, an IEEE standard 1149.1 (JTAG) interface without boundary scan capability is used for emulation purposes only and is interfaced to other internal scanning logic circuitry that has access to all of the on-chip resources. Thus, the C5x can perform on-board emulation by means of the IEEE standard 1149.1 serial scan pins and the emulation-dedicated pins. The on-chip analysis block in conjunction with the C5x debugger software provides the capability to perform debugging and performance evaluation functions in a target system. The full analysis block provides the following capabilities:
- Flexible breakpoint setup. Breakpoints can be triggered based on the fol-

lowing events:
J J J J J

Program fetches/reads/writes EMU0/1 pin activity Data reads/writes CPU events (calls, returns, interrupts/traps, branches, pipeline clock) Event counter overflow

- Counting of the following events for performance analysis: J J J J J J

CPU clocks Pipeline advances Instruction fetches Calls, returns, interrupts/traps, branches Program fetches/reads/writes Data reads/writes

- Program counter discontinuity trace buffer to monitor program counter

flow. The reduced analysis block on the C53S and LC53S provides the capability for breakpoint triggering based on program fetches/reads/writes and EMU0/1 pin activity. Table 22 lists the IEEE standard 1149.1 (JTAG) interface, boundary scan capability, and on-chip analysis block functions supported by the C5x. See IEEE Std. 1149.1 for more details.
Architectural Overview
2-11

Test/Emulation

Table 22. IEEE Std.1149.1 (JTAG)/Boundary-Scan Interface Configurations for the C5x

Refer to the TMS320 DSP Development Support Reference Guide for additional information on available TMS320 development tools.
LC57 C57S/LC57S LC56 C53S/LC53S C53/LC53 C52/LC52 C51/LC51 C50/LC50 TMS320 Device IEEE Std.1149.1 Interface Yes Yes Yes Yes Yes Yes Yes Yes Boundary Scan Capability Yes Yes Yes Yes No No No No On-Chip Analysis Block Reduced Full Full Full Full Full Full Full

2-12

Chapter 3

Central Processing Unit (CPU)

The TMS320C5x DSP central processing unit (CPU) can perform high-speed arithmetic within a short instruction cycle by means of its highly parallel architecture, which consists of the following elements:
-

Program controller Central arithmetic logic unit (CALU) Parallel logic unit (PLU) Auxiliary register arithmetic unit (ARAU) Memory-mapped registers

This chapter does not discuss the memory and peripheral segments, except in relation to the CPU.

Topic
3.1 3.2 3.3 3.4 3.5

Page
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Central Arithmetic Logic Unit (CALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Parallel Logic Unit (PLU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Auxiliary Register Arithmetic Unit (ARAU) . . . . . . . . . . . . . . . . . . . . . 3-17 Summary of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

Central Processing Unit (CPU)

3-1

Functional Overview

3.1 Functional Overview

The block diagram shown in Figure 31 outlines the principal blocks and data paths within the C5x. The succeeding sections provide further details of the functional blocks of the CPU. The internal hardware of the C5x executes functions that other processors typically implement in software or microcode. For example, the C5x contains hardware for single-cycle 16  16-bit multiplication, data shifting, and address manipulation. This hardware-intensive approach provides computing power previously unavailable on a single chip. Table 31 presents a summary of the C5xs internal hardware. This summary table is alphabetized. The table includes the internal processing elements, registers, and buses. All of the symbols used in the table correspond to the the functional blocks illustrated in Figure 31, the succeeding block diagrams in this chapter, and the text throughout this document.

3-2

Functional Overview

Figure 31. Block Diagram of C5x DSP Central Processing Unit (CPU)
CLKMD1 CLKMD2 CLKMD3 IS DS PS RW STRB READY BR XF HOLD HOLDA IAQ BIO RS IACK MP/MC INT(14) PROGRAM BUS Software waitstates PDWSR IOWSR Program Controller 16 CWSR(5) X1 CLKOUT1 X2/CLKIN CLKIN2 PFC PAER MUX COMPARE MCS RD WE NMI Address 4 ROM MUX A15A0 Stack (8x16) PC PASR IREG BMAR ST0 ST1 PMST RPTC IMR IFR GREG BRCR TREG1(5) TREG2(4) Serial Port 1

Instruction RBIT PROGRAM BUS MUX D15D0

Serial Port 2

DATA BUS 7 LSB from IREG 3 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 CBCR(8) CBSR1 CBSR2 CBER1 CBER2 INDX 32 32 PRESCALER SFR(016) 32 Emulation DRB PRESCALER SFL(016) MULTIPLIER PREG(32) 32 MUX PSCALER (6,0,1,4) PLU TREG0 MUX Timer ST0 [DP] MUX 9 DBMR Time-Division Multiplexed Serial Port

DATA BUS

Buffered Serial Port

ST0 [ARP]

Host Port Interface

MUX I/O Ports PA0

ARCR

. . .

MUX ARAU MUX 32 Data/Program MUX SARAM Data/Program DARAM B0 MUX Data DARAM B2 B1 MUX MUX POSTSCALER (07) ST1 [C] 32 PROGRAM BUS DATA BUS ALU(32) 32 32

PA15

ACCH

ACCL 32

ACCB(32)

Notes: All registers and data lines are 16-bits wide unless otherwise specified. Not available on all devices.

Central Processing Unit (CPU)

3-3

Functional Overview

Table 31. C5x CPU Internal Hardware Summary

Symbol A15A0 ACC(32) ACCB(32) ACCH ACCL ALU(32) AR0AR7 ARAU ARB(3) ARCR ARP(3) BMAR BRAF(1) BRCR C CALU CBCR(8) CBER1, CBER2 CBSR1, CBSR2 CNF COMPARE D15D0 DATA BUS DBMR dma(7) DP(9) Name Address bus Accumulator Accumulator buffer Accumulator high byte Accumulator low byte Arithmetic logic unit Auxiliary registers Auxiliary register arithmetic unit Auxiliary register buffer bits Auxiliary register compare register Auxiliary register pointer bits Block move address register Block repeat active flag bit Block repeat counter register Carry bit Central arithmetic logic unit Circular buffer control register Circular buffer end registers Circular buffer start registers Configuration control bit Compare of program address Data bus Data bus Dynamic bit manipulation register Data memory address (immediate register) Data memory page pointer bits

3-4

Functional Overview

Table 31. C5x CPU Internal Hardware Summary (Continued)

Symbol DRB GREG HM(1) IFR IMR INDX INTM(1) IPTR(5) IREG MCS MP/MC MULTIPLIER MUX NDX(1) OV(1) OVLY(1) OVM(1) P-SCALER (6, 0, 1, 4) PAER PASR PC PFC PLU PM(2) PMST POSTSCALER(07) Name Direct data memory address bus Global memory allocation register Hold mode bit Interrupt flag register Interrupt mask register Index register Interrupt mode bit Interrupt vector pointer bits Instruction register Microcall stack Microprocessor/microcomputer bit Multiplier Multiplexer Enable extra index register bit Overflow bit RAM overlay bit Overflow mode bit Product shifter Block repeat program address end register Block repeat program address start register Program counter Prefetch counter Parallel logic unit Product shifter mode bits Processor mode status register Accumulator postscaling shifter

Central Processing Unit (CPU)

3-5

Functional Overview

Table 31. C5x CPU Internal Hardware Summary (Continued)

Symbol PREG(32) PRESCALER, SFL(016), SFR(016) PROGRAM BUS RAM(1) RPTC ST0, ST1 STACK SXM(1) TC(1) TREG0 TREG1(5) TREG2(4) TRM(1) XF(1) Name Product register Prescaling shifters Program bus Program RAM enable bit Repeat counter register Status registers Stack Sign-extension mode bit Test/control bit Temporary register (multiplicand) Temporary register (dynamic shift count) Temporary register (bit pointer in dynamic bit test) Enable multiple temporary registers bit External flag pin status bit

3-6

Central Arithmetic Logic Unit (CALU)

3.2

Central Arithmetic Logic Unit (CALU)

The CALU components, shown in Figure 32, consists of the following:
-

16-bit  16-bit parallel multiplier 32-bit 2s-complement arithmetic logic unit (ALU) 32-bit accumulator (ACC) 32-bit accumulator buffer (ACCB) 0-, 1-, or 4-bit left or 6-bit right shifter 0- to 16-bit left barrel shifter 0- to 16-bit right barrel shifter 0- to 7-bit left barrel shifter

3.2.1

Multiplier, Product Register (PREG), and Temporary Register 0 (TREG0)

The 16-bit  16-bit hardware multiplier can compute a signed or an unsigned 32-bit product in a single machine cycle. All multiply instructions except the multiply unsigned (MPYU) instruction perform a signed multiply operation in the multiplier. That is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number. One input to the multiplier is from memory-mapped temporary register 0 (TREG0), and the other input is from the data bus or the program bus. The 32-bit result from the multiplier is stored in the PREG and is available to the ALU. The ALU uses the 16-bit words taken from data memory or derived from an immediate instruction, or the ALU uses the 32-bit result stored in the PREG to perform arithmetic operations. The ALU can also perform Boolean operations. The 32-bit result from the ALU is stored in the ACC; the ACC also supplies the second input to the ALU. Instructions are provided for storing the highand low-order accumulator words in memory. The shifters (p-scaler, prescaler, and postscaler) make it possible for the CALU to perform numerical scaling, bit extraction, extended-precision arithmetic, and overflow prevention. These shifters are connected to the output of the PREG and the ACC. The four product shift modes (PM) at the PREG output are useful for performing multiply/accumulate operations and fractional arithmetic and for justifying fractional products. The PM field of status register ST1 specifies the PM shift mode of the p-scaler:
- If PM = 002, the PREG 32-bit output is not shifted when transferred into the

ALU or stored.
- If PM = 012, the PREG output is left-shifted 1 bit when transferred into the

ALU or stored, and the LSB is zero filled. This shift mode compensates for the extra sign bit gained when multiplying two 16-bit 2s-complement numbers.
Central Processing Unit (CPU)
3-7

Central Arithmetic Logic Unit (CALU)

Figure 32. Central Arithmetic Logic Unit

Data Bus

MUX

TREG0 Multiplier
PRESCALER SFL(016)

TREG1(5)

PREG(32) 32 PSCALER (6,0,1,4) 32 32

MUX 32
PRESCALER SFR(016)

MUX 32

32 ST1

ALU(32) C(1) 32

32

ACCH

ACCL 32

ACCB(32)

POSTSCALER (07)

Program Bus

Data Bus

Notes: All registers and data lines are 16-bits wide unless otherwise specified.

- If PM = 102, the PREG output is left-shifted 4 bits when transferred into the

ALU or stored, and the 4 LSBs are zero filled. This shift mode is used in conjunction with the MPY instruction with a short immediate value (13 bits or less) to eliminate the four extra sign bits gained when multiplying a16-bit number times a 13-bit number.
- If PM = 112, the PREG output is right-shifted 6 bits, sign extended, when

transferred into the ALU or stored, and the 6 LSBs are lost. This shift mode enables the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow. Note that the product is always sign extended, regardless of the value of the sign extension mode (SXM) bit in ST1.
3-8

Central Arithmetic Logic Unit (CALU)

The PM shifts also occur when the PREG contents are stored to data memory. The PREG contents remain unchanged during the shifts. The LT (load TREG0) instruction loads TREG0, from the data bus, with the first operand; the MPY instruction provides the second operand for multiplication operations. To perfrom a multiplication with a short or long immediate operand, use the MPY instruction with an immediate operand. A product can be obtained every two cycles except when a long immediate operand is used. Four multiply/accumulate instructions (MAC, MACD, MADD, and MADS) fully utilize the computational bandwidth of the multiplier, which allows both operands to be processed simultaneously. The data for these operations can be transferred to the multiplier each cycle via the program and data buses. When any of the four multiply/accumulate instructions are used with the RPT or RPTZ instruction, the instruction becomes a single-cycle multiply/accumulate function. In these repeated instructions, the coefficient addresses are generated by the PC while the data addresses are generated by the ARAU. This allows the RPT instruction to sequentially access the values from the coefficient table and step through the data in any of the indirect addressing modes. The RPTZ instruction also clears the ACC and the PREG to initialize the multiply/ accumulate operation. For example, consider multiplying the row of one matrix times the column of a second matrix: there are 10  10 matrices, MTRX1 points to the beginning of the first matrix, INDX = 10, and the current AR points to the beginning of the second matrix:
RPTZ MAC #9 MTRX1,*0+ ;For i = 0, i < 10, i++ ;PREG=DATA(MTRX1+i) x DATA[MTRX2 + ;(i x INDX)] ;ACC += PREG. ;ACC += PREG.

APAC

The MAC and MACD instructions obtain their coefficient pointer from a long immediate address and are, therefore, 2-word instructions. The MADS and MADD instructions obtain their coefficient pointer from the BMAR and are, therefore, 1-word instructions. When you use the BMAR as a source to the coefficient table, one block of code can support multiple applications, and you can change the long immediate address without modifying executable code. The MACD and MADD instructions include a data move (DMOV) operation that, in conjunction with the fetch of the data multiplicand, writes the data value to the next higher data address.
Central Processing Unit (CPU)
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Central Arithmetic Logic Unit (CALU)

The MACD and MADD instructions, when repeated, support filter constructs (weighted running averages) so that as the sum-of-products operation is executed, the sample data is shifted in memory to make room for the next sample and to throw away the oldest sample. Circular addressing with MAC and MADS instructions can also be used to support filter implementation. In the next example, the current AR points to the oldest of the samples; BMAR points to the coefficient table. In addition to initiating the repeat operation, the RPTZ instruction also clears the ACC and the PREG. In this example, the PC is stored in a temporary register while the repeated operation is executed. Next, the PC is loaded with the value stored in BMAR. The program bus is used to address the coefficients and, as the MADD instruction is repeatedly executed, the PC increments to step through the coefficient table. The ARAU generates the address of the sample data. Indirect addressing with decrement steps through the sample data, starting with the oldest data. As the data is fetched, it is also written to the next higher location in data memory. This operation aligns the data for the next execution of the filter by moving the oldest sample out past the end of the samples array and making room for the new sample at the beginning of the sample array. The previous product of the PREG is added to the ACC, while the two fetched values are multiplied and the new product value is loaded into the PREG. Note that the DMOV portion of the MACD and MADD instructions does not function with external data memory addresses.
RPTZ MADD APAC #9 * ;ACC = PREG = 0. For I = 9 TO 0 Do ;SUM AI x XI. XI+1 = XI. ;FINAL SUM.

The MPYU instruction performs an unsigned multiplication that facilitates extended-precision arithmetic operations. The unsigned contents of TREG0 are multiplied by the unsigned contents of the addressed data memory location; the result is placed in PREG. This allows operands larger than 16 bits to be broken down into 16-bit words and processed separately to generate products larger than 32 bits. The square/add (SQRA) and square/subtract (SQRS) instructions pass the same value to both inputs of the multiplier for squaring a data memory value. After the multiplication of two 16-bit numbers, this 32-bit product is loaded into PREG. The product from the PREG can be transferred to the ALU or to data memory via the store product high (SPH) and store product low (SPL) instructions.
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Central Arithmetic Logic Unit (CALU)

3.2.2

Arithmetic Logic Unit (ALU) and Accumulators

The 32-bit general-purpose ALU and ACC implement a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle. Once an operation is performed in the ALU, the result is transferred to the ACC, where additional operations, such as shifting, can occur. Data that is input to the ALU can be scaled by the prescaler. The following steps occur in the implementation of a typical ALU instruction: 1) Data is fetched from memory on the data bus, 2) Data is passed through the prescaler and the ALU, where the arithmetic is performed, and 3) The result is moved into the ACC. The ALU operates on 16-bit words taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can perform Boolean operations, thereby facilitating the bit manipulation ability required of a high-speed controller. One input to the ALU is always supplied by the ACC. The other input can be transferred from the PREG of the multiplier, the ACCB, or the output of the prescaler (that has been read from data memory or from the ACC). After the ALU has performed the arithmetic or logical operation, the result is stored in the ACC. For the following example, assume that ACC = 0, PREG = 0022 2200h, PM = 002, and ACCB = 0033 3300h:
LACC APAC ADDB #01111h,8 ;ACC = 00111100h. Load ACC from prescaling ;shifter ;ACC = 00333300h. Add to ACC the ;product register. ;ACC = 00666600h. Add to ACC the ;accumulator buffer.

The 32-bit ACC can be split into two 16-bit segments (ACCH and ACCL) for storage in data memory (see Figure 32). A postscaler at the output of the ACC provides a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus for storage. The contents of the ACC remain unchanged. When the postscaler is used on the high word of the ACC (bits 16 31), the MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0 15). When the postscaler is used on the low word, the LSBs are zero filled. For the following example, assume that ACC = FF23 4567h:
SACL SACH TEMP1,7 TEMP2,7 ;TEMP1 = B380h ;TEMP2 = 91A2h ACC = FF234567h. ACC = FF234567h.
3-11

Central Processing Unit (CPU)

Central Arithmetic Logic Unit (CALU)

The C5x supports floating-point operations for applications requiring a large dynamic range. By performing left shifts, the NORM (normalization) instruction normalizes fixed-point numbers contained in the ACC. The four bits of the TREG1 define a variable shift through the prescaler for the add to/load to/subtract from accumulator with shift specified by TREG1 (ADDT/LACT/SUBT) instructions. These instructions denormalize a number (convert it from floating-point to fixed-point) and also execute an automatic gain control (AGC) going into a filter. The single-cycle 1-bit to 16-bit right shift of the ACC can efficiently align its contents. This shift, coupled with the 32-bit temporary buffer on the ACC, enhances the effectiveness of the CALU in extended-precision arithmetic. The ACCB provides a temporary storage place for a fast save of the ACC. The ACCB can also be used as an input to the ALU. The minimum or maximum value in a string of numbers can be found by comparing the contents of the ACCB with the contents of the ACC. The minimum or maximum value is placed in both registers, and, if the condition is met, the carry bit (C) is set. The minimum and maximum functions are executed by the CRLT and CRGT instructions, respectively. These operations are signed arithmetic operations. In the next example, assume that ACC = 1234 5678h and ACCB = 7654 3210h:
CRLT CRGT ;ACC = ACCB = 1234 5678h. C = 1. ;ACC = ACCB = 7654 3210h. C = 0.

The ACC overflow saturation mode can be enabled by setting and disabled by clearing the overflow mode (OVM) bit of ST0. When the ACC is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the ACC is loaded with either the most positive or the most negative value representable in the ACC, depending upon the direction of the overflow. The value of the ACC upon saturation is 7FFF FFFFh (positive) or 8000 0000h (negative). If the OVM bit is cleared and an overflow occurs, the overflowed results are loaded into the ACC without modification. Note that logical operations cannot result in overflow. The C5x can execute a variety of branch instructions that depend on the status of the ALU and the ACC. For example, execution of the instruction BCND can depend on a variety of conditions in the ALU and the ACC. The BACC instruction allows branching to an address stored in the ACC. The bit test instructions (BITT and BIT) facilitate branching on the condition of a specified bit in data memory.

3-12

Central Arithmetic Logic Unit (CALU)

The ACC has an associated carry bit that is set or cleared, depending on various operations within the C5x. The carry bit allows more efficient computation of extended-precision products and additions or subtractions; it is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instructions. The carry bit is not affected by loading the ACC, logical operations, or other nonarithmetic or control instructions. Examples of carry bit operations are shown in Figure 33.

Figure 33. Examples of Carry Bit Operations

C X 1 C X 0 C 1 0 MSB LSB F F F F F F F F ACC + 1 0 0 0 0 0 0 0 0 C X 0 MSB LSB 0 0 0 0 0 0 0 0 ACC 1 F F F F F F F F MSB LSB 8 0 0 0 0 0 0 1 ACC 2(OVM = 0) 7 F F F F F F F MSB LSB F F F F F F F F ACC 1 (SUBB) F F F F F F F D

MSB LSB C 7 F F F F F F F ACC X + 1 (OVM = 0) 8 0 0 0 0 0 0 0 1 MSB LSB 0 0 0 0 0 0 0 0 ACC + 0 (ADDC) 0 0 0 0 0 0 0 1 C 0 1

The value added to or subtracted from the ACC can come from the prescaler, ACCB, or PREG. The carry bit is set if the result of an addition or accumulation process generates a carry; it is cleared if the result of a subtraction generates a borrow. Otherwise, it is cleared after an addition or set after a subtraction. The add to ACC with carry (ADDC) and add ACCB to ACC with carry (ADCB) instructions use the previous value of carry in their addition operation. The subtract from ACC with borrow (SUBB) and subtract ACCB from ACC with borrow (SBBB) instructions use the logical inversion of the previous value of carry. The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to ACCH) and SUB with a shift count of 16 (subtract from ACCH). These instructions can generate a carry or a borrow, but they will not clear a carry or borrow, as is normally the case if a carry or borrow is not generated. This feature is useful for extended-precision arithmetic. Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing according to the status of the carry bit. The CLRC, LST #1, and SETC instructions can be used to load the carry bit. The carry bit is set on a reset. The 1-bit shift to the left (SFL) or right (SFR) and the rotate to the left (ROL) or right (ROR) instructions shift or rotate the contents of the ACC through the
Central Processing Unit (CPU)
3-13

Central Arithmetic Logic Unit (CALU)

carry bit. The SXM bit affects the definition of the shift accumulator right (SFR) instruction. When SXM = 1, SFR performs an arithmetic right shift, maintaining the sign of the ACC data. When SXM = 0, SFR performs a logical shift, shifting out the LSBs and shifting in a 0 for the MSB. The shift accumulator left (SFL) instruction is not affected by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a 0. The RPT and RPTZ instructions can be used with the shift and rotate instructions for multiple-bit shifts. The SFLB, SFRB, RORB, and ROLB instructions can shift or rotate the 65-bit combination of the ACC, ACCB, and carry bit as described above. The ACC can also be shifted 031 bits right in two instruction cycles or 116 bits right in one cycle. The bits shifted out are lost, and the bits shifted in are either 0s or copies of the original sign bit, depending on the value of the SXM bit. A shift count of 1 to 16 is embedded in the instruction word of the BSAR instruction. For example, let ACC = 1234 5678h:
BSAR 7 ;ACC = 0246 8ACEh.

The right shift can also be controlled via TREG1. The SATL instruction shifts the ACC by 015 bits, as defined by bits 03 of TREG1. The SATH instruction shifts the ACC 16 bits to the right if bit 4 of TREG1 is a 1. The following code sequence executes a 0- to 31-bit right shift of the ACC, depending on the shift count stored at SHIFT. For example, consider the value stored at SHIFT = 01Bh and ACC = 1234 5678h:
LMMR SATH SATL TREG1,SHIFT ;TREG1 = shift count 0 31. TREG1 = 1B ;If shift count > 15, then ACC >> 16 ;ACC = 00001234 ;ACC >> shift count. ACC = 0000 0002

3.2.3

Scaling Shifters and Temporary Register 1 (TREG1)

The prescaler has a 16-bit input connected to the data bus and a 32-bit output connected to the ALU (see Figure 32). The prescaler produces a left shift of 0 to 16 bits on the input data. The shift count is specified by a constant embedded in the instruction word or by the value in TREG1. The LSBs of the output are filled with 0s; the MSBs can be filled with 0s or sign-extended, depending upon the value of the SXM bit of ST1. The p-scaler and postscaler make it possible for the CALU to perform numerical scaling, bit extraction, extended-precision arithmetic, and overflow prevention. These shifters are connected to the output of the PREG and the ACC (see Figure 32 on page 3-8).

3-14

Parallel Logic Unit (PLU)

3.3

Parallel Logic Unit (PLU)

The parallel logic unit (PLU) can directly set, clear, test, or toggle multiple bits in a control/status register or any data memory location. The PLU provides a direct logic operation path to data memory values without affecting the contents of the ACC or the PREG (see Figure 34). The PLU executes a read-modify-write operation on data stored in data space. First, one operand is fetched from data memory space, and the second is fetched from a long immediate on the program bus or from the dynamic bit manipulation register (DBMR). Then, the PLU executes a logical operation on the two operands as defined by the instruction. The result is written to the same data memory location from which the first operand was fetched.

Figure 34. Parallel Logic Unit Block Diagram

Data Bus

DBMR

MUX

PLU

Note:

All registers and data lines are 16-bits wide unless otherwise specified.

The PLU makes it possible to directly manipulate bits in any location in data memory space by ANDing, ORing, exclusive-ORing, or loading a 16-bit long immediate value to a data location. For example, to use AR1 for circular buffer 1 and AR2 for circular buffer 2 but not enable the circular buffers, initialize the circular buffer control register (CBCR) by executing the following code:
SPLK #021h,CBCR ;Store peripheral long immediate ;(DP = 0).

Next, enable circular buffers 1 and 2 by executing the code:

OPL #088h,CBCR ;Set bit 7 and bit 3 in CBCR.
Central Processing Unit (CPU)
3-15

Program Bus

Parallel Logic Unit (PLU)

To test for individual bits in a specific register or data word, use the BIT instruction; however, to test for a pattern of bits, use the compare parallel long immediate (CPL) instruction. If the data value is equal to the long immediate value, then the test/control (TC) bit in ST1 is set. The TC bit is set if the result of any PLU instruction is 0. The set, clear, and toggle functions can be executed with a 16-bit dynamic register value instead of the long immediate value. This is done with the following three instructions: AND DBMR register to data (APL), OR DBMR register to data (OPL), and exclusive-OR DBMR register to data (XPL). The TC bit is also set by the APL, OPL, and XPL instructions if the result of the PLU operation (value written back into data memory) is 0. This allows bits to be tested and cleared simultaneously. For example,
APL BCND #0FF00h,TEMP HIGH_BITS_SET,NTC ;Clear low byte and check for ;bits set in high byte. ;If bits active in high byte, ;then branch.

or
XPL BCND #1,TEMP BIT_SET,TC ;Toggle bit 0. ;If bit was set, branch. If not, ;bit set now.

In the first example, the low byte of a flag word is cleared while the high byte is checked for any active flags (bits = 1). If none of the flags in the high byte is set, then the resulting APL operation yields a 0 to TEMP and the TC bit is set. If any of the flags in the high byte are set, then the resulting APL operation yields a nonzero value to TEMP and the TC bit is cleared. Therefore, the conditional branch (BCND) following the APL instruction branches if any of the bits in the high byte are nonzero. The second example tests the flag. If the flag is low, the flag is set high; if the flag is high, the flag is cleared and the branch is taken. The PLU instructions can operate anywhere in data address space, so they can operate with flags stored in RAM locations as well as in control registers for both on- and off-chip peripherals. The PLU instructions are listed in Table 66 on page 6-14.

3-16

Auxiliary Register Arithmetic Unit (ARAU)

3.4 Auxiliary Register Arithmetic Unit (ARAU)

The auxiliary register file contains eight memory-mapped auxiliary registers (AR0AR7), which can be used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary register addressing (see Figure 35) allows placement of the data memory address of an instruction operand into one of the AR. The ARs are pointed to by a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 07, designating AR0AR7, respectively. The ARs and the ARP can be loaded from data memory, the ACC or the PREG or by an immediate operand defined in the instruction. The contents of the ARs can be stored in data memory or used as inputs to the CALU. The memory-mapped ARs reside in data page 0, as described in subsection 8.3.2, Local Data Memory Address Map, on page 8-17. The auxiliary register file (AR0AR7) is connected to the auxiliary register arithmetic unit (ARAU), shown in Figure 36. The ARAU can autoindex the current AR while the data memory location is being addressed; it indexes either by 1 or by the contents of the index register (INDX). As a result, the CALU is not needed for address manipulation when tables of information are accessed; it is free for other operations in parallel. For more advanced address manipulation, such as multidimensional array addressing, the CALU can directly read from or write to the ARs.

Figure 35. Indirect Auxiliary Register Addressing Example

Auxiliary Register File AR0 Auxiliary Register Pointer (in ST0) ARP 0 1 1 AR1 AR2 AR3 AR4 AR5 AR6 AR7 0 5 3 7 h 5 1 5 0 h 0 E 9 F C h 0 F F 3 A h 1 0 3 B h 2 6 B 1 h 0 0 0 8 h 8 4 3 D h 0 FF3 Ah 0 FFFFh 3121h Data Memory Map Location 00 0 0 h

Central Processing Unit (CPU)

3-17

Auxiliary Register Arithmetic Unit (ARAU)

Figure 36. Auxiliary Register Arithmetic Unit

A15A0 To Program Control MUX 3 3 3 MUX

ST0 ARP(3)

ST1 ARB(3)

Data Bus

16 ARAU MUX

MUX SARAM DARAM B0

MUX DARAM B2 B1

Notes: All registers and data lines are 16-bits wide unless otherwise specified.

The ARAU updates the ARs during the decode phase (second stage) of the pipeline, while the CALU writes during the execution phase (fourth stage). Therefore, the two instructions that immediately follow the CALU write to an AR should not use the same AR for address generation. See Chapter 7, Pipeline, for more details.

As shown in Figure 36, the INDX, auxiliary register compare register (ARCR), or eight LSBs of the instruction register (IREG) can be used as one of the inputs to the ARAU. The other input is provided by the contents of the current AR pointed to by ARP. Table 32 defines the functions of the ARAU.
3-18

Program Bus

AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 CBCR(8) CBSR1 CBSR2 CBER1 CBER2 INDX ARCR

IREG

DRB

Auxiliary Register Arithmetic Unit (ARAU)

Table 32. Auxiliary Register Arithmetic Unit Functions

Function Current AR + INDX Current AR Current AR INDX Current AR Current AR + 1 Current AR Current AR 1 Current AR Current AR Current AR Current AR + IR(70) Current AR Current AR IR(70) Current AR Current AR + rc(INDX) Current AR Current AR rc(INDX) Current AR If (Current AR) = (ARCR), then TC = 1 If (Current AR) < (ARCR), then TC = 1 If (Current AR) > (ARCR), then TC = 1 If (Current AR) (ARCR), then TC = 1 If (Current AR) = (CBER), then Current AR = CBSR Description Index the current AR by adding an unsigned 16-bit integer contained in INDX. Example: ADD *0+ Index the current AR by subtracting an unsigned 16-bit integer contained in INDX. Example: ADD *0 Increment the current AR by 1. Example: ADD *+ Decrement the current AR by 1. Example: ADD * Do not modify the current AR. Example: ADD * Add an 8-bit immediate value to current AR. Example: ADRK #55h Subtract an 8-bit immediate value from the current AR. Example: SBRK #55h Bit-reversed indexing; add INDX with reversed-carry (rc) propagation. Example: ADD *BR0+ Bit-reversed indexing; subtract INDX with reversedcarry (rc) propagation. Example: ADD *BR0 Compare the current AR to ARCR and, if the condition is true, then set the TC bit of the status register ST1. If false, then clear the TC bit. Example: CMPR 3 If the current AR is at the end of circular buffer, reload the start address. The test for this condition is performed before the execution of the AR modification. Example: ADD *+

The INDX can be added to or subtracted from the current AR on any AR update cycle. The INDX can be used to increment or decrement the address in steps larger than 1; this is useful for operations such as addressing down a matrix column. The ARCR limits blocks of data and supports logical comparisons between the current AR and ARCR in conjunction with the CMPR instruction. Note that the C2x uses AR0 for this implementation. After reset, you can use the load auxiliary register (LAR) instruction to load AR0; if the enable extra index register (NDX) bit in the PMST is set, LAR also loads INDX and ARCR to maintain compatibility with the C2x.
Central Processing Unit (CPU)
3-19

Auxiliary Register Arithmetic Unit (ARAU)

Because the ARs are memory-mapped, the CALU can act directly upon them and use more advanced indirect addressing techniques. For example, the multiplier can calculate the addresses of 3-dimensional matrices. After a CALU load of the AR, there is, however, a 2-instruction-cycle delay before the ARs can be used for address generation. The INDX and ARCR are accessible via the CALU, regardless of the condition of the NDX bit (that is, SAMM ARCR writes only to the ARCR). The ARAU can serve as an additional general-purpose arithmetic unit because the auxiliary register file can directly communicate with data memory. The ARAU implements 16-bit unsigned arithmetic, whereas the CALU implements 32-bit 2s-complement arithmetic. The BANZ and BANZD instructions permit the ARs to be used as loop counters. The 3-bit auxiliary register pointer buffer (ARB), shown in Figure 36, stores the ARP on subroutine calls when the automatic context switch feature of the C5x is not used. Two circular buffers can operate at a given time and are controlled via the circular buffer control register (CBCR). Upon reset (rising edge of RS), both circular buffers are disabled. To define a circular buffer, load CBSR1 or CBSR2 with the start address of the buffer and CBER1 or CBER2 with the end address; then load the AR to be used with the circular buffer with an address between the start and end addresses. Finally, load CBCR with the appropriate AR number and set the enable (CENB1 or CENB2) bit.

Do not use the same AR to access both circular buffers or unexpected results will occur.

As the address is stepping through the circular buffer, the AR value is compared against the value contained in CBER prior to the update to the AR value. If the current AR value and the CBER are equal and an AR modification occurs, the value contained in CBSR is automatically loaded into the AR. If the values in the CBER and the AR are not equal, the AR is modified as specified. Circular buffers can be used with either increment- or decrement-type updates. If increment is used, then the value in CBER must be larger than the value in CBSR. If decrement is used, the value in CBER must be smaller than the value in CBSR. The other indirect addressing modes can be used; however, the ARAU tests only for the condition current AR = CBER. The ARAU does not detect an AR update that steps over the value contained in CBER. See Section 5.6, Circular Addressing, on page 5-21 for more details.
3-20

Summary of Registers

3.5 Summary of Registers

CPU registers (except ST0 and ST1), peripheral registers, and I/O ports occupy data memory space.

3.5.1

Auxiliary Registers (AR0AR7)

The eight 16-bit auxiliary registers (AR0AR7) can be accessed by the CALU and modified by the ARAU or the PLU. The primary function of the ARs is to provide a 16-bit address for indirect addressing to data space. However, the ARs can also be used as general-purpose registers or counters. Section 5.2, Indirect Addressing, on page 5-4 describes how the ARs are used in indirect addressing. Use of ARs is described in Section 3.4 on page 3-17.

3.5.2

Auxiliary Register Compare Register (ARCR)

The 16-bit ARCR is used for address boundary comparison. The CMPR instruction compares the ARCR to the selected AR and places the result of the compare in the TC bit of ST1. Section 5.2, Indirect Addressing, on page 5-4 describes how the ARCR can be used in memory management. See also Section 3.4 on page 3-17.

3.5.3

Block Move Address Register (BMAR)

The 16-bit BMAR holds an address value to be used with block moves and multiply/accumulate operations. This register provides the 16-bit address for an indirect-addressed second operand. See Section 5.4, Dedicated-Register Addressing, on page 5-17.

3.5.4

Block Repeat Registers (RPTC, BRCR, PASR, PAER)

The 16-bit repeat counter register (RPTC) holds the repeat count in a repeat single-instruction operation and is loaded by the RPT and RPTZ instructions. See Section 4.6, Single Instruction Repeat Function, on page 4-22.

Although the RPTC is a memory-mapped register, you should avoid writing to this register. Writing to this register can cause undesired results.

Central Processing Unit (CPU)

3-21

Summary of Registers

The 16-bit block repeat counter register (BRCR) holds the count value for the block repeat feature. This value is loaded before a block repeat operation is initiated. The value can be changed while a block repeat is in progress; however, take care to avoid infinite loops. The block repeat program address start register (PASR) indicates the 16-bit address where the repeated block of code starts. The block repeat program address end register (PAER) indicates the 16-bit address where the repeated block of code ends. The PASR and PAER are loaded by the RPTB instruction. Block repeats are described in Section 4.7, Block Repeat Function, on page 4-31.

3.5.5

Buffered Serial Port Registers (ARR, AXR, BKR, BKX, SPCE)

The buffered serial port (BSP) is available on C56 and C57 devices. The BSP comprises a full-duplex, double-buffered serial port interface and an autobuffering unit (ABU). The BSP has a 2K-word buffer, which resides in the C5x internal memory. Five registers control and operate the BSP. The 16-bit BSP control extension register (SPCE) contains the mode control and status bits of the BSP. The 11-bit BSP address receive register (ARR) and 11-bit BSP receive buffer size register (BKR) support address generation for writing to the data receive register (DRR) in the C5x internal memory. The 11-bit BSP address transmit register (AXR) and 11-bit BSP transmit buffer size register (BKX) support address generation for reading a word from the C5x internal memory to the data transmit register (DXR). The BSP is described in Section 9.8, Buffered Serial port (BSP) Interface, on page 9-53.

3.5.6

Circular Buffer Registers (CBSR1, CBER1, CBSR2, CBER2, CBCR)

The C5x devices support two concurrent circular buffers operating in conjunction with user-specified auxiliary registers. Two 16-bit circular buffer start registers (CBSR1 and CBSR2) indicate the address where the circular buffer starts. Two 16-bit circular buffer end registers (CBER1 and CBER2) indicate the address where the circular buffer ends. The 16-bit circular buffer control register (CBCR) controls the operation of these circular buffers and identifies the auxiliary registers to be used. Section 5.6, Circular Addressing, on page 5-21 describes how circular buffers can be used in memory management. Section 3.4 on page 3-17 describes how circular buffer registers are used in addressing. See also subsection 4.4.1, Circular Buffer Control Register (CBCR), on page 4-6.

3.5.7

Dynamic Bit Manipulation Register (DBMR)

The 16-bit DBMR is used in conjunction with the PLU as a dynamic (executiontime programmable) mask register. The DBMR is described in Section 3.3 on page 3-15.

3-22

Summary of Registers

3.5.8

Global Memory Allocation Register (GREG)

The 16-bit GREG allocates parts of the local data space as global memory and defines what amount of the local data space will be overlayed by global data space. See Section 8.4, Global Data Memory, on page 8-20.

3.5.9

Host Port Interface Registers (HPIC, HPIA)

The 8-bit wide parallel host port interface (HPI) is available on the C57 device. The HPI interfaces a host processor to the C57 device. The HPI control register (HPIC) holds the control word. The host processor addresses HPI memory via the HPI address register (HPIA). See Section 9.10, Host Port Interface (C57S and LC57 only), on page 9-87.

3.5.10 Index Register (INDX)

The 16-bit INDX is used by the ARAU as a step value (addition or subtraction by more than 1) to modify the address in the ARs during indirect addressing. For example, when the ARAU steps across a row of a matrix, the indirect address is incremented by 1. However, when the ARAU steps down a column, the address is incremented by the dimension of the matrix. The ARAU can add or subtract the value stored in the INDX from the current AR as part of the indirect address operation. INDX can also map the dimension of the address block used for bit-reversal addressing. Section 5.2, Indirect Addressing, on page 5-4 describes how the INDX can be used in memory management. See also Section 3.4 on page 3-17.

3.5.11 I/O Space (PA0PA15)

The I/O space makes it possible to address 16 locations (50h5Fh) of I/O space via the addressing modes of the local data space. This means that these locations can be read directly into the CALU or written from the ACC. It also means that these locations can be acted upon by the PLU or addressed via the memory-mapped addressing mode. The locations can also be addressed with the IN and OUT instructions.

3.5.12 Instruction Register (IREG)

The 16-bit IREG holds the opcode of the instruction being executed. The IREG is used during program control.

3.5.13 Interrupt Registers (IMR, IFR)

The 16-bit interrupt mask register (IMR) individually masks specific interrupts at required times. The 16-bit interrupt flag register (IFR) indicates the current status of the interrupts. The status of the interrupts is updated regardless of the IMR and INTM bit in the ST0. Interrupts are described in Section 4.8, Interrupts, on page 4-36.
Central Processing Unit (CPU)
3-23

Summary of Registers

3.5.14 Processor Mode Status Register (PMST)

The 16-bit PMST contains status and control information for the C5x device. Subsection 8.2.1, Program Memory Configurability, on page 8-7 and subsection 8.3.1, Local Data Memory Configurability, on page 8-15 describe how the PMST configures memory. See also subsection 4.4.2, Processor Mode Status Register (PMST), on page 4-7.

3.5.15 Product Register (PREG)

The 32-bit PREG holds the result of a multiply operation. The high and low words of PREG can be accessed individually. See subsection 3.2.1 on page 3-7.

3.5.16 Serial Port Interface Registers (SPC, DRR, DXR, XSR, RSR)
Five registers control and operate the serial port interface. The 16-bit serial port control register (SPC) contains the mode control and status bits of the serial port. The 16-bit data receive register (DRR) holds the incoming serial data, and the 16-bit data transmit register (DXR) holds the outgoing serial data. The 16-bit data transmit shift register (XSR) controls the shifting of the data from the DXR to the output pin. The 16-bit data receive shift register (RSR) controls the storing of the data from the input pin to the DRR. The serial port is described in Section 9.7, Serial Port Interface, on page 9-23.

3.5.17 Software-Programmable Wait-State Registers (PDWSR, IOWSR, CWSR)

The software wait states are determined by three registers. These registers serve different purposes on different devices. On most C5x devices the 16-bit program/data wait-state register (PDWSR) contains the wait-state count for the eight 16K-word blocks of program and data memory. The PDWSR is divided into eight 2-bit wait-state fields assigned to each 16K-word block. The I/O space is mapped into the 16-bit I/O wait-state register (IOWSR) under control of the 5-bit wait-state control register (CWSR). The CWSR determines the range of wait states selected. The BIG bit in the CWSR determines how the I/O space is partitioned. If the BIG bit is cleared, the IOWSR is divided into eight pairs of I/O ports with the 2-bit wait-state fields assigned to each pair of port addresses. If the BIG bit is set, the I/O space is divided into eight 8K-word blocks with each having its own 2-bit wait-state field, similar to PDWSR. For the C52, LC56, C57S, and LC57 devices, the program, data, and I/O space wait states are each specified by a single (3-bit) wait-state value. Each memory space can be independently set to 07 wait states by a 3-bit wait-state field in PDWSR. See Section 9.4, Software-Programmable Wait-State Generators, on page 9-13.
3-24

Summary of Registers

3.5.18 Status Registers (ST0, ST1)

The two 16-bit status registers contain status and control bits for the CPU and are described in subsection 4.4.3, Status Registers (ST0 and ST1), on page 4-10.

3.5.19 Temporary Registers (TREG0, TREG1, TREG2)

The 16-bit TREG0 holds one of the multiplicands of the multiplier. TREG0 can also be loaded via the CALU with the following instructions: LT, LTA, LTD, LTP, LTS, SQRA, SQRS, MAC, MACD, MADS, and MADD. The 5-bit TREG1 holds a dynamic (execution-time programmable) shift count for the prescaling shifter. The 4-bit TREG2 holds a dynamic bit address for the BITT instruction. The TREG0 is described in subsection 3.2.1 on page 3-7. Software compatibility can be maintained with the C2x by clearing the enable multiple TREGs (TRM) bit in the PMST. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x.

3.5.20 Timer Registers (TIM, PRD, TCR)

Three registers control and operate the timer. The timer counter register (TIM) gives the current count of the timer. The timer period register (PRD) defines the period for the timer. The 16-bit timer control register (TCR) controls the operations of the timer. See Section 9.3, Timer, on page 9-9.

3.5.21 TDM Serial Port Registers (TRCV, TDXR, TSPC, TCSR, TRTA, TRAD, TRSR)
The time-division-multiplexed (TDM) serial port interface is a feature superset of the serial port interface and supports applications that require serial communication in a multiprocessing environment. Six registers control and operate the TDM serial port interface. The 16-bit TDM serial port control register (TSPC) contains the mode control and status bits of the TDM serial port interface. The 16-bit TDM data receive register (TRCV) holds the incoming TDM serial data, and the 16-bit TDM data transmit register (TDXR) holds the outgoing TDM serial data. The 16-bit TDM data receive shift register (TRSR) controls the storing of the data, from the input pin, to the TRCV. The 16-bit TDM channel select register (TCSR) specifies in which time slot(s) each C5x device is to transmit. The 16-bit TDM receive/transmit address register (TRTA) specifies in the eight LSBs (RA0RA7) the receive address of the C5x device and in the eight MSBs (TA0TA7) the transmit address of the C5x device. The 16-bit TDM receive address register (TRAD) contains various information regarding the status of the TDM address line (TADD). See Section 9.9, Time-Division Multiplexed (TDM) Serial Port Interface, on page 9-74.
Central Processing Unit (CPU)
3-25

Chapter 4

Program Control
Program control on the TMS320C5x is provided by the program counter, hardware stack, repeat counters, status registers, program counter-related hardware, and several software mechanisms. Software mechanisms used for program control include branches, calls, conditional instructions, repeat instructions, reset, and interrupts.

Topic
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Page
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Hardware Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Program-Memory Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Single Instruction Repeat Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Block Repeat Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45

4.10 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50

Program Control

4-1

Program Counter (PC)

4.1 Program Counter (PC)

The C5x has a 16-bit program counter (PC) which contains the address of internal or external program memory used to fetch instructions. The PC addresses program memory, either on-chip or off-chip, via the program address bus (PAB). Through the PAB, an instruction is loaded into the instruction register (IREG). Then the PC is ready to start the next instruction fetch cycle. Refer to Figure 41 for a functional block diagram of the program control elements. The PC is loaded in a number of ways. Table 41 shows what address is loaded into the PC, depending on the code operation performed.

Figure 41. Program Control Functional Block Diagram

CLKMD1 CLKMD2 CLKMD3 IS DS PS RW STRB READY BR XF HOLD HOLDA IAQ BIO RS IACK MP/MC INT(14) Program Address Bus

Controller

X1 CLKOUT1 X2/CLKIN CLKIN2

PFC PAER MUX Compare MCS PC PASR IREG BMAR ST0 ST1 PMST RPTC IMR IFR GREG BRCR TREG2(4)

RD WE NMI Address Program ROM Instruction Stack (8x16)

MUX

A15A0

To ARAU

RBIT MUX

D15D0

Data Bus

DP(9)

ST0

Notes: All registers and data lines are 16 bits wide unless otherwise specified.

4-2

Program Counter (PC)

Table 41. Address Loading Into the Program Counter

Code Operation Sequential code Branch (B instruction) Subroutine call Address Loaded to the PC The PC is loaded with PC + 1. The PC is loaded with the long immediate value directly following the branch instruction. The PC + 2 is pushed onto the stack and then the PC is loaded with the long immediate value directly following the call instruction. The return instruction pops the stack back into the PC to return to the calling or interrupting sequence of code. The PC is loaded with the address of the appropriate interrupt vector. The content of the accumulator low byte (ACCL) is loaded into the PC. The BACC (branch to location specified by the accumulator) or CALA (call subroutine at location specified by the accumulator) instructions can be used to perform GOTO operations. The PC is loaded with the a long immediate address.

Software (INTR, TRAP, or NMI instruction) or interrupt trap Computed GOTO

BLDD, BLDP, BLPD, MAC, or MACD instruction BACC, BACCD, CALA, TBLR, or TBLW instruction BLDD, BLDP, BLPD, MADD, or MADS instruction End of a block repeat loop Return instruction

The PC is loaded with the contents of the accumulator low byte (ACCL). The PC is loaded with the content of the block move address register (BMAR). The PC is loaded with the content of the block repeat program address start register (PASR). The PC is loaded with the top of the stack.

The PC can also be loaded with coefficients residing in program memory for some instructions used with the repeat operation (see Section 4.6, Single Instruction Repeat Function, on page 4-22). In a repeat operation, once the instruction is repeated, it is no longer prefetched, and the PC can be used to address program memory sequentially. The multiply/accumulate instructions (MAC, MACD, MADD, and MADS), memory move from data-to-data instruction (BLDD), memory move from program-to-data instructions (BLPD and TBLR), and memory move from data-to-program instructions (BLDP and TBLW), use this capability.
Program Control
4-3

Hardware Stack

4.2 Hardware Stack

The stack which is 16 bits wide and 8 levels deep, is accessible via the PUSH and POP instructions. Whenever the contents of the PC are pushed onto the top of the stack (TOS), the previous contents of each level are pushed down, and the bottom (eighth) location of the stack is lost. Therefore, data is lost if more than eight successive pushes occur before a pop. The reverse happens on pop operations. Any pop after seven sequential pops yields the value at the bottom stack level, and then all of the stack levels contain the same value. Two additional instructions PSHD (push a data memory value onto TOS) and POPD (pop a value from TOS to data memory) are also available. These instructions allow a stack to be built in data memory for the nesting of subroutines and interrupts beyond eight levels. The software can use the stack to save and restore context or for other purposes through the following software instructions:
- POP, which pops a value from the stack to the accumulator low byte - POPD, which pops a value from the stack to a data memory address - PSHD, which pushes a data-memory value into the stack - PUSH, which pushes the contents of the accumulator low byte into the

stack The stack is used during interrupts and subroutines to save and restore the PC contents. When a subroutine is called (CALA, CALAD, CALL, CALLD, CC, or CCD instruction) or an interrupt occurs (hardware interrupt, NMI, INTR, or TRAP instruction), the return address is automatically saved in the stack (a PUSH operation). When a subroutine returns (RET, RETC, RETCD, RETD, RETE, or RETI instruction), the return address is retrieved from the stack (a POP operation) and loaded into the PC.

4-4

Program-Memory Address Generation

4.3 Program-Memory Address Generation

The program memory space contains the code for applications and holds table information and immediate operands. The program memory is accessed only by the program address bus (PB). The address for this bus is generated by the program counter (PC) when instructions and long immediate operands are accessed. The PB can also be loaded with a long immediate operand and the lower 16-bit word of the accumulator for block transfers, multiply/accumulates, table reads and writes, branching, and subroutine calls. The C5x fetches instructions by putting the PC on the PAB and reading the appropriate location in memory. While the read is executing, the PC is incremented for the next fetch. If a program address discontinuity (for example, a branch, a call, a return, an interrupt, or a block repeat) occurs, the appropriate address is loaded into the PC. The PC is also loaded when operands are fetched from program memory. Operands are fetched from program memory when the C5x reads from (TBLR) or writes to (TBLW) a table or when it transfers data to (BLPD) or from (BLDP) data space. Some instructions (MAC, MACD, MADD, and MADS) use the program bus to fetch a second multiplicand. The PC can address data stored in either program or data space. This makes it possible, within repeated instructions, to fetch a second operand in parallel with the data bus for 2-operand operations. For repeated instructions, the array is sequentially accessed by the PAB by incrementing the PC. The block transfer instructions (BLDD, BLDP, and BLPD) use both buses so that the pipeline structure can read the next operand while writing to the current one. The BLPD instruction loads the PC with either the long immediate address or with the BMAR contents and then uses the PB to fetch the source data from program space for the block move operation. The BLDP executes in the same way, except that the PAB is used for the destination operation. The BLDD instruction uses the PAB to address data space. The TBLR and TBLW instructions operate like the BLPD and BLDP instructions, respectively, except that the PC is loaded with the accumulator low byte instead of the long immediate address or the BMAR contents. This allows lookup table operations. The multiply/accumulate operations (MAC, MACD, MADD, and MADS) use the PAB to address their coefficient table. The MAC and MACD instructions load the PC with the long immediate address following the instruction. The MADD and MADS instructions load the PC with BMAR contents. For a more detailed explanation of how the program address is loaded into the PC, see Section 4.1, Program Counter, on page 4-2. See also Section 4.6, Single Instruction Repeat Function, on page 4-22, and Chapter 6, Assembly Language Instructions, for more information.
Program Control
4-5

Status and Control Registers

4.4 Status and Control Registers

The C5x has four status and control registers:
- Circular buffer control register (CBCR) and processor mode status regis-

ter (PMST) contain status and control information. Since these registers are memory-mapped, they can be stored into and loaded from data memory; therefore, the status of the CPU can be saved and restored for subroutines and interrupt service routines (ISRs).
- Status registers ST0 and ST1 contain the status of various conditions and

modes compatible with the C2x.

4.4.1

Circular Buffer Control Register (CBCR)

The CBCR resides in the memory-mapped register space of data memory page 0 and can be saved in the same way as any other data memory location. The CBCR can be acted upon directly by the CALU and the PLU. The CALU and the PLU operations change the status register bits during the execution phase of the pipeline. The next two instructions after a status register update must not be affected by the reconfiguration caused by the status update. Table 710 on page 7-24 shows the required latencies between instructions and register accesses. The CBCR bits are shown in Figure 42 and defined in Table 42. Do not use the same AR to access both circular buffers or unexpected results will occur.

4-6

Status and Control Registers

Figure 42. Circular Buffer Control Register (CBCR) Diagram

158 7 64 3 20 Reserved CENB2 CAR2 CENB1 CAR1

Table 42. Circular Buffer Control Register (CBCR) Bit Summary

Bit 158 7 Name Reserved CENB2 Reset value 0

Function
These bits are reserved. Circular buffer 2 enable bit. This bit enables/disables circular buffer 2. CENB2 = 0 CENB2 = 1 Circular buffer 2 is disabled. Circular buffer 2 is enabled.

64 3

CAR2 CENB1

Circular buffer 2 auxiliary register bits. These bits select which auxiliary register (AR0AR7) is assigned to circular buffer 2. Circular buffer 1 enable bit. This bit enables/disables circular buffer 1. CENB1 = 0 CENB1 = 1 Circular buffer 1 is disabled. Circular buffer 1 is enabled.

20

CAR1

Circular buffer 1 auxiliary register bits. These bits select which auxiliary register (AR0AR7) is assigned to circular buffer 1.

4.4.2

Processor Mode Status Register (PMST)

The PMST resides in the memory-mapped register space of data memory page 0 and can be saved in the same way as any other data memory location. The PMST can be acted upon directly by the CALU and the PLU. The CALU and the PLU operations change the status register bits during the execution phase of the pipeline. The next two instructions after a status register update must not be affected by the reconfiguration caused by the status update. The PMST has an associated 1-level deep shadow register stack for automatic context-saving when an interrupt trap is taken. The PMST is automatically restored upon a return from interrupt (RETI) or return from interrupt with interrupt enable (RETE) instruction. Table 710 on page 7-24 shows the required latencies between instructions and register accesses. The PMST bits are shown in Figure 43 and defined in Table 43.
Program Control
4-7

Status and Control Registers

Figure 43. Processor Mode Status Register (PMST) Diagram

1511 IPTR 10 0 9 0 8 0 7 6 0 5 4 3 2 1 0 AVIS OVLY RAM MP/MC NDX TRM BRAF

Table 43. Processor Mode Status Register (PMST) Bit Summary

Bit 1511 Name IPTR Reset value 00000

Function
Interrupt vector pointer bits. These bits select any of 32 2K-word pages where the interrupt vectors reside. The interrupt vectors can be remapped to RAM for bootloaded operations by loading the IPTR bits. At reset, the IPTR bits are cleared; therefore, the reset vector always resides at address 0h in program memory space. These bits are read as 0. Address visibility bit. This bit enables/disables the internal program address to be visible at the address pins. AVIS = 0 The internal program address is driven to the pins so that the address can be traced and the interrupt vector can be decoded in conjunction with IACK when the interrupt vectors reside in on-chip memory. The address lines do not change with the internal program address. The control and data lines are not affected and the address bus is driven with the last address on the bus.

108 7 AVIS

000 0

AVIS = 1

6 5 OVLY

0 0

This bit is read as 0. RAM overlay bit. This bit enables/disables the on-chip single-access RAM (SARAM) to be addressable in data memory space. The OVLY bit is used in conjunction with the RAM bit to configure the on-chip SARAM. See Table 44 on page 4-10 for specific mappings of the on-chip SARAM. OVLY = 0 OVLY = 1 The on-chip SARAM is not addressable in data memory space. The on-chip SARAM is mapped into data memory space.

RAM

Program RAM enable bit. This bit enables/disables the on-chip single-access RAM (SARAM) to be addressable in program memory space. The RAM bit is used in conjunction with the OVLY bit to configure the on-chip SARAM. See Table 44 on page 4-10 for specific mappings of the on-chip SARAM. RAM = 0 RAM = 1 The on-chip SARAM is not addressable in program memory space. The on-chip SARAM is mapped into program memory space.

MP/MC is the logic level of MP/MC pin reset value.

4-8

Status and Control Registers

Table 43. Processor Mode Status Register (PMST) Bit Summary (Continued)
Bit 3 Name MP/MC Reset value

Function
Microprocessor/microcomputer bit. This bit enables/disables the on-chip ROM to be addressable in program memory space. At reset, the MP/MC bit is set to the value corresponding to the logic level on the MP/MC pin. The level on the MP/MC pin is sampled at reset only and can have no effect until the next reset. MP/MC = 0 MP/MC = 1 The on-chip ROM is mapped into program memory space. The on-chip ROM is not addressable in program memory space.

NDX

Enable extra index register bit. This bit determines whether a C2x-compatible instruction that modifies or writes to auxiliary register 0 (AR0) also modifies or writes to the index register (INDX) and the auxiliary register compare register (ARCR) to maintain C5x object-code compatibility with the TMS320C2x. NDX = 0 C2x-compatible mode. Any C2x-compatible instruction that modifies or writes AR0 also modifies or writes the INDX and ARCR because the C2x uses AR0 for indexing and AR compare operations. C5x-enhanced mode. Any C2x-compatible instruction does not affect the INDX and ARCR. The C2x-compatible instructions affect only AR0 of the C5x.

NDX = 1

TRM

Enable multiple TREGs bit. This bit determines whether a C2x-compatible instruction that loads TREG0 also loads TREG1 and TREG2 to maintain C5x object-code compatibility with the TMS320C2x. TRM = 0 C2x-compatible mode. Any C2x-compatible instruction that loads TREG0 also loads TREG1 and TREG2 because the C2x uses TREG as a shift count for the prescaling shifter and as a bit address in the BITT instruction. C5x-enhanced mode. Any C2x-compatible instruction does not load TREG1 and TREG2. The C2x-compatible instructions affect only TREG0 of the C5x.

TRM = 1

BRAF

Block repeat active flag bit. This bit indicates that a block repeat is currently active. BRAF = 0 The block repeat is deactivated. The BRAF bit is cleared when the block repeat counter register (BRCR) decrements below 0. The block repeat is active. The BRAF bit is automatically set when an RPTB instruction is executed.

BRAF = 1

MP/MC is the logic level of MP/MC pin reset value.

Program Control

4-9

Status and Control Registers

Table 44. On-Chip RAM Configuration Using OVLY and RAM Bits
Bit values OVLY 0 0 1 1 RAM 0 1 0 1 On-Chip SARAM Configuration Disabled. The on-chip SARAM is not addressable. The on-chip SARAM is mapped into program space. The on-chip SARAM is mapped into data space. The on-chip SARAM is mapped into both program and data spaces.

4.4.3

Status Registers (ST0 and ST1)

The status registers can be stored into data memory and loaded from data memory, thereby allowing the C5x status to be saved and restored for subroutines. The LST instruction writes to ST0 and ST1, and the SST instruction reads from them, except that the ARP bits and INTM bit are not affected by the LST #0 instruction. Unlike the PMST and CBCR, the ST0 and ST1 do not reside in the memory map and, therefore, cannot be handled by using the PLU instructions. The ST0 and ST1 each have an associated 1-level deep shadow register stack for automatic context-saving when an interrupt trap is taken. The registers are automatically restored upon a return from interrupt (RETI) or return from interrupt with interrupt enable (RETE) instruction. Note that the INTM bit in ST0 and the XF bit in ST1 are not saved on the stack or restored from the stack on an automatic context save. This feature allows the XF pin to be toggled in an interrupt service routine and also allows automatic context saves. The INTM and OVM bits in ST0 and the C, CNF, HM, SXM, TC, and XF bits in ST1 can be individually set using the SETC instruction or individually cleared using the CLRC instruction. For example, the sign-extension mode (SXM) bit is set with SETC SXM or cleared with CLRC SXM. The DP bits in ST0 can be loaded using the LDP instruction. The PM bits in ST1 can be loaded using the SPM instruction. The ST0 bits are shown in Figure 44 and defined in Table 45.

4-10

Status and Control Registers

Figure 44. Status Register 0 (ST0) Diagram

1513 ARP 12 11 10 1 9 80 DP OV OVM INTM

Table 45. Status Register 0 (ST0) Bit Summary

Bit 1513 Name ARP Reset value X

Function
Auxiliary register pointer. These bits select the auxiliary register (AR) to be used in indirect addressing. When the ARP is loaded, the previous ARP value is copied to the auxiliary register buffer (ARB) in ST1. The ARP can be modified by memory-reference instructions when you use indirect addressing, and by the MAR or LST #0 instruction. When an LST #1 instruction is executed, the ARP is loaded with the same value as the ARB. Overflow flag bit. This bit indicates that an arithmetic operation overflow in the arithmetic logic unit (ALU). The OV bit can be modified by the LST #0 instruction. OV = 0 OV = 1 Overflow did not occur in the ALU. The OV bit is cleared by a reset or a conditional branch (BCND/BCNDD on OV/NOV). Overflow does occur in the ALU. As a latched overflow signal, the OV bit remains set.

12

OV

11

OVM

Overflow mode bit. This bit enables/disables the accumulator overflow saturation mode in the arithmetic logic unit (ALU). The OVM bit can be modified by the LST #0 instruction. OVM = 0 Disabled. An overflowed result is loaded into the accumulator without modification. The OVM bit can be cleared by the CLRC OVM instruction. Overflow saturation mode. An overflowed result is loaded into the accumulator with either the most positive (00 7FFF FFFFh) or the most negative value (FF 8000 0000h). The OVM bit can be set by the SETC OVM instruction.

OVM = 1

10

This bit is read as 1.

Program Control

4-11

Status and Control Registers

Table 45. Status Register 0 (ST0) Bit Summary (Continued)

Bit 9 Name INTM Reset value 1

Function
Interrupt mode bit. This bit globally masks or enables all interrupts. The INTM bit has no effect on the nonmaskable RS and NMI interrupts. Note that the INTM bit is unaffected by the TRAP and LST #0 instructions. The INTM bit is not saved on the stack or restored from the stack on an automatic context save during interrupt service routines. INTM = 0 INTM = 1 All unmaskable interrupts are enabled. The INTM bit can be cleared by the CLRC INTM or RETE instruction. All maskable interrupts are disabled. The INTM bit can be set by the SETC INTM or INTR instruction, a RS and IACK signal, or when a maskable interrupt trap is taken.

80

DP

Data memory page pointer bits. These bits specify the address of the current data memory page. The DP bits are concatenated with the 7 LSBs of an instruction word to form a direct memory address of 16 bits. The DP bits can be modified by the LST #0 or LDP instruction.

4-12

Status and Control Registers

The ST1 bits are shown in Figure 45 and defined in Table 46.

Figure 45. Status Register 1 (ST1) Diagram

1513 ARB 12 11 10 9 8 1 7 1 6 5 1 4 3 1 2 1 1 0 CNF TC SXM C HM XF PM

Table 46. Status Register 1 (ST1) Bit Summary

Bit 1513 Name ARB Reset value XXX

Function
Auxiliary register buffer. This 3-bit field holds the previous value contained in the auxiliary register pointer (ARP) in ST0. Whenever the ARP is loaded, the previous ARP value is copied to the ARB, except when using the LST #0 instruction. When the ARB is loaded using the LST #1 instruction, the same value is also copied to the ARP. This is useful when restoring context (when not using the automatic context save) in a subroutine that modifies the current ARP. On-chip RAM configuration control bit. This 1-bit field enables the on-chip dual-access RAM block 0 (DARAM B0) to be addressable in data memory space or program memory space. The CNF bit can be modified by the LST #1 instruction. CNF = 0 The on-chip DARAM block 0 is mapped into data memory space. The CNF bit can be cleared by a reset or the CLRC CNF instruction. The on-chip DARAM block 0 is mapped into program memory space. The CNF bit can be set by the SETC CNF instruction.

12

CNF

CNF = 1 11 TC X

Test/control flag bit. This 1-bit flag stores the results of the arithmetic logic unit (ALU) or parallel logic unit (PLU) test bit operations. The TC bit is affected by the APL, BIT, BITT, CMPR, CPL, NORM, OPL, and XPL instructions. The status of the TC bit determines if the conditional branch, call, and return instructions execute. The TC bit can be modified by the LST #1 instruction. TC = 0 The TC bit can be cleared by the CLRC TC instruction or any one of the following events:
-

The result of the logical operation is 1 when tested by the APL, OPL, or XPL instructions. A bit tested by the BIT or BITT instruction is equal to 0. A compare condition is false when tested by the CMPR or CPL instruction. The result of the exclusive-OR operation is false when tested by the NORM instruction.

Program Control

4-13

Status and Control Registers

Table 46. Status Register 1 (ST1) Bit Summary (Continued)

Bit Name Reset value

Function
TC = 1 The TC bit can be set by the SETC TC instruction or any one of the following events:
-

The result of the logical operation is 0 when tested by the APL, OPL, or XPL instructions. A bit tested by the BIT or BITT instruction is equal to 1. A compare condition is true when tested by the CMPR or CPL instruction. The result of the exclusive-OR operation is true when tested by the NORM instruction.

10

SXM

Sign-extension mode bit. This 1-bit field enables/disables sign extension of an arithmetic operation. The SXM bit does not affect the operations of certain arithmetic or logical instructions; the ADDC, ADDS, SUBB, or SUBS instruction suppresses sign extension, regardless of SXM. The SXM bit can be modified by the LST #1 instruction. SXM = 0 SXM = 1 Sign extension is suppressed. The SXM bit can be cleared by the CLRC SXM instruction. Sign extension is produced on data as the data is passed into the accumulator through the scaling shifter. The SXM bit can be set by a reset or the SETC SXM instruction.

Carry bit. This 1-bit field indicates an arithmetic operation carry or borrow in the arithmetic logic unit (ALU). The single-bit shift and rotate instructions affect the C bit. The C bit can be modified by the LST #1 instruction. C=0 The result of a subtraction generates a borrow or the result of an addition (except ADD with a 16-bit shift instruction) did not generate a carry. The ADD with a 16-bit shift instruction can only set the bit (by a carry operation); otherwise, the bit is unaffected. The C bit can be cleared by the CLRC C instruction. The result of an addition generates a carry or the result of a subtraction (except SUB with a 16-bit shift instruction) did not generate a borrow. The SUB with a 16-bit shift instruction can only clear the bit (by a borrow operation); otherwise, the bit is unaffected. The C bit can be set by a reset or the SETC C instruction.

C=1

4-14

Status and Control Registers

Table 46. Status Register 1 (ST1) Bit Summary (Continued)

Bit 87 6 HM Name Reset value 11 1

Function
These bits are read as 1. Hold mode bit. This 1-bit field determines whether the central processing unit (CPU) stops or continues execution when acknowledging an active HOLD signal. The HM bit can be modified by the LST #1 instruction. HM = 0 The CPU continues execution from on-chip program memory but puts its external interface in the high-impedance state. The HM bit can be cleared by the CLRC HM instruction. The CPU halts internal execution. The HM bit can be set by a reset or the SETC HM instruction.

HM = 1 5 4 XF 1 1

This bit is read as 1. XF pin status bit. This 1-bit field determines the level of the external flag (XF) output pin. The XF bit can be modified by the LST #1 instruction. The XF bit is not saved or restored from the stack on an automatic context save during interrupt service routines. XF = 0 XF = 1 The XF output pin is set to a logic low. The XF bit can be cleared by the CLRC XF instruction. The XF output pin is set to a logic high. The XF bit can be set by a reset or the SETC XF instruction.

32 10 PM

11 00

These bits are read as 1. Product shift mode bits. This 2-bit field determines the product shifter (P-SCALER) mode and shift value for the product register (PREG) output into the arithmetic logic unit (ALU). The PM bits can be set by the SPM or LST #1 instruction. See Table 47 for the product shifter modes. The PM shifts also occur when the PREG contents are stored to data memory. The PREG contents remain unchanged during the shifts. See Section 3.2, Central Arithmetic Logic Unit (CALU), on page 3-7 for details.

Program Control

4-15

Status and Control Registers

Table 47. Product Shifter Mode as Determined by PM Bits

PM bit values Bit 1 0 0 1 1 Bit 0 0 1 0 1 P-SCALER mode for PREG output No shift. Left-shifted 1 bit; LSB zero-filled. Left-shifted 4 bits; 4 LSBs zero-filled. Right-shifted 6 bits; sign extended; 6 LSBs lost. The product is always sign extended, regardless of the value of the SXM bit.

4-16

Conditional Operations

4.5 Conditional Operations

In addition to unconditional branches, calls, and returns, the C5x has a full complement of conditional branches, calls, and returns. The execution of these instructions is based on the conditions listed in Table 48.

Table 48. Conditions for Branch, Call, and Return Instructions

Mnemonic EQ NEQ LT LEQ GT GEQ NC C NOV OV BIO NTC TC UNC Condition ACC = 0 ACC 0 ACC < 0 ACC 0 ACC > 0 ACC 0 C=0 C=1 OV = 0 OV = 1 BIO is low TC = 0 TC = 1 none Description Accumulator equal to 0 Accumulator not equal to 0 Accumulator less than 0 Accumulator less than or equal to 0 Accumulator greater than 0 Accumulator greater than or equal to 0 Carry bit cleared Carry bit set No accumulator overflow detected Accumulator overflow detected BIO signal is low Test/control flag cleared Test/control flag set Unconditional operation

4.5.1

Conditional Branch
The BCND (conditional branch) is a 2-word instruction. The conditions for the branch are not stable until the fourth cycle of the branch instruction pipeline execution, because the previous instruction must have completely executed for the accumulators status bits to be accurate. Therefore, following the branch, the pipeline controller stops the decode of instructions until the conditions are valid. If the conditions defined in the operands of the instruction are met, the PC is loaded with the second word and the CPU starts filling the pipeline with instructions at the branch address. Because the pipeline has been flushed, the branch instruction has an effective execution time of four cycles if the branch is taken. If, however, any of the conditions are not met, the pipeline controller allows the next instruction (already fetched) to be decoded. This means that if the branch is not taken, the effective execution time of the branch is two cycles.
Program Control
4-17

Conditional Operations

4.5.2

Conditional Call
The CC (conditional call) is a 2-word instruction. The CC instruction operates like the BCND except that the PC pointing to the instruction following the CC is pushed onto the stack. Thus, the return (RET) operation can pop the stack to return to the calling sequence. A subroutine or function can have multiple return paths depending on the data being processed.

4.5.3

Conditional Return
The C5x supports conditional returns (RETC) to avoid conditionally branching around the return. Example 41 shows an overflow-handling subroutine called if the main algorithm causes an overflow condition. During the subroutine, the ACC is checked and, if it is positive, the subroutine returns to the calling sequence. If it is not positive, additional processing is necessary before the return. Note that RETC, like RET, is a 1-word instruction. However, because of the potential PC discontinuity, RETC operates with the same effective execution time as BCND and CC.

Example 41. Use of Conditional Returns (RETC Instruction)

CC . . . OVER_FLOW . . . RETC . . . RET OVER_FLOW,OV ;If overflow,then execute the ;overflow-handling routine.

;Overflow-handling routine.

GEQ

;If ACC >= 0, then return.

;Return.

4.5.4

Multiconditional Instructions
Multiple conditions can be defined in the operands of the conditional instructions. All defined conditions must be met. The C5x includes instructions that test multiple conditions before passing control to another section of the program. These instructions are: BCND, BCNDD, CC, CCD, RETC, RETCD, and XC. These instructions can test the conditions listed in Table 48 individually or in combination with other conditions.

4-18

Conditional Operations

You can combine conditions from the following four groups (Table 49). You can select up to four conditions; however, each of these conditions must be from different groups. You cannot have two conditions from the same group. For example, you can test EQ and TC at the same time but not NEQ and GEQ. For example:
BCND BRANCH,LT,NOV,TC ; If ACC < 0, no overflow ; and TC bit set.

In this example, LT (ACC < 0), NOV (OV = 0), and TC (TC = 1) conditions must be met for the branch to be taken. For a description of the condition codes, see Section 4.5, Conditional Operations, on page 4-17.

Table 49. Groups for Multiconditional Instructions

Group 1 EQ NEQ GT LT GEQ LEQ Group 2 OV NOV Group 3 C NC Group 4 TC NTC BIO

4.5.5

Delayed Conditional Branches, Calls, and Returns

To avoid flushing the pipeline and causing extra cycles, the C5x has a full set of delayed conditional branches, calls, and returns. The one 2-word instruction or two 1-word instructions following a delayed instruction are executed while the instructions at and following the branch address are being fetched, thereby giving an effective 2-cycle branch instead of flushing the pipeline. If the instruction following the delayed instruction is 2 words, only that 2-word instruction is executed before the branch is taken. Conditions tested in the branch are not affected by the instructions following the delayed branch, as shown in Example 42 and Example 43.

Example 42. Use of Conditional Branch (BCND Instruction)

OPL BCND #030h,PMST NEW_ADRS,EQ

Program Control

4-19

Conditional Operations

Example 43. Use of Delayed Conditional Branch (BCNDD Instruction)

BCNDD NEW_ADRS,EQ OPL #030h,PMST

The code in Example 42 executes in six cycles (two for the OPL and four for the BCND). The code in Example 43 executes in four cycles because the two dead cycles following the BCNDD are filled with the OPL instruction. The condition tested on the branch is not affected by the OPL instruction, thereby allowing it to be executed after the branch.

4.5.6

Conditional Execution
In cases where you want the conditional branch to skip over one or two words of code, the branch can be replaced with the execute conditionally (XC) instruction. There are two forms of the XC instruction. One form is the conditional execute of a 1-word instruction (XC 1). The second form is the conditional execute of one 2-word instruction or two 1-word instructions (XC 2). Conditions for XC are the same as for conditional branches, calls, and returns (see Table 48 on page 4-17). Example 44 shows a code example for a conditional branch and Example 45 shows a code example for a conditional execution.

Example 44. Conditional Branch Operation

BCND SUM,NC ADD ONE APAC

SUM

Example 45. Use of Conditional Execution (XC Instruction)

XC 1,C ADD ONE APAC

The code in Example 44 executes in six cycles (four for the BCND, one for the ADD, and one for the APAC). The code in Example 45 executes in three cycles (one each for the XC, ADD, and APAC). If the condition (C = 1) is met in Example 45, the ADD instruction is executed. If the condition is not met, a no operation (NOP) instruction is executed instead of the ADD.
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Conditional Operations

The condition (C = 1) must be stable one full cycle before the XC instruction is executed. This ensures that the decision is made before the instruction following XC is decoded. You should avoid changing the XC test conditions in the 1-word instruction before XC. If no interrupts occur, this instruction has no effect on XC. However, if an interrupt occurs, it can trap between the instruction and XC, thus, affecting the condition before XC is executed. Example 46 and Example 47 show cycle dependency for the XC instruction.

Example 46. XC Execution with Unstable Condition

LACL ADD XC SPLK #0 TEMP1 2,EQ #0EEEEh,TEMP2 ;ACC = 0 ;ACC = TEMP1 ;If ACC = = 0, ;then TEMP2 = 0EEEEh

Example 47. XC Execution with Stable Condition

LACL ADD XC SPLK #0 #01234h 2,EQ #0EEEEh,TEMP2 ;ACC = 0 ;ACC = 0000 1234 ;If ACC = = 0, ;then TEMP2 is unmodified

In the code in Example 46, the NEQ condition (ACC = TEMP1  0) is not stable one full cycle before the XC instruction is executed. The NEQ status, caused by the ADD instruction, is not established because the ADD is only a 1-cycle instruction. Therefore, the previous EQ condition, caused by the LACL instruction, determines the conditional execute. Since the condition is met (ACC = 0), the one 2-word instruction is executed, and TEMP2 is loaded by the SPLK instruction. If an interrupt occurs, it can trap before XC and after ADD so the SPLK instruction cannot execute. In the code in Example 47, the NEQ condition (ACC  0) is stable one full cycle before the XC instruction is executed. The NEQ status, caused by the ADD instruction, is established because the long immediate value (#01234h) used with ADD is a 2-cycle instruction. Since the condition is not met, a NOP instruction is executed instead of the one 2-word instruction, and TEMP2 is not affected. If an interrupt occurs, it has no effect on this instruction sequence.

Program Control

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Single Instruction Repeat Function

4.6 Single Instruction Repeat Function

A single instruction can be repeated N + 1 times, where N is the value loaded into a 16-bit repeat counter register (RPTC) by the RPT or RPTZ instruction. The maximum number of executions of a given instruction is 65 536. The RPTC cannot be programmed; it is is cleared by reset and loaded only by the RPT or RPTZ instruction. When the repeat function is used, RPTC is decremented each time the instruction is executed until the RPTC equals 0. Once a repeat instruction is decoded, all interrupts, including NMI (but not RS), are masked until the completion of the repeat loop. However, the C5x responds to the HOLD signal while executing a repeat loop.

The RPTC is a memory-mapped register. However, you should avoid writing to this register. Writing to this register can cause undesired results. You can use the repeat function with instructions such as multiply/accumulates, block moves, I/O transfers, and table reads/writes. When you use the repeat function, these multicycle instructions are pipelined and the instruction effectively becomes a single-cycle instruction after the first iteration. Absolute program or data addresses are automatically incremented when you use the repeat function. For example, the TBLR instruction can require three or more cycles to execute, but when the instruction is repeated, a table location can be read every cycle. Not all instructions can be repeated or are meaningful to repeat. Table 410 through Table 413 list all C5x instructions according to their repeatability.

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Single Instruction Repeat Function

Table 410. Multi-cycle Instructions Transformed Into Single-Cycle Instructions by the Repeat Function
Mnemonic BLDD BLDP BLPD IN MAC MACD Description Block move from data to data memory Block move from data to program memory with destination address in BMAR Block move from program to data memory Input data from I/O port to data memory location Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by program memory value and store result in PREG Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by program memory value and store result in PREG; and move data Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by value specified in BMAR and store result in PREG; and move data Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by value specified in BMAR and store result in PREG Output data from data memory location to I/O port Transfer data from program to data memory with source address in ACCL Transfer data from data to program memory with destination address in ACCL

MADD

MADS OUT TBLR TBLW

Bold typeface indicates instructions that are new for the C5x instruction set.

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Single Instruction Repeat Function

Table 411. Repeatable Instructions

Mnemonic ADCB ADD ADDB ADDC ADDS ADDT APAC APL BLDD BLDP BLPD BSAR DMOV IN LMMR LTA LTD LTS MAC MACD Description Add ACCB and carry bit to ACC Add data memory value, with left shift, to ACC Add ACCB to ACC Add data memory value and carry bit to ACC with sign extension suppressed Add data memory value to ACC with sign extension suppressed Add data memory value, with left shift specified by TREG1, to ACC Add PREG, with shift specified by PM bits, to ACC AND data memory value with DBMR, and store result in data memory location Block move from data to data memory Block move from data to program memory with destination address in BMAR Block move from program to data memory Barrel-shift ACC right Move data in data memory Input data from I/O port to data memory location Load data memory value to memory-mapped register Load data memory value to TREG0; add PREG, with shift specified by PM bits, to ACC Load data memory value to TREG0; add PREG, with shift specified by PM bits, to ACC; and move data Load data memory value to TREG0; subtract PREG, with shift specified by PM bits, from ACC Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by program memory value and store result in PREG Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by program memory value and store result in PREG; and move data Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by value specified in BMAR and store result in PREG; and move data

MADD

Bold typeface indicates instructions that are new for the C5x instruction set.

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Single Instruction Repeat Function

Table 411. Repeatable Instructions (Continued)

Mnemonic MADS MPYA MPYS MAR NOP NORM OPL OUT POP POPD PSHD PUSH ROL ROLB ROR RORB SACH SACL SAMM SAR SATH SATL SBB SBBB AR, {ind} Description Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by value specified in BMAR and store result in PREG Add PREG, with shift specified by PM bits, to ACC; multiply data memory value by TREG0 and store result in PREG Subtract PREG, with shift specified by PM bits, from ACC; multiply data memory value by TREG0 and store result in PREG Modify ARn No operation Normalize ACC OR data memory value with DBMR and store result in data memory location Output data from data memory location to I/O port Pop top of stack to ACCL; zero ACCH Pop top of stack to data memory location Push data memory value to top of stack Push ACCL to top of stack Rotate ACC left 1 bit Rotate ACCB and ACC left 1 bit Rotate ACC right 1 bit Rotate ACCB and ACC right 1 bit Store ACCH, with left shift, in data memory location Store ACCL, with left shift, in data memory location Store ACCL in memory-mapped register Store ARn (modified in indirect addressing mode) in data memory location Barrel-shift ACC right 0 or 16 bits as specified by TREG1 Barrel-shift ACC right as specified by TREG1 Subtract ACCB from ACC Subtract ACCB and logical inversion of carry bit from ACC

Bold typeface indicates instructions that are new for the C5x instruction set.

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Single Instruction Repeat Function

Table 411. Repeatable Instructions (Continued)

Mnemonic SFL SFLB SFR SFRB SMMR SPAC SPH SPL SQRA SQRS SST SUB SUBB SUBC SUBS SUBT TBLR TBLW XPL Description Shift ACC left 1 bit Shift ACCB and ACC left 1 bit Shift ACC right 1 bit Shift ACCB and ACC right 1 bit Store memory-mapped register in data memory location Subtract PREG, with shift specified by PM bits, from ACC Store PREG high byte, with shift specified by PM bits, in data memory location Store PREG low byte, with shift specified by PM bits, in data memory location Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; square value and store result in PREG Subtract PREG, with shift specified by PM bits, from ACC; load data memory value to TREG0; square value and store result in PREG Store STn in data memory location Subtract data memory value, with left shift, from ACC Subtract data memory value and logical inversion of carry bit from ACC with sign extension suppressed Conditional subtract Subtract data memory value from ACC with sign extension suppressed Subtract data memory value, with left shift specified by TREG1, from ACC Transfer data from program to data memory with source address in ACCL Transfer data from data to program memory with destination address in ACCL Exclusive-OR data memory value with DBMR and store result in data memory location

Bold typeface indicates instructions that are new for the C5x instruction set.

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Single Instruction Repeat Function

Table 412. Instructions Not Meaningful to Repeat

Mnemonic ABS AND ANDB BIT BITT CLRC CMPL CMPR CPL CRGT CRLT EXAR LACB LACC LACL LACT LAMM LAR LDP LPH LST LT LTP MPY MPYU Description Absolute value of ACC; zero carry bit AND data memory value with ACCL; zero ACCH AND ACCB with ACC Test bit Test bit specified by TREG2 Clear status bit 1s complement ACC Compare ARn with ARCR as specified by CM bits Compare data memory value with DBMR Store ACC in ACCB if ACC > ACCB Store ACC in ACCB if ACC < ACCB Exchange ACCB with ACC Load ACC to ACCB Load data memory value, with left shift, to ACC Load data memory value to ACCL; zero ACCH Load data memory value, with left shift specified by TREG1, to ACC Load contents of memory-mapped register to ACCL; zero ACCH Load data memory value to ARx Load data memory value to DP bits Load data memory value to PREG high byte Load data memory value to STm Load data memory value to TREG0 Load data memory value to TREG0; store PREG, with shift specified by PM bits, in ACC Multiply data memory value by TREG0 and store result in PREG Multiply unsigned data memory value by TREG0 and store result in PREG

Bold typeface indicates instructions that are new for the C5x instruction set.

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Single Instruction Repeat Function

Table 412. Instructions Not Meaningful to Repeat (Continued)

Mnemonic NEG OR ORB PAC SACB SAR AR, dma SETC SPM XOR XORB ZALR ZAP ZPR Description Negate (2s complement) ACC OR data memory value with ACCL OR ACCB with ACC Load PREG, with shift specified by PM bits, to ACC Store ACC in ACCB Store ARn direct addressed in data memory location Set status bit Set product shift mode (PM) bits Exclusive-OR data memory value with ACCL Exclusive-OR ACCB with ACC Zero ACCL and load ACCH with rounding Zero ACC and PREG Zero PREG

Bold typeface indicates instructions that are new for the C5x instruction set.

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Single Instruction Repeat Function

Table 413. Nonrepeatable Instructions

Mnemonic ADD #k ADD #lk, shift ADRK AND #lk, shift APL #lk B BACC BACCD BANZ BANZD BCND BCNDD BD CALA CALAD CALL CALLD CC CCD CPL #lk IDLE IDLE2 INTR LACC #lk, shift LACL #k LAR #k LAR #lk LDP #k Description Add short immediate to ACC Add long immediate, with left shift, to ACC Add short immediate to AR AND long immediate, with left shift, with ACC AND data memory value with long immediate and store result in data memory location Branch unconditionally Branch to program memory location specified by ACCL Delayed branch to program memory location specified by ACCL Branch to program memory location if AR not zero Delayed branch to program memory location if AR not zero Branch conditionally to program memory location Delayed branch conditionally to program memory location Delayed branch unconditionally Call to subroutine addressed by ACCL Delayed call to subroutine addressed by ACCL Call to subroutine unconditionally Delayed call to subroutine unconditionally Call to subroutine conditionally Delayed call to subroutine conditionally Compare data memory value with long immediate Idle until nonmaskable interrupt or reset Idle until nonmaskable interrupt or reset low-power mode Software interrupt that branches program control to program memory location Load long immediate, with left shift, to ACC Load short immediate to ACCL; zero ACCH Load short immediate to ARx Load long immediate to ARx Load short immediate to DP bits

Bold typeface indicates instructions that are new for the C5x instruction set.

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Single Instruction Repeat Function

Table 413. Nonrepeatable Instructions (Continued)

Mnemonic MPY #k MPY #lk NMI OPL #lk OR #lk, shift RET RETC RETCD RETD RETE RETI RPT RPTB RPTZ SBRK SPLK #lk SUB #k SUB #lk, shift TRAP XC XOR #lk, shift XPL #lk Description Multiply short immediate by TREG0 and store result in PREG Multiply long immediate by TREG0 and store result in PREG Nonmaskable interrupt and globally disable interrupts (INTM = 1) OR data memory value with long immediate and store result in data memory location OR long immediate, with left shift, with ACC Return from subroutine Return from subroutine conditionally Delayed return from subroutine conditionally Delayed return from subroutine Return from interrupt with context switch and globally enable interrupts (INTM = 0) Return from interrupt with context switch Repeat next instruction specified by data memory value Repeat block of instructions specified by BRCR Clear ACC and PREG; repeat next instruction specified by long immediate Subtract short immediate from AR Store long immediate in data memory location Subtract short immediate from ACC Subtract long immediate, with left shift, from ACC Software interrupt that branches program control to program memory location 22h Execute next instruction(s) conditionally XOR long immediate, with left shift, with ACC Exclusive-OR data memory value with long immediate and store result in data memory location

Bold typeface indicates instructions that are new for the C5x instruction set.

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Block Repeat Function

4.7 Block Repeat Function

A block of instructions can be repeated N + 1 times, where N is the value loaded into a 16-bit block repeat counter register (BRCR) by the RPTB instruction. The maximum number of executions of a given instruction block is 65 536. The block repeat feature provides no-overhead looping for implementation of FOR and DO loops. The block repeat function is controlled by three registers (PASR, PAER, and BRCR) and the block repeat active flag (BRAF) bit in the PMST. You can set or clear the BRAF bit via the PMST. When the repeat block (RPTB) instruction is executed, it automatically sets the BRAF bit, loads the program address start register (PASR) with the address of the instruction following the RPTB instruction, and loads the program address end register (PAER) with its long immediate operand. The long immediate operand is the address of the instruction following the last instruction in the loop, minus 1. The repeat block must contain at least three instruction words. With each PC update, the PAER is compared to the PC. If they are equal, the BRCR contents are compared to 0. If the BRCR is greater than 0, it is decremented, and the PASR is loaded into the PC, therefore restarting the loop. If they are not equal, the BRAF bit is cleared and the processor resumes execution past the end of the codes loop. Example 48 shows how the RPTB instruction can be used.

Example 48. Use of Block Repeat (RPTB Instruction)

SPLK RPTB * ZAP SQRA SPL MPY LTA MPY APAC ADD SACL CRGT END_LOOP *,AR2 SQRX * SQRX * *,0,AR3 *,0,AR1 ;ACC = PREG = 0. ;PREG = X2. ;Save X2. ;PREG = b x X. ;ACC = bX. TREG = X2. ;PREG = aX2. ;ACC = aX2 + bX. ;ACC = aX2 + bX + c = Y. ;Save Y. ;Save MAX. #0Fh,BRCR ;Set loop count to 16. END_LOOP1 ;For I = BRCR; I > =0; I .

Example 48 implements 16 executions of Y = aX2 + bX + c and saves the maximum value in ACCB. Note that the initialization of the auxiliary registers is not shown in the coded example. PAER is loaded with the address of the last word in the code segment. The label END_LOOP is placed after the last instruction, and the RPTB instruction long immediate is defined as END_LOOP1, in case the last word in the loop is a 2-word instruction.
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Block Repeat Function

4.7.1

Context Save and Restore Used With Block Repeat

There is only one set of block repeat registers, so multiple block repeats cannot be nested without saving the context of the outside block or using the BANZD instruction. The simplest method of executing nested loops is to use the RPTB instruction for only the innermost loop and using the BANZD instruction for all the outer loops. This is still a valuable cycle-saving operation because the innermost loop is repeated significantly more times than the outer loops. You can nest block repeats by storing the context of the outer loop before initiating the inner loop, then restoring the outer loops context after the inner loop completes. The context save and restore are shown in Example 49.

Example 49. Context Save and Restore Used With Block Repeat
SMMR SMMR SMMR SPLK RPTB . . . END_INNER LMMR OPL LMMR LMMR BRCR,TEMP1 PASR,TEMP2 PAER,TEMP3 #NUM_LOOP,BRCR END_INNER ;Save block repeat counter ;Save block start address ;Save block end address ;Set inner loop count ;For I = 0; I<=BRCR; I++

BRCR,TEMP1 #1,PMST PASR,TEMP2 PAER,TEMP3

;Restore block repeat counter ;Set BRAF to continue outer loop ;Restore block start address ;Restore block end address

In Example 49, the context save and restore operations require 14 cycles. Repeated single and BANZ/BANZD loops can also be inside a block repeat and can include subroutine calls. Upon returning from a subroutine call, the block repeat resumes. Repeated blocks can also be interrupted. When an enabled interrupt occurs during a repeated block of code, the CALU traps to the interrupt and, when the interrupt service routine returns, the block repeat resumes. Caution should be exercised when interrupting block repeats. If the interrupt service routine uses block repeats, check whether a block repeat has been interrupted and, if so, save the context of the block repeat, as shown in Example 49. Smaller external loops can be implemented with the BANZDlooping method that requires two extra cycles per loop (that is, if the loop count is less than eight, it can be more efficient to use the BANZD technique). Singlecycle instructions can be repeated within a block repeat by using the RPT or RPTZ instructions. WHILE loops can be implemented with the RPTB instruction and a conditional reset of the BRAF bit. The following code example clears BRAF bit so that the
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Block Repeat Function

processor will drop out of the code loop and continue to sequentially access instructions past the end of the loop if an overflow occurs:
XC APL 2,OV ;If overflow, #0FFFEh,PMST ;then turn off block repeat.

The equivalent of a WHILE loop can be implemented by clearing the BRAF bit if the exit condition is met. If this is done, the program completes the current pass through the loop but does not go back to the top. To exit, the BRAF bit must be cleared at least four instruction words before the end of the loop. You can exit block repeat loops and return to them without stopping and restarting the loop. Branches, calls, and interrupts do not necessarily affect the loop. When program control is returned to the loop, loop execution is resumed. Example 410 shows the block repeat with a small loop of code that executes a series of tasks. The tasks are stored in a table addressed by TEMP0F. The number of tasks to be executed is defined at NUM_TASKS.

Example 410. Block Repeat with Small Loop of Code

BLPD SPLK RPTB NUM_TASKS,BRCR #(TASKS1),TEMP0F ENDCALL1 ;Set loop count. ;TEMP0F points to list of ;tasks. ;For I = 0, I <= NUM_TASKS; ;I++. ;ACC points to task table. ;Increment pointer to next ;task. ;Save for next pass of loop. ;Get task address. ;ACC = task address. ;Call task.

TASK_HANDLER LACC TEMP0F ADD #1 SACL TBLR LACC CALA ENDCALL TEMP0F TEMP0E TEMP0E

In the setup of Example 410, the BRCR is loaded with the number of tasks to be executed. Next, the address of the task table is loaded into a temporary register. The block repeat is started with the execution of the RPTB instruction. The PASR is loaded with the address of the LACC TEMP0F instruction. The PAER is loaded with the address of the last word of code. Notice that the label marking the end of the loop is placed after the last instruction, then the PAER is loaded with that label, minus 1. It is possible to place the label before the CALA instruction, then load the PAER with the label address because this is a 1-word instruction. However, if the last instruction in this loop had been a 2-word instruction, the second word of the instruction would not be read and the long immediate operand would be substituted with the first instruction in the loop.
Program Control
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Block Repeat Function

Inside the loop, the pointer to the task table is incremented and saved. Then, the task address is read from the table and loaded into the ACC. Next, the task is called by the CALA instruction. Notice that, when the task returns to the task handler, it returns to the top of the loop. This is because the PC has already been loaded with the PASR before the CALA executes the PC discontinuity. Therefore, when the CALA is executed, the address at the top of the loop is pushed onto the PC stack.

4.7.2

Interrupt Operation in a Block Repeat

The single-word instruction at the end of a repeat block is not interruptible, except, when the previous instruction is a single-word multiple cycles instruction as shown in Example 411 and Example 412. Since BLDD BMAR, *+ is a single-word multiple-cycle instruction, the interrupt return is to the end of the repeat block (see Example 412). An incoming interrupt is latched by the C5x as soon as it meets the interrupt timing requirement. However, the PC does not branch to the corresponding interrupt service routine vector if it is fetching the last word of a repeat block loop. This is the functional equivalent to disabling interrupts before the last instruction word is fetched and reenabling interrupts afterward. Interrupt operation with repeat blocks can potentially increase the worst-case interrupt latency time. Note: When the case in Example 412 occurs, execute the following steps: 1) Save the PMST at the beginning of the interrupt service routine. 2) Clear the BRAF bit inside the interrupt service routine. 3) Restore the PMST before returning from the interrupt service routine.

Example 411. Interrupt Operation With a Single-Word Instruction at the End of an RPTB
RPTB END_LOOP1 SAR AR0,* return from interrupt here if not the last loop iteration . . . LACC *+ SACL * interrupt occurs here ENDLOOP: MAR *,AR1 return from interrupt here if interrupt occurs during last two instruction words of the last loop iteration

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Block Repeat Function

Example 412. Interrupt Operation With a Single-Word Instruction Before the End of RPTB
RPTB END_LOOP1 SAR AR0,* . . . BLDD BMAR,*+ SACL * END_LOOP: MAR *,AR1

Interrupt occurs here and return at SACL

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Interrupts

4.8

Interrupts
The C5x CPU supports 16 user-maskable interrupts (INT16INT1); however, each C5x DSP does not necessarily use all 16 interrupts. For example, all the C5x DSPs use only 9 of these interrupts except C57, which uses 10 of them (the others are tied high internally). External interrupts are generated by external hardware using INT1INT4. Internal interrupts generated by the on-chip peripherals are:
- The timer (TINT) - The serial ports (RINT, XINT, TRNT, TXNT, BRNT, and BXNT) - Host port interface (HINT)

In addition, the C5x has three software interrupt instructions, INTR, NMI, and TRAP; and two external nonmaskable interrupts, RS and NMI. The reset (RS) interrupt has the highest priority, and the INT16 interrupt has the lowest priority. The INT1INT4 and NMI interrupts are valid if the signal is high for at least two machine cycles and low for a minimum of three machine cycles. This triggering gives the C5x the ability to avoid false interrupts from noise or taking multiple interrupts on a single, long interrupt signal. Note: If the CPU is in IDLE2 mode, an interrupt input must be high for at least four machine cycles and low for a minimum of five machine cycles to be properly recognized.

4.8.1

Interrupt Vector Locations

Table 414 shows interrupt vector locations and priorities for all internal and external interrupts. Interrupt addresses are spaced two locations apart so that branch instructions can be accommodated in these locations. The TRAP instruction (software interrupt) is not prioritized but is included here because it has its own vector location. To make vectors stored in ROM reprogrammable, you can use the following code:
LAMM TEMP0 BACC ;ACC = ISR address. ;Branch to ISR.

TEMP0 resides in DARAM block B2 and holds the address of the interrupt service routine (ISR). Note that the ISR addresses must be loaded into block B2 before interrupts are enabled. For further information regarding interrupt operation with respect to specific DSPs in the C5x generation, see subsection 9.1.2, External Interrupts, on page 9-4.
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RINT2 on C52; BRNT on C56/C57 XINT2 on C52; BXNT on C56/C57

Table 414. Interrupt Vector Locations and Priorities

NMI

TRAP

HINT

INT4

TXNT

TRNT{

XINT

RINT

TINT

INT3

INT2

INT1

RS

Name

4063

3839

2633

2023

Dec

36

34

24

18

16

14

12

10

The interrupt vectors can be remapped to the beginning of any 2K-word page in program memory space. The interrupt vector address is generated by concatenating the IPTR bits in the PMST (see subsection 4.4.2, Processor Mode Status Registers (PMST), on page 4-7) with the interrupt vector number (116) shifted by 1 as shown in Figure 46.

Upon reset, the IPTR bits are all cleared, thereby mapping the vectors to page 0 in program memory space. Therefore, the reset vector always resides at location 0h in program memory space. You can move the interrupt vectors to another location by loading a nonzero value into the IPTR bits. For example, you can move the interrupt vectors of INT 5 (as shown in Figure 46) to location 080Ah by loading the IPTR with 1.
Location 1A21 283F 2627 1417 Hex 24 22 18 12 10 C E A 8 6 4 2 0 1 (highest) Priority N/A N/A N/A N/A N/A 10 11 2 9 8 7 6 5 4 3 Software interrupts Reserved for emulation and test Nonmaskable interrupt Software trap instruction Reserved HINT (C57 only) Reserved External user interrupt #4 TDM port transmit interrupt TDM port receive interrupt Serial port transmit interrupt Serial port receive interrupt Internal timer interrupt External user interrupt #3 External user interrupt #2 External user interrupt #1 External nonmaskable reset signal Function

Program Control

Interrupts

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Interrupts

Figure 46. Interrupt Vector Address Generation

IPTR = 00001 INT = 5

Vector

0 A

4.8.2

Interrupt Operation
When an interrupt occurs, a flag is activated in the 16-bit interrupt flag register (IFR). The interrupt flag is activated whether the interrupt is enabled or disabled. An interrupt flag (other than from an active serial port) is automatically cleared when the corresponding interrupt trap is taken. The number of the specific interrupt being acknowledged is indicated by address bits A5A1 on the falling edge of the interrupt acknowledge (IACK) signal. If the interrupt vectors reside in on-chip memory, the CPU should operate in address visibility mode (AVIS = 0) so the interrupt number can be decoded. If an interrupt occurs while the CPU is on hold and HM = 0, the address will not be present when the IACK is activated. Upon receiving an interrupt, the following actions occur:
-

The CPU completes execution of current instruction. Interrupts are globally disabled (INTM = 1). The PC is pushed to the top of the stack (TOS). The PC is set to the interrupt vector address. Key registers are saved into context shadow registers. IACK signal goes low. Corresponding interrupt flag bit in the IFR is cleared.

The C5x recognizes pending interrupts on a priority basis. At the start of each machine cycle (when INTM = 0), the interrupt status is polled and the highest priority interrupt present and enabled is executed. When an interrupt is being serviced, even higher priority interrupts cannot be serviced until interrupts are reenabled usually at the end of the ISR.

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4.8.3

Interrupt Flag Register (IFR)

The IFR is a memory-mapped CPU register located at address 06h in data memory space. The IFR can be read to identify pending external and internal interrupts and written to clear interrupts. An interrupt sets its corresponding interrupt flag in the IFR until the interrupt is recognized by the CPU. Any one of the following events clears the interrupt flag:
- The C5x is reset (RS is active). - An interrupt trap is taken. - A 1 is written to the appropriate bit in the IFR.

Note that when interrupts are disabled (INTM = 1) and an interrupt causes an IDLE or IDLE2 instruction to be exited, none of the IFR bits are cleared (including the IFR bit that caused the IDLE or IDLE2 to be exited). The only event, other than reset or clearing the IFR bits directly in software, that can cause an IFR bit to be cleared is actually taking the interrupt trap when the the ISR is entered. Therefore, if an interrupt causes an IDLE or IDLE2 instruction to be exited when interrupts are disabled, the corresponding IFR bit is not cleared; whereas, if interrupts are enabled and the ISR is entered, the IFR bit is cleared. Figure 47 shows the IFR fields. A value of 1 in an IFR bit indicates a pending interrupt. A 1 can be written to a specific bit to clear the corresponding interrupt. Writing a 0 to a specific bit has no effect. All pending interrupts can be cleared by writing the current contents of the IFR back into the IFR. The following example clears two interrupts, INT1 and INT3, without affecting any other flags that have been set:
SPLK #5,IFR ;Clear flags for INT1 and INT3.

The IFR sets only one flag for each interrupt recognized. If several hardware interrupts occur on the same pin before the interrupt is recognized by the CPU, the CPU will respond as though only a single interrupt (the last one) had occurred.

Figure 47. Interrupt Flag Register (IFR) Diagram

Lowest Priority Highest

1512

11

10

Reserved

HINT

Reserved

INT4

TXNT

TRNT

XINT

RINT

TINT

INT3

INT2

INT1

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4.8.4

Interrupt Mask Register (IMR)

The IMR is a memory-mapped CPU register located at address 04h in data memory space. The IMR is used for masking external and internal interrupts. Neither NMI nor RS are in the IMR; therefore, the IMR has no effect on these nonmaskable interrupts. Figure 48 shows the IMR fields.

Figure 48. Interrupt Mask Register (IMR) Diagram

1512 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HINT Reserved INT4 TXNT TRNT XINT RINT TINT INT3 INT2 INT1

A value of 1 in an IMR bit enables the corresponding interrupt, provided that the INTM bit in ST0 (see subsection 4.4.3, Status Registers (ST0 and ST1), on page 4-10) is cleared. The IMR is accessible with both read and write operations.

4.8.5

Interrupt Mode (INTM) Bit

The INTM bit in ST0 (see subsection 4.4.3, Status Registers (ST0 and ST1), on page 4-10) globally enables or disables all maskable interrupts:
- When INTM = 0, all unmasked interrupts are enabled. - When INTM = 1, all unmasked interrupts are disabled.

The INTM bit does not modify the IFR or IMR. Any one of the following events sets the INTM bit:
-

The C5x is reset (RS is active). An interrupt trap is taken. The NMI instruction is executed. The SETC INTM instruction is executed.

Any one of the following events clears the INTM bit:

- The CLRC INTM instruction is executed. - The RETE instruction is executed.

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4.8.6

Nonmaskable Interrupts
The two nonmaskable interrupts, RS and NMI, are unaffected by either the INTM bit or the contents of the IMR. You can use the NMI as a soft reset of the C5x or as the input to a systems most time-critical interrupt event. When used as a soft reset, NMI does not perform any of the control bit or register initializations that are provided by the RS function. The NMI trap can be initiated via software using the NMI instruction. Upon receiving an NMI, the following actions occur: 1) The CPU completes execution of all instructions in the pipeline. 2) Interrupts are globally disabled (INTM = 1). 3) The PC is set to the NMI interrupt vector (location 24h). Because it is possible to service an NMI, even during an ISR, the key registers are not saved automatically. The NMI is different from RS because it does not affect any of the C5x modes. The NMI is delayed by multicycle instructions (including RPT) and by HOLD, as described in subsection 4.8.9, Interrupt Latency, on page 4-43. RS is discussed in Section 4.9, Reset, on page 4-45.

4.8.7

Software-Initiated Interrupts
Not all of the 16 CPU interrupts are utilized on any given C5x DSP. The vectors for the interrupts that are not tied to specific external pins or internal peripherals can be used as software interrupts. The three software interrupt instructions, INTR, NMI, and TRAP, are unaffected by either the INTM bit or the contents of the IMR. These instructions allow interrupts to be invoked under software control. The INTR instruction (page 6-111) allows any ISR to be executed from your software. An INTR interrupt for the external interrupts (INT1INT4) executes like an external interrupt described in subsection 4.8.2, Interrupt Operation. The NMI instruction (page 6-179) has the same affect as a hardware nonmaskable interrupt (NMI). The NMI instruction transfers program control to program memory location 24h. Interrupts are globally disabled (INTM = 1), but key registers are not saved into context shadow registers. The TRAP instruction (page 6-277) transfers program control to program memory location 22h. The TRAP instruction disables interrupts (INTM = 1), but key registers are not saved into context shadow registers.
Program Control
4-41

Interrupts

4.8.8

Interrupt Context Save

When an interrupt is executed, certain key CPU registers are saved automatically. The PC is saved on an 8-deep hardware stack (see Section 4.2, Hardware Stack), which is also used for subroutine calls. Therefore, the CPU supports subroutine calls within an ISR as long as the 8-level stack is not exceeded. Also, there is a 1-deep stack (or shadow registers) for each of the following registers:
-

Accumulator (ACC) Accumulator buffer (ACCB) Auxiliary register compare register (ARCR) Index register (INDX) Processor mode status register (PMST) Product register (PREG) Status register 0 (ST0) Status register 1 (ST1) Temporary register 0 (TREG0) for multiplier Temporary register 1 (TREG1) for shift count Temporary register 2 (TREG2) for bit test

When the interrupt trap is taken, the contents of all these registers are pushed onto a 1-level stack, with the exception of the the INTM bit in ST0 and the XF bit in ST1. On an interrupt, the INTM bit is always set to disable interrupts. The values in the registers at the time of the interrupt trap are still available to the ISR but are also protected in the shadow registers. The shadow registers are copied back to the CPU registers when the RETI or RETE instruction is executed. This function allows the CPU to be used for the ISR without requiring context save and restore overhead in the ISR. With only a 1-level stack for the registers, nested interrupts cannot be supported. In most cases this is not a problem, because without the context save and restore overhead, serial processing of the interrupts is so efficient that nested interrupt handling is less effective. If the application requires nested interrupts, they can be handled by using a software stack. Software compatibility with the C2x is maintained because the RET instruction, if it is used to return from the ISR on a C2x, cannot restore these registers. Interrupts are not enabled unless a RETE or CLRC INTM instruction is executed. In the case where the ISR needs to modify values in these registers with respect to the interrupted code, these registers can be restored from the stack and modified as shown in Example 413.
4-42

Interrupts

Example 413. Modifying Register Values During Interrupt Context Save

ISR LACC #ISR_RE_ENTER PUSH RETI ISR_RE_ENTER . . . CLRC INTM RET ;ACC = address of reentry point. ;Top of stack = reentry point. ;Pop all the stacks.

;Return to interrupted code.

In Example 413, the address of the re-entry point within the ISR is pushed onto the PC stack. The RETI instruction pops all the stacks, including the PC stack, and resumes execution. At the end of the ISR, a standard return is executed because the stack is already popped.

4.8.9

Interrupt Latency
The interrupt latency of the C5x depends on the current contents of the pipeline. The CPU always completes all instructions in the pipeline before executing a software vector. Figure 49 shows the minimum latency from the time an interrupt occurs externally to the IACK. The minimum IACK time is defined as eight cycles:
- 3 cycles to externally synchronize the interrupt - 1 cycle for the interrupt to be recognized by the CPU - 4 cycles to execute the INTR instruction and flush the pipeline

On the sixth cycle, an INTR is jammed into the pipeline and the INTM bit is set to 1. On the ninth cycle, the interrupt vector is fetched and the IACK signal is generated. Note that if the instruction immediately ahead of the INTR in the pipeline (Main5 in Figure 49) is an SST #0 and INTM was previously cleared, INTM gets set before this instruction executes and INTM is stored as a 1. Therefore, if ST0 is restored in order to return to the previous context, interrupts will be disabled (INTM = 1) rather than enabled. Accordingly, if this is critical in an application, an SST #0 instruction should be executed only with interrupts disabled or interrupts should be reenabled after loading ST0, if necessary.
Program Control
4-43

Interrupts

Figure 49. Minimum Interrupt Latency

Interrupt occurs before the fetch of this instruction
Fetch Decode Read Execute
Main1 Main2 Main1

Interrupt written to IFR

Main3 Main2 Main1 Main4 Main3 Main2 Main1 Main5 Main4 Main3 Main2

This instruction will be refetched after return from interrupt

Main6 Main5 Main4 Main3 Dummy INTR Main5 Main4 Dummy Dummy INTR Main5 Dummy Dummy Dummy INTR Vec1 Dummy Dummy Dummy Vec2 Vec1 Dummy Dummy Dummy Vec2 Vec1 Dummy Dummy Dummy Vec2 Vec1 ISR1 Dummy Dummy Vec2

Interrupt latched external to the CPU

INTR jammed into the pipeline and INTM = 1

IACK generated here

The maximum latency is a function of the contents of the pipeline. Multicycle instructions add additional cycles to empty the pipeline. This applies to instructions that are extended via wait-state insertion on memory accesses. The wait states required for interrupt vector accesses also affect the latency. The repeat instructions (RPT and RPTZ) delay execution of interrupts (including NMI, but not RS). The repeat instructions require that all executions of the next instruction be completed before allowing an interrupt to execute to protect the context of the repeated instructions. This protection is necessary, because these instructions run parallel operations in the pipeline, and the context of these additional parallel operations cannot be saved in the ISR. The HOLD function takes precedence over interrupts and can delay the interrupt trap. If an interrupt occurs when the CPU is in hold (HOLD asserted), the interrupt is not taken until HOLDA is deasserted when the hold state ends. However, if the CPU is in the concurrent hold mode (HM = 0) and the interrupt vector table is located in on-chip memory, the CPU takes the interrupt regardless of the HOLD status. Interrupts cannot be processed between the CLRC INTM instruction and the next instruction in a program sequence. If an interrupt occurs during the decode phase of the CLRC INTM instruction, the CPU always completes CLRC INTM and the following instruction before the pending interrupt is processed. Waiting for these instructions to complete, ensures that a return (RET) can be executed in an ISR before the next interrupt is processed to protect against PC stack overflow. If the ISR is ends with an RETE instruction, the CLRC INTM instruction is unnecessary. Similarly, the SETC INTM instruction and the next instruction cannot be interrupted.
4-44

Reset

4.9 Reset
Reset (RS) is a nonmaskable external interrupt that can be used at any time to place the C5x into a known state. Reset is typically applied after power-up when the C5x is in an unknown state. The reset signal aborts memory operations; therefore, the system should be reinitialized after each reset. Reset is the highest priority interrupt; thus, no other interrupt takes precedence over a reset. You can use the NMI interrupt for soft resets because the NMI does not abort memory operations or initialize status bits. A hardware reset clears all pending interrupt flags. Driving the RS signal low causes the C5x to terminate execution and forces the PC to the reset vector location 0h in program memory space. At power-up, the state of the C5x is undefined. For correct system operation after power-up, the RS signal must be asserted low for a minimum of six clock cycles so that the data lines are placed into the high-impedance state and the address lines are driven low. The C5x latches the reset pulse and generates an internal reset pulse long enough to guarantee a reset. After the RS signal is high for 17 clock cycles, CPU execution begins at location 0h, which normally contains a branch instruction to the system initialization routine. When the C5x receives a reset signal, the following sequence of actions occur: 1) The program currently being executed is asynchronously aborted. 2) The CPU registers status bits are set per Table 415. Note that any remaining status bits remain undefined and should be initialized appropriately. 3) The PC is cleared. The address bus is unknown while RS is low. If HOLD is asserted while RS is low, HOLDA is generated. In this case, the address lines are placed into a high-impedance state until HOLD is brought back high. 4) A synchronized reset (SRESET) signal is sent to the peripheral circuits to initialize them. The peripheral registers status bits are set per Table 416 on page 4-47. See subsection 9.1.3, Peripheral Reset, on page 9-6. Execution starts from program memory location 0h when the RS signal is driven high. If HOLD is asserted while RS is low, normal reset operation occurs internally, but all buses and control lines remain in a high-impedance state, and HOLDA is asserted, as shown in Figure 410(a) and (b) on page 4-49. However, if RS is asserted while HOLD and HOLDA are low, the CPU comes out of the hold mode momentarily by deactivating HOLDA. This condition should be avoided. Upon release of HOLD and RS, execution starts from location 0h.
Program Control
4-45

Reset

Note that the external parallel interface signals are asynchronously disabled during reset; therefore, external DMA is not supported during reset. See subsection 8.6.2, External DMA, on page 8-24 for more information.

Table 415. CPU Registers Bit Status at Reset

Register ST0 Bit Status INTM 1 OV ST1 C CNF HM PM SXM XF PMST AVIS 0 1 0 1 0 1 1 0 Result All maskable interrupts are disabled. Note that RS and NMI are nonmaskable. Overflow bit is cleared. Carry bit is set. DARAM block B0 is mapped into data memory space. Processor halts execution during HOLD. PREG output is not shifted. Sign extension on data is enabled. External flag pin is set high. Internal program address appears at address pins. Block repeat is disabled. Reset vector is cleared. MP/MC pin is sampled to determine use of on-chip ROM. C2x-compatible mode is selected. SARAM block is not mapped to data memory space. SARAM block is not mapped to program memory space. C2x-compatible mode is selected. No interrupts are pending. Circular buffer 1 is disabled. Circular buffer 2 is disabled. All data memory space is configured as local. Repeat counter is cleared.

BRAF 0 IPTR 0

MP/MC (pin) NDX 0

OVLY 0 RAM TRM IFR CBCR 0 0

All bits 0 CENB1 0 CENB2 0

GREG RPTC

All bits 0 All bits 0

4-46

Reset

Table 416. Peripheral Registers Bit Status at Reset

Register PDWSR IOWSR CWSR Bit Status All bits All bits BIG D I/O High I/O Low P DRR DXR SPC/BSPC/ TSPC All bits All bits DLB FO Free FSM IN0 IN1 MCM RRDY RRST RSRFULL Soft TDM TXM XRDY XRST 1 1 0 1 1 1 1 0 0 0 0 0 0 (pin) (pin) 0 0 0 0 0 0 0 1 0 Result All program and data wait-state registers are set to 7. All I/O wait-state registers are set to 7. I/O space is divided into eight 8K-word blocks. Wait states are enabled for data memory space. Wait states are enabled for upper half of I/O space. Wait states are enabled for lower half of I/O space. Wait states are enabled for program memory space. Data receive register is cleared. Data transmit register is cleared. Digital loop back is disabled. Data is transmitted/received as 16-bit words. Stop serial clock is enabled. Serial port is operated in continuous mode. IN0 reflects the current level of the CLKR pin. IN1 reflects the current level of the CLKX pin. CLKX pin is configured as input pin. Receive ready is reset. Receive serial port is reset. SPC only: receive shift register full flag is reset. Stop serial clock immediately is enabled. TSPC only: TDM port is configured as standard serial port. FSX pin is configured as input pin. Transmit ready is reset. Transmit serial port is reset. SPC only: transmit shift register empty flag is reset.

XSREMPTY 0

Program Control

4-47

Reset

Table 416. Peripheral Registers Bit Status at Reset (Continued)

Register SPCE Bit Status BRE BXE CLKDV CLKP FE FIG FSP HALTR HALTX PCM RH XH TIM PRD TCR All bits All bits TDDR TSS HPIC SMOD HINT 0 0 00011 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 Result Autobuffering receive is disabled. Autobuffering transmit is disabled. Internal transmit clock division factor is set to 3. Data is sampled by the receiver on CLKRs falling edge and sent by the transmitter on CLKXs rising edge. Data is transmitted/received as 16-bit words. The frame pulses following first frame restart the serial port interface. Frame sync pulses are active high. Autobuffering halt receive is reset. Autobuffering halt transmit is reset. Pulse coded modulation is not active. Receive buffer half received bit is reset. Transmit buffer half transmitted bit is reset. Timer counts down from FFFFh. Timer is disabled. Each cycle decrements timer by 1. Timer is in run mode. Zero while in reset, set to one when reset goes high. No interrupt (external HINT pin is high)

4-48

Reset

Figure 410. RS and HOLD Interaction

a)
RS

HOLD

HOLDA

b)
RS

HOLD

HOLDA

Program Control

4-49

Power-Down Mode

4.10 Power-Down Mode

In the power-down mode, the C5x enters a dormant state and dissipates less power than in the normal mode. You can invoke the power-down mode by executing either the IDLE or IDLE2 instruction, or by driving the HOLD input low with the HM status bit set. While the C5x is in power-down mode, all its internal contents are maintained; this allows operations to continue unaltered when the power-down mode is terminated.

4.10.1 IDLE Instruction

The IDLE instruction halts all CPU activities except the system clock. Since the system clock remains applied to the peripherals, the peripheral circuits continue operating and the CLKOUT1 pin remains active. Thus peripherals such as serial ports and timers can take the CPU out of its power-down state. This power-down mode is terminated upon receipt of an interrupt. If INTM = 0 when the interrupt takes place, then the CPU enters the ISR when IDLE is terminated. If INTM = 1, then the CPU continues with the instruction following the IDLE.

4.10.2 IDLE2 Instruction

The IDLE2 instruction halts all CPU activities and the on-chip peripherals. Unlike the IDLE instruction, the IDLE2 instruction disables the CLKOUT1 signal. Because the on-chip peripherals are stopped in this power-down mode, they cannot be used to generate the interrupt to wake up the CPU as in the IDLE mode. However, the power is significantly reduced because the complete DSP is stopped. Note that the HPI has some special IDLE2 considerations, see Section 9.10, Host Port Interface, on page 9-87. This power-down mode is terminated by activating any of the external interrupt pins (RS, NMI, INT1, INT2, INT3, and INT4) for at least five machine cycles. If INTM = 0 when the interrupt takes place, then the CPU enters the ISR when IDLE2 is terminated. If INTM = 1, then the CPU continues with the instruction following the IDLE2. Reset all peripherals when IDLE2 terminates, especially if the peripherals are externally clocked.

4-50

Power-Down Mode

4.10.3 Power Down Using HOLD

The power-down mode can also be initiated by the HOLD signal. When the HOLD signal initiates power-down and HM = 1, the CPU stops executing and address, data, and control lines go into high impedance for further power reduction. When the HOLD signal initiates power-down and HM = 0, the address, data, and control lines go into high impedance, but the CPU continues to execute internally. When external memory accesses are not required in the system, the HM = 0 mode can be used. The C5x continues to operate normally unless an off-chip access is required by an instruction, then the CPU halts until the hold is removed. This power-down mode is terminated when the HOLD signal becomes inactive. HOLD does not stop the operation of on-chip peripherals (serial ports and timers); the peripherals continue to operate regardless of the level on HOLD or the status of the HM bit.

Program Control

4-51

Chapter 5

Addressing Modes
This chapter describes each of the following addressing modes and gives the opcode formats and some examples.
-

Direct addressing Indirect addressing Immediate addressing Dedicated-register addressing Memory-mapped register addressing Circular addressing

Topic
5.1 5.2 5.3 5.4 5.5 5.6

Page
Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Dedicated-Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Memory-Mapped Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21

Addressing Modes

5-1

Direct Addressing

5.1 Direct Addressing

In the direct memory addressing mode, the instruction contains the lower 7 bits of the data memory address (dma). The 7-bit dma is concatenated with the 9 bits of the data memory page pointer (DP) in status register 0 to form the full 16-bit data memory address. This 16-bit data memory address is placed on an internal direct data memory address bus (DAB). The DP points to one of 512 possible data memory pages and the 7-bit address in the instruction points to one of 128 words within that data memory page. You can load the DP bits by using the LDP or the LST #0 instruction. Figure 51 illustrates how the 16-bit data memory address is formed.

Figure 51. Direct Addressing

ST0 DP (9) IREG (16) 7 LSBs
6 0

9
15

16-bit data memory address

DP

dma

PAGE 511 PAGE 510

512 DATA PAGES

PAGE 3 PAGE 2

DAB

PAGE 1 PAGE 0

128-WORD PAGE

(MEMORYMAPPED REGISTERS AND DARAM B2)

5-2

Direct Addressing

Note: The DP is not initialized by reset and, therefore, is undefined after power-up. The C5x development tools, however, use default values for many parameters, including the DP. Because of this, programs that do not explicitly initialize the DP may execute improperly, depending on whether they are executed on a C5x device or with a development tool. Thus, it is critical that all programs initialize the DP in software.

Figure 52 illustrates the direct addressing mode. Bits 15 through 8 contain the opcode. Bit 7, with a value of 0, defines the addressing mode as direct, and bits 6 through 0 contain the dma.

Figure 52. Direct Addressing Mode

LDP ADD #019Dh 010h, 5
15

ADD opcode
8 7 6

010h
0

Machine Code

0 0 1 0

0 1 0 1

0 0 0 1

0 0 0 0

DP

1 1 0 0

1 1 1 0

DAB Operand
Note:

1 1 0 0 Data(DAB)

1 1 1 0

1 0 0 1

0 0 0 0

DAB is the 16-bit internal data memory address bus.

Addressing Modes

5-3

Indirect Addressing

5.2 Indirect Addressing

Eight 16-bit auxiliary registers (AR0AR7) provide flexible and powerful indirect addressing. In indirect addressing, any location in the 64K-word data memory space can be accessed using a 16-bit address contained in an AR. Figure 53 shows the hardware for indirect addressing.

Figure 53. Indirect Addressing

Data bus (16) 3 3 3

Auxiliary registers AR0

ARB

ARP 3 (ARP = 2)

AR1 AR2 AR3 AR4 AR5 AR6 AR7 16 ARAU 16-bit data address 16 16

To select a specific AR, load the auxiliary register pointer (ARP) with a value from 0 through 7, designating AR0 through AR7, respectively. The register pointed to by the ARP is referred to as the current auxiliary register (current AR). You can load the address into the AR using the LAR instruction and you can change the content of the AR by the:
-

ADRK instruction MAR instruction SBRK instruction Indirect addressing field of any instruction supporting indirect addressing.

The content of the current AR is used as the address of the data memory operand. After the instruction uses the data value, the content of the current AR can be incremented or decremented by the auxiliary register arithmetic unit (ARAU), which implements unsigned 16-bit arithmetic.
5-4

Indirect Addressing

The ARAU performs auxiliary register arithmetic operations in the decode phase of the pipeline (when the instruction specifying the operation is being decoded). This allows the address to be generated before the decode phase of the next instruction. The content of the current AR is incremented or decremented after it is used in the current instruction. You can load the ARs via the data bus by using memory-mapped writes to the ARs. The following instructions can write to the memory-mapped ARs: APL BLDD LMMR OPL SACH SACL SAMM SMMR SPLK XPL

Be careful when using these memory-mapped loads of the ARs because, in this case, the memory-mapped ARs are modified in the execute phase of the pipeline. This causes a pipeline conflict if one of the next two instruction words modifies that AR. For further information on the pipeline and possible pipeline conflicts, see Chapter 7, Pipeline. There are two ways to use the ARs for purposes other than referencing data memory addresses:
- Use the ARs to support conditional branches, calls, and returns by using

the CMPR instruction. This instruction compares the content of the current AR with the content of the auxiliary register compare register (ARCR) and puts the result in the test/control (TC) flag bit of status register ST1.
- Use the ARs for temporary storage by using the LAR instruction to load

a value into the AR and the SAR instruction to store the AR value to a data memory location.

5.2.1

Indirect Addressing Options

The C5x provides four indirect addressing options:
- No increment or decrement. The instruction uses the content of the current

AR as the data memory address, but neither increments nor decrements the content of the current AR.
- Increment or decrement by one. The instruction uses the content of the

current AR as the data memory address and then increments or decrements the content of the current AR by 1.
- Increment or decrement by an index amount. The value in INDX is the

index amount. The instruction uses the content of the current AR as the data memory address and then increments or decrements the content of the current AR by the index amount.
Addressing Modes
5-5

Indirect Addressing

- Increment or decrement by an index amount using reverse carry. The

value in INDX is the index amount. The instruction uses the content of the current AR as the data memory address and then increments or decrements the content of the current AR by the index amount. The addition or subtraction is done using reverse carry propagation. The contents of the current AR are used as the address of the data memory operand. Then, the ARAU performs the specified mathematical operation on the indicated AR. Additionally, the ARP can be loaded with a new value. All indexing operations are performed on the current AR in the same cycle as the original instruction decode phase of the pipeline. Indirect auxiliary register addressing lets you make post-access adjustments of the current AR. The adjustment may be an increment or decrement by one or may be based upon the contents of the INDX. To maintain compatibility with the C2x devices, clear the NDX bit in the PMST. In the C2x architecture, the current AR can be incremented or decremented by the value in the AR0. When the NDX bit is cleared, every AR0 modification or LAR write also writes the ARCR and INDX with the same value. Subsequent modifications of the current ARs with indexed addressing will use the INDX, therefore maintaining compatibility with existing C2x code. The NDX bit is cleared at reset. The bit-reversed addressing modes (see subsection 5.2.3 on page 5-12) helps you achieve efficient I/O by the resequencing of data points in a radix-2 fast Fourier transform (FFT) program. The direction of carry propagation in the ARAU is reversed when bit-reversed addressing is selected, and INDX is added to/subtracted from the current AR. Normally, this addressing mode requires that INDX first be set to a value corresponding to one-half of the arrays size, and that the current AR be set to the base address of the data (the first data point). The following indirect-addressing symbols are used in the C5x assembly language instructions: * No increment or decrement. Content of the current AR is used as the data memory address and is neither incremented nor decremented. Increment by 1. Content of the current AR is used as the data memory address. After the memory access, the content of the current AR is incremented by 1. Decrement by 1. Content of current AR is used as the data memory address. After the memory access, the content of the current AR is decremented by 1. Increment by index amount. Content of current AR is used as the data memory address. After the memory access, the content of INDX is added to the content of the current AR.

*+

*0+

5-6

Indirect Addressing

*0

Decrement by index amount. Content of current AR is used as the data memory address. After the memory access, the content of INDX is subtracted from the content of the current AR. Increment by index amount, adding with reverse carry. Content of current AR is used as the data memory address. After the memory access, the content of INDX with reverse carry propagation is added to the content of the current AR. Decrement by index amount, subtracting with reverse carry. Content of current AR is used as the data memory address. After the memory access, the content of INDX with reverse carry propagation is subtracted from the content of the current AR.

*BR0+

*BR0

5.2.2

Indirect Addressing Opcode Format

Indirect addressing can be used with all instructions except those with immediate operands or with no operands. The indirect addressing format is shown in Figure 54 and described in Table 51. Table 53 on page 5-9 shows the instruction field bit values, notation, and operation used for indirect addressing. Example 51 through Example 58 illustrate the indirect addressing formats. Example 59 shows an indirect addressing routine.

Figure 54. Indirect Addressing Opcode Format Diagram

158 7 I 6 5 4 3 20 Opcode IDV INC DEC N NAR

Table 51. Indirect Addressing Opcode Format Summary

Bit 158 7 I Name Description Opcode. This 8-bit field is the opcode for the instruction. Addressing mode bit. This 1-bit field determines the addressing mode. I=0 I=1 Direct addressing mode. Indirect addressing mode.

Addressing Modes

5-7

Indirect Addressing

Table 51. Indirect Addressing Opcode Format Summary (Continued)

Bit 6 Name IDV Description Index register bit. This 1-bit field determines whether the INDX is used to increment or decrement the current AR. The IDV bit works in conjunction with the INC and DEC bits to determine the arithmetic operation. IDV = 0 IDV = 1 The INDX is not used in the arithmetic operation. An increment or decrement (if any) by 1 occurs to the current AR. The INDX is used in the arithmetic operation. An increment or decrement (if any) by the contents of INDX or by reverse carry propagation occurs to the current AR.

INC

Auxiliary register increment bit. This 1-bit field determines whether the current AR is incremented. The INC bit works in conjunction with the IDV and DEC bits to determine the arithmetic operation. INC = 0 INC = 1 The current AR is not incremented. The current AR is incremented as determined by the IDV bit.

DEC

Auxiliary register decrement bit. This 1-bit field determines whether the current AR is decremented. The DEC bit works in conjunction with the IDV and INC bits to determine the arithmetic operation. See Table 52 for specific arithmetic operations. DEC = 0 DEC = 1 The current AR is not decremented. The current AR is decremented as determined by the IDV bit.

Next auxiliary register indicator bit. This 1-bit field determines whether the instruction will change the ARP value. N=0 N=1 The content of the ARP will remain unchanged. The content of NAR will be loaded into the ARP, and the old ARP value is loaded into the auxiliary register buffer (ARB) of status register ST1.

20

NAR

Next auxiliary register value bits. This 3-bit field contains the value of the next auxiliary register. If the N bit is set, NAR is loaded into the ARP.

5-8

Indirect Addressing

Table 52. Indirect Addressing Arithmetic Operations

Bit values IDV 0 0 0 0 1 1 1 1 INC 0 0 1 1 0 0 1 1 DEC 0 1 0 1 0 1 0 1 Arithmetic Operation Performed on Current AR No operation on current AR (Current AR) 1 current AR (Current AR) + 1 current AR Reserved (Current AR) INDX [reverse carry propagation] current AR (Current AR) INDX current AR (Current AR) + INDX current AR (Current AR) + INDX [reverse carry propagation] current AR

Table 53. Instruction Field Bit Values for Indirect Addressing

Instruction Field Bit Values 158 Opcode Opcode Opcode Opcode Opcode Opcode Opcode Opcode Opcode Opcode Opcode Opcode 7 1 1 1 1 1 1 1 1 1 1 1 1 6 0 0 0 0 0 0 1 1 1 1 1 1 5 0 0 0 0 1 1 0 0 0 0 1 1 4 0 0 1 1 0 0 0 0 1 1 0 0 3 0 1 0 1 0 1 0 1 0 1 0 1 20 NAR NAR NAR NAR NAR NAR NAR NAR NAR NAR NAR NAR Notation * *, ARn * *, ARn *+ *+, ARn *BR0 *BR0, ARn *0 *0, ARn *0+ *0+, ARn Operation No operation on current AR NAR ARP (Current AR) 1 current AR (Current AR) 1 current AR, NAR ARP (Current AR) + 1 current AR (Current AR) + 1 current AR, NAR ARP (Current AR) rcINDX current AR (Current AR) rcINDX current AR, NAR ARP (Current AR) INDX current AR (Current AR) INDX current AR, NAR ARP (Current AR) + INDX current AR (Current AR) + INDX current AR, NAR ARP

Addressing Modes

5-9

Indirect Addressing

Table 53. Instruction Field Bit Values for Indirect Addressing (Continued)
Instruction Field Bit Values 158 Opcode Opcode 7 1 1 6 1 1 5 1 1 4 1 1 3 0 1 20 NAR NAR Notation *BR0+ *BR0+, ARn Operation (Current AR) + rcINDX current AR (Current AR) + rcINDX current AR, NAR ARP

Example 51. Indirect Addressing With No Change to AR

ADD *,8

Example 52. Indirect Addressing With Autodecrement

ADD *,8

Example 53. Indirect Addressing With Autoincrement

ADD *+,8

5-10

0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0

In Example 51, the content of the data memory address, defined by the content of the current AR, is shifted left 8 bits and added to the ACC. The current AR is not changed. The instruction word is 2880h.

0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0

In Example 52, the content of the data memory address, defined by the content of the current AR, is shifted left 8 bits and added to the ACC. The current AR is decremented by 1. The instruction word is 2890h.

0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0

In Example 53, the content of the data memory address, defined by the content of the current AR, is shifted left 8 bits and added to the ACC. The current AR is incremented by 1. The instruction word is 28A0h.

Indirect Addressing

Example 54. Indirect Addressing With Autoincrement and Change AR

ADD *+,8,AR3

Example 55. Indirect Addressing With INDX Subtracted from AR

ADD *0 ,8

Example 56. Indirect Addressing With INDX Added to AR

ADD *0+,8

Example 57. Indirect Addressing With INDX Subtracted from AR With Reverse Carry

0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1

In Example 54, the content of the data memory address, defined by the content of the current AR, is shifted left 8 bits and added to the ACC. The current AR is incremented by 1. The auxiliary register pointer (ARP) is loaded with the value 3 for subsequent instructions. The instruction word is 28ABh.

0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0

In Example 55, the content of the data memory address, defined by the content of the current AR, is shifted left 8 bits and added to the ACC. The content of INDX is subtracted from the current AR. The instruction word is 28D0h.

0 0 1 0 1 0 0 0 1 1 1 0 0 0 0 0

In Example 56, the content of the data memory address, defined by the content of the current AR, is shifted left 8 bits and added to the ACC. The content of INDX is added to the current AR. The instruction word is 28E0h.

0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0

ADD *BR0 ,8

In Example 57, the content of the data memory address, defined by the content of the current AR, is shifted left 8 bits and added to the ACC. The content of INDX with reverse carry propagation is subtracted from the current AR. The instruction word is 28C0h.

Addressing Modes

5-11

Indirect Addressing

Example 58. Indirect Addressing With INDX Added to AR With Reverse Carry
ADD *BR0+,8

Example 59. Indirect Addressing Routine

* This routine uses indirect addressing to calculate the following equation: * * 10 * * \ X(I) x Y(I) * / * * I = 1 * * The routine assumes that the X values are located in on-chip RAM block B0, * and the Y values in block B1. The efficiency of the routine is due to the * use of indirect addressing and the repeat instruction. * SERIES MAR *,AR4 ;ARP POINTS TO ADDRESS REGISTER 4. SETC CNF ;CONFIGURE BLOCK B0 AS PROGRAM MEMORY. LAR AR4,#0300h ;POINT AT BEGINNING OF DATA MEMORY. RPTZ #9 ;CLEAR ACC AND PREG; REPEAT NEXT INST. 10 TIMES MAC 0FF00h,*+ ;MULTIPLY AND ACCUMULATE; INCREMENT AR4. APAC ;ACCUMULATE LAST PRODUCT. RET ;ACCUMULATOR CONTAINS RESULT.

5.2.3

Bit-Reversed Addressing
In the bit-reversed addressing mode, INDX specifies one-half the size of the FFT. The value contained in the current AR must be equal to 2n1, where n is an integer, and the FFT size is 2n. An auxiliary register points to the physical location of a data value. When you add INDX to the current AR using bitreversed addressing, addresses are generated in a bit-reversed fashion. Assume that the auxiliary registers are eight bits long, that AR2 represents the base address of the data in memory (0110 00002), and that INDX contains the value 0000 10002. Example 510 shows a sequence of modifications to AR2 and the resulting values of AR2. Table 54 shows the relationship of the bit pattern of the index steps and the four LSBs of AR2, which contain the bitreversed address.

5-12

0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0

In Example 58, the content of the data memory address, defined by the content of the current AR, is shifted left 8 bits and added to the ACC. The content of INDX with reverse carry propagation is added to the current AR. The instruction word is 28F0h.

Indirect Addressing

Example 510. Sequence of Auxiliary Register Modifications in Bit-Reversed Addressing

*BR0+ *BR0+ *BR0+ *BR0+ *BR0+ *BR0+ *BR0+ *BR0+ ;AR2 ,AR2 ;AR2 ;AR2 ;AR2 ;AR2 ;AR2 ;AR2 = = = = = = = = 0110 0110 0110 0110 0110 0110 0110 0110 0000 1000 0100 1100 0010 1010 0110 1110 (0th (1st (2nd (3rd (4th (5th (6th (7th value) value) value) value) value) value) value) value)

Table 54. Bit-Reversed Addresses

Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Pattern 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bit-Reversed Pattern 0000 1000 0100 1100 0010 1010 0110 1110 0001 1001 0101 1101 0011 1011 0111 1111 Bit-Reversed Step 0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15

Addressing Modes

5-13

Immediate Addressing

5.3 Immediate Addressing

In immediate addressing, the instruction word(s) contains the value of the immediate operand. The C5x has both 1-word (8-bit, 9-bit, and 13-bit constant) short immediate instructions and 2-word (16-bit constant) long immediate instructions. Table 55 lists the instructions that support immediate addressing.

Table 55. Instructions That Support Immediate Addressing

Short Immediate (1-Word) 8-Bit Constant ADD ADRK LACL LAR RPT SBRK SUB 9-Bit Constant LDP 13-Bit Constant MPY Long Immediate (2-Word) 16-Bit Constant ADD AND APL CPL LACC LAR MPY OPL OR RPT RPTZ SPLK SUB XOR XPL

5.3.1

Short Immediate Addressing

In short immediate instructions, the operand is contained within the instruction machine code. Figure 55 shows an example of the short immediate mode. Note that in this example, the lower 8 bits are the operand and will be added to the ACC by the CALU.

Figure 55. Short Immediate Addressing Mode

ADD #0FFh Machine Code ADD opcode 1 0 1 1 1 0 0 0 1 1 1 1 0FFh 1 1 1 1

Operand

1 1 1 1

1 1 1 1

5-14

Immediate Addressing

5.3.2

Long Immediate Addressing

In long immediate instructions, the operand is contained in the second word of a two-word instruction. There are two long immediate addressing modes:
- One-operand instructions - Two-operand instructions

5.3.2.1

Long Immediate Addressing with Single/No Data Memory Access

Figure 56 shows an example of long immediate addressing with no data memory access. In Figure 56, the second word of the 2-word instruction is added to the ACC by the CALU.

Figure 56. Long Immediate Addressing Mode No Data Memory Access

ADD opcode ADD #01234h Machine Code Operand 1 0 1 1 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0

01234h

5.3.2.2

Long Immediate Addressing with Dual Data Memory Access

The long immediate addressing also could apply for a second data memory access for the execution of the instruction. The prefetch counter (PFC) is pushed onto the microcall stack (MCS), and the long immediate value is loaded into the PFC. The program address/data bus is then used for the operand fetch or write. At the completion of the instruction, the MCS is popped back to the PFC, the program counter (PC) is incremented by two, and execution continues. The PFC is used so that when the instruction is repeated, the address generated can be autoincremented. Figure 57 shows an example of long immediate addressing with two operands. In Figure 57, the source address (OPERAND1) is fetched via PAB, and the destination address (OPERAND2) uses the direct addressing mode. Bits 15 through 8 of machine code1 contain the opcode. Bit 7, with a value of 0, defines the addressing mode as direct, and bits 6 through 0 contain the dma.
Addressing Modes
5-15

Immediate Addressing

Figure 57. Long Immediate Addressing Mode Two Operands

BLDD opcode BLDD #02345h,012h
15 8 7 6 0

012h

Machine Code1

1 0 1 0

1 0 0 0

0 0 0 1

0 0 1 0

DP

1 1 0 0

1 1 1 0

DAB

1 1 0 0

1 1 1 0

1 0 0 1

0 0 1 0

02345h Machine Code2 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1

PC Operand1 Operand2
Note:

0 0 1 0 Data (PC) Data (DAB)

0 0 1 1

0 1 0 0

0 1 0 1

DAB is the 16-bit internal data memory address bus.

5-16

Dedicated-Register Addressing

5.4 Dedicated-Register Addressing

The dedicated-registered addressing mode operates like the long immediate addressing mode, except that the address comes from one of two special-purpose memory-mapped registers in the CPU: the block move address register (BMAR) and the dynamic bit manipulation register (DBMR). The advantage of this addressing mode is that the address of the block of memory to be acted upon can be changed during execution of the program. The syntax for dedicated-register addressing can be stated in one of two ways:
- Specify BMAR by its predefined symbol:

BLDD BMAR,DAT100 ;DP = 0. BMAR contains the value 200h.

The content of data memory location 200h is copied to data memory location 100 on the current data page.
- Exclude the immediate value from a parallel logic unit (PLU) instruction:

OPL

DAT10 ;DP = 6. DBMR contains the value FFF0h. ;Address 030Ah contains the value 01h

The content of data memory location 030Ah is ORed with the content of the DBMR. The resulting value FFF1h is stored back in memory location 030Ah.

5.4.1

Using the Contents of the BMAR

The BLDD, BLDP, and BLPD instructions use the BMAR to point at the source or destination space of a block move. The MADD and MADS instructions also use the BMAR to address an operand in program memory for a multiplyaccumulate operation. Figure 58 shows how the BMAR is used in the dedicated-register addressing mode. Bits 15 through 8 of the machine code contain the opcode. Bit 7, with a value of 0, defines the addressing mode as direct, and bits 6 through 0 contain the dma.

Addressing Modes

5-17

Dedicated-Register Addressing

Figure 58. Dedicated-Register Addressing Using the BMAR

BLDD opcode BLDD BMAR, 012h
15 8 7 6 0

012h

Machine Code

1 0 1 0

1 1 0 0 0 0 0 1

0 0 1 0

DP

1 1 0 0

1 1 1 0

DAB BMAR Operand1 Operand2

Note:

1 1 0 0 PFC Data (PFC) Data (DAB)

1 1 1 0

1 0 0 1

0 0 1 0

DAB is the 16-bit internal data memory address bus.

5.4.2

Using the Contents of the DBMR

The APL, CPL, OPL, and XPL instructions use the PLU and the contents of the DBMR when an immediate value is not specified as one of the operands. Figure 59 illustrates how the DBMR is used as an AND mask in the APL instruction. Bits 15 through 8 of the machine code contain the opcode. Bit 7, with a value of 0, defines the addressing mode as direct, and bits 6 through 0 contain the dma.

Figure 59. Dedicated-Register Addressing Using the DBMR

APL opcode APL 010h
15 8 7 6 0

010h

Machine Code

0 1 0 1

1 0 1 0

0 0 0 1

0 0 0 0

DP

1 1 0 0

1 1 1 0

DAB Operand1 Operand2

Note:

1 1 0 0 Data(DAB) DBMR

1 1 1 0

1 0 0 1

0 0 0 0

DAB is the 16-bit internal data memory address bus.

5-18

Memory-Mapped Register Addressing

5.5 Memory-Mapped Register Addressing

With memory-mapped register addressing, you can modify the memorymapped registers without affecting the current data page pointer value. In addition, you can modify any scratch pad RAM (DARAM B2) location or data page 0. The memory-mapped register addressing mode operates like the direct addressing mode, except that the 9 MSBs of the address are forced to 0 instead of being loaded with the contents of the DP. This allows you to address the memory-mapped registers of data page 0 directly without the overhead of changing the DP or auxiliary register. The following instructions operate in the memory-mapped register addressing mode. Using these instructions does not affect the contents of the DP:
-

LAMM Load accumulator with memory-mapped register LMMR Load memory-mapped register SAMM Store accumulator in memory-mapped register SMMR Store memory-mapped register

Figure 510 illustrates how this is done by forcing the 9 MSBs of the data memory address to 0, regardless of the current value of the DP when direct addressing is used or of the current AR value when indirect addressing is used. Example 511 uses memory-mapped register addressing in the direct addressing mode and Example 512 uses the indirect addressing mode.

Figure 510. Memory-Mapped Register Addressing

7 LSBs from IREG (direct addressing) or current AR (indirect addressing) 7 LSBs
15 6 0

16-bit memory-mapped register address

dma

PAGE 0

DAB

128-WORD PAGE

(MEMORYMAPPED REGISTERS AND DARAM B2)

Addressing Modes

5-19

Memory-Mapped Register Addressing

Example 511. Memory-Mapped Register Addressing in the Indirect Addressing Mode

SAMM *+ ;STORE ACC TO PMST REGISTER

In Example 511, assume that ARP = 3 and AR3 = FF07h. The content of the ACC is stored to the PMST (address 07h) pointed at by the 7 LSBs of AR3.

Example 512. Memory-Mapped Register Addressing in the Direct Addressing Mode

LAMM 07h ;ACC = PMST

In Example 512, assume that DP = 0184h and TEMP1 = 8060h. The content of memory location 07h (PMST) is loaded into the ACC. Figure 511 illustrates memory-mapped register addressing in the direct addressing mode.

Figure 511.Memory-Mapped Addressing in the Direct Addressing Mode

LAMM opcode LAMM PMST
15 8 7 6 0

07h

Machine Code

0 0 0 0

1 0 0 0

0 0 0 0

0 1 1 1

Value

0 0 0 0

0 0 0 0

DAB Operand
Note:

0 0 0 0 Data(DAB)

0 0 0 0

0 0 0 0

0 1 1 1

DAB is the 16-bit internal data memory address bus.

5-20

Circular Addressing

5.6 Circular Addressing

Many algorithms such as convolution, correlation, and finite impulse response (FIR) filters can use circular buffers in memory to implement a sliding window, which contains the most recent data to be processed. The C5x supports two concurrent circular buffers operating via the ARs. The following five memory-mapped registers control the circular buffer operation:
-

CBSR1 Circular buffer 1 start register CBSR2 Circular buffer 2 start register CBER1 Circular buffer 1 end register CBER2 Circular buffer 2 end register CBCR Circular buffer control register

The 8-bit CBCR enables and disables the circular buffer operation and is defined in subsection 4.4.1, Circular Buffer Control Register (CBCR), on page 4-6. To define circular buffers, you first load the start and end addresses into the corresponding buffer registers; next, load a value between the start and end registers for the circular buffer into an AR. Load the proper AR value, and set the corresponding circular buffer enable bit in the CBCR. Note that you must not enable the same AR for both circular buffers; if you do, unexpected results occur. The algorithm for circular buffer addressing below shows that the test of the AR value is performed before any modifications: If (ARn = CBER) and (any AR modification), Then: ARn = CBSR. Else: ARn = ARn + step. If ARn = CBER and no AR modification occurs, the current AR is not modified and is still equal to CBER. When the current AR = CBER, any AR modification (increment or decrement) will set the current AR = CBSR. Example 513 illustrates the operation of circular addressing.

Addressing Modes

5-21

Circular Addressing

Example 513. Circular Addressing

mar lpd splk splk splk lar lacc lar lacc lar lacc lar lacc lar lacc lar lacc lar adrk lar adrk *,ar6 #,0 #200h,CBSR1 #203h,CBER1 #0Eh,CBCR ar6,#200h * ar6,#203h * ar6,#200h *+ ar6,#203h *+ ar6,#200h * ar6,#203h * ar6,#202h 2 ar6,#203h 2 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Circular buffer start register Circular buffer end register Enable AR6 pointing to buffer 1 Case 1 AR6 = 200h Case 2 AR6 = 203h Case 3 AR6 = 201h Case 4 AR6 = 200h Case 5 AR6 = 1FFh Case 6 AR6 = 200h Case 7 AR6 = 204h Case 8 AR6 = 200h

In circular addressing, the step is the quantity that is being added to or subtracted from the specified AR. Take care when using a step of greater than 1 to modify the AR pointing to an element of the circular buffer. If an update to an AR generates an address outside the range of the circular buffer, the ARAU does not detect this situation, and the buffer does not wrap around. AR updates are performed as described in Section 5.2, Indirect Addressing. Because of the pipeline, there is a two-cycle latency between configuring the CBCR and performing AR modifications. Circular buffers can be used in increment- or decrement-type updates. For incrementing the value in the AR, the value in CBER must be greater than the value in CBSR. For decrementing the value in the AR, the value in CBSR must be greater than the value in CBER.

5-22

Chapter 6

Assembly Language Instructions

The C5x instruction set supports numerically intensive signal-processing operations as well as general-purpose applications, such as multiprocessing and high-speed control. The instruction set is a superset of the C1x and C2x instruction sets and is source-code upward compatible with both devices. Section 6.3, Instruction Set Descriptions, describes individual instructions in detail. Chapter 5, Addressing Modes, discusses the addressing modes associated with the instruction set. Section C.4, C2x-to-C5x Instruction Set Mapping, includes a table that maps C2x instructions to C5x instructions. Note that the Texas Instruments C5x assembler accepts C2x instructions as well as C5x instructions.

Topic
6.1 6.2 6.3

Page
Instruction Set Symbols and Notations . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Instruction Set Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22

Assembly Language Instructions

6-1

Instruction Set Symbols and Notations

6.1 Instruction Set Symbols and Notations

For the sake of convenience and as a memory aid, this chapter uses many symbols and notations while describing the assembly language instructions. This section provides a centralized list of definitions for these symbols and notations.

6.1.1

Symbols and Abbreviations Used in the Instruction Set Opcodes

Table 61 explains the symbols and abbreviations used in the opcode of the instruction set summaries (Table 64 through Table 610) and instruction set descriptions (Section 6.3, page 6-22).

Table 61. Instruction Set Opcode Symbols and Abbreviations

Symbol AAA AAAA Meaning The data memory address bits. When indirect addressing (I = 1) is being used, the seven As are the seven least significant bits (LSBs) of a data memory address. For indirect addressing, the seven As are bits that control auxiliary register manipulation (see Section 5.2, Indirect Addressing, on page 5-4.) A 3-bit value used in the LAR and SAR instructions to designate which auxiliary register (07) will be loaded (LAR) or have its contents stored (SAR). A 4-bit value (called the bit code) that determines which bit of a designated data memory value will be tested by the BIT instruction. A 2-bit value that determines the comparison performed by the CMPR instruction. The addressing mode bit. When I = 0, the direct addressing mode is being used. When I =1, the indirect addressing mode is being used. An 8-bit constant used in short immediate addressing for the ADD, ADRK, LACL, LAR, RPT, SBRK, and SUB instructions. A 9-bit constant used in short immediate addressing for the LDP instruction. A 13-bit constant used in short immediate addressing for the MPY instruction. The interrupt vector number. A 5-bit value representing a number from 0 to 31. The INTR instruction uses this number to change program control to one of the 32 interrupt vector addresses. A 2-bit value copied into the product shift mode (PM) bits of status register ST1 by the SPM instruction. A 3-bit shift value for the SACH and SACL instructions. A 4-bit shift value for the ADD, AND, BSAR, LACC, OR, SUB, and XOR instructions.

ARX BITX CM I kkkk kkkk k kkkk kkkk k kkkk kkkk kkkk I NTR #

PM SHF SHFT

6-2

Instruction Set Symbols and Notations

Table 61. Instruction Set Opcode Symbols and Abbreviations (Continued)

Symbol N Meaning A 1-bit field for the XC instruction indicating the number of instructions (one or two) to conditionally execute. If N = 0, one instruction will execute. If N = 1, two instructions will execute. A 2-bit value used by the conditional execution instructions to represent the following conditions: TP 00 01 10 11 ZLVC ZLVC Condition BIO pin low TC = 1 TC = 0 (NTC) None of the above conditions

TP

Two 4-bit fields designating the following bit conditions to be tested and the bit states: Bit Z L V C Condition ACC = 0 ACC < 0 Overflow Carry

A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a mask field. A 1 in a mask bit indicates that the corresponding condition is being tested. The second 4-bit field (bits 47) indicates the state of the conditions being tested. For example, to test for ACC 0, the Z and L bits of the 4-LSB field are set, while the V and C bits are not set. When the Z bit is set, it indicates to test for the condition ACC = 0; when the L bit is set, it indicates to test for the condition ACC 0. The conditions possible with these 8 bits are shown in the BCND, BCNDD, CC, CCD, RETC, RETCD, and XC instructions. To determine if the conditions are met, the 4-LSB field is ANDed with the 4-bit field containing the state of the conditions. If any bits are set, the conditions are met. + 1 word The second word of a two-word opcode. This second word contains a 16-bit constant. Depending on the instruction, this constant is a long immediate value, a program memory address, or an address for an I/O port or an I/O-mapped register.

Assembly Language Instructions

6-3

Instruction Set Symbols and Notations

6.1.2

Symbols and Abbreviations Used in the Instruction Set Descriptions

Table 62 explains the symbols and abbreviations used in the instruction set descriptions (Section 6.3, page 6-22).

Table 62. Instruction Set Descriptions Symbols and Abbreviations

Symbol ACC ACCB ACCH ACCL addr ALU AR ARB ARCR ARn ARP AVIS BIO bit code BMAR BRAF C CNF cond current AR D dst DATn DBMR dma Meaning Accumulator Accumulator buffer Accumulator high byte, ACC(3116) Accumulator low byte, ACC(150) 16-bit data memory address Arithmetic logic unit Auxiliary register Auxiliary register buffer (in ST1). This register stores the previous ARP value. Auxiliary register compare register A value n from 0 to 7 designating the next auxiliary register (AR), the register that will be pointed to by the ARP when the instruction is complete Auxiliary register pointer (in ST0). This register points to the current auxiliary register (AR). Address visibility bit (in PMST) Branch control input A 4-bit value that determines which bit of a designated data memory value will be tested by the BIT instruction. Block move address register Block repeat active flag bit (in PMST) Carry bit (in ST1) On-chip RAM configuration control bit (in ST1) An operand representing a condition used by instructions that execute conditionally. The current auxiliary register; that is, the auxiliary register (AR) pointed to by the ARP. Data memory address field Destination address field Label assigned to data memory location n Dynamic bit manipulation register The 7 LSBs of a data memory address.

6-4

Instruction Set Symbols and Notations

Table 62. Instruction Set Descriptions Symbols and Abbreviations (Continued)

Symbol DP HM ind INTM k K lk MCS MP/MC Meaning Data memory page pointer bits (in ST0) Hold mode bit (in ST1) Indirect addressing operand (see Section 5.2, Indirect Addressing, on page 5-4.) Interrupt mode flag bit (in ST0) Short immediate operand (an 8-, 9-, or 13-bit constant) A value from 0 to 31 indicating one of the 32 interrupt vector locations. The INTR instruction forces a branch to the location referenced by K. Long immediate operand (a 16-bit constant) Microcall stack Microprocessor/Microcomputer bit (in PMST)

n A value of 1 or 2 designating the number of words following the XC instruction. Overflow bit (in ST0) OV OVLY OVM NDX PA PAER PASR RAM overlay bit (in PMST) Overflow mode bit (in ST0) Enable extra index register bit (in PMST) A 16-bit address for an I/O port or an I/O-mapped register ( 0 PA 65535 ) Block Repeat Program Address End Register

Block Repeat Program Address Start Register Program counter Prefetch counter PC PFC PGMn PM pma PREG RAM bit Label assigned to program memory location n Product shift mode bits (in ST1) A 16-bit program memory address Product register Program RAM enable bit (in PMST) Repeat counter

RPTC shift A 4-bit shift value from 015 A 3-bit shift value from 07 Source address field shift2 src

Assembly Language Instructions

6-5

Instruction Set Symbols and Notations

Table 62. Instruction Set Descriptions Symbols and Abbreviations (Continued)

Symbol STm SXM TREGn TC TOS TRM x XF Meaning Status register m (m = 0 or 1) Sign-extension mode bit (in ST1) Temporary register n (n = 0, 1, or 2) Test/control bit (in ST1) Top of stack Enable multiple TREGs bit (in PMST) A value from 0 to 7 designating one of the eight auxiliary registers (AR0AR7). XF pin status bit (in ST1)

6.1.3

Notations Used in the Instruction Set Descriptions

Special notations have been used to describe the execution of the instructions and to indicate how a particular instruction is to be written. Table 63 explains the notations used in the instruction set descriptions (Section 6.3, page 6-22).

Table 63. Instruction Set Descriptions Notations

Notation x |x| { nnh (r) xy } Meaning Logical inversion (1s complement) of x Absolute value of x Alternative items, one of which must be entered Indicates that nn represents a hexadecimal number The content of register or location r. Example: (dma) means: The value at data memory address dma. Value x is assigned to register or location y. Example: (dma) ACC means: The content of the data memory address is put into the accumulator. Value x is switched with value y. Example: (ACCB) (ACC) means: The content of the accumulator buffer is switched with the content of the accumulator. Bits n through m of register or location r. Example: ACC(150) means: Bits 15 through 0 of the accumulator. The content of bits n through m of register or location r. Example: (ACC(31:16)) means: The content of bits 31 through 16 of the accumulator.

xy

r(nm) (r(nm))

6-6

Instruction Set Symbols and Notations

Table 63. Instruction Set Descriptions Notations (Continued)

Notation Boldface Characters Meaning Boldface characters in an instruction syntax are to be typed as shown. Example: For the syntax: ADD dma, 16, you may use a variety of values for dma, but the word ADD and the number 16 should be typed as shown. Samples with this syntax follow: ADD 7h, 16 ADD X, 16 Italic symbols in an instruction syntax represent variables. Example: For the syntax: ADD dma, you may use a variety of values for dma. Samples with this syntax follow: ADD DAT ADD 15 The # symbol is a prefix for constants used in immediate addressing. For short- or long-immediate operands, it is used in instructions where there is ambiguity with other addressing modes. Example: RPT #15 uses short immediate addressing. It causes the next instruction to be repeated 16 times. RPT 15 uses direct addressing. The number of times the next instruction repeats is determined by a value stored in memory. Operand x is optional. Example: For the syntax: ADD dma, [,shift ], you may use a variety of values for dma. Samples with this syntax follow: ADD 7h You have the option of adding a shift value, as in the instruction: ADD 7h, 5 Operands x1 and x2 are optional, but you cannot include x2 without also including x1. Example: For the syntax: ADD ind, [,shift [,ARn ] ], you must supply ind, as in the instruction: ADD *+ You have the option of including shift, as in the instruction: ADD *+, 5 If you wish to include ARn, you must also include shift, as in: ADD *+, 0, AR2

italic symbols

[,x]

[,x1 [,x2 ] ]

Assembly Language Instructions

6-7

Instruction Set Summary

6.2 Instruction Set Summary

This section summarizes the instruction set and instruction set opcodes for the C5x. Table 64 through Table 610 alphabetically list the C5x instructions within the following functional groups:
- Accumulator memory reference instructions (Table 64) - Auxiliary registers and data memory page pointer instructions (Table 65

on page 6-13)
- Parallel logic unit (PLU) instructions (Table 66 on page 6-14) - TREG0, PREG, and multiply instructions (Table 67 on page 6-15) - Branch and call instructions (Table 68 on page 6-17) - I/O and data memory operation instructions (Table 69 on page 6-19) - Control instructions (Table 610 on page 6-20)

The number of words that an instruction occupies in program memory is specified in the Words column of the table. Several instructions specify two values in the Words column because different forms of the instruction occupy a different number of words. For example, the ADD instruction occupies one word when the operand is a short immediate value or two words if the operand is a long immediate value. The number of cycles that an instruction requires to execute is in the Cycles column of the table. The tables assume that all instructions are executed from internal program memory (ROM) and internal data memory (RAM). The cycle timings are for single-instruction execution, not for repeat mode. Additional information is presented in Section 6.3, Instruction Set Descriptions on page 6-22. Bold typeface indicates instructions that are new for the C5x instruction set.

A read or write access to any peripheral memory-mapped register in data memory locations 20h4Fh will add one cycle to the cycle time shown. This occurs because all peripherals perform these accesses over the TI Bus, which requires an additional cycle.

Note that all writes to external memory require two cycles. Reads require one cycle. Any write access immediately before or after a read cycle will require three cycles (refer to Chapter 8). In addition, if two pipelined instructions try to access the same 2K-word single-access memory block simultaneously, one
6-8

Instruction Set Summary

extra cycle is required. For example, the DMOV instruction when used with the RPT instruction, requires one cycle in the dual-access RAM but requires two cycles in the single-access RAM. Wait states are added to all external accesses according to the configuration of the software wait-state registers described in Section 9.4, Software-Programmable Wait-State Generators, on page 9-13.

Table 64. Accumulator Memory Reference Instructions

Mnemonic ABS ADCB ADD Description Absolute value of ACC; zero carry bit Add ACCB and carry bit to ACC Add data memory value, with left shift, to ACC Add data memory value, with left shift of 16, to ACC Add short immediate to ACC Add long immediate, with left shift, to ACC ADDB ADDC Add ACCB to ACC Add data memory value and carry bit to ACC with sign extension suppressed Add data memory value to ACC with sign extension suppressed Add data memory value, with left shift specified by TREG1, to ACC AND data memory value with ACCL; zero ACCH AND long immediate, with left shift, with ACC AND long immediate, with left shift of 16, with ACC ANDB BSAR AND ACCB with ACC Barrel-shift ACC right Words 1 1 1 1 1 2 1 1 Cycles 1 1 1 1 1 2 1 1 Opcode 1011 1011 0010 0110 1011 1110 1110 0000 0001 0000 0001 AAAA AAAA kkkk SHFT 0000 AAAA Page 6-28 6-30 6-31 6-31 6-31 6-31 6-35 6-36

SHFT IAAA 0001 1000 IAAA kkkk 1001 0001 IAAA

1011 1111 + 1 word 1011 0110 1110 0000

ADDS ADDT AND

1 1 1 2 2 1 1

1 1 1 2 2 1 1

0110 0110 0110

0010 0011 1110

IAAA IAAA IAAA 1011 1000 0001 1110

AAAA AAAA AAAA SHFT 0001 0010 SHFT

6-38 6-40 6-43 6-43 6-43 6-46 6-82

1011 1111 + 1 word 1011 1110 + 1 word 1011 1011 1110 1111

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode. Peripheral memory-mapped register access

Assembly Language Instructions

6-9

Instruction Set Summary

Table 64. Accumulator Memory Reference Instructions (Continued)

Mnemonic CMPL CRGT CRLT EXAR LACB LACC Description 1s complement ACC Store ACC in ACCB if ACC > ACCB Store ACC in ACCB if ACC < ACCB Exchange ACCB with ACC Load ACC to ACCB Load data memory value, with left shift, to ACC Load long immediate, with left shift, to ACC Load data memory value, with left shift of 16, to ACC LACL Load data memory value to ACCL; zero ACCH Load short immediate to ACCL; zero ACCH LACT LAMM Load data memory value, with left shift specified by TREG1, to ACC Load contents of memorymapped register to ACCL; zero ACCH Negate (2s complement) ACC Normalize ACC OR data memory value with ACCL OR long immediate, with left shift, with ACC OR long immediate, with left shift of 16, with ACC Words 1 1 1 1 1 1 2 1 1 1 1 1 Cycles 1 1 1 1 1 1 2 1 1 1 1 1 or 2 Opcode 1011 1011 1011 1011 1011 0001 1110 1110 1110 1110 1110 0000 0001 0001 0001 0001 0001 1011 1100 1101 1111 AAAA SHFT AAAA AAAA kkkk AAAA AAAA Page 6-94 6-100 6-102 6-106 6-113 6-114 6-114 6-114 6-117 6-117 6-120 6-122

SHFT IAAA 1000 IAAA IAAA kkkk IAAA IAAA

1011 1111 + 1 word 0110 0110 1011 0110 0000 1010 1001 1001 1011 1000

NEG NORM OR

1 1 1 2 2

1 1 1 2 2

1011 1010 0110

1110 0000 1101

0000 IAAA IAAA 1100 1000

0010 AAAA AAAA SHFT 0010

6-177 6-181 6-187 6-187 6-187

1011 1111 + 1 word 1011 1110 + 1 word

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode. Peripheral memory-mapped register access

6-10

Instruction Set Summary

Table 64. Accumulator Memory Reference Instructions (Continued)

Mnemonic ORB ROL ROLB ROR RORB SACB SACH SACL SAMM SATH SATL SBB SBBB SFL SFLB SFR SFRB Description OR ACCB with ACC Rotate ACC left 1 bit Rotate ACCB and ACC left 1 bit Rotate ACC right 1 bit Rotate ACCB and ACC right 1 bit Store ACC in ACCB Store ACCH, with left shift, in data memory location Store ACCL, with left shift, in data memory location Store ACCL in mapped register memoryWords 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Cycles 1 1 1 1 1 1 1 1 1 or 2 1 1 1 1 1 1 1 1 Opcode 1011 1011 1011 1011 1011 1011 1001 1001 1000 1011 1011 1011 1011 1011 1011 1011 1011 1110 1110 1110 1110 1110 1110 0001 0000 0001 0000 0001 0001 0011 1100 0100 1101 0101 1110 AAAA AAAA AAAA 1010 1011 1000 1001 1001 0110 1010 0111 Page 6-190 6-210 6-211 6-212 6-213 6-220 6-221 6-223 6-225 6-229 6-231 6-232 6-233 6-237 6-238 6-239 6-241

1SHF IAAA 0SHF IAAA 1000 1110 1110 1110 1110 1110 1110 1110 1110 IAAA 0101 0101 0001 0001 0000 0001 0000 0001

Barrel-shift ACC right 0 or 16 bits as specified by TREG1 Barrel-shift ACC right as specified by TREG1 Subtract ACCB from ACC Subtract ACCB and logical inversion of carry bit from ACC Shift ACC left 1 bit Shift ACCB and ACC left 1 bit Shift ACC right 1 bit Shift ACCB and ACC right 1 bit

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode. Peripheral memory-mapped register access

Assembly Language Instructions

6-11

Instruction Set Summary

Table 64. Accumulator Memory Reference Instructions (Continued)

Mnemonic SUB Description Subtract data memory value, with left shift, from ACC Subtract data memory value, with left shift of 16, from ACC Subtract short immediate from ACC Subtract long immediate, with left shift, from ACC SUBB Subtract data memory value and logical inversion of carry bit from ACC with sign extension suppressed Conditional subtract Subtract data memory value from ACC with sign extension suppressed Subtract data memory value, with left shift specified by TREG1, from ACC Exclusive-OR data value with ACCL memory Words 1 1 1 2 1 Cycles 1 1 1 2 1 Opcode 0011 0110 1011 SHFT IAAA AAAA 0101 1010 IAAA AAAA kkkk kkkk Page 6-259 6-259 6-259 6-259 6-263

1011 1111 + 1 word 0110 0100

1010 SHFT IAAA AAAA

SUBC SUBS

1 1

1 1

0000 0110

1010 0110

IAAA AAAA IAAA AAAA

6-265 6-267

SUBT

0110

0111

IAAA AAAA

6-269

XOR

1 2 2 1 1 1

1 2 2 1 1 1

0110

1100

IAAA AAAA 1000 0011 1101 SHFT

6-280 6-280 6-280 6-283 6-287 6-289

Exclusive-OR long immediate, with left shift of 16, with ACC Exclusive-OR long immediate, with left shift, with ACC XORB ZALR ZAP Exclusive-OR ACCB with ACC Zero ACCL and load ACCH with rounding Zero ACC and PREG

1011 1110 + 1 word 1011 1111 + 1 word 1011 0110 1011 1110 1000 1110

0001 1010 IAAA AAAA 0101 1001

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode. Peripheral memory-mapped register access

6-12

Instruction Set Summary

Table 65. Auxiliary Registers and Data Memory Page Pointer Instructions
Mnemonic ADRK CMPR LAR Description Add short immediate to AR Compare AR with ARCR as specified by CM bits Load data memory value to ARx Load short immediate to ARx Load long immediate to ARx LDP Load data memory value to DP bits Load short immediate to DP bits MAR SAR SBRK Modify AR Store ARx in data memory location Subtract short immediate from AR Words 1 1 1 1 2 1 1 1 1 1 Cycles 1 1 2 2 2 2 2 1 1 1 Opcode 0111 1011 0000 1011 1000 1111 kkkk 0100 kkkk 01CM AAAA kkkk 1ARX AAAA kkkk AAAA AAAA kkkk Page 6-42 6-95 6-124 6-124 6-124 6-127 6-127 6-166 6-227 6-234

0ARX IAAA 0ARX kkkk 0000 IAAA kkkk IAAA

1011 1111 + 1 word 0000 1011 1000 1000 0111 1101 110I 1011

0ARX IAAA 1100 kkkk

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode.

Assembly Language Instructions

6-13

Instruction Set Summary

Table 66. Parallel Logic Unit (PLU) Instructions

Mnemonic APL Description AND data memory value with DBMR, and store result in data memory location AND data memory value with long immediate and store result in data memory location CPL Compare data memory value with DBMR Compare data memory value with long immediate OPL OR data memory value with DBMR and store result in data memory location OR data memory value with long immediate and store result in data memory location SPLK XPL Store long immediate in data memory location Exclusive-OR data memory value with DBMR and store result in data memory location Exclusive-OR data memory value with long immediate and store result in data memory location LPH LT Load data memory value to PREG high byte Load data memory value to TREG0 Words 1 Cycles 1 Opcode 0101 1010 IAAA AAAA Page 6-48

0101 1110 + 1 word 0101 1011

IAAA

AAAA

6-48

1 2 1

1 2 1

IAAA IAAA IAAA

AAAA AAAA AAAA

6-97 6-97 6-184

0101 1111 + 1 word 0101 1001

0101 1101 + 1 word 1010 1110 + 1 word 0101 1000

IAAA

AAAA

6-184

2 1

2 1

IAAA IAAA

AAAA AAAA

6-251 6-284

0101 1100 + 1 word

IAAA

AAAA

6-284

1 1

1 1

0111 0111

0101 0011

IAAA IAAA

AAAA AAAA

6-133 6-138

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode.

6-14

Instruction Set Summary

Table 67. TREG0, PREG, and Multiply Instructions

Mnemonic LTA Description Load data memory value to TREG0; add PREG, with shift specified by PM bits, to ACC Load data memory value to TREG0; add PREG, with shift specified by PM bits, to ACC; and move data Load data memory value to TREG0; store PREG, with shift specified by PM bits, in ACC Load data memory value to TREG0; subtract PREG, with shift specified by PM bits, from ACC Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by program memory value and store result in PREG Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by program memory value and store result in PREG; and move data Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by value specified in BMAR and store result in PREG; and move data Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by value specified in BMAR and store result in PREG Words 1 Cycles 1 Opcode 0111 0000 IAAA AAAA Page 6-140

LTD

0111

0010

IAAA

AAAA

6-142

LTP

0111

0001

IAAA

AAAA

6-145

LTS

0111

0100

IAAA

AAAA

6-147

MAC

1010 0010 + 1 word

IAAA

AAAA

6-149

MACD

1010 0011 + 1 word

IAAA

AAAA

6-153

MADD

1010

1011

IAAA

AAAA

6-158

MADS

1010

1010

IAAA

AAAA

6-162

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode.

Assembly Language Instructions

6-15

Instruction Set Summary

Table 67. TREG0, PREG, and Multiply Instructions (Continued)

Mnemonic MPY Description Multiply data memory value by TREG0 and store result in PREG Multiply short immediate by TREG0 and store result in PREG Multiply long immediate by TREG0 and store result in PREG MPYA Add PREG, with shift specified by PM bits, to ACC; multiply data memory value by TREG0 and store result in PREG Subtract PREG, with shift specified by PM bits, from ACC; multiply data memory value by TREG0 and store result in PREG Multiply unsigned data memory value by TREG0 and store result in PREG Load PREG, with shift specified by PM bits, to ACC Subtract PREG, with shift specified by PM bits, from ACC Subtract PREG, with shift specified by PM bits, from ACC Store PREG high byte, with shift specified by PM bits, in data memory location Store PREG low byte, with shift specified by PM bits, in data memory location Set product shift mode (PM) bits Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; square value and store result in PREG Words 1 1 2 1 Cycles 1 1 2 1 Opcode 0101 110k 0100 kkkk IAAA kkkk 1000 IAAA AAAA kkk 0000 AAAA Page 6-168 6-168 6-168 6-171

1011 1110 + 1 word 0101 0000

MPYS

0101

0001

IAAA

AAAA

6-173

MPYU

0101

0101

IAAA

AAAA

6-175

PAC SPAC SPAC SPH

1 1 1 1

1 1 1 1

1011 1011 1011 1000

1110 1110 1110 1101

0000 0000 0000 IAAA

0011 0101 0101 AAAA

6-193 6-246 6-246 6-247

SPL

1000

1100

IAAA

AAAA

6-249

SPM SQRA

1 1

1 1

1011 0101

1111 0010

0000 IAAA

00PM AAAA

6-252 6-253

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode.

6-16

Instruction Set Summary

Table 67. TREG0, PREG, and Multiply Instructions (Continued)

Mnemonic SQRS Description Subtract PREG, with shift specified by PM bits, from ACC; load data memory value to TREG0; square value and store result in PREG Zero PREG Words 1 Cycles 1 Opcode 0101 0011 IAAA AAAA Page 6-255

ZPR

1011

1110

0101

1000

6-290

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode.

Table 68. Branch and Call Instructions

Mnemonic B BACC BACCD Description Branch unconditionally to program memory location Branch to program memory location specified by ACCL Delayed branch to program memory location specified by ACCL Branch to program memory location if AR not zero Delayed branch to program memory location if AR not zero Branch conditionally to program memory location Delayed branch conditionally to program memory location Delayed branch unconditionally to program memory location Call to subroutine addressed by ACCL Words 2 1 1 Cycles 4 4 2 Opcode 0111 1001 + 1 word 1011 1011 1110 1110 1AAA AAAA 0010 0010 0000 0001 Page 6-51 6-52 6-53

BANZ BANZD BCND BCNDD BD CALA

2 2 2 2 2 1

4 or 2# 2 4 or 2# 2 2 4

0111 1011 + 1 word 0111 1111 + 1 word

1AAA AAAA 1AAA AAAA

6-54 6-56 6-58 6-60 6-62 6-83

1110 00TP ZLVC ZLVC + 1 word 1111 00TP ZLVC ZLVC + 1 word 0111 1101 + 1 word 1011 1110 1AAA AAAA 0011 0000

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode. Conditions true # Condition false

Assembly Language Instructions

6-17

Instruction Set Summary

Table 68. Branch and Call Instructions (Continued)

Mnemonic CALAD CALL CALLD CC CCD INTR Description Delayed call to subroutine addressed by ACCL Call to subroutine unconditionally Delayed call to subroutine unconditionally Call to subroutine conditionally Delayed call to subroutine conditionally Software interrupt that branches program control to program memory location Nonmaskable interrupt and globally disable interrupts (INTM = 1) Return from subroutine Return from subroutine conditionally Delayed return from subroutine conditionally Delayed return from subroutine Return from interrupt with context switch and globally enable interrupts (INTM = 0) Return from interrupt with context switch Software interrupt that branches program control to program memory location 22h Execute next conditionally instruction(s) Words 1 2 2 2 2 1 Cycles 2 4 2 4 or 2# 2 4 Opcode 1011 1110 0011 1101 Page 6-84 6-85 6-86 6-88 6-90 6-111

0111 1010 + 1 word 0111 1110 + 1 word

1AAA AAAA 1AAA AAAA

1110 10TP ZLVC ZLVC + 1 word 1111 10TP ZLVC ZLVC + 1 word 1011 1110 011 I NTR#

NMI RET RETC RETCD RETD RETE

1 1 1 1 1 1

4 4 2 4 or 2# 2 4

1011 1110 1110 1111 1111 1011

1110 1111 11TP 11TP 1111 1110

0101 0000

0010 0000

6-179 6-202 6-203 6-205 6-207 6-208

ZLVC ZLVC ZLVC ZLVC 0000 0011 0000 1010

RETI TRAP

1 1

4 4

1011 1011

1110 1110

0011 0101

1000 0001

6-209 6-277

XC

111N

01TP ZLVC ZLVC

6-278

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode. Conditions true # Condition false

6-18

Instruction Set Summary

Table 69. I/O and Data Memory Operation Instructions

Mnemonic BLDD Description Block move from data to data memory Block move from data to data memory with destination address long immediate Block move from data to data memory with source address in BMAR Block move from data to data memory with destination address in BMAR BLDP Block move from data to program memory with destination address in BMAR Block move from program to data memory with source address in BMAR Block move from program to data memory with source address long immediate DMOV IN LMMR OUT SMMR TBLR Move data in data memory Input data from I/O port to data memory location Load data memory value to memory-mapped register Output data from data memory location to I/O port Store memory-mapped register in data memory location Transfer data from program to data memory with source address in ACCL Transfer data from data to program memory with destination address in ACCL Words 2 2 Cycles 3 3 Opcode 1010 1000 + 1 word 1010 1001 + 1 word 1010 1100 IAAA IAAA AAAA AAAA Page 6-67 6-67

IAAA

AAAA

6-67

1010

1101

IAAA

AAAA

6-67

0101

0111

IAAA

AAAA

6-73

BLPD

1010

0100

IAAA

AAAA

6-76

1010 0101 + 1 word 0111 0111

IAAA

AAAA

6-76

1 2 2 2 2 1

1 2 2 or 3 3 2 or 3 3

IAAA IAAA IAAA IAAA IAAA IAAA

AAAA AAAA AAAA AAAA AAAA AAAA

6-104 6-109 6-130 6-191 6-243 6-271

1010 1111 + 1 word 1000 1001 + 1 word 0000 1100 + 1 word 0000 1001 + 1 word 1010 0110

TBLW

1010

0111

IAAA

AAAA

6-274

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode. Peripheral memory-mapped register access

Assembly Language Instructions

6-19

Instruction Set Summary

Table 610. Control Instructions

Mnemonic BIT BITT CLRC Description Test bit Test bit specified by TREG2 Clear overflow mode (OVM) bit Clear sign extension mode (SXM) bit Clear hold mode (HM) bit Clear test/control (TC) bit Clear carry (C) bit Clear configuration (CNF) bit control Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Cycles 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 Opcode 0100 0110 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 0000 0000 1000 1011 1000 0111 1011 BITX 1111 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1111 1011 1110 1010 0110 1110 IAAA IAAA 0100 0100 0100 0100 0100 0100 0100 0100 0010 0010 IAAA IAAA 0000 0011 IAAA IAAA 0011 AAAA AAAA 0010 0110 1000 1010 1110 0100 0000 1100 0010 0011 AAAA AAAA 0000 0010 AAAA AAAA 1100 Page 6-63 6-65 6-92 6-92 6-92 6-92 6-92 6-92 6-92 6-92 6-107 6-108 6-135 6-135 6-180 6-194 6-196 6-198 6-200

Clear interrupt mode (INTM) bit Clear external flag (XF) pin IDLE IDLE2 LST Idle until nonmaskable interrupt or reset Idle until nonmaskable interrupt or reset low-power mode Load data memory value to ST0 Load data memory value to ST1 NOP POP POPD PSHD PUSH No operation Pop top of stack to ACCL; zero ACCH Pop top of stack to data memory location Push data memory value to top of stack Push ACCL to top of stack

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode.

6-20

Instruction Set Summary

Table 610. Control Instructions (Continued)

Mnemonic RPT Description Repeat next instruction specified by data memory value Repeat next instruction specified by short immediate Repeat next instruction specified by long immediate RPTB RPTZ Repeat block of instructions specified by BRCR Clear ACC and PREG; repeat next instruction specified by long immediate Set overflow mode (OVM) bit Set sign extension mode (SXM) bit Set hold mode (HM) bit Set test/control (TC) bit Set carry (C) bit Set external flag (XF) pin high Set configuration control (CNF) bit Set interrupt mode (INTM) bit SST Store ST0 in data memory location Store ST1 in data memory location Words 1 1 2 2 2 Cycles 1 2 2 2 2 Opcode 0000 1011 1011 1011 IAAA kkkk 1100 1100 1100 AAAA kkkk 0100 0110 0101 Page 6-214 6-214 6-214 6-217 6-219

1011 1110 + 1 word 1011 1110 + 1 word 1011 1110 + 1 word 1011 1011 1011 1011 1011 1011 1011 1011 1000 1000 1110 1110 1110 1110 1110 1110 1110 1110 1110 1111

SETC

1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1

0100 0100 0100 0100 0100 0100 0100 0100 IAAA IAAA

0011 0111 1001 1011 1111 1101 0101 0001 AAAA AAAA

6-235 6-235 6-235 6-235 6-235 6-235 6-235 6-235 6-257 6-257

Bold typeface indicates instructions that are new for the C5x instruction set. The cycle timings are for single-instruction execution, not for repeat mode.

Assembly Language Instructions

6-21

Instruction Set Descriptions

6.3 Instruction Set Descriptions

This section provides detailed information on the instruction set for the C5x family; see Table 64 through Table 610 for a complete list of available instructions. Each instruction description presents the following information:
-

Assembler syntax Operands Opcodes Execution Status Bits Description Words Cycles Examples

The EXAMPLE instruction is provided to familiarize you with the format of the instruction descriptions and to explain what is described under each heading.

6-22

Syntax

Direct: Indirect: Short immediate: Long immediate:

EXAMPLE dma [,shift ] EXAMPLE {ind} [,shift ] [,ARn ] EXAMPLE #k EXAMPLE #lk

Each instruction description begins with an assembly language syntax expression. A source statement can contain four ordered fields. The general syntax for source statements is as follows: [label ] [:]

mnemonic

[operand list ]

[;comment ]

Follow these guidelines:

- All statements must begin with a label, a blank, an asterisk, or a semicolon. - Labels are optional; if used, they must begin in column 1. Labels may be

placed either before the instruction mnemonic on the same line or on the preceding line in the first column.
- One or more blanks must separate each field. Tab characters are equiva-

lent to blanks.
- Comments are optional. Comments that begin in column 1 can begin with

an asterisk or a semicolon (* or ;), but comments that begin in any other column must begin with a semicolon. See Table 62 on page 6-4 for definitions of symbols and abbreviations used in the syntax expression. Operands 0 dma 127 0 pma 65535 0 shift 15 0 shift2 7 0n7 0 k 255 0 lk 65535 0x7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Operands can be constants or assembly-time expressions that refer to memory, I/O ports, register addresses, pointers, shift counts, and a variety of other constants. This section also gives the range of acceptable values for the operand types. Opcode
15 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x

The opcode graphic shows bit values or field names that make up each instruction. See Table 61 on page 6-2 for definitions of symbols and abbreviations used in the instruction opcodes.
6-23

Execution

(PC) + 1 PC (ACC) + (dma) ACC 0 C The execution section symbolically represents the process that takes place when the instruction is executed. See Table 62 on page 6-4 for definitions of symbols and abbreviations used in the execution section.

Status Bits

Affected by: OVM

Not affected by: SXM

Affects: C and OV

An instructions execution may be affected by the state of the fields in the status registers; also it may affect the state of the status register fields. Both the effects on and the effects of the status register fields are listed in this section. Description This section describes the instruction execution and its effect on the rest of the processor or memory contents. Any constraints on the operands imposed by the processor or the assembler are discussed. The description parallels and supplements the information given symbolically in the execution section. This section specifies the number of memory words required to store the instruction and its extension words. This section provides tables showing the number of cycles required for a given instruction to execute in a given memory configuration both as a single instruction and in the repeat (RPT) mode. The following are examples of the cycle timing tables.
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1 1+d External Memory 1+p 1+p 2+d+p

Words

Cycles

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n n+nd External Memory n+p n+p n+1+p+nd

6-24

The column headings in the tables indicate the program source location. The program source locations are defined as follows: ROM DARAM SARAM The instruction executes from on-chip program ROM. The instruction executes from on-chip dual-access program RAM. The instruction executes from on-chip single-access program RAM.

External Memory The instruction executes from external program memory.

If an instruction requires memory operand(s), the rows in the tables indicate the location(s) of the operand(s). The operands are defined as follows: DARAM SARAM External ROM MMR MMPORT The operand is in internal dual-access RAM. The operand is in internal single-access RAM. The operand is in external memory. The operand is in internal program ROM. The operand is a memory-mapped register. The operand is a memory-mapped I/O port.

The number of cycles required for each instruction is given in terms of the processor machine cycles (CLKOUT1 period). The additional wait states for program/data memory and I/O accesses are defined below. Note that these additional cycles can be generated by the on-chip software wait-state generator or by the external READY signal. These variables can also use the subscripts src, dst, and code to indicate source, destination, and code, respectively. d Data memory wait states. Represents the number of additional clock cycles the device waits for external data memory to respond to an access. I/O wait states. Represents the number of additional clock cycles the device waits for an external I/O to respond to an access. Repetitions (where n > 2 to fill the pipeline). Represents the number of times a repeated instruction is executed. Program memory wait states. Represents the number of additional clock cycles the device waits for external program memory to respond to an access.

io n p

6-25

Table 611 lists the on-chip single-access RAM available on each C5x processor. The on-chip single-access RAM is divided into 1K- and/or 2K-word blocks contiguous in address memory space. All C5x processors support parallel accesses to these on-chip SARAM blocks. However, one SARAM block allows only one access per cycle. In other words, the processor can read/write on one SARAM block while accessing another SARAM block. All external reads require at least one machine cycle while all external writes require at least two machine cycles. However, if an external write is immediately followed or preceded by an external read cycle, then the external write requires three cycles. See Section 8.9, External Memory Interface Timings, on page 8-39 for details. If you use an on-chip wait-state generator to add m (m>0) wait states to an external access, then both the external reads and the external writes require m+1 cycles, assuming that the external READY line is driven high. If you use the READY input line to add m additional cycles to an external access, then external reads require m+1 cycles and external write accesses require m+2 cycles. See Section 9.4, Software-Programmable Wait-State Generators, on page 9-13 and the data sheet for READY electrical specifications.

Table 611. Address Blocks for On-Chip Single-Access RAM

6-26

Device C50 SARAM Block size Hex Address Range 08000FFF 100017FF 9K-word 2K-word block 2K-word block 2K-word block 2K-word block 1K-word block 1K-word block 2K-word block 1K-word block 2K-word block 2K-word block 2K-word block 2K-word block 2K-word block 2K-word block 18001FFF 200027FF 28002BFF C51 1K-word 3K-word 08000BFF 08000FFF 100013FF C53/C53S LC56 6K-word 08000FFF 100017FF 18001FFF 08000FFF 100017FF C57S/LC57 6K-word 18001FFF

The instruction cycles are based on the following assumptions:

- At least four instructions following the current instruction are fetched from

the same memory section (on-chip or external) as the current instruction, except in instructions that cause a program counter discontinuity, such as B, CALL, etc.
- When executing a single instruction, there is no pipeline conflict between

the current instruction and the instructions immediately preceding or following that instruction. The only exception is the conflict between the fetch phase of the pipeline and the memory read/write (if any) access of the instruction under consideration. See Chapter 7 for pipeline operation.
- In the repeat execution mode, all conflicts caused by the pipelined execu-

tion of that instruction are considered. Refer to Appendix B for a summary of instruction cycle classifications. Example Example code is shown for each instruction. The effect of the code on memory and/or registers is summarized.

6-27

Syntax Operands Opcode Execution

ABS None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

(PC) + 1 PC |(ACC)| ACC 0 C

Status Bits Description

Affected by: OVM

Not affected by: SXM

Affects: C and OV

If the contents of the accumulator (ACC) are greater than or equal to 0, the contents of the ACC is unchanged. If the contents of the ACC are less than 0, the contents of the ACC is replaced by its 2s-complement value. The ABS instruction clears the C bit. Note that 8000 0000h is a special case. When the OVM bit is cleared, the ABS of 8000 0000h is 8000 0000h. When the OVM bit is set, the ABS of 8000 0000h is 7FFF FFFFh. In either case, the OV bit is set. ABS is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example 1

ABS
Before Instruction ACC X C 1234h ACC 0 C After Instruction 1234h

Example 2

ABS
Before Instruction ACC X C FFFF FFFFh ACC 0 C After Instruction 1h

6-28

Example 3

ABS ;(OVM = 1)
Before Instruction ACC X C X OV 8000 0000h ACC 0 C 1 OV After Instruction 7FFF FFFFh

Example 4

ABS ;(OVM = 0)
Before Instruction ACC X C X OV 8000 0000h ACC 0 C 1 OV After Instruction 8000 0000h

6-29

Syntax Operands Opcode

ADCB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 0 0 1

Execution

(PC) + 1 PC (ACC) + (ACCB) + (C) ACC

Status Bits

Affected by: OVM

Affects: C and OV

Description

The contents of the accumulator buffer (ACCB) and the value of the C bit are added to the contents of the accumulator (ACC). The result is stored in the ACC and the contents of the ACCB are unaffected. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. ADCB is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

ADCB
Before Instruction ACC ACCB 1 C 1234h 2h ACC ACCB 0 C After Instruction 1237h 2h

6-30

Syntax

Direct: Indirect: Short immediate: Long immediate:

ADD dma [,shift ] ADD {ind} [,shift ] [,ARn ] ADD #k ADD #lk [,shift]

Operands

0 dma 127 0 shift 16 (defaults to 0) 0n7 0 k 255 32768 lk 32767 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing with shift
15 0 14 0 13 1 12 0 11 10 9 SHFT 8 7 0 6 5 4 3 2 dma 1 0

Opcode

See Table 61 on page 6-2.

Indirect addressing with shift

15 0 14 0 13 1 12 0 11 10 9 SHFT 8 7 1 6 5 4 3 2 See Section 5.2 1 0

See Table 61 on page 6-2.

Direct addressing with shift of 16

15 0 14 1 13 1 12 0 11 0 10 0 9 0 8 1 7 0 6 5 4 3 2 dma 1 0

Indirect addressing with shift of 16

15 0 14 1 13 1 12 0 11 0 10 0 9 0 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Short immediate addressing

15 1 14 0 13 1 12 1 11 1 10 0 9 0 8 0 7 6 5 4 3 2 8-Bit Constant 1 0

Long immediate addressing with shift

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 7 6 5 1 1 0 0 16-Bit Constant 4 1 3 2 1 SHFT 0

See Table 61 on page 6-2.

Execution

Direct or indirect addressing: (PC) + 1 PC (ACC) + ((dma)  2shift ) ACC

6-31

Short immediate addressing: (PC) + 1 PC (ACC) + k ACC Long immediate addressing: (PC) + 2 PC (ACC) + (lk  2shift ) ACC Status Bits

Affected by: OVM and SXM OVM OVM and SXM

Affects: C and OV C and OV C and OV

Direct or indirect addressing Short immediate addressing Long immediate addressing

Description

If direct, indirect, or long immediate addressing is used, the contents of the data memory address (dma) or a 16-bit constant are shifted left, as defined by the shift code, and added to the contents of the accumulator (ACC). The result is stored in the ACC. During shifting, the accumulator low byte (ACCL) is zero-filled. If the SXM bit is cleared, the high-order bits of the ACC are zerofilled; if the SXM bit is set, the high-order bits of the ACC are sign-extended. Note that when the auxiliary register pointer (ARP) is updated during indirect addressing, you must specify a shift operand. If you dont want a shift, you must enter a 0 for this operand. For example:
ADD*+,0,AR0

If short immediate addressing is used, an 8-bit positive constant is added to the contents of the ACC. The result is stored in the ACC. In this mode, no shift value may be specified and the addition is unaffected by the SXM bit. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. If a 16-bit shift is specified with the ADD instruction, the C bit is set only if the result of the addition generates a carry; otherwise, the C bit is unaffected. This allows the accumulation to generate the proper single carry when a 32-bit number is added to the ACC. ADD is an accumulator memory reference instruction (see Table 64). Words 1 2 (Direct, indirect, or short immediate addressing) (Long immediate addressing)

6-32

Cycles

For the short and long immediate addressing modes, the ADD instruction is not repeatable.
Cycles for a Single Instruction (direct or indirect addressing) Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing) Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing) ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Single Instruction (long immediate addressing) ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

Example 1

ADD

DAT1,1

;(DP = 6)
Before Instruction After Instruction Data Memory 301h ACC 0 C 1h 04h

Data Memory 301h ACC X C

1h 2h

6-33

Example 2

ADD

*+,0,AR0
Before Instruction ARP AR4 Data Memory 302h ACC X C 4 0302h 2h 2h ARP AR4 Data Memory 302h ACC 0 C After Instruction 0 0303h 2h 04h

Example 3

ADD

#1h ;Add short immediate

Before Instruction ACC X C 2h ACC 0 C After Instruction 03h

Example 4

ADD

#1111h,1 ;Add long immediate with shift of 1

Before Instruction ACC X C 2h ACC 0 C After Instruction 2224h

6-34

Syntax Operands Opcode

ADDB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 0 0 0

Execution

(PC) + 1 PC (ACC) + (ACCB) ACC

Status Bits

Affected by: OVM

Affects: C and OV

Description

The contents of the accumulator buffer (ACCB) are added to the contents of the accumulator (ACC). The result is stored in the ACC and the contents of the ACCB are unaffected. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. ADDB is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

ADDB
Before Instruction ACC ACCB X C 1234h 2h ACC ACCB 0 C After Instruction 1236h 2h

6-35

Syntax Operands

Direct: Indirect:

ADDC dma ADDC {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 0 11 0 10 0 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 0 10 0 9 0 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution Status Bits Description

(PC) + 1 PC (ACC) + (dma) + (C) ACC

Affected by: OVM

Not affected by: SXM

Affects: C and OV

The contents of the data memory address (dma) and the value of the C bit are added to the contents of the accumulator (ACC) with sign extension suppressed. The result is stored in the ACC. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. The ADDC instruction can be used in performing multiple-precision arithmetic. ADDC is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

6-36

Example 1

ADDC DAT0 ;(DP = 6)

Before Instruction Data Memory 300h ACC 1 C 04h 13h Data Memory 300h ACC 0 C After Instruction 04h 18h

Example 2

ADDC *,AR4 ;(OVM = 0)

Before Instruction ARP AR0 Data Memory 300h ACC 1 C X OV 0 300h 0h FFFF FFFFh ARP AR0 Data Memory 300h ACC 1 C 0 OV After Instruction 4 299h 0h 0h

6-37

Syntax

Direct: Indirect:

ADDS dma ADDS {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 0 11 0 10 0 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 0 10 0 9 1 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (ACC) + (dma) ACC (dma) is an unsigned16-bit number

Status Bits

Affected by: OVM

Not affected by: SXM

Affects: C and OV

Description

The contents of the data memory address (dma) are added to the contents of the accumulator (ACC) with sign extension suppressed. The data is treated as an unsigned 16-bit number, regardless of the SXM bit. The contents of the ACC are treated as a signed number. The result is stored in the ACC. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. The ADDS instruction produces the same results as an ADD instruction with the SXM bit cleared and a shift count of 0. ADDS is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

6-38

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

ADDS DAT0 ;(DP = 6)

Before Instruction Data Memory 300h ACC X C F006h 0000 0003h Data Memory 300h ACC 0 C After Instruction F006h 0000 F009h

Example 2

ADDS *
Before Instruction ARP AR0 Data Memory 300h ACC X C 0 0300h FFFFh 7FFF 0000h ARP AR0 Data Memory 300h ACC 0 C After Instruction 0 0300h FFFFh 7FFF FFFFh

6-39

Syntax

Direct: Indirect:

ADDT dma ADDT {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 0 11 0 10 0 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 0 10 0 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (ACC) + ((dma)  2TREG1(30) ) ACC If SXM = 0: (dma) is not sign-extended If SXM = 1: (dma) is sign-extended

Status Bits

Affected by: OVM, SXM, and TRM

Affects: C and OV

Description

The contents of the data memory address (dma) are shifted left from 0 to 15 bits, as defined by the 4 LSBs of TREG1, and added to the contents of the accumulator (ACC). The result is stored in the ACC. Sign extension on the dma value is controlled by the SXM bit. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs. Subsequent calls to the ADDT instruction will shift the value by the TREG1 value (which is the same as TREG0), maintaining C5x object-code compatibility with the C2x. ADDT is an accumulator memory reference instruction (see Table 64).

Words

6-40

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

ADDT DAT127 ;(DP = 4, SXM = 0)

Before Instruction Data Memory 027Fh TREG1 ACC X C 09h FF94h F715h Data Memory 027Fh TREG1 ACC 0 C After Instruction 09h FF94h F7A5h

Example 2

ADDT *,AR4 ;(SXM = 0)

Before Instruction ARP AR0 Data Memory 027Fh TREG1 ACC X C 0 027Fh 09h FF94h F715h ARP AR0 Data Memory 027Fh TREG1 ACC 0 C After Instruction 4 027Eh 09h FF94h F7A5h

6-41

Syntax Operands Opcode

ADRK #k 0 k 255
15 0 14 1 13 1 12 1 11 1 10 0 9 0 8 0 7 6 5 4 3 2 8-Bit Constant 1 0

Execution

(PC) + 1 PC (current AR) + 8-bit positive constant current AR None affected. The 8-bit immediate value, right-justified, is added to the current auxiliary register (AR). The result is stored in the AR. The addition takes place in the auxiliary register arithmetic unit (ARAU), with the immediate value treated as an 8-bit positive integer. All arithmetic operations on the AR are unsigned. ADRK is an auxiliary registers and data memory page pointer instruction (see Table 65).

Status Bits Description

Words Cycles

1 The ADRK instruction is not repeatable.

Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Example

ADRK #80h
Before Instruction ARP AR5 5 4321h ARP AR5 After Instruction 5 43A1h

6-42

Syntax

Direct: Indirect: Long immediate:

AND dma AND {ind} [,ARn ] AND #lk [,shift ]

Operands

0 dma 127 0n7 lk: 16-bit constant 0 shift 16 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 0 14 1 13 1 12 0 11 1 10 1 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 1 10 1 9 1 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Long immediate addressing with shift

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 7 6 5 1 1 0 1 16-Bit Constant 4 1 3 2 1 SHFT 0

See Table 61 on page 6-2.

Long immediate addressing with shift of 16

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 7 6 5 0 1 0 0 16-Bit Constant 4 0 3 0 2 0 1 0 0 1

Execution

Direct or indirect addressing: (PC) + 1 PC (ACC(150)) AND (dma) ACC(150) 0 ACC(3116) Long immediate addressing: (PC) + 2 PC (ACC(300)) AND (lk  2shift ) ACC

Status Bits Description

Not affected by: SXM

Long immediate addressing

If a long immediate constant is specified, the constant is shifted left and zeroextended on both ends and is ANDed with the contents of the accumulator (ACC). The result is stored in the ACC. If a constant is not specified, the contents of the data memory address (dma) are ANDed with the contents of the accumulator low byte (ACCL). The result is stored in the ACCL and the accumulator high byte (ACCH) is zero-filled. AND is an accumulator memory reference instruction (see Table 64).
6-43

Words Cycles

1 2

(Direct or indirect addressing) (Long immediate addressing)

For the long immediate addressing modes, the AND instruction is not repeatable.
Cycles for a Single Instruction (direct or indirect addressing) Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block.

Cycles for a Repeat (RPT) Execution (direct or indirect addressing) Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block.

Cycles for a Single Instruction (long immediate addressing) ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

Example 1

AND DAT16 ;(DP = 4)

Before Instruction Data Memory 0210h ACC 00FFh 1234 5678h Data Memory 0210h ACC After Instruction 00FFh 0000 0078h

Example 2

AND *
Before Instruction ARP AR0 Data Memory 0301h ACC 0 0301h FF00h 1234 5678h ARP AR0 Data Memory 0301h ACC After Instruction 0 0301h FF00h 0000 5600h

6-44

Example 3

AND #00FFh,4
Before Instruction ACC 1234 5678h ACC After Instruction 0000 0670h

6-45

Syntax Operands Opcode

ANDB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 1 0 0

Execution

(PC) + 1 PC (ACC) AND (ACCB) ACC None affected. The contents of the accumulator (ACC) are ANDed with the contents of the accumulator buffer (ACCB). The result is stored in the ACC and the contents of the ACCB are unaffected. ANDB is an accumulator memory reference instruction (see Table 64).

Status Bits Description

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

ANDB
Before Instruction ACC ACCB 0F0F FFFFh 5555 5555h ACC ACCB After Instruction 0505 5555h 5555 5555h

6-46

Syntax Operands Opcode

APAC None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 1 1 0 0 0

Execution

(PC) + 1 PC (ACC) + (shifted PREG) ACC

Status Bits

Affected by: OVM and PM

Not affected by: SXM

Affects: C and OV

Description

The contents of the product register (PREG) are shifted, as defined by the PM bits, and added to the contents of the accumulator (ACC). The result is stored in the ACC. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. The contents of the PREG are always sign extended. The APAC instruction is a subset of the LTA, LTD, MAC, MACD, MADS, MADD, MPYA, and SQRA instructions. APAC is a TREG0, PREG, and multiply instruction (see Table 67).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

APAC ;(PM = 01)

Before Instruction PREG ACC X C 40h 20h PREG ACC 0 C After Instruction 40h A0h

6-47

Syntax Operands

Direct: Indirect:

APL [#lk,] dma APL [#lk,] {ind} [,ARn ]

0 dma 127 lk: 16-bit constant 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing with long immediate not specified
15 0 14 1 13 0 12 1 11 1 10 0 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing with long immediate not specified

15 0 14 1 13 0 12 1 11 1 10 0 9 1 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Direct addressing with long immediate specified

15 0 14 1 13 0 12 1 11 1 10 1 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

16-Bit Constant

Indirect addressing with long immediate specified

15 0 14 1 13 0 12 1 11 1 10 1 9 8 7 6 1 0 1 16-Bit Constant 5 4 3 2 See Section 5.2 1 0

Execution

Long immediate not specified: (PC) + 1 PC (dma) AND (DBMR) dma Long immediate specified: (PC) + 2 PC (dma) AND lk dma

Status Bits Description

Affects: TC
If a long immediate constant is specified, the constant is ANDed with the contents of the data memory address (dma). If a constant is not specified, the contents of the dma are ANDed with the contents of the dynamic bit manipulation register (DBMR). In both cases, the result is written directly back to the dma and the contents of the accumulator (ACC) are unaffected. The TC bit is set, if the result of the AND operation is 0; otherwise, the TC bit is cleared. APL is a parallel logic unit (PLU) instruction (see Table 66).

Words

1 2

(Long immediate not specified) (Long immediate specified)

6-48

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction (second operand DBMR) ROM 1 1 2+2d DARAM 1 1 2+2d SARAM 1 1, 3 2+2d External Memory 1+p 1+p 5+2d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (second operand DBMR) Operand DARAM SARAM External ROM n 2n2 4n2+2nd DARAM n 2n2 4n2+2nd SARAM n 2n2, 2n+1 4n2+2nd External Memory n+p 2n2+p 4n+1+2nd+p

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate specified) ROM DARAM SARAM External 2 2 3+2d DARAM 2 2 3+2d SARAM 2 2 3+2d External Memory 2+2p 2+2p 6+2d+2p

Cycles for a Repeat (RPT) Execution (long immediate specified) ROM DARAM SARAM External n+1 2n1 4n1+2nd DARAM n+1 2n1 4n1+2nd SARAM n+1 2n1, 2n+2 4n1+2nd External Memory n+1+2p 2n1+2p 4n+2+2nd+2p

If the operand and the code reside in same SARAM block

6-49

Example 1

APL #0023h,DAT96 ;(DP = 0)

Before Instruction Data Memory 60h X TC 00h Data Memory 60h 1 TC After Instruction 00h

Example 2

APL DAT96 ;(DP = 0)

Before Instruction DBMR Data Memory 60h X TC FF00h 1111h DBMR Data Memory 60h 0 TC After Instruction FF00h 1100h

Example 3

APL #0100h,*,AR6
Before Instruction ARP AR5 Data Memory 300h X TC 5 300h 0FFFh ARP AR5 Data Memory 300h 0 TC After Instruction 6 300h 0100h

Example 4

APL *,AR7
Before Instruction ARP AR6 DBMR Data Memory 310h X TC 6 310h 0303h 0EFFh ARP AR6 DBMR Data Memory 310h 0 TC After Instruction 7 310h 0303h 0203h

6-50

Syntax Operands

B pma [, {ind} [,ARn ] ] 0 pma 65535 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0}
15 0 14 1 13 1 12 1 11 1 10 0 9 8 7 6 0 1 1 16-Bit Constant 5 4 3 2 See Section 5.2 1 0

Opcode

Execution

pma PC Modify current AR and ARP as specified None affected. Control is passed to the program memory address (pma). The current auxiliary register (AR) and auxiliary register pointer (ARP) are modified as specified. The pma can be either a symbolic or numeric address. B is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

2 The B instruction is not repeatable.

Cycles for a Single Instruction ROM 4 DARAM 4 SARAM 4 External Memory 4+4p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example

B 191,*+,AR1

The value 191 is loaded into the program counter (PC), and the program continues executing from that location. The current AR is incremented by 1, and ARP is set to 1.

6-51

Syntax Operands Opcode

BACC None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 0 3 0 2 0 1 0 0 0

Execution Status Bits Description

ACC(150) PC None affected. Control is passed to the 16-bit address residing in the accumulator low byte (ACCL). BACC is a branch and call instruction (see Table 68).

Words Cycles

1 The BACC instruction is not repeatable.

Cycles for a Single Instruction ROM 4 DARAM 4 SARAM 4 External Memory 4+3p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example

BACC ;(ACC contains the value 191)

The value 191 is loaded into the program counter (PC), and the program continues executing from that location.

6-52

Syntax Operands Opcode

BACCD None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 0 3 0 2 0 1 0 0 1

Execution Status Bits Description

ACC(150) PC None affected. The one 2-word instruction or two 1-word instructions following the BACCD instruction are fetched from program memory and executed before the branch is taken. After the instructions are executed, control is passed to the 16-bit address residing in the accumulator low byte (ACCL). BACCD is a branch and call instruction (see Table 68).

Words Cycles

1 The BACCD instruction is not repeatable.

Cycles for a Single Instruction ROM 2 DARAM 2 SARAM 2 External Memory 2+p

Example

BACCD MAR *+,AR1 LDP #5

;(ACC contains the value 191)

After the current AR, ARP, and DP are modified as specified, program execution continues from location 191.

6-53

Syntax Operands

BANZ pma [, {ind} [,ARn ] ] 0 pma 65535 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0}
15 0 14 1 13 1 12 1 11 1 10 0 9 8 7 6 1 1 1 16-Bit Constant 5 4 3 2 See Section 5.2 1 0

Opcode

Execution

If (current AR) 0: pma PC Else: (PC) + 2 PC Modify current AR as specified None affected. If the contents of the current auxiliary register (AR) are not 0, control is passed to the program memory address (pma); otherwise, control is passed to the next instruction. The default modification to current AR is a decrement by 1. You can cause N loop iterations to be executed by initializing the auxiliary register loop counter to N1 before loop entry. The pma can be either a symbolic or numeric address. BANZ is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

2 The BANZ instruction is not repeatable.

Cycles for a Single Instruction Condition True False ROM 4 2 DARAM 4 2 SARAM 4 2 External Memory 4+4p 2+2p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

6-54

Example 1

BANZ PGM0
Before Instruction ARP AR0 0 5h ARP AR0 After Instruction 0 4h

0 is loaded into the program counter (PC), and the program continues executing from that location. or
Before Instruction ARP AR0 0 0h ARP AR0 After Instruction 0 FFFFh

The PC is incremented by 2, and execution continues from that location. Example 2

MAR *,AR0 LAR AR1,#3 LAR AR0,#60h ADD *+,AR1 BANZ PGM191,AR0

PGM191

The contents of data memory locations 60h63h are added to the accumulator (ACC).

6-55

Syntax Operands

BANZD pma [, {ind} [,ARn ] ] 0 pma 65535 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0}
15 0 14 1 13 1 12 1 11 1 10 1 9 8 7 6 1 1 1 16-Bit Constant 5 4 3 2 See Section 5.2 1 0

Opcode

Execution

If (current AR) 0: pma PC Else: (PC) + 2 PC Modify current AR as specified None affected. The one 2-word instruction or two 1-word instructions following the branch instruction are fetched from program memory and executed before the branch is taken. After the instructions are executed if the contents of the current auxiliary register (AR) are not 0, control is passed to the program memory address (pma); otherwise, control is passed to the next instruction. The default modification to current AR is a decrement by 1. You can cause N loop iterations to be executed by initializing the auxiliary register loop counter to N1 before loop entry. The pma can be either a symbolic or numeric address. BANZD is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

2 The BANZD instruction is not repeatable.

Cycles for a Single Instruction ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

6-56

Example

BANZD PGM0 LACC #01h LDP #5

Before Instruction ARP AR0 DP ACC 0 5h 4 00h ARP AR0 DP ACC After Instruction 0 4h 5 01h

After the current DP and accumulator (ACC) are modified as specified, program execution continues from location 0.

6-57

Syntax Operands

BCND pma, cond [,cond1 ] [,...] 0 pma 65535 Conditions: ACC = 0 ACC 0 ACC < 0 ACC 0 ACC > 0 ACC 0 C=0 C=1 OV = 0 OV = 1 TC = 0 TC = 1 BIO low Unconditionally
12 0 11 0 10 0

EQ NEQ LT LEQ GT GEQ NC C NOV OV NTC TC BIO UNC

4 3 2 1 ZLVC 0

Opcode

15 1

14 1

13 1

9 8 7 6 5 TP ZLVC 16-Bit Constant

See Table 61 on page 6-2.

Execution

If (condition(s)): pma PC Else: (PC) + 2 PC None affected. If the specified conditions are met, control is passed to the program memory address (pma); otherwise, control is passed to the next instruction. Not all combinations of the conditions are meaningful and testing BIO is mutually exclusive to testing TC. BCND is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

2 The BCND instruction is not repeatable.

Cycles for a Single Instruction Condition True False ROM 4 2 DARAM 4 2 SARAM 4 2 External Memory 4+4p 2+2p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

6-58

Example

BCND PGM191,LEQ,C

If the accumulator (ACC) contents are less than or equal to 0 and the C bit is set, program address 191 is loaded into the program counter (PC), and the program continues executing from that location. If these conditions are not met, execution continues from location PC + 2.

6-59

Syntax Operands

BCNDD pma, cond [,cond1 ] [,...] 0 pma 65535 Conditions: ACC = 0 ACC 0 ACC < 0 ACC 0 ACC > 0 ACC 0 C=0 C=1 OV = 0 OV = 1 TC = 0 TC = 1 BIO low Unconditionally
12 1 11 0 10 0

EQ NEQ LT LEQ GT GEQ NC C NOV OV NTC TC BIO UNC

4 3 2 1 ZLVC 0

Opcode

15 1

14 1

13 1

9 8 7 6 5 TP ZLVC 16-Bit Constant

See Table 61 on page 6-2.

Execution

If (condition(s)): pma PC Else: (PC) + 2 PC None affected. The one 2-word instruction or two 1-word instructions following the branch are fetched from program memory and executed before the branch is taken. The two instruction words following the BCNDD instruction have no effect on the conditions being tested. After the instructions are executed if the specified conditions are met, control is passed to the program memory address (pma); otherwise, control is passed to the next instruction. Not all combinations of the conditions are meaningful and testing BIO is mutually exclusive to testing TC. BCNDD is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

2 The BCNDD instruction is not repeatable.

Cycles for a Single Instruction ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

6-60

Example

BCNDD PGM191,OV MAR *,AR1 LDP #5

After the current AR, ARP, and DP are modified as specified, program execution continues at location 191 if the overflow (OV) bit is set. If the OV bit is cleared, execution continues at the instruction following the LDP instruction.

6-61

Syntax Operands

BD pma [, {ind} [,ARn ] ] 0 pma 65535 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0}
15 0 14 1 13 1 12 1 11 1 10 1 9 8 7 6 0 1 1 16-Bit Constant 5 4 3 2 See Section 5.2 1 0

Opcode

Execution

pma PC Modify current AR and ARP as specified None affected. The one 2-word instruction or two 1-word instructions following the branch instruction are fetched from program memory and executed before the branch is taken. After the instructions are executed, control is passed to the program memory address (pma). The current auxiliary register (AR) and auxiliary register pointer (ARP) are modified as specified. The pma can be either a symbolic or numeric address. BD is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

2 The BD instruction is not repeatable.

Cycles for a Single Instruction ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

Example

BD 191 MAR *+,AR1 LDP #5

After the current AR, ARP, and DP are modified as specified, program execution continues from location 191.

6-62

Syntax Operands

Direct: Indirect:

BIT dma, bit code BIT {ind} , bit code [,ARn ]

0 dma 127 0n7 0 bit code 15 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 0 14 1 13 0 12 0 11 10 9 BITX 8 7 0 6 5 4 3 dma 2 1 0

Opcode

See Table 61 on page 6-2.

Indirect addressing
15 0 14 1 13 0 12 0 11 10 9 BITX 8 7 1 6 5 4 3 2 See Section 5.2 1 0

See Table 61 on page 6-2.

Execution Status Bits Description

(PC) + 1 PC (dma bit at bit address (15 bit code)) TC

Affects: TC
The specified bit of the data memory address (dma) value is copied to the TC bit in ST1. The APL, BITT, CMPR, CPL, LST1, NORM, OPL, and XPL instructions also affect the TC bit. The bit code value corresponds to a specified bit of the dma, as given by the following table:
Bit (LSB) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (MSB) 15 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Bit Code 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

BIT is a control instruction (see Table 610).

6-63

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

BIT 0h,15 ;(DP = 6).Test LSB at 300h

Before Instruction Data Memory 300h TC 4DC8h 0 Data Memory 300h TC After Instruction 4DC8h 0

Example 2

BIT *,0,AR1 ;Test MSB at 310h

Before Instruction ARP AR0 Data Memory 310h TC 0 310h 8000h 0 ARP AR0 Data Memory 310h TC After Instruction 1 310h 8000h 1

6-64

Syntax

Direct: Indirect:

BITT dma BITT {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 0 11 1 10 1 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 1 10 1 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (dma bit at bit address (15 TREG2(30))) TC

Status Bits Description

Affects: TC
The specified bit of the data memory address (dma) value is copied to the TC bit in ST1. The APL, BIT, CMPR, CPL, LST1, OPL, NORM, and XPL instructions also affect the TC bit. The bit code value contained in the 4 LSBs of the TREG2 corresponds to a specified bit of the dma, as given by the following table:
Bit (LSB) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (MSB) 15 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Bit Code 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

6-65

You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instructions that load TREG0 to write to all three TREGs. Subsequent calls to the BITT instruction will use the TREG2 value (which is the same as TREG0), maintaining C5x object-code compatibility with the C2x. BITT is a control instruction (see Table 610). Words Cycles
Operand DARAM SARAM External

1
Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

BITT 00h ;(DP = 6). Test bit 14 of data at 300h

Before Instruction Data Memory 300h TREG2 TC 4DC8h 1h 0 Data Memory 300h TREG2 TC After Instruction 4DC8h 1h 1

Example 2

BITT * ;Test bit 1 of data at 310h

Before Instruction ARP AR1 Data Memory 310h TREG2 TC 1 310h 8000h 0Eh 0 ARP AR1 Data Memory 310h TREG2 TC After Instruction 1 310h 8000h 0Eh 0

6-66

Syntax

General syntax:

BLDD src, dst

All valid cases have the general syntax: Direct BMAR/DMA: BLDD BMAR, dma Indirect BMAR/DMA: BLDD BMAR, {ind} [,ARn ] Direct DMA/BMAR: BLDD dma, BMAR Indirect DMA/BMAR: BLDD {ind}, BMAR [,ARn ] Direct K/DMA: BLDD #addr, dma Indirect K/DMA: BLDD #addr, {ind} [,ARn ] Direct DMA/K: BLDD dma, #addr Indirect DMA/K: BLDD {ind}, #addr [,ARn ] Operands 0 addr 65535 0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing with SRC specified by BMAR
15 1 14 0 13 1 12 0 11 1 10 1 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing with SRC specified by BMAR

15 1 14 0 13 1 12 0 11 1 10 1 9 0 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Direct addressing with DEST specified by BMAR

15 1 14 0 13 1 12 0 11 1 10 1 9 0 8 1 7 0 6 5 4 3 dma 2 1 0

Indirect addressing with DEST specified by BMAR

15 1 14 0 13 1 12 0 11 1 10 1 9 0 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Direct addressing with SRC specified by long immediate

15 1 14 0 13 1 12 0 11 1 10 0 9 8 7 6 0 0 0 16-Bit Constant 5 4 3 2 dma 1 0

Indirect addressing with SRC specified by long immediate

15 1 14 0 13 1 12 0 11 1 10 0 9 8 7 6 0 0 1 16-Bit Constant 5 4 3 2 See Section 5.2 1 0

Direct addressing with DEST specified by long immediate

15 1 14 0 13 1 12 0 11 1 10 0 9 8 7 6 0 1 0 16-Bit Constant 5 4 3 2 dma 1 0

6-67

Indirect addressing with DEST specified by long immediate

15 1 14 0 13 1 12 0 11 1 10 0 9 8 7 6 0 1 1 16-Bit Constant 5 4 3 2 See Section 5.2 1 0

Execution

(PFC) MCS If long immediate: (PC) + 2 PC #lk PFC Else: (PC) + 1 PC (BMAR) PFC While (repeat counter) 0: (src, addressed by PFC) dst or src (dst, addressed by PFC) Modify current AR and ARP as specified (PFC) + 1 PFC (repeat counter) 1 repeat counter (src, addressed by PFC) dst or src (dst, addressed by PFC) Modify current AR and ARP as specified (MCS) PFC

Status Bits Description

None affected. The contents of the data memory address (dma) pointed at by src (source) are copied to the dma pointed at by dst (destination). The source and/or destination space can be pointed at by a long immediate value, the contents of the block move address register (BMAR), or a dma. Not all src/dst combinations of pointer types are valid. The source and destination blocks do not have to be entirely on-chip or off-chip. In the indirect addressing mode, you can use the RPT instruction with the BLDD instruction to move consecutive words in data memory. The number of words to be moved is one greater than the number contained in the repeat counter register (RPTC) at the beginning of the instruction. If a long immediate value or the contents of the BMAR is specified in the repeat mode, the source and/or destination address is automatically incremented. If a dma is specified in the repeat mode, the dma address is not automatically incremented. When used with the RPT instruction, the BLDD instruction becomes a single-cycle instruction, once the RPT pipeline is started. Interrupts are inhibited during a BLDD operation used with the RPT instruction. BLDD is an I/O and data memory operation instruction (see Table 69).

6-68

Neither the long immediate value nor the BMAR can be used as the address to the on-chip memory-mapped registers. The direct or indirect addressing mode can be used as the address to the on-chip memory-mapped registers.

Words

1 2

(One source or destination is specified by BMAR) (One source or destination is specified by long immediate)

Cycles
Cycles for a Single Instruction (SRC or DEST in BMAR) Operand Source: DARAM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM 2 2 2+dsrc 2 2 2+dsrc 3+ddst 3+ddst 3+dsrc +ddst DARAM 2 2 2+dsrc 2 2 2+dsrc 3+ddst 3+ddst 3+dsrc +ddst SARAM 2 2 2+dsrc 2, 3 2, 3 2+dsrc , 3+dsrc 3+ddst 3+ddst 3+dsrc +ddst External Memory 2+p 2+p 2+dsrc +p 2+p 2+p 2+dsrc +p 5+ddst +p 5+ddst +p 5+dsrc +ddst +p

If the destination operand and the code are in the same SARAM block

6-69

Cycles for a Repeat (RPT) Execution (SRC or DEST in BMAR) Operand Source: DARAM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM n+1 n+1 n+1+ndsrc n+1 n+1, 2n1 n+1+ndsrc 2n+1+nddst 2n+1+nddst 4n1+ndsrc +nddst DARAM n+1 n+1 n+1+ndsrc n+1 n+1, 2n1 n+1+ndsrc 2n+1+nddst 2n+1+nddst 4n1+ndsrc +nddst SARAM n+1 n+1 n+1+ndsrc n+1, n+3 n+1, 2n1, n+3, 2n+1 n+1+ndsrc , n+3+ndsrc 2n+1+nddst 2n+1+nddst 4n1+ndsrc +nddst External Memory n+1+p n+1+p n+1+ndsrc +p n+1+p n+1+p, 2n1+p n+1+ndsrc +p 2n+1+nddst +p 2n+1+nddst +p 4n+1+ndsrc +nddst +p

If the destination operand and the code are in the same SARAM block If both the source and the destination operands are in the same SARAM block If both operands and the code are in the same SARAM block

Cycles for a Single Instruction (SRC or DEST long immediate) Operand Source: DARAM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM Destination: SARAM Source: SARAM Destination: SARAM ROM 3 3 3+dsrc 3 3 DARAM 3 3 3+dsrc 3 3 SARAM 3 3 3+dsrc 3, 4 3, 4 External Memory 3+2p 3+2p 3+dsrc +2p 3+2p 3+2p

If the destination operand and the code are in the same SARAM block

6-70

Cycles for a Single Instruction (SRC or DEST long immediate) (Continued) Operand Source: External Destination: SARAM Source: DARAM Destination: External Source: SARAM Destination: External Source: External Destination: External Source: DARAM Destination: DARAM ROM 3+dsrc 4+ddst 4+ddst 4+dsrc +ddst n+2 DARAM 3+dsrc 4+ddst 4+ddst 4+dsrc +ddst n+2 SARAM 3+dsrc , 4+dsrc 4+ddst 4+ddst 4+dsrc +ddst n+2 External Memory 3+dsrc +2p 6+ddst +2p 6+ddst +2p 6+dsrc +ddst +2p n+2+2p

If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (SRC or DEST long immediate) Operand Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM n+2 n+2+ndsrc n+2 n+2, 2n n+2ndsrc 2n+2+nddst 2n+2+nddst 4n+ndsrc +nddst DARAM n+2 n+2+ndsrc n+2 n+2, 2n n+2ndsrc 2n+2+nddst 2n+2+nddst 4n+ndsrc +nddst SARAM n+2 n+2+ndsrc n+2, n+4 n+2, 2n, n+4, 2n+2 n+2ndsrc , n+4+ndsrc 2n+2+nddst 2n+2+nddst 4n+ndsrc +nddst External Memory n+2+2p n+2+ndsrc n+2+2p n+2+2p, 2n+2p n+2+ndsrc +2p 2n+2+nddst +2p 2n+2+nddst +2p 4n+2+ndsrc +nddst +2p

If the destination operand and the code are in the same SARAM block If both the source and the destination operands are in the same SARAM block If both operands and the code are in the same SARAM block

6-71

Example 1

BLDD #300h,20h ;(DP = 6)

Before Instruction Data Memory 300h 320h 0h 0Fh Data Memory 300h 320h After Instruction 0h 0h

Example 2

BLDD *+,#321h,AR3
Before Instruction ARP AR2 Data Memory 301h 321h 2 301h 01h 0Fh ARP AR2 Data Memory 301h 321h After Instruction 3 302h 01h 01h

Example 3

BLDD BMAR,*
Before Instruction ARP BMAR AR2 Data Memory 320h 340h 2 320h 340h 01h 0Fh ARP BMAR AR2 Data Memory 320h 340h After Instruction 2 320h 340h 01h 01h

Example 4

BLDD 00h,BMAR ;(DP = 6)

Before Instruction Data Memory 300h BMAR Data Memory 320h 0Fh 320h 01h Data Memory 300h BMAR Data Memory 320h After Instruction 0Fh 320h 0Fh

Example 5

RPT 2 BLDD #300h,*+

Before Instruction ARP AR0 300h 301h 302h 320h 321h 322h 0 320h 7F98h FFE6h 9522h 8DEEh 9315h 2531h ARP AR0 300h 301h 302h 320h 321h 322h After Instruction 0 323h 7F98h FFE6h 9522h 7F98h 0FFE6h 9522h

6-72

Syntax Operands

Direct: Indirect:

BLDP dma BLDP {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 0 12 1 11 0 10 1 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 0 12 1 11 0 10 1 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (PFC) MCS (BMAR) PFC While (repeat counter) 0: dma (dst, addressed by PFC) Modify current AR and ARP as specified (PFC) + 1 PFC (repeat counter) 1 repeat counter dma (dst, addressed by PFC) Modify current AR and ARP as specified (MCS) PFC

Status Bits Description

None affected. The contents of the data memory address (dma) are copied to the program memory address (pma) pointed at by the block move address register (BMAR). The source and destination blocks do not have to be entirely on-chip or off-chip. In the indirect addressing mode, you can use the RPT instruction with the BLDP instruction to move consecutive words in data memory to a contiguous program memory space pointed at by the BMAR. The number of words to be moved is one greater than the number contained in the repeat counter register (RPTC) at the beginning of the instruction. The contents of the BMAR are automatically incremented when used in the repeat mode. When used with the RPT instruction, the BLDP instruction becomes a single-cycle instruction, once the RPT pipeline is started. Interrupts are inhibited during a BLDP operation used with the RPT instruction. BLDP is an I/O and data memory operation instruction (see Table 69).
6-73

Words Cycles

Cycles for a Single Instruction Operand Source: DARAM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM 2 2 2+dsrc 2 2 2+dsrc 3+pdst 3+pdst 3+dsrc +pdst DARAM 2 2, 3 2+dsrc 2 2 2+dsrc 3+pdst 3+pdst 3+dsrc +pdst SARAM 2 2 2+dsrc 2, 3 2, 3 , 4 2+dsrc , 3+dsrc 3+pdst 3+pdst , 4+pdst 3+dsrc +pdst External Memory 2+p 2+p 3+dsrc +pcode 2+p 2+p 3+dsrc +pcode 4+pdst +pcode 4+pdst +pcode 5+dsrc +pdst +pcode

If the destination operand and the code are in the same SARAM block If both operands and the code are in the same SARAM block If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand Source: DARAM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM ROM n+1 n+1 n+1+ndsrc DARAM n+1 n+1 n+1+ndsrc SARAM n+1 n+1, n+2 n+1+ndsrc External Memory n+1+pcode n+1+pcode n+2+ndsrc +pcode

If the destination operand and the code are in the same SARAM block If both the source and the destination operands are in the same SARAM block If both operands and the code are in the same SARAM block If the source operand and the code are in the same SARAM block

6-74

Cycles for a Repeat (RPT) Execution (Continued) Operand Source: DARAM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM n+1 n+1, 2n1 n+1+ndsrc 2n+1+npdst 2n+1+npdst 4n1+ndsrc +npdst DARAM n+1 n+1, 2n1 n+1+ndsrc 2n+1+npdst 2n+1+npdst 4n1+ndsr +npdst SARAM n+1, n+2 n+1, 2n1, n+2 , 2n+1 n+1+ndsrc , n+2+npsrc 2n+1+npdst 2n+1+npdst , 2n+2+npdst 4n1+ndsrc +npdst External Memory n+1+pcode n+1+pcode , 2n1+pcode n+2+ndsrc +pcode 2n+2+npdst +pcode 2n+2+npdst +pcode 4n+1+ndsrc +npdst +pcode

If the destination operand and the code are in the same SARAM block If both the source and the destination operands are in the same SARAM block If both operands and the code are in the same SARAM block If the source operand and the code are in the same SARAM block

Example 1

BLDP 00h ;(DP=6)

Before Instruction Data Memory 300h BMAR Program Memory 2800h A089h 2800h 1234h Data Memory 300h BMAR Program Memory 2800h After Instruction A089h 2800h A089h

Example 2

BLDP *,AR0
Before Instruction ARP AR7 Data Memory 310h BMAR Program Memory 2800h 7 310h F0F0h 2800h 1234h ARP AR7 Data Memory 310h BMAR Program Memory 2800h After Instruction 0 310h F0F0h 2800h F0F0h

6-75

Syntax

General syntax:

BLPD src, dst

All valid cases have the general syntax: Direct BMAR/DMA: BLPD BMAR, dma Indirect BMAR/DMA: BLPD BMAR, {ind} [,ARn ] Direct K/DMA: BLPD #pma, dma Indirect K/DMA: BLPD #pma, {ind} [,ARn ] Operands 0 pma 65535 0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing with SRC specified by BMAR
15 1 14 0 13 1 12 0 11 0 10 1 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing with SRC specified by BMAR

15 1 14 0 13 1 12 0 11 0 10 1 9 0 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Direct addressing with SRC specified by long immediate

15 1 14 0 13 1 12 0 11 0 10 1 9 8 7 6 0 1 0 16-Bit Constant 5 4 3 dma 2 1 0

Indirect addressing with SRC specified by long immediate

15 1 14 0 13 1 12 0 11 0 10 1 9 8 7 6 0 1 1 16-Bit Constant 5 4 3 2 See Section 5.2 1 0

Execution

If long immediate: (PC) + 2 PC (PFC) MCS lk PFC Else: (PC) + 1 PC (PFC) MCS (BMAR) PFC

6-76

While (repeat counter) 0: (pma, addressed by PFC) dst Modify current AR and ARP as specified (PFC) + 1 PFC (repeat counter) 1 repeat counter (pma, addressed by PFC) dst Modify current AR and ARP as specified (MCS) PFC Status Bits Description None affected. The contents of the program memory address (pma) pointed at by src (source) are copied to the data memory address (dma) pointed at by dst (destination). The source space can be pointed at by a long immediate value or the contents of the block move address register (BMAR). The destination space can be pointed at by a dma or the contents of current AR. Not all src/dst combinations of pointer types are valid. The source and destination blocks do not have to be entirely on-chip or off-chip. In the indirect addressing mode, you can use the RPT instruction with the BLPD instruction to move consecutive words in program memory to data memory. The number of words to be moved is one greater than the number contained in the repeat counter register (RPTC) at the beginning of the instruction. If a long immediate value or the contents of the BMAR is specified in the repeat mode, the source address is automatically incremented. When used with the RPT instruction, the BLPD instruction becomes a single-cycle instruction, once the RPT pipeline is started. Interrupts are inhibited during a BLPD operation used with the RPT instruction. BLPD is an I/O and data memory operation instruction (see Table 69). Words 1 2 Cycles
Cycles for a Single Instruction (SRC in BMAR) Operand Source: DARAM/ROM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM ROM 2 2 2+psrc DARAM 2 2 2+psrc SARAM 2 2 2+psrc External Memory 2+pcode 2+pcode 2+psrc +pcode

(Source is specified by BMAR) (Source is specified by long immediate)

If the destination operand and the code are in the same SARAM block

6-77

Cycles for a Single Instruction (SRC in BMAR) (Continued) Operand Source: DARAM/ROM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM/ROM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM 2 2 2+psrc 3+ddst 3+ddst 3+psrc +ddst DARAM 2 2 2+psrc 3+ddst 3+ddst 3+psrc +ddst SARAM 2, 3 2, 3 2+psrc , 3+psrc 3+ddst 3+ddst 3+psrc +ddst External Memory 2+pcode 2+pcode 2+psrc +2pcode 5+ddst +pcode 5+ddst +pcode 5+psrc +ddst +pcode

If the destination operand and the code are in the same SARAM block

6-78

Cycles for a Repeat (RPT) Execution (SRC in BMAR) Operand Source: DARAM/ROM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM/ROM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM/ROM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM n+1 n+1 n+1+npsrc n+1 n+1, 2n1 n+1+npsrc 2n+1+nddst 2n+1+nddst 4n1+npsrc +nddst DARAM n+1 n+1 n+1+npsrc n+1 n+1, 2n1 n+1+npsrc 2n+1+nddst 2n+1+nddst 4n1+npsrc +nddst SARAM n+1 n+1 n+1+npsrc n+1, n+3 n+1, 2n1, n+3, 2n+1 n+1+npsrc , n+3+npsrc 2n+1+nddst 2n+1+nddst 4n1+npsrc +nddst External Memory n+1+pcode n+1+pcode n+1+npsrc +pcode n+1+pcode n+1+pcode , 2n1+pcode n+1+npsrc +pcode 2n+1+nddst +pcode 2n+1+nddst +pcode 4n+1+npsrc +nddst +pcode

If the destination operand and the code are in the same SARAM block If both the source and the destination operands are in the same SARAM block If both operands and the code are in the same SARAM block

Cycles for a Single Instruction (SRC long immediate) Operand Source: DARAM/ROM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM/ROM Destination: SARAM Source: SARAM Destination: SARAM ROM 3 3 3+psrc 3 3 DARAM 3 3 3+psrc 3 3 SARAM 3 3 3+psrc 3, 4 3, 4 External Memory 3+2pcode 3+2pcode 3+psrc +2pcode 3+2pcode 3+2pcode

If the destination operand and the code are in the same SARAM block

6-79

Cycles for a Single Instruction (SRC long immediate) (Continued) Operand Source: External Destination: SARAM Source: DARAM/ROM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM 3+psrc 4+ddst 4+ddst 4+psrc +ddst DARAM 3+psrc 4+ddst 4+ddst 4+psrc +ddst SARAM 3+psrc , 4+psrc 4+ddst 4+ddst 4+psrc +ddst External Memory 3+psrc +2pcode 6+ddst +2pcode 6+ddst +2pcode 6+psrc +ddst +2pcode

If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (SRC long immediate) Operand Source: DARAM/ROM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM/ROM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM/ROM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM n+2 n+2 n+2+npsrc n+2 n+2, 2n n+2+npsrc 2n+2+nddst 2n+2+nddst 4n+npsrc +nddst DARAM n+2 n+2 n+2+npsrc n+2 n+2, 2n n+2+npsrc 2n+2+nddst 2n+2+nddst 4n+npsrc +nddst SARAM n+2 n+2 n+2+npsrc n+2, n+4 n+2, 2n, n+4, 2n+2 n+2+npsrc , n+4+npsrc 2n+2+nddst 2n+2+nddst 4n+npsrc +nddst External Memory n+2+2pcode n+2+2pcode n+2+npsrc +2pcode n+2+2pcode n+2+2pcode , 2n+2pcode n+2+npsrc +2pcode 2n+2+nddst +2pcode 2n+2+nddst +2pcode 4n+2+npsrc +nddst +2pcode

If the destination operand and the code are in the same SARAM block If both the source and the destination operands are in the same SARAM block If both operands and the code are in the same SARAM block

6-80

Example 1

BLPD #800h,00h ;(DP=6)

Before Instruction Program Memory 800h Data Memory 300h 0Fh 0h Program Memory 800h Data Memory 300h After Instruction 0Fh 0Fh

Example 2

BLPD #800h,*,AR7
Before Instruction ARP AR0 Program Memory 800h Data Memory 310h 0 310h 1111h 0100h ARP AR0 Program Memory 800h Data Memory 310h After Instruction 7 310h 1111h 1111h

Example 3

BLPD BMAR,00h ;(DP=6)

Before Instruction BMAR Program Memory 800h Data Memory 300h 800h 0Fh 0h BMAR Program Memory 800h Data Memory 300h After Instruction 800h 0Fh 0Fh

Example 4

BLPD BMAR,*+,AR7
Before Instruction ARP AR0 BMAR Program Memory 810h Data Memory 300h 0 300h 810h 4444h 0100h ARP AR0 BMAR Program Memory 810h Data Memory 300h After Instruction 7 301h 810h 4444h 4444h

6-81

Syntax Operands Opcode

BSAR shift 1 shift 16

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 0 3 2 1 SHFT 0

See Table 61 on page 6-2.

Execution

(PC) + 1 PC (ACC) / 2shift ACC

Status Bits Description

Affected by: SXM

The contents of the accumulator (ACC) are right-barrel arithmetic shifted 1 to 16 bits, as defined by the shift code, in a single cycle. If the SXM bit is cleared, the high-order bits of the ACC are zero-filled; if the SXM bit is set, the high-order bits of the ACC are sign-extended. BSAR is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example 1

BSAR 16 ;(SXM=0)
Before Instruction ACC 0001 0000h ACC After Instruction 0000 0001h

Example 2

BSAR 4 ;(SXM=1)
Before Instruction ACC FFF1 0000h ACC After Instruction FFFF 1000h

6-82

Syntax Operands Opcode

CALA None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 1 3 0 2 0 1 0 0 0

Execution

(PC) + 1 TOS (ACC(150)) PC None affected. The current program counter (PC) is incremented and pushed onto the top of the stack (TOS). The contents of the accumulator low byte (ACCL) are loaded into the PC. Execution continues at this address. The CALA instruction is used to perform computed subroutine calls. CALA is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

1 The CALA instruction is not repeatable.

Cycles for a Single Instruction ROM 4 DARAM 4 SARAM 4 External Memory 4+3p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example

CALA
Before Instruction PC ACC TOS 25h 83h 100h PC ACC TOS After Instruction 83h 83h 26h

6-83

Syntax Operands Opcode Execution Status Bits Description

CALAD None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 1 3 1 2 1 1 0 0 1

(PC) + 3 TOS (ACC(150)) PC None affected. The current program counter (PC) is incremented by 3 and pushed onto the top of the stack (TOS). Then, the one 2-word instruction or two 1-word instructions following the CALAD instruction are fetched from program memory and executed before the call is executed. Then, the contents of the accumulator low byte (ACCL) are loaded into the PC. Execution continues at this address. The CALAD instruction is used to perform computed subroutine calls. CALAD is a branch and call instruction (see Table 68).

Words Cycles

1 The CALAD instruction is not repeatable.

Cycles for a Single Instruction ROM 2 DARAM 2 SARAM 2 External Memory 2+p

Example

CALAD MAR *+,AR1 LDP #5

Before Instruction ARP AR0 DP PC ACC TOS 0 8 0 25h 83h 100h ARP AR0 DP PC ACC TOS After Instruction 1 9 5 83h 83h 28h

After the current AR, ARP, and DP are modified as specified, the address of the instruction following the LDP instruction is pushed onto the stack, and program execution continues from location 83h.
6-84

Syntax Operands

CALL pma [,{ind} [,ARn ] ] 0 pma 65535 0 n 7 ind: {* *+ * *0+ *0 *BR0+ *BR0}
15 0 14 1 13 1 12 1 11 1 10 0 9 8 7 6 1 0 1 16-Bit Constant 5 4 3 2 See Section 5.2 1 0

Opcode

Execution

(PC) + 2 TOS pma PC Modify current AR and ARP as specified None affected. The current program counter (PC) is incremented and pushed onto the top of the stack (TOS). The program memory address (pma) is loaded into the PC. Execution continues at this address. The current auxiliary register (AR) and auxiliary register pointer (ARP) are modified as specified. The pma can be either a symbolic or numeric address. CALL is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

2 The CALL instruction is not repeatable.

Cycles for a Single Instruction ROM 4 DARAM 4 SARAM 4 External Memory 4+4p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example

CALL PRG191,*+,AR0
Before Instruction ARP AR1 PC TOS 1 05h 30h 100h ARP AR1 PC TOS After Instruction 0 06h 0BFh 32h

0BFh is loaded into the PC, and the program continues executing from that location.
6-85

Syntax Operands

CALLD pma [,{ind} [,ARn ] ] 0 pma 65535 0 n 7 ind: {* *+ * *0+ *0 *BR0+ *BR0}
15 0 14 1 13 1 12 1 11 1 10 1 9 8 7 6 1 0 1 16-Bit Constant 5 4 3 2 See Section 5.2 1 0

Opcode

Execution

(PC) + 4 TOS pma PC Modify current AR and ARP as specified None affected. The current program counter (PC) is incremented by 4 and pushed onto the top of the stack (TOS). Then, the one 2-word instruction or two 1-word instructions following the CALLD instruction are fetched from program memory and executed before the call is executed. Then, the program memory address (pma) is loaded into the PC. Execution continues at this address. The current auxiliary register (AR) and auxiliary register pointer (ARP) are modified as specified. The pma can be either a symbolic or numeric address. CALLD is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

2 The CALLD instruction is not repeatable.

Cycles for a Single Instruction ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

6-86

Example

CALLD PRG191 MAR *+,AR1 LDP #5

Before Instruction ARP AR0 DP PC TOS 0 09h 1 30h 100h ARP AR0 DP PC TOS After Instruction 1 0Ah 5 0BFh 34h

After the current AR, ARP, and DP are modified as specified, the address of the instruction following the LDP instruction is pushed onto the stack, and program execution continues from location 0BFh.

6-87

Syntax Operands

CC pma cond [,cond1 ] [,...] 0 pma 65535 Conditions: ACC = 0 ACC 0 ACC < 0 ACC 0 ACC > 0 ACC 0 C=0 C=1 OV = 0 OV = 1 TC = 0 TC = 1 BIO low Unconditionally
12 0 11 1 10 0

EQ NEQ LT LEQ GT GEQ NC C NOV OV NTC TC BIO UNC

4 3 2 1 ZLVC 0

Opcode

15 1

14 1

13 1

9 8 7 6 5 TP ZLVC 16-Bit Constant

See Table 61 on page 6-2.

Execution

If (condition(s)): (PC) + 2 TOS pma PC Else: (PC) + 2 PC None affected. If the specified conditions are met, the current program counter (PC) is incremented and pushed onto the top of the stack (TOS). The program memory address (pma) is loaded into the PC. Execution continues at this address. The pma can be either a symbolic or numeric address. Not all combinations of the conditions are meaningful. In addition, the NTC, TC, and BIO conditions are mutually exclusive. If the specified conditions are not met, control is passed to the next instruction. The CC instruction functions in the same manner as the CALL instruction (page 6-85) if all conditions are true. CC is a branch and call instruction (see Table 68).

Status Bits Description

Words
6-88

Cycles

The CC instruction is not repeatable.

Cycles for a Single Instruction Condition True False ROM 4 2 DARAM 4 2 SARAM 4 2 External Memory 4+4p 2+2p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example

CC PGM191,LEQ,C

If the accumulator (ACC) contents are less than or equal to 0 and the C bit is set, 0BFh is loaded into the program counter (PC), and the program continues executing from that location. If the conditions are not met, execution continues at the instruction following the CC instruction.

6-89

Syntax Operands

CCD pma cond [,cond1 ] [,...] 0 pma 65535 Conditions: ACC = 0 ACC 0 ACC < 0 ACC 0 ACC > 0 ACC 0 C=0 C=1 OV = 0 OV = 1 TC = 0 TC = 1 BIO low Unconditionally
12 1 11 1 10 0

EQ NEQ LT LEQ GT GEQ NC C NOV OV NTC TC BIO UNC

4 3 2 1 ZLVC 0

Opcode

15 1

14 1

13 1

9 8 7 6 5 TP ZLVC 16-Bit Constant

See Table 61 on page 6-2.

Execution

If (condition(s)): (PC) + 4 TOS pma PC Else: (PC) + 2 PC None affected. If the specified conditions are met, the current program counter (PC) is incremented by 4 and pushed onto the top of the stack (TOS). Then, the one 2-word instruction or two 1-word instructions following the CCD instruction are fetched from program memory and executed before the call is executed. Then, the program memory address (pma) is loaded into the PC. Execution continues at this address. The pma can be either a symbolic or numeric address. Not all combinations of the conditions are meaningful. In addition, the NTC, TC, and BIO conditions are mutually exclusive. If the specified conditions are not met, control is passed to the next instruction. The CCD functions in the same manner as the CALLD instruction (page 6-86) if all conditions are true. CCD is a branch and call instruction (see Table 68).

Status Bits Description

6-90

Words Cycles

2 The CCD instruction is not repeatable.

Cycles for a Single Instruction ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

Example

CCD PGM191,LEQ,C MAR *+,AR1 LDP #5

The current AR, ARP, and DP are modified as specified. If the accumulator (ACC) contents are less than or equal to 0 and the C bit is set, the address of the instruction following the LDP instruction is pushed onto the stack and program execution continues from location 0BFh. If the conditions are not met, execution continues at the instruction following the LDP instruction.

6-91

Syntax Operands Opcode

CLRC control bit

control bit: {C, CNF, HM, INTM, OVM, SXM, TC, XF}
CLRC OVM (Clear overflow mode)
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 0 2 0 1 1 0 0

CLRC SXM (Clear sign extension mode)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 0 2 1 1 1 0 0

CLRC HM (Clear hold mode)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 1 2 0 1 0 0 0

CLRC TC (Clear test/control)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 1 2 0 1 1 0 0

CLRC C (Clear carry)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 1 2 1 1 1 0 0

CLRC CNF (Clear configuration control)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 0 2 1 1 0 0 0

CLRC INTM (Clear interrupt mode)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 0 2 0 1 0 0 0

CLRC XF (Clear external flag pin)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 1 2 1 1 0 0 0

Execution

(PC) + 1 PC 0 control bit Affects selected control bit. The specified control bit is cleared. The LST instruction can also be used to load ST0 and ST1. See Section 4.4, Status and Control Registers, for more information on each control bit. CLRC is a control instruction (see Table 610).

Status Bits Description

Words
6-92

Cycles
ROM 1

Cycles for a Single Instruction DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

CLRC TC ;TC is bit 11 of ST1

Before Instruction ST1 x9xxh ST1 After Instruction x1xxh

6-93

Syntax Operands Opcode

CMPL None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1

Execution

(PC) + 1 PC (ACC) ACC

Status Bits Description

Does not affect: C

The contents of the accumulator (ACC) are replaced with its logical inversion (1s complement). CMPL is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

CMPL
Before Instruction ACC X C F798 2513h ACC X C After Instruction 0867 DAECh

6-94

Syntax Operands Opcode

CMPR CM 0 CM 3
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 0 6 1 5 0 4 0 3 0 2 1 1 0 CM

See Table 61 on page 6-2.

Execution

(PC) + 1 PC Compare (current AR) to (ARCR) If condition true: 1 TC If condition false: 0 TC

Status Bits

Affected by: NDX

Not affected by: SXM

Affects: TC

Does not affect: SXM

Description

The contents of the current auxiliary register (AR) are compared with the contents of the auxiliary register compare register (ARCR), as defined by the value of CM: If CM = 00, test for (current AR) = (ARCR) If CM = 01, test for (current AR) < (ARCR) If CM = 10, test for (current AR) > (ARCR) If CM = 11, test for (current AR) (ARCR) If the condition is true, the TC bit is set. If the condition is false, the TC bit is cleared. The ARs are treated as unsigned integers in the comparisons. You can maintain software compatibility with the C2x by clearing the NDX bit. This causes any C2x instruction that loads auxiliary register 0 (AR0) to load the ARCR and index register (INDX) also, maintaining C5x object-code compatibility with the C2x. CMPR is an auxiliary registers and data memory page pointer instruction (see Table 65).

Words

6-95

Cycles
ROM 1

Cycles for a Single Instruction DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

CMPR 2
Before Instruction ARP ARCR AR4 TC 4 FFFFh 7FFFh 1 ARP ARCR AR4 TC After Instruction 4 FFFFh 7FFFh 0

6-96

Syntax

Direct: Indirect:

CPL [,#lk ] dma CPL [,#lk ] {ind} [,ARn ]

Operands

0 dma 127 lk: 16-bit constant 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing with long immediate not specified
15 0 14 1 13 0 12 1 11 1 10 0 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing with long immediate not specified

15 0 14 1 13 0 12 1 11 1 10 0 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Direct addressing with long immediate specified

15 0 14 1 13 0 12 1 11 1 10 1 9 8 7 6 1 1 0 16-Bit Constant 5 4 3 dma 2 1 0

Indirect addressing with long immediate specified

15 0 14 1 13 0 12 1 11 1 10 1 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

16-Bit Constant

Execution

Long immediate not specified: (PC) + 1 PC Compare (DBMR) to (dma) If (DBMR) = (dma): 1 TC Else: 0 TC Long immediate specified: (PC) + 2 PC Compare lk to (dma) If lk = (dma): 1 TC Else: 0 TC

Status Bits

Not affected by: SXM

Affects: TC
6-97

Description

If a long immediate constant is specified, the constant is compared with the contents of the data memory address (dma). If a constant is not specified, the contents of the dma are compared with the contents of the dynamic bit manipulation register (DBMR). If the two quantities involved in the comparison are equal, the TC bit is set. If the condition is false, the TC bit is cleared. CPL is a parallel logic unit (PLU) instruction (see Table 66).

Words

1 2

(Long immediate not specified) (Long immediate specified)

Cycles for a Single Instruction

Cycles
Operand DARAM SARAM External

ROM 1 1 1+d

DARAM 1 1 1+d

SARAM 1 1, 2 1+d

External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate specified) Operand DARAM SARAM External ROM 2 2 2+d DARAM 2 2 2+d SARAM 2 2, 3 2+d External Memory 2+2p 2+2p 3+d+2p

If the operand and the code are in the same SARAM block

6-98

Cycles for a Repeat (RPT) Execution (long immediate specified) Operand DARAM SARAM External ROM n+1 n+1 n+1 DARAM n+1 n+1 n+1 SARAM n+1 n+1, n+2 n+1 External Memory n+1+2p n+1+2p n+2+2p

If the operand and the code are in the same SARAM block

Example 1

CPL #060h,60h
Before Instruction Data Memory 60h TC 066h 1 Data Memory 60h TC After Instruction 066h 0

Example 2

CPL 60h
Before Instruction Data Memory 60h DBMR TC 066h 066h 0 Data Memory 60h DBMR TC After Instruction 066h 066h 1

Example 3

CPL #0F1h,*,AR6
Before Instruction ARP AR7 Data Memory 300h TC 7 300h 0F1h 1 ARP AR7 Data Memory 300h TC After Instruction 6 300h 0F1h 1

Example 4

CPL *,AR7
Before Instruction ARP AR6 Data Memory 300h DBMR TC 6 300h 0F1h 0F0h 0 ARP AR6 Data Memory 300h DBMR TC After Instruction 7 300h 0F1h 0F0h 0

6-99

Syntax Operands Opcode

CRGT None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 1 2 0 1 1 0 1

Execution

(PC) + 1 PC Compare (ACC) to (ACCB) If (ACC) > (ACCB): (ACC) ACCB 1 C If (ACC) < (ACCB): (ACCB) ACC 0 C If (ACC) = (ACCB): 1 C

Status Bits Description

Affects: C
The contents of the accumulator (ACC) are compared to the contents of the accumulator buffer (ACCB). The larger value (signed) is loaded into both registers. If the contents of the ACC are greater than or equal to the contents of the ACCB, the C bit is set; otherwise, the C bit is cleared. CRGT is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

6-100

Example 1

CRGT
Before Instruction ACCB ACC C 4h 5h 0 ACCB ACC C After Instruction 5h 5h 1

Example 2

CRGT
Before Instruction ACCB ACC C 5h 5h 0 ACCB ACC C After Instruction 5h 5h 1

6-101

Syntax Operands Opcode

CRLT None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 0 0 0

Execution

(PC) + 1 PC Compare (ACC) to (ACCB) If (ACC) < (ACCB): (ACC) ACCB 1 C If (ACC) > (ACCB): (ACCB) ACC 0 C If (ACC) = (ACCB): 0 C

Status Bits Description

Affects: C
The contents of the accumulator (ACC) are compared to the contents of the accumulator buffer (ACCB). The smaller (signed) value is loaded into both registers. If the contents of the ACC are less than the contents of the ACCB, the C bit is set; otherwise, the C bit is cleared. CRLT is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

6-102

Example 1

CRLT
Before Instruction ACCB ACC C 5h 4h 0 ACCB ACC C After Instruction 4h 4h 1

Example 2

CRLT
Before Instruction ACCB ACC C 4h 4h 1 ACCB ACC C After Instruction 4h 4h 0

6-103

Syntax

Direct: Indirect:

DMOV dma DMOV {ind} [,ARn ]

Operands

0 dma 127 0 n 7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 1 11 0 10 1 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 1 11 0 10 1 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (dma) dma + 1

Status Bits Description

Affected by: CNF and OVLY

The contents of the data memory address (dma) are copied to the next higher dma. The DMOV instruction works only within on-chip data RAM blocks and within any configurable RAM block that is configured as data memory. In addition, the DMOV instruction is continuous across on-chip dual-access RAM block B0 and B1 boundaries. The DMOV instruction cannot be used on external data memory or memory-mapped registers. If the DMOV instruction is used on external memory or memory-mapped registers, the DMOV instruction will read the specified memory location but will perform no operations. When data is copied from the addressed location to the next higher location, the contents of the addressed location remain unaffected. You can use the DMOV instruction in implementing the z 1 delay encountered in digital signal processing. The DMOV function is included in the LTD, MACD, and MADD instructions (see their individual descriptions on page 6-142, 6-153, and 6-158, respectively, for more information). DMOV is an I/O and data memory operation instruction (see Table 69).

Words

6-104

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 2+2d DARAM 1 1 2+2d SARAM 1 1, 3 2+2d External Memory 1+p 1+p 5+2d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n 2n2 4n2+2nd DARAM n 2n2 4n2+2nd SARAM n 2n2, 2n+1 4n2+2nd External Memory n+p 2n2+p 4n+1+2nd+p

If the operand and the code are in the same SARAM block

Example 1

DMOV DAT8 ;(DP = 6)

Before Instruction Data Memory 308h Data Memory 309h 43h 2h Data Memory 308h Data Memory 309h After Instruction 43h 43h

Example 2

DMOV *,AR1
Before Instruction ARP AR1 Data Memory 30Ah Data Memory 30Bh 0 30Ah 40h 41h ARP AR1 Data Memory 30Ah Data Memory 30Bh After Instruction 1 30Ah 40h 40h

6-105

Syntax Operands Opcode

EXAR None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 0 0 1

Execution

(PC) + 1 PC (ACCB) (ACC) None affected. The contents of the accumulator (ACC) are exchanged (switched) with the contents of the accumulator buffer (ACCB). 1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Status Bits Description

Words Cycles

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

EXAR
Before Instruction ACC ACCB 043h 02h ACC ACCB After Instruction 02h 043h

6-106

Syntax Operands Opcode

IDLE None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 0 3 0 2 0 1 1 0 0

Execution Status Bits Description

(PC) + 1 PC

Affected by: INTM

The program being executed is forced to wait until an unmasked (external or internal) interrupt or reset occurs. The program counter (PC) is incremented only once, and the device remains in idle mode until interrupted. The idle mode is exited by an unmasked interrupt, even if the INTM bit is set. If the INTM bit is set, the program continues executing at the instruction following the IDLE. If the INTM bit is cleared, the program branches to the corresponding interrupt service routine (ISR). When an interrupt causes IDLE to be exited with the interrupts disabled (INTM = 1), no interrupt flag register (IFR) bits are cleared. The IFR bits are cleared only if interrupts are enabled and IDLE is exited by entering the ISR. Executing the IDLE instruction causes the C5x to enter the power-down mode. During the idle mode, the timer and serial port peripherals are still active. Therefore, timer and peripheral interrupts, as well as reset or external interrupts, will remove the processor from the idle mode. IDLE is a control instruction (see Table 610).

Words Cycles

1 The IDLE instruction is not repeatable.

Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Example

IDLE ;The processor idles until a reset or unmasked ;interrupt occurs.

6-107

Syntax Operands Opcode

IDLE2 None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 0 3 0 2 0 1 1 0 1

Execution Status Bits Description

(PC) + 1 PC

Affected by: INTM

The program being executed is forced to wait until an unmasked (external or internal) interrupt or reset occurs. The functional clock input is removed from the internal device to make an extremely low-power mode possible. The program counter (PC) is incremented only once, and the device remains in idle mode until interrupted. The idle2 mode is exited by an unmasked interrupt, even if the INTM bit is set. If the INTM bit is set, the program continues executing at the instruction following the IDLE2. If the INTM bit is cleared, then the program branches to the corresponding interrupt service routine (ISR). When an interrupt causes IDLE2 to be exited with the interrupts disabled (INTM = 1), no interrupt flag register (IFR) bits are cleared. The IFR bits are cleared only if interrupts are enabled and IDLE2 is exited by entering the ISR. Executing the IDLE2 instruction causes the C5x to enter the power-down mode. During the idle2 mode, the timer and serial port peripherals are not active. The idle2 mode is exited by a low logic level on an external interrupt (INT1INT4), RS, or NMI with a duration of at least five machine cycles because interrupts are not latched as in normal device operation. IDLE2 is a control instruction (see Table 610).

Words Cycles

1 The IDLE2 instruction is not repeatable.

Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Example

IDLE2 ;The processor idles until a reset or unmasked ;external interrupt occurs.

6-108

Syntax

Direct: Indirect:

IN dma, PA IN {ind} ,PA [,ARn ]

Operands

0 dma 127 0 n 7 0 port address PA 65535 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 1 14 0 13 1 12 0 11 1 10 1 9 8 7 6 1 1 0 16-Bit Constant 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 1 14 0 13 1 12 0 11 1 10 1 9 8 7 6 1 1 1 16-Bit Constant 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 2 PC While (repeat counter) 0 Port address address bus A15A0 Data bus D15D0 dma Port address dma Port address + 1 Port address (repeat counter 1) repeat counter None affected. A 16-bit value from an external I/O port is read into the data memory address (dma). The IS line goes low to indicate an I/O access, and the STRB, RD, and READY timings are the same as for an external data memory read. While port addresses 50h5Fh are memory-mapped (see subsection 9.1.1, MemoryMapped Peripheral Registers and I/O Ports); the other port addresses are not. You can use the RPT instruction with the IN instruction to read consecutive words in I/O space to data space. The number of words to be moved is one greater than the number contained in the repeat counter register (RPTC) at the beginning of the instruction. When used with the RPT instruction, the IN instruction becomes a single-cycle instruction, once the RPT pipeline is started, and the port address is incremented after each access. IN is an I/O and data memory operation instruction (see Table 69).

Status Bits Description

Words

2
6-109

Cycles
Cycles for a Single Instruction Operand Destination: DARAM Destination: SARAM Destination: External ROM 2+iosrc 2+iosrc 3+ddst +iosrc DARAM 2+iosrc 2+iosrc 3+ddst +iosrc SARAM 2+iosrc 2+iosrc , 3+iosrc 3+ddst +iosrc External Memory 3+iosrc +2pcode 3+iosrc +2pcode 6+ddst +iosrc +2pcode

If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand Destination: DARAM Destination: SARAM Destination: External ROM 2n+niosrc 2n+niosrc 4n1+nddst +niosrc DARAM 2n+niosrc 2n+niosrc 4n1+nddst +niosrc SARAM 2n+niosrc 2n+niosrc , 2n+2+niosrc 4n1+nddst +niosrc External Memory 2n+1+niosrc +2pcode 2n+1+niosrc +2pcode 4n+2+nddst +niosrc +2pcode

If the destination operand and the code are in the same SARAM block

Example 1

IN DAT7,PA5 ;Read in word from peripheral on port ;address 5(i.e., I/O port 55h). Store in ;data memory location 307h (DP=6). IN *,1024 ;Read in word from peripheral on I/O ;port 400h. Store in data memory location ;specified by current auxiliary register.

Example 2

6-110

Syntax Operands Opcode

INTR K 0 K 31
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 1 4 3 2 1 INTR# 0

See Table 61 on page 6-2.

Execution Status Bits Description

(PC) + 1 stack corresponding interrupt vector PC

Not affected by: INTM

Affects: INTM

A software interrupt that transfers program control to a program memory address (pma) interrupt vector specified by K. The current program counter (PC) is incremented and pushed onto the stack. The pma is loaded into the PC. The K value corresponds to a pma specified by the following table:
K 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Interrupt RS INT1 INT2 INT3 TINT RINT XINT TRNT TXNT INT4 Reserved Reserved Reserved Reserved Reserved Reserved Hex Location 0 2 4 6 8 A C E 10 12 14 16 18 1A 1C 1E K 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Interrupt Reserved TRAP NMI Reserved User-defined User-defined User-defined User-defined User-defined User-defined User-defined User-defined User-defined User-defined User-defined User-defined Hex Location 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E

The INTR instruction allows any interrupt service routine (ISR) to be executed from your software. The INTM bit has no affect on the INTR instruction. An INTR interrupt for the INT1INT4 interrupts looks exactly like an external interrupt except the interrupt will not clear the appropriate bit in the IFR. See Section 4.8, Interrupts, on page 4-36 for a complete description of interrupt operation. INTR is a branch and call instruction (see Table 68).
6-111

The reserved interrupt vectors can be used for the C50, C51, and C53. However, software compatibility with other fifth generation devices is not guaranteed.

Words Cycles

1 The INTR instruction is not repeatable.

Cycles for a Single Instruction ROM 4 DARAM 4 SARAM 4 External Memory 4+3p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example

INTR 3 ;Control is passed to program memory location 6h ;PC + 1 is pushed onto the stack.

6-112

Syntax Operands Opcode

LACB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 1 0 1

Execution

(PC) + 1 PC (ACCB) ACC None affected. The contents of the accumulator buffer (ACCB) are loaded into the accumulator (ACC). LACB is an accumulator memory reference instruction (see Table 64).

Status Bits Description

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

LACB
Before Instruction ACC ACCB 01376h 5555 AAAAh ACC ACCB After Instruction 5555 AAAAh 5555 AAAAh

6-113

Syntax

Direct: Indirect: Long immediate:

LACC dma [,shift ] LACC {ind} [,shift [,ARn ] ] LACC #lk [,shift]

Operands

0 dma 127 0n7 0 shift 16 (defaults to 0) 32768 lk 32767 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing with shift
15 0 14 0 13 0 12 1 11 10 9 SHFT 8 7 0 6 5 4 3 2 dma 1 0

Opcode

See Table 61 on page 6-2.

Indirect addressing with shift

15 0 14 0 13 0 12 1 11 10 9 SHFT 8 7 1 6 5 4 3 2 See Section 5.2 1 0

See Table 61 on page 6-2.

Direct addressing with shift of 16

15 0 14 1 13 1 12 0 11 1 10 0 9 1 8 0 7 0 6 5 4 3 2 dma 1 0

Indirect addressing with shift of 16

15 0 14 1 13 1 12 0 11 1 10 0 9 1 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Long immediate addressing with shift

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 7 6 5 1 1 0 0 16-Bit Constant 4 0 3 2 1 SHFT 0

See Table 61 on page 6-2.

Execution

Direct or indirect addressing: (PC) + 1 PC (dma) 2shift1 ACC Long immediate addressing: (PC) + 2 PC lk 2shift2 ACC

Status Bits
6-114

Affected by: SXM

Description

The contents of the data memory address (dma) or a 16-bit constant are shifted left, as defined by the shift code, and loaded into the accumulator (ACC). During shifting, the low-order bits of the ACC are zero-filled. If the SXM bit is cleared, the high-order bits of the ACC are zero-filled; if the SXM bit is set, the high-order bits of the ACC are sign-extended. LACC is an accumulator memory reference instruction (see Table 64).

Words

1 2

(Direct or indirect addressing) (Long immediate addressing)

Cycles

For the long immediate addressing modes, the LACC instruction is not repeatable.
Cycles for a Single Instruction (direct or indirect addressing) Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing) Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate addressing) ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

6-115

Example 1

LACC DAT6,4 ;(DP = 8, SXM = 0)

Before Instruction Data Memory 406h ACC X C 01h 1234 5678h Data Memory 406h ACC X C After Instruction 01h 10h

Example 2

LACC *,4 ;(SXM = 0)

Before Instruction ARP AR2 Data Memory 300h ACC X C 2 0300h 0FFh 1234 5678h ARP AR2 Data Memory 300h ACC X C After Instruction 2 0300h 0FFh 0FF0h

Example 3

LACC #F000h,1 ;(SXM = 1)

Before Instruction ACC X C 1234 5678h ACC X C After Instruction FFFF E000h

6-116

Syntax

Direct: Indirect: Short immediate:

LACL dma LACL {ind} [,ARn ] LACL #k

Operands

0 dma 127 0n7 0 k 255 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 0 14 1 13 1 12 0 11 1 10 0 9 0 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 1 10 0 9 0 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Short immediate addressing

15 1 14 0 13 1 12 1 11 1 10 0 9 0 8 1 7 6 5 4 3 2 8-Bit Constant 1 0

Execution

(PC) + 1 PC Direct or indirect addressing: 0 ACC(3116) (dma) ACC(150) Short immediate addressing: 0 ACC(318) k ACC(70)

Status Bits Description

Not affected by: SXM

The contents of the data memory address (dma) or a zero-extended 8-bit constant are loaded into the accumulator low byte (ACCL). The accumulator high byte (ACCH) is zero-filled. The data is treated as an unsigned 16-bit number rather than a 2s-complement number. The operand is not sign extended with the LACL instruction, regardless of the state of the SXM bit. LACL is an accumulator memory reference instruction (see Table 64).

Words

6-117

Cycles

For the short immediate addressing modes, the LACL instruction is not repeatable.
Cycles for a Single Instruction (direct or indirect addressing) Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing) Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing) ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Example 1

LACL DAT1 ;(DP = 6)

Before Instruction Data Memory 301h ACC X C 0h 7FFF FFFFh Data Memory 301h ACC X C After Instruction 0h 0h

Example 2

LACL *,AR4
Before Instruction ARP AR0 Data Memory 401h ACC X C 0 401h 00FFh 7FFF FFFFh ARP AR0 Data Memory 401h ACC X C After Instruction 4 400h 00FFh 0FFh

6-118

Example 3

LACL #10h
Before Instruction ACC X C ACC 7FFF FFFFh X C After Instruction 010h

6-119

Syntax

Direct: Indirect:

LACT dma LACT {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 0 11 1 10 0 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 1 10 0 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (dma) 2TREG1(30) ACC If SXM = 0: (dma) is not sign extended If SXM = 1: (dma) is sign extended

Status Bits Description

Affected by: SXM

The contents of the data memory address (dma) are shifted left from 0 to 15 bits, as defined by the 4 LSBs of TREG1, and loaded into the accumulator (ACC). You can use the contents of TREG1 as a shift code to provide a dynamic shift mechanism. During shifting, if the SXM bit is cleared, the high-order bits are zero-filled; if the SXM bit is set, the high-order bits are sign-extended. You may use the LACT instruction to denormalize a floating-point number, if the actual exponent is placed in the 4 LSBs of the TREG1 and the mantissa is referenced by the dma. You can use this method of denormalization only when the magnitude of the exponent is 4 bits or less. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs. Subsequent calls to the LACT instruction will shift the value by the TREG1 value (which is the same as TREG0), maintaining C5x object-code compatibility with the C2x. LACT is an accumulator memory reference instruction (see Table 64).

Words
6-120

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

LACT DAT1 ;(DP = 6, SXM = 0)

Before Instruction Data Memory 301h ACC TREG1 X C 1376h 98F7 EC83h 14h Data Memory 301h ACC TREG1 X C After Instruction 1376h 13760h 14h

Example 2

LACT *,AR3 ;(SXM = 1)

Before Instruction ARP AR1 Data Memory 310h ACC TREG1 X C 1 310h FF00h 98F7 EC83h 11h ARP AR1 Data Memory 310h ACC TREG1 X C After Instruction 3 309h FF00h FFFF FE00h 11h

6-121

Syntax Operands

Direct: Indirect:

LAMM dma LAMM {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 0 13 0 12 0 11 1 10 0 9 0 8 0 7 0 6 5 4 3 2 1 Data Memory Address 0

Opcode

Indirect addressing
15 0 14 0 13 0 12 0 11 1 10 0 9 0 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (dma) ACC(150) 0 ACC(3116)

Status Bits Description

Not affected by: SXM

The contents of the addressed memory-mapped register are loaded into the accumulator low byte (ACCL). The accumulator high byte (ACCH) is zerofilled. The 9 MSBs of the data memory address are cleared, regardless of the current value of data memory page pointer (DP) bits or the upper 9 bits of the current AR. The LAMM instruction allows any memory location on data memory page 0 to be loaded into the ACC without modifying the DP bits. LAMM is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction Operand MMR MMPORT ROM 1 1+iosrc DARAM 1 1+iosrc SARAM 1 1+iodsrc External Memory 1+p 1+2+p+iodsrc

Add one more cycle for peripheral memory-mapped access

Cycles for a Repeat (RPT) Execution Operand MMR MMPORT ROM n n+miosrc DARAM n n+miosrc SARAM n n+miosrc External Memory n+p n+p+miosrc

Add n more cycles for peripheral memory-mapped access

6-122

Example 1

LAMM BMAR ;(DP = 6)

Before Instruction ACC BMAR Data Memory 31Fh 2222 1376h 5555h 1000h ACC BMAR Data Memory 31Fh After Instruction 5555h 5555h 1000h

Example 2

LAMM *
Before Instruction ARP AR1 ACC PRD Data Memory 325h 1 325h 2222 1376h 0Fh 1000h ARP AR1 ACC PRD Data Memory 325h After Instruction 1 325h 0Fh 0Fh 1000h

The value in data memory location 325h is not loaded into the ACC, the value at data memory location 25h (address of the PRD) is loaded into the ACC.

6-123

Syntax

Direct: Indirect: Short immediate: Long immediate:

LAR ARx, dma LAR ARx, {ind} [,ARn ] LAR ARx, #k LAR ARx, #lk

Operands

0x7 0 dma 127 0n7 0 k 255 0 lk 65535 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 0 14 0 13 0 12 0 11 0 10 9 8 ARX 7 0 6 5 4 3 dma 2 1 0

Opcode

See Table 61 on page 6-2.

Indirect addressing
15 0 14 0 13 0 12 0 11 0 10 9 8 ARX 7 1 6 5 4 3 2 See Section 5.2 1 0

See Table 61 on page 6-2.

Short immediate addressing

15 1 14 0 13 1 12 1 11 0 10 9 8 ARX 7 6 5 4 3 2 8-Bit Constant 1 0

See Table 61 on page 6-2.

Long immediate addressing

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 0 6 0 5 0 4 0 3 1 2 1 0 ARX

16-Bit Constant
See Table 61 on page 6-2.

Execution

Direct or indirect addressing: (PC) + 1 PC (dma) AR Short immediate addressing: (PC) + 1 PC k AR Long immediate addressing: (PC) + 2 PC lk AR

Status Bits

Affected by: NDX

Not affected by: SXM

6-124

Description

The contents of the data memory address (dma), an 8-bit constant, or a 16-bit constant are loaded into the auxiliary register (AR). The constant is acted upon like an unsigned integer, regardless of the value of the SXM bit. You can maintain software compatibility with the C2x by clearing the NDX bit. This causes any C2x instruction that loads auxiliary register 0 (AR0) to load the auxiliary register compare register (ARCR) and index register (INDX) also, maintaining C5x object-code compatibility with the C2x. You can use the LAR and SAR (store auxiliary register) instructions to load and store the ARs during subroutine calls and interrupts. If you do not use an AR for indirect addressing, LAR and SAR enable the register to be used as an additional storage register, especially for swapping values between data memory locations without affecting the contents of the accumulator (ACC). LAR is an auxiliary registers and data memory page pointer instruction (see Table 65).

Words

1 2

(Direct, indirect, or short immediate addressing) (Long immediate addressing)

Cycles

For the short and long immediate addressing modes, the LAR instruction is not repeatable.
Cycles for a Single Instruction (direct or indirect addressing) Operand Source: DARAM Source: SARAM Source: External ROM 2 2 2+dsrc DARAM 2 2 2+dsrc SARAM 2 2, 3 2+dsrc External Memory 2+pcode 2+pcode 3+dsrc +pcode

If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing) Operand Source: DARAM Source: SARAM Source: External ROM 2n 2n 2n+ndsrc DARAM 2n 2n 2n+ndsrc SARAM 2n 2n, 2n+1 2n+ndsrc External Memory 2n+pcode 2n+pcode 2n+1+ndsrc +pcode

If the source operand and the code are in the same SARAM block

6-125

Cycles for a Single Instruction (short immediate addressing) Operand ROM 2 DARAM 2 SARAM 2 External Memory 2+pcode

If the source operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate addressing) ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

Example 1

LAR AR0,DAT16 ;(DP = 6)

Before Instruction Data Memory 310h AR0 18h 6h Data Memory 310h AR0 After Instruction 18h 18h

Example 2

LAR AR4,*
Before Instruction ARP Data Memory 300h AR4 4 32h 300h ARP Data Memory 300h AR4 After Instruction 4 32h 32h

Note: LAR in the indirect addressing mode ignores any AR modifications if the AR specified by the instruction is the same as that pointed to by the ARP. Therefore, in Example 2, AR4 is not decremented after the LAR instruction. Example 3
LAR AR4,#01h
Before Instruction AR4 FF09h AR4 After Instruction 01h

Example 4

LAR AR4,#3FFFh
Before Instruction AR4 0h AR4 After Instruction 3FFFh

6-126

Syntax

Direct: Indirect: Short immediate:

LDP dma LDP {ind} [,ARn ] LDP #k

Operands

0 dma 127 0n7 0 k 511 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 0 14 0 13 0 12 0 11 1 10 1 9 0 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 0 13 0 12 0 11 1 10 1 9 0 8 1 7 1 6 5 4 3 See Section 5.2 2 1 0

Short immediate addressing

15 1 14 0 13 1 12 1 11 1 10 1 9 0 8 7 6 5 4 3 9-Bit Constant 2 1 0

Execution

(PC) + 1 PC Direct or indirect addressing: Nine LSBs of (dma) DP bits Short immediate addressing: k DP bits

Status Bits Description

Affects: DP
The 9 LSBs of the data memory address (dma) contents or a 9-bit constant are loaded into the data memory page pointer (DP) bits. The DP bits and the 7-bit dma are concatenated to form the 16-bit dma. The DP bits can also be loaded by the LST instruction. LDP is an auxiliary registers and data memory page pointer instruction (see Table 65).

Words

6-127

Cycles

For the short immediate addressing modes, the LDP instruction is not repeatable.
Cycles for a Single Instruction (direct or indirect addressing) Operand Source: DARAM Source: SARAM Source: External ROM 2 2 2+dsrc DARAM 2 2 2+dsrc SARAM 2 2, 3 2+dsrc External Memory 2+pcode 2+pcode 3+dsrc +pcode

If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing) Operand Source: DARAM Source: SARAM Source: External ROM 2n 2n 2n+ndsrc DARAM 2n 2n 2n+ndsrc SARAM 2n 2n, 2n+1 2n+ndsrc External Memory 2n+pcode 2n+pcode 2n+1+ndsrc +pcode

If the source operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing) Operand ROM 2 DARAM 2 SARAM 2 External Memory 2+pcode

If the source operand and the code are in the same SARAM block

Example 1

LDP DAT127 ;(DP = 511)

Before Instruction Data Memory FFFFh DP FEDCh 1FFh Data Memory FFFFh DP After Instruction FEDCh 0DCh

Example 2

LDP #0h
Before Instruction DP 1FFh DP After Instruction 0h

6-128

Example 3

LDP *,AR5
Before Instruction ARP AR4 Data Memory 300h DP 4 300h 06h 1FFh ARP AR4 Data Memory 300h DP After Instruction 5 300h 06h 06h

6-129

Syntax

Direct: Indirect:

LMMR dma, #addr LMMR {ind}, #addr [,ARn ]

Operands

0 dma 127 0n7 0 addr 65535 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 1 14 0 13 0 12 0 11 1 10 0 9 0 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

16-Bit Constant

Indirect addressing
15 1 14 0 13 0 12 0 11 1 10 0 9 0 8 1 7 1 6 5 4 3 2 1 0 See Section 5.2

16-Bit Constant

Execution

PFC MCS (PC) + 2 PC lk PFC While (repeat counter 0): (src, addressed by PFC) (dst, specified by lower 7 bits of dma) (PFC) + 1 PFC (repeat counter) 1 repeat counter MCS PFC None affected. The memory-mapped register pointed at by the lower 7 bits of the data memory address (dma) is loaded with the contents of the data memory location addressed by the 16-bit source address, #addr. The 9 MSBs of the dma are cleared, regardless of the current value of the data memory page pointer (DP) bits or the upper 9 bits of the current AR. The LMMR instruction allows any memory location on data memory page 0 to be loaded from anywhere in data memory without modification of the DP bits. When you use the LMMR instruction with the RPT instruction, the source address, #addr, is incremented after every memory-mapped load operation. LMMR is an I/O and data memory operation instruction (see Table 69).

Status Bits Description

Words
6-130

Cycles
Cycles for a Single Instruction Operand Source: DARAM Destination: MMR Source: SARAM Destination: MMR Source: External Destination: MMR Source: DARAM Destination: MMPORT Source: SARAM Destination: MMPORT Source: External Destination: MMPORT ROM 2 2 2+psrc 3+iodst 3+iodst 3+psrc +iodst DARAM 2 2 2+psrc 3+iodst 3+iodst 3+psrc +iodst SARAM 2 2, 3 2+psrc 3+iodst 3+iodst , 4 3+psrc +iodst External Memory 2+2pcode 2+2pcode 3+psrc +2pcode 5+2pcode +iodst 5+2pcode +iodst 6+psrc +2pcode +iodst

If the source operand and the code are in the same SARAM block Add one more cycle for peripheral memory-mapped register access

Cycles for a Repeat (RPT) Execution Operand Source: DARAM Destination: MMR Source: SARAM Destination: MMR Source: External Destination: MMR Source: DARAM Destination: MMPORT Source: SARAM Destination: MMPORT Source: External Destination: MMPORT ROM 2n 2n 2n+ndsrc 3n+niodst 3n+niodst 4n1+ndsrc +niodst DARAM 2n 2n 2n+ndsrc 3n+niodst 3n+niodst 4n1+ndsrc +niodst SARAM 2n 2n, 2n+1 2n+ndsrc 3n+niodst 3n+niodst , 3n+1+niodst 4n1+ndsrc +niodst External Memory 2n+2pcode 2n+2pcode 2n+1+ndsrc +2pcode 3n+3+niodst +2pcode 3n+3+niodst +2pcode 4n+2+ndsrc + niodst +2pcode

If the source operand and the code are in the same SARAM block Add n more cycles for peripheral memory-mapped register access

6-131

Example 1

LMMR DBMR,#300h
Before Instruction Data Memory 300h DBMR 1376h 5555h Data Memory 300h DBMR After Instruction 1376h 1376h

Example 2

LMMR *,#300h,AR4 ;CBCR = 1Eh

Before Instruction ARP AR0 Data Memory 300h CBCR 0 31Eh 20h 0h ARO AR0 Data Memory 300h CBCR After Instruction 4h 31Eh 20h 20h

6-132

Syntax Operands

Direct: Indirect:

LPH dma LPH {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 1 11 0 10 1 9 0 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 1 11 0 10 1 9 0 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution Status Bits Description

(PC) + 1 PC (dma) PREG (3116) None affected. The contents of the data memory address (dma) are loaded into the product register (PREG) high byte. The contents of the PREG low byte are unaffected. You can use the LPH instruction to restore the contents of the PREG high byte after interrupts and subroutine calls, if automatic context save is not used. LPH is a TREG0, PREG, and multiply instruction (see Table 67).

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

6-133

Example 1

LPH DAT0 ;(DP = 4)

Before Instruction Data Memory 200h PREG F79Ch 3007 9844h Data Memory 200h PREG After Instruction F79Ch F79C 9844h

Example 2

LPH *,AR6
Before Instruction ARP AR5 Data Memory 200h PREG 5 200h F79Ch 3007 9844h ARP AR5 Data Memory 200h PREG After Instruction 6 200h F79Ch F79C 9844h

6-134

Syntax Operands

Direct: Indirect:

LST #m, dma LST #m, {ind} [,ARn ]

0 dma 127 m = 0 or 1 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing for LST #0
15 0 14 0 13 0 12 0 11 1 10 1 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing for LST #0

15 0 14 0 13 0 12 0 11 1 10 1 9 1 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Direct addressing for LST #1

15 0 14 0 13 0 12 0 11 1 10 1 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Indirect addressing for LST #1

15 0 14 0 13 0 12 0 11 1 10 1 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (dma) STm dma (1315) ARP (regardless of n)

Status Bits

Affects: ARB, ARP, C, CNF, DP, HM, OV, OVM, PM, SXM, TC, and XF

Does not affect: INTM

Description

The contents of the data memory address (dma) are loaded into status register STm. The INTM bit is unaffected by an LST #0 instruction. In addition, the LST #0 instruction does not affect the auxiliary register buffer (ARB), even though a new auxiliary register pointer (ARP) is loaded. If a next ARP value is specified via the indirect addressing mode, the specified value is ignored. Instead, ARP is loaded with the value contained within the addressed data memory word. Note: When ST1 is loaded (LST #1), the value loaded into ARB is also loaded into ARP. You can use the LST instruction to restore the status registers after subroutine calls and interrupts. LST is a control instruction (see Table 610).
6-135

Words Cycles

1
Cycles for a Single Instruction Operand Source: DARAM Source: SARAM Source: External ROM 2 2 2+dsrc DARAM 2 2 2+dsrc SARAM 2 2, 3 2+dsrc External Memory 2+pcode 2+pcode 3+dsrc +pcode

If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand Source: DARAM Source: SARAM Source: External ROM 2n 2n 2n+ndsrc DARAM 2n 2n 2n+ndsrc SARAM 2n 2n, 2n+1 2n+ndsrc External Memory 2n+pcode 2n+pcode 2n+1+ndsrc +pcode

If the source operand and the code are in the same SARAM block

Example 1

MAR *,AR0 LST #0,*,AR1 ;The data memory word addressed by the contents ;of auxiliary register AR0 is loaded into ;status register ST0,except for the INTM bit. ;Note that even though a next ARP value is ;specified, that value is ignored, and the ;old ARP is not loaded into the ARB. LST #0,60h ;(DP = 0)
Before Instruction Data Memory 60h ST0 ST1 2404h 6E00h 0580h Data Memory 60h ST0 ST1 After Instruction 2404h 2604h 0580h

Example 2

6-136

Example 3

LST #0,*,AR1
Before Instruction ARP AR4 Data Memory 3FFh ST0 ST1 4 3FFh EE04h 1E00h F7A0h ARP AR4 Data Memory 3FFh ST0 ST1 After Instruction 7 3FEh EE04h EE04h F7A0h

Example 4

LST #1,00h ;(DP = 6)

Before Instruction Data Memory 300h ST0 ST1 E1BCh 0406h 09A0h Data Memory 300h ST0 ST1 After Instruction E1BCh E406h E1BCh

6-137

Syntax

Direct: Indirect:

LT dma LT {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 1 11 0 10 0 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 1 11 0 10 0 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (dma) TREG0 If TRM = 0: (dma) TREG1 (dma) TREG2

Status Bits Description

Affected by: TRM

The contents of the data memory address (dma) are loaded into TREG0. You can use the LT instruction to load TREG0 in preparation for multiplication. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. LT is a TREG0, PREG, and multiply instruction (see Table 67).

Words

6-138

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

LT DAT24 ;(DP = 8. TRM = 1)

Before Instruction Data Memory 418h TREG0 62h 3h Data Memory 418h TREG0 After Instruction 62h 62h

Example 2

LT *,AR3 ;(TRM = 0)
Before Instruction ARP AR2 Data Memory 418h TREG0 TREG1 TREG2 2 418h 62h 3h 4h 5h ARP AR2 Data Memory 418h TREG0 TREG1 TREG2 After Instruction 3 418h 62h 62h 2h 2h

6-139

Syntax

Direct: Indirect:

LTA dma LTA {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 1 11 0 10 0 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 1 11 0 10 0 9 0 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (dma) TREG0 (ACC) + (shifted PREG) ACC If TRM = 0: (dma) TREG1 (dma) TREG2

Status Bits

Affected by: OVM, PM, and TRM

Affects: C and OV

Description

The contents of the data memory address (dma) are loaded into TREG0. The contents of the product register (PREG) are shifted, as defined by the PM bits, and added to the accumulator (ACC). The result is stored in the ACC. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. LTA is a TREG0, PREG, and multiply instruction (see Table 67).

Words

6-140

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

LTA DAT36 ;(DP = 6, PM = 0, TRM = 1)

Before Instruction Data Memory 324h TREG0 PREG ACC X C 62h 3h 0Fh 5h Data Memory 324h TREG0 PREG ACC 0 C After Instruction 62h 62h 0Fh 14h

Example 2

LTA *,5 ;(TRM = 0)

Before Instruction ARP AR4 Data Memory 324h TREG0 TREG1 TREG2 PREG ACC X C 4 324h 62h 3h 4h 5h 0Fh 5h ARP AR4 Data Memory 324h TREG0 TREG1 TREG2 PREG ACC 0 C After Instruction 5 324h 62h 62h 2h 2h 0Fh 14h

6-141

Syntax Operands

Direct: Indirect:

LTD dma LTD {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 1 11 0 10 0 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 1 11 0 10 0 9 1 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (dma) TREG0 (dma) dma + 1 (ACC) + (shifted PREG) ACC If TRM = 0: (dma) TREG1 (dma) TREG2

Status Bits Description

Affected by: OVM, PM, and TRM

Affects: C and OV

The contents of the data memory address (dma) are loaded into TREG0. The contents of the dma are also copied to the next higher dma. The contents of the product register (PREG) are shifted, as defined by the PM bits, and added to the accumulator (ACC). The result is stored in the ACC. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. See the DMOV instruction, page 6-104, for information on the data move feature. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. The LTD instruction functions in the same manner as the LTA instruction with the addition of data move for on-chip RAM blocks. If you use the LTD instruction with external data memory, its function is identical to that of the LTA instruction (page 6-140). LTD is a TREG0, PREG, and multiply instruction (see Table 67).

6-142

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 2+2d DARAM 1 1 2+2d SARAM 1 1, 3 2+2d External Memory 1+p 1+p 5+2d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n 2n2 4n2+2nd DARAM n 2n2 4n2+2nd SARAM n 2n2, 2n+1 4n2+2nd External Memory n+p 2n2+p 4n+1+2nd+p

If the operand and the code are in the same SARAM block

Example 1

LTD DAT126 ;(DP = 7, PM = 0, TRM = 1)

Before Instruction Data Memory 3FEh Data Memory 3FFh TREG0 PREG ACC X C 62h 0h 3h 0Fh 5h Data Memory 3FEh Data Memory 3FFh TREG0 PREG ACC 0 C After Instruction 62h 62h 62h 0Fh 14h

6-143

Example 2

LTD *,AR3 ;(TRM = 0)

Before Instruction ARP AR1 Data Memory 3FEh Data Memory 3FFh TREG0 TREG1 TREG2 PREG ACC X C 1 3FEh 62h 0h 3h 4h 5h 0Fh 5h ARP AR1 Data Memory 3FEh Data Memory 3FFh TREG0 TREG1 TREG2 PREG ACC 0 C After Instruction 3 3FEh 62h 62h 62h 2h 2h 0Fh 14h

6-144

Syntax

Direct: Indirect:

LTP dma LTP {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 1 11 0 10 0 9 0 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 1 11 0 10 0 9 0 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (dma) TREG0 (shifted PREG) ACC If TRM = 0: (dma) TREG1 (dma) TREG2

Status Bits Description

Affected by: PM and TRM

The contents of the data memory address (dma) are loaded into TREG0. The contents of the product register (PREG) are shifted, as defined by the PM bits, and stored in the accumulator (ACC). You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. LTP is a TREG0, PREG, and multiply instruction (see Table 67).

Words

6-145

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

LTP DAT36 ;(DP = 6, PM = 0, TRM = 1)

Before Instruction Data Memory 324h TREG0 PREG ACC X C 62h 3h 0Fh 5h Data Memory 324h TREG0 PREG ACC X C After Instruction 62h 62h 0Fh 0Fh

Example 2

LTP *,AR5 ;(PM = 0, TRM = 0)

Before Instruction ARP AR2 Data Memory 324h TREG0 TREG1 TREG2 PREG ACC X C 2 324h 62h 3h 4h 5h 0Fh 5h ARP AR2 Data Memory 324h TREG0 TREG1 TREG2 PREG ACC X C After Instruction 5 324h 62h 62h 2h 2h 0Fh 0Fh

6-146

Syntax

Direct: Indirect:

LTS dma LTS {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 1 11 0 10 1 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 1 11 0 10 1 9 0 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (dma) TREG0 (ACC) (shifted PREG) ACC If TRM = 0: (dma) TREG1 (dma) TREG2

Status Bits

Affected by: OVM, PM, and TRM

Affects: C and OV

Description

The contents of the data memory address (dma) are loaded into TREG0. The contents of the product register (PREG) are shifted, as defined by the PM bits, and subtracted from the accumulator (ACC). The result is stored in the ACC. The C bit is cleared, if the result of the subtraction generates a borrow; otherwise, the C bit is set. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. LTS is a TREG0, PREG, and multiply instruction (see Table 67).

Words

6-147

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

LTS DAT36 ;(DP = 6, PM = 0, TRM = 1)

Before Instruction Data Memory 324h TREG0 PREG ACC X C 62h 3h 0Fh 05h Data Memory 324h TREG0 PREG ACC 0 C After Instruction 62h 62h 0Fh FFFF FFF6h

Example 2

LTS *,AR2 ;(TRM = 0)

Before Instruction ARP AR1 324h TREG0 TREG1 TREG2 PREG ACC X C 1 324h 62h 3h 4h 5h 0Fh 05h ARP AR1 324h TREG0 TREG1 TREG2 PREG ACC 0 C After Instruction 2 324h 62h 62h 2h 2h 0Fh FFFF FFF6h

6-148

Syntax

Direct: Indirect:

MAC pma, dma MAC pma, {ind} [,ARn ]

Operands

0 pma 65535 0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 1 14 0 13 1 12 0 11 0 10 0 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

16-Bit Constant

Indirect addressing
15 1 14 0 13 1 12 0 11 0 10 0 9 1 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

16-Bit Constant

Execution

(PC) + 2 PC (PFC) MCS (pma) PFC If (repeat counter) 0: (ACC) + (shifted PREG) ACC (dma) TREG0 (dma) (pma, addressed by PFC) PREG Modify current AR and ARP as specified (PFC) + 1 PFC (repeat counter) 1 repeat counter Else: (ACC) + (shifted PREG) ACC (dma) TREG0 (dma) (pma, addressed by PFC) PREG Modify current AR and ARP as specified (MCS) PFC If TRM = 0: (dma) TREG1 (dma) TREG2

Status Bits

Affected by: OVM, PM, and TRM

Affects: C and OV

Description

The contents of the product register (PREG) are shifted, as defined by the PM bits, and added to the accumulator (ACC). The result is stored in the ACC. The contents of the data memory address (dma) are loaded into TREG0. The
6-149

contents of the dma are multiplied by the contents of the program memory address (pma). The result is stored in the PREG. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. The data and program memory locations on the C5x can be any nonreserved on-chip or off-chip memory locations. If the program memory is block B0 of onchip RAM, then the CNF bit must be set. When the MAC instruction is used in the direct addressing mode, the dma cannot be modified during repetition of the instruction. When the MAC instruction is repeated, the pma contained in the prefetch counter (PFC) is incremented by 1 during its operation. This allows access to a series of operands in memory. When used with the RPT instruction, the MAC instruction is useful for long sum-of-products operations because the instruction becomes a single-cycle instruction, once the RPT pipeline is started. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. MAC is a TREG0, PREG, and multiply instruction (see Table 67). Words Cycles
Cycles for a Single Instruction Operand 1: DARAM/ROM 2: DARAM 1: SARAM 2: DARAM 1: External 2: DARAM 1: DARAM/ROM 2: SARAM 1: SARAM 2: SARAM 1: External 2: SARAM ROM 3 3 3+pop1 3 3, 4 3+pop1 DARAM 3 3 3+pop1 3 3, 4 3+pop1 SARAM 3 3 3+pop1 3 3, 4 3+pop1 External Memory 3+2pcode 3+2pcode 3+pop1 +2pcode 3+2pcode 3+2pcode , 4+2pcode 3+pop1 +2pcode

If both operands are in the same SARAM block.

6-150

Cycles for a Single Instruction (Continued) Operand 1: DARAM/ROM 2: External 1: SARAM 2: External 1: External 2: External ROM 3+dop2 3+dop2 4+pop1 +do p2 DARAM 3+dop2 3+dop2 4+pop1 +dop2 SARAM 3+dop2 3+dop2 4+pop1 +dop2 External Memory 3+dop2+2pcode 3+dop2 +2pcode 4+pop1 +dop2 +2pcode

If both operands are in the same SARAM block.

Cycles for a Repeat (RPT) Execution Operand 1: DARAM/ROM 2: DARAM 1: SARAM 2: DARAM 1: External 2: DARAM 1: DARAM/ROM 2: SARAM 1: SARAM 2: SARAM 1: External 2: SARAM 1: DARAM/ROM 2: External 1: SARAM 2: External 1: External 2: External ROM n+2 n+2 n+2+npop1 n+2 n+2, 2n+2 n+2+npop1 n+2+ndop2 n+2+ndop2 2n+2+npop1 +ndop2 DARAM n+2 n+2 n+2+npop1 n+2 n+2, 2n+2 n+2+npop1 n+2+ndop2 n+2+ndop2 2n+2+npop1 +ndop2 SARAM n+2 n+2 n+2+npop1 n+2 n+2, 2n+2 n+2+npop1 n+2+ndop2 n+2+ndop2 2n+2+npop1 +ndop2 External Memory n+2+2pcode n+2+2pcode n+2+npop1 +2pcode n+2+2pcode n+2+2pcode , 2n+2 n+2+npop1 +2pcode n+2+ndop2 +2pcode n+2+ndop2 +2pcode 2n+2+npop1 +ndop2 +2pcode

If both operands are in the same SARAM block.

6-151

Example 1

MAC 0FF00h,02h ;(DP = 6, PM = 0, CNF = 1)

Before Instruction Data Memory 302h Program Memory FF00h TREG0 PREG ACC X C 23h 4h 45h 0045 8972h 0723 EC41h Data Memory 302h Program Memory FF00h TREG0 PREG ACC 0 C After Instruction 23h 4h 23h 8Ch 0769 75B3h

Example 2

MAC 0FF00h,*,AR5 ;(PM = 0, CNF = 1)

Before Instruction ARP AR4 Data Memory 302h Program Memory FF00h TREG0 PREG ACC X C 4 302h 23h 4h 45h 0045 8972h 0723 EC41h ARP AR4 Data Memory 302h Program Memory FF00h TREG0 PREG ACC 0 C After Instruction 5 302h 23h 4h 23h 8Ch 0769 75B3h

6-152

Syntax

Direct: Indirect:

MACD pma, dma MACD pma, {ind} [,ARn ]

Operands

0 pma 65535 0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 1 14 0 13 1 12 0 11 0 10 0 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

16-Bit Constant

Indirect addressing
15 1 14 0 13 1 12 0 11 0 10 0 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

16-Bit Constant

Execution

(PC) + 2 PC (PFC) MCS (pma) PFC If (repeat counter) 0: (ACC) + (shifted PREG) ACC (dma) TREG0 (dma) (pma, addressed by PFC) PREG Modify current AR and ARP as specified (PFC) + 1 PFC (dma) (dma) + 1 (repeat counter) 1 repeat counter Else: (ACC) + (shifted PREG) ACC (dma) TREG0 (dma) (pma, addressed by PFC) PREG (dma) (dma) + 1 Modify current AR and ARP as specified (MCS) PFC If TRM = 0: (dma) TREG1 (dma) TREG2

Status Bits

Affected by: OVM, PM, and TRM

Affects: C and OV
6-153

Description

The contents of the product register (PREG) are shifted, as defined by the PM bits, and added to the accumulator (ACC). The result is stored in the ACC. The contents of the data memory address (dma) are loaded into TREG0. The contents of the dma are multiplied by the contents of the program memory address (pma). The result is stored in the PREG. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. See the DMOV instruction, page 6-104, for information on the data move feature. The data and program memory locations on the C5x can be any nonreserved on-chip or off-chip memory locations. If the program memory is block B0 of onchip RAM, then the CNF bit must be set. When the MACD instruction is used in the direct addressing mode, the dma cannot be modified during repetition of the instruction. If the MACD instruction addresses one of the memorymapped registers or external memory as a data memory location, the effect of the instruction will be that of a MAC instruction. When the MACD instruction is repeated, the pma contained in the prefetch counter (PFC) is incremented by 1 during its operation. This allows access to a series of operands in memory. When used with the RPT instruction, the MACD instruction becomes a single-cycle instruction, once the RPT pipeline is started. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. The MACD instruction functions in the same manner as the MAC instruction with the addition of data move for on-chip RAM blocks. The data move feature makes the MACD instruction useful for applications such as convolution and transversal filtering. If you use the MACD instruction with external data memory, its function is identical to that of the MAC instruction (page 6-149). MACD is a TREG0, PREG, and multiply instruction (see Table 67).

Words

6-154

Cycles
Cycles for a Single Instruction Operand 1: DARAM/ROM 2: DARAM 1: SARAM 2: DARAM 1: External 2: DARAM 1: DARAM/ROM 2: SARAM 1: SARAM 2: SARAM 1: External 2: SARAM 1: DARAM/ROM 2: External 1: SARAM 2: External 1: External 2: External ROM 3 3 3+pop1 3 3 3+pop1 3+dop2 3+dop2 4+pop1 +dop2 DARAM 3 3 3+pop1 3 3 3+pop1 3+dop2 3+dop2 4+pop1 +dop2 SARAM 3 3 3+pop1 3 3, 4, 5 3+pop1 3+dop2 3+dop2 4+pop1 +dop2 External Memory 3+2pcode 3+2pcode 3+pop1 +2pcode 3+2pcode 3+2pcode , 4+2pcode 3+pop1 +2pcode 3+dop2 +2pcode 3+dop2 +2pcode 4+pop1 +dop2 +2pcode

If both operands are in the same SARAM block If both operands and the code are in the same SARAM block Data move operation is not performed when operand2 is in external data memory.

6-155

Cycles for a Repeat (RPT) Execution Operand 1: DARAM/ROM 2: DARAM 1: SARAM 2: DARAM 1: External 2: DARAM 1: DARAM/ROM 2: SARAM 1: SARAM 2: SARAM 1: External 2: SARAM 1: DARAM/ROM 2: External 1: SARAM 2: External 1: External 2: External ROM n+2 n+2 n+2+npop1 2n 2n, 3n 2n+npop1 n+2+ndop2 n+2+ndop2 2n+2+npop1 +ndop2 DARAM n+2 n+2 n+2+npop1 2n 2n, 3n 2n+npop1 n+2+ndop2 n+2+ndop2 2n+2+npop1 +ndop2 SARAM n+2 n+2 n+2+npop1 2n, 2n+2 2n, 2n+2, 3n, 3n+2 2n+npop1 , 2n+2+npop1 n+2+ndop2 n+2+ndop2 2n+2+npop1 +ndop2 External Memory n+2+2pcode n+2+2pcode n+2+npop1 +2pcode 2n+2pcode 2n+2pcode , 3n 2n+npop1 +2pcode n+2+ndop2 +2pcode n+2+ndop2 +2pcode 2n+2+npop1 +ndop2 +2pcode

If operand2 and code are in the same SARAM block If both operands are in the same SARAM block If both operands and the code are in the same SARAM block Data move operation is not performed when operand2 is in external data memory.

Example 1

MACD 0FF00h,08h ;(DP = 6, PM = 0, CNF = 1)

Before Instruction Data Memory 308h Data Memory 309h Program Memory FF00h TREG0 PREG ACC X C 23h 18h 4h 45h 0045 8972h 0723 EC41h Data Memory 308h Data Memory 309h Program Memory FF00h TREG0 PREG ACC 0 C After Instruction 23h 23h 4h 23h 8Ch 0769 75B3h

6-156

Example 2

MACD 0FF00h,*,AR6 ;(PM = 0, CF = 1)

Before Instruction ARP AR5 Data Memory 308h Data Memory 309h Program Memory FF00h TREG0 PREG ACC X C 5 308h 23h 18h 4h 45h 0045 8972h 0723 EC41h ARP AR5 Data Memory 308h Data Memory 309h Program Memory FF00h TREG0 PREG ACC 0 C After Instruction 6 308h 23h 23h 4h 23h 8Ch 0769 75B3h

The data move function for MACD can occur only within on-chip data RAM blocks.

6-157

Syntax Operands

Direct: Indirect:

MADD dma MADD {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 1 14 0 13 1 12 0 11 1 10 0 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 1 14 0 13 1 12 0 11 1 10 0 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 2 PC (PFC) MCS (BMAR) PFC If (repeat counter) 0: (ACC) + (shifted PREG) ACC (dma) TREG0 (dma) (pma, addressed by PFC) PREG Modify current AR and ARP as specified (PFC) + 1 PFC (dma) (dma) + 1 (repeat counter) 1 repeat counter Else: (ACC) + (shifted PREG) ACC (dma) TREG0 (dma) (pma, addressed by PFC) PREG (dma) (dma) + 1 Modify current AR and ARP as specified (MCS) PFC

Status Bits Description

Affected by: OVM and PM

Affects: C and OV

The contents of the product register (PREG) are shifted, as defined by the PM bits, and added to the accumulator (ACC). The result is stored in the ACC. The contents of the data memory address (dma) are loaded into TREG0. The contents of the dma are multiplied by the contents of the program memory address (pma). The result is stored in the PREG. The pma is contained in the block move address register (BMAR) and is not specified by a long immediate constant; this enables dynamic addressing of coefficient tables. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. See the DMOV instruction, page 6-104, for information on the data move feature.

6-158

The data and program memory locations on the C5x can be any nonreserved on-chip or off-chip memory locations. If the program memory is block B0 of onchip RAM, then the CNF bit must be set. When the MADD instruction is used in the direct addressing mode, the dma cannot be modified during repetition of the instruction. If the MADD instruction addresses one of the memorymapped registers or external memory as a data memory location, the effect of the instruction is that of a MADS instruction. When the MADD instruction is repeated, the pma contained in the prefetch counter (PFC) is incremented by 1 during its operation. This allows access to a series of operands in memory. When used with the RPT instruction, the MADD instruction becomes a single-cycle instruction, once the RPT pipeline is started. The MADD instruction functions in the same manner as the MADS instruction with the addition of data move for on-chip RAM blocks. The data move feature makes the MADD instruction useful for applications such as convolution and transversal filtering. If you use the MADD instruction with external data memory, its function is identical to that of the MADS instruction (page 6-162). MADD is a TREG0, PREG, and multiply instruction (see Table 67). Words Cycles
Cycles for a Single Instruction Operand 1: DARAM/ROM 2: DARAM 1: SARAM 2: DARAM 1: External 2: DARAM 1: DARAM/ROM 2: SARAM 1: SARAM 2: SARAM 1: External 2: SARAM ROM 2 2 2+pop1 2 2 2+pop1 DARAM 2 2 2+pop1 2 2 2+pop1 SARAM 2 2 2+pop1 2 2, 3, 4 2+pop1 External Memory 2+pcode 2+pcode 2+pop1 +pcode 2+pcode 2+pcode , 3+pcode 2+pop1 +pcode

If both operands are in the same SARAM block If both operands and code are in the same SARAM block Data move operation is not performed when operand2 is in external data memory.

6-159

Cycles for a Single Instruction (Continued) Operand 1: DARAM/ROM 2: External 1: SARAM 2: External 1: External 2: External ROM 2+dop2 2+dop2 3+pop1 +dop2 DARAM 2+dop2 2+dop2 3+pop1 +dop2 SARAM 2+dop2 2+dop2 3+pop1 +dop2 External Memory 2+dop2 +pcode 2+dop2 +pcode 3+pop1 +dop2 +pcode

If both operands are in the same SARAM block If both operands and code are in the same SARAM block Data move operation is not performed when operand2 is in external data memory.

Cycles for a Repeat (RPT) Execution Operand 1: DARAM/ROM 2: DARAM 1: SARAM 2: DARAM 1: External 2: DARAM 1: DARAM/ROM 2: SARAM 1: SARAM 2: SARAM 1: External 2: SARAM 1: DARAM/ROM 2: External 1: SARAM 2: External 1: External 2: External ROM n+1 n+1 DARAM n+1 n+1 SARAM n+1 n+1 External Memory n+1+pcode n+1+pcode

n+1+npop1 2n1 2n1, 3n1 2n1+npop1 n+1+ndop2 n+1+ndop2 2n+1+npop1 +ndop2

n+1+npop1 2n1 2n1, 3n1 2n1+npop1 n+1+ndop2 n+1+ndop2 2n+1+npop1 +ndop2

n+1+npop1 2n1, 2n+1 2n1, 2n+1, 3n1, 3n+1 2n1+npop1 , 2n+1+npop1 n+1+ndop2 n+1+ndop2 2n+1+npop1 +ndop2

n+1+npop1 +pcode 2n1+pcode 2n1+pcode , 3n1 2n1+npop1 +pcode n+1+ndop2 +pcode n+1+ndop2 +pcode 2n+1+npop1 +ndop2 +pcode

If operand2 and code are in the same SARAM block If both operands are in the same SARAM block If both operands and code are in the same SARAM block Data move operation is not performed when operand2 is in external data memory.

6-160

Example 1

MADD DAT7 ;(DP = 6, PM = 0, CNF = 1)

Before Instruction Data Memory 307h Data Memory 308h BMAR TREG0 FF00h PREG ACC X C 8h 9h FF00h 4Eh 2h 0045 8972h 0723 EC41h Data Memory 307h Data Memory 308h BMAR TREG0 FF00h PREG ACC 0 C After Instruction 8h 8h FF00h 8h 2h 10h 0769 75B3h

Example 2

MADD *,3 ;(PM = 0, CNF = 1)

Before Instruction ARP AR2 Data Memory 307h Data Memory 308h BMAR TREG0 FF00h PREG ACC X C 2 307h 8h 9h FF00h 4Eh 2h 0045 8972h 0723 EC41h ARP AR2 Data Memory 307h Data Memory 308h BMAR TREG0 FF00h PREG ACC 0 C After Instruction 3 307h 8h 8h FF00h 8h 2h 10h 0769 75B3h

The data move function for MADD can occur only within on-chip data RAM blocks.

6-161

Syntax

Direct: Indirect:

MADS dma MADS {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 1 14 0 13 1 12 0 11 1 10 0 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 1 14 0 13 1 12 0 11 1 10 0 9 1 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (PFC) MCS (BMAR) PFC If (repeat counter) 0: (ACC) + (shifted PREG) ACC (dma) TREG0 (dma)  (pma, addressed by PFC) PREG Modify current AR and ARP as specified (PFC) + 1 PFC (repeat counter) 1 repeat counter Else: (ACC) + (shifted PREG) ACC (dma) TREG0 (dma)  (pma, addressed by PFC) PREG Modify current AR and ARP as specified (MCS) PFC

Status Bits

Affected by: OVM and PM

Affects: C and OV

Description

The contents of the product register (PREG) are shifted, as defined by the PM bits, and added to the accumulator (ACC). The result is stored in the ACC. The contents of the data memory address (dma) are loaded into TREG0. The contents of the dma are multiplied by the contents of the program memory address (pma). The result is stored in the PREG. The pma is contained in the block move address register (BMAR) and is not specified by a long immediate constant; this enables dynamic addressing of coefficient tables. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared.

6-162

The data and program memory locations on the C5x can be any nonreserved on-chip or off-chip memory locations. If the program memory is block B0 of onchip RAM, then the CNF bit must be set. When the MADS instruction is used in the direct addressing mode, the dma cannot be modified during repetition of the instruction. When the MADS instruction is repeated, the pma contained in the prefetch counter (PFC) is incremented by 1 during its operation. This allows access to a series of operands in memory. When used with the RPT instruction, the MADS instruction is useful for long sum-of-products operations because the instruction becomes a single-cycle instruction, once the RPT pipeline is started. MADS is a TREG0, PREG, and multiply instruction (see Table 67). Words Cycles
Cycles for a Single Instruction Operand 1: DARAM/ROM 2: DARAM 1: SARAM 2: DARAM 1: External 2: DARAM 1: DARAM/ROM 2: SARAM 1: SARAM 2: SARAM 1: External 2: SARAM 1: DARAM/ROM 2: External 1: SARAM 2: External 1: External 2: External ROM 2 2 2+pop1 2 2, 3 2+pop1 2+dop2 2+dop2 3+pop1 +do p2 DARAM 2 2 2+pop1 2 2, 3 2+pop1 2+dop2 2+dop2 3+pop1 +do p2 SARAM 2 2 2+pop1 2 2, 3 2+pop1 2+dop2 2+dop2 3+pop1 +dop2 2+pcode 2+pcode , 3+pcode 2+pop1+pcode 2+dop2 +pcode 2+dop2 +pcode 3+pop1 +dop2 +pcode External Memory 2+pcode 2+pcode

If both operands are in the same SARAM block.

6-163

Cycles for a Repeat (RPT) Execution Operand 1: DARAM/ROM 2: DARAM 1: SARAM 2: DARAM 1: External 2: DARAM 1: DARAM/ROM 2: SARAM 1: SARAM 2: SARAM 1: External 2: SARAM 1: DARAM/ROM 2: External 1: SARAM 2: External 1: External 2: External ROM n+1 n+1 n+1+npop1 n+1 n+1, 2n+1 n+1+npop1 n+1+ndop2 n+1+ndop2 2n+1+npop1 +ndop2 DARAM n+1 n+1 n+1+npop1 n+1 n+1, 2n+1 n+1+npop1 n+1+ndop2 n+1+ndop2 2n+1+npop1 +ndop2 SARAM n+1 n+1 n+1+npop1 n+1 n+1, 2n+1 n+1+npop1 n+1+ndop2 n+1+ndop2 2n+1+npop1 +ndop2 External Memory n+1+pcode n+1+pcode n+1+npop1 +pcode n+1+pcode n+1+pcode , 2n+1 n+1+npop1 +pcode n+1+ndop2 +pcode n+1+ndop2 +pcode 2n+1+npop1 +ndop2 +pcode

If both operands are in the same SARAM block.

Example 1

MADS DAT12 ;(DP = 6, PM = 0, CNF = 1)

Before Instruction Data Memory 30Ch BMAR TREG0 Program Memory FF00h PREG ACC X C 8h FF00h 4Eh 2h 0045 8972h 0723 EC41h Data Memory 30Ch BMAR TREG0 Program Memory FF00h PREG ACC 0 C After Instruction 8h FF00h 8h 2h 10h 0769 75B3h

6-164

Example 2

MADS *,AR3 ;(PM = 0, CNF = 1)

Before Instruction ARP AR2 Data Memory 30Ch BMAR TREG0 Program Memory FF00h PREG ACC X C 2 30Ch 8h FF00h 4Eh 2h 0045 8972h 0723 EC41h ARP AR2 Data Memory 30Ch BMAR TREG0 Program Memory FF00h PREG ACC 0 C After Instruction 3 30Ch 8h FF00h 8h 2h 10h 0769 75B3h

6-165

Syntax Operands Opcode

Direct: Indirect:

MAR dma MAR {ind} [,ARn ]

0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 1 14 0 13 0 12 0 11 1 10 0 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Indirect addressing
15 1 14 0 13 0 12 0 11 1 10 0 9 1 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC Indirect addressing: Modify current AR and ARP as specified Direct addressing: Executes as a NOP

Status Bits Description

Affected by: NDX

In the indirect addressing mode, the auxiliary registers (ARs) and the auxiliary register pointer (ARP) are modified; however, the memory being referenced is unaffected. You can maintain software compatibility with the C2x by clearing the NDX bit. This causes any C2x instruction that modifies AR0 to modify the auxiliary register compare register (ARCR) and index register (INDX) also, maintaining C5x object-code compatibility with the C2x. The MAR instruction modifies the ARs or the ARP bits, and the old ARP bits are copied to the auxiliary register buffer (ARB) bits. Any operation performed with the MAR instruction can also be performed with any instruction that supports indirect addressing. The ARP bits can also be loaded by an LST instruction. Note: The LARP instruction from the C2x instruction set is a subset of the MAR instruction (that is, MAR *,4 performs the same function as LARP 4). MAR is an auxiliary registers and data memory page pointer instruction (see Table 65).

Words
6-166

Cycles
ROM 1

Cycles for a Single Instruction DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example 1

MAR *,AR1 ;Load ARP with 1

Before Instruction ARP ARB 0 7 ARP ARB After Instruction 1 0

Example 2

MAR *+,AR5 ;Increment current auxiliary register (AR1) ;and load ARP with 5.
Before Instruction AR1 ARP ARB 34h 1 0 AR1 ARP ARB After Instruction 35h 5 1

6-167

Syntax

Direct: Indirect: Short immediate: Long immediate:

MPY dma MPY {ind} [,ARn ] MPY #k MPY #lk

Operands

0 dma 127 0n7 4096 k 4095 32768 lk 32767 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 0 14 1 13 0 12 1 11 0 10 1 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 0 12 1 11 0 10 1 9 0 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Short immediate addressing

15 1 14 1 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 13-Bit Constant

Long immediate addressing

15 1 14 0 13 1 12 1 11 1 10 1 9 8 7 6 1 0 1 0 16-Bit Constant 5 0 4 0 3 0 2 0 1 0 0 0

Execution

Direct or indirect addressing: (PC) + 1 PC (TREG0) (dma) PREG Short immediate addressing: (PC) + 1 PC (TREG0) k PREG Long immediate addressing: (PC) + 2 PC (TREG0) lk PREG

Status Bits Description

Affected by: TRM

Not affected by: SXM

If a constant is specified, the constant is multiplied by the contents of TREG0. If a constant is not specified, the contents of TREG0 are multiplied by the contents of the data memory address (dma). The result is stored in the product register (PREG). Short immediate addressing multiplies TREG0 by a signed 13-bit constant. The short immediate constant is right-justified and sign-extended before the multiplication, regardless of the SXM bit.

6-168

You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. MPY is a TREG0, PREG, and multiply instruction (see Table 67). Words 1 2 Cycles (Direct, indirect, or short immediate addressing) (Long immediate addressing)

For the short and long immediate addressing modes, the MPY instruction is not repeatable.
Cycles for a Single Instruction (direct or indirect addressing) Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing) Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing) ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Single Instruction (long immediate addressing) ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

6-169

Example 1

MPY DAT13 ;(DP = 8)

Before Instruction Data Memory 40Dh TREG0 PREG 7h 6h 36h Data Memory 40Dh TREG0 PREG After Instruction 7h 6h 2Ah

Example 2

MPY *,AR2
Before Instruction ARP AR1 Data Memory 40Dh TREG0 PREG 1 40Dh 7h 6h 36h ARP AR1 Data Memory 40Dh TREG0 PREG After Instruction 2 40Dh 7h 6h 2Ah

Example 3

MPY #031h
Before Instruction TREG0 PREG 2h 36h TREG0 PREG After Instruction 2h 62h

Example 4

MPY #01234h
Before Instruction TREG0 PREG 2h 36h TREG0 PREG After Instruction 2h 2468h

6-170

Syntax

Direct: Indirect:

MPYA dma MPYA {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 0 12 1 11 0 10 0 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 0 12 1 11 0 10 0 9 0 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (ACC) + (shifted PREG) ACC (TREG0) (dma) PREG

Status Bits

Affected by: OVM, PM, and TRM

Affects: C and OV

Description

The contents of the product register (PREG) are shifted, as defined by the PM bits, and added to the contents of the accumulator (ACC). The result is stored in the ACC. The contents of TREG0 are multiplied by the contents of the data memory address (dma). The result is stored in the PREG. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. MPYA is a TREG0, PREG, and multiply instruction (see Table 67).

Words

6-171

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

MPYA DAT13 ;(DP = 6, PM = 0)

Before Instruction Data Memory 30Dh TREG0 PREG ACC X C 7h 6h 36h 54h Data Memory 30Dh TREG0 PREG ACC 0 C After Instruction 7h 6h 2Ah 8Ah

Example 2

MPYA *,AR4 ;(PM = 0)

Before Instruction ARP AR3 Data Memory 30Dh TREG0 PREG ACC X C 3 30Dh 7h 6h 36h 54h ARP AR3 Data Memory 30Dh TREG0 PREG ACC 0 C After Instruction 4 30Dh 7h 6h 2Ah 8Ah

6-172

Syntax

Direct: Indirect:

MPYS dma MPYS {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 0 12 1 11 0 10 0 9 0 8 1 7 0 6 5 4 3 2 dma 1 0

Opcode

Indirect addressing
15 0 14 1 13 0 12 1 11 0 10 0 9 0 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (ACC) (shifted PREG) ACC (TREG0) (dma) PREG

Status Bits

Affected by: OVM, PM, and TRM

Affects: C and OV

Description

The contents of the product register (PREG) are shifted, as defined by the PM bits, and subtracted from the contents of the accumulator (ACC). The result is stored in the ACC. The contents of TREG0 are multiplied by the contents of the data memory address (dma). The result is stored in the PREG. The C bit is cleared, if the result of the subtraction generates a borrow; otherwise, the C bit is set. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. MPYS is a TREG0, PREG, and multiply instruction (see Table 67).

Words

6-173

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

MPYS DAT13 ;(DP = 6, PM = 0)

Before Instruction Data Memory 30Dh TREG0 PREG ACC X C 7h 6h 36h 54h Data Memory 30Dh TREG0 PREG ACC 1 C After Instruction 7h 6h 2Ah 1Eh

Example 2

MPYS *,AR5 ;(PM = 0)

Before Instruction ARP AR4 Data Memory 30Dh TREG0 PREG ACC X C 4 30Dh 7h 6h 36h 54h ARP AR4 Data Memory 30Dh TREG0 PREG ACC 1 C After Instruction 5 30Dh 7h 6h 2Ah 1Eh

6-174

Syntax Operands

Direct: Indirect:

MPYU dma MPYU {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 0 12 1 11 0 10 1 9 0 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 0 12 1 11 0 10 1 9 0 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC Unsigned (TREG0) unsigned (dma) PREG

Status Bits

Affected by: TRM

Not affected by: SXM

Description

The unsigned contents of TREG0 are multiplied by the unsigned contents of the data memory address (dma). The result is stored in the product register (PREG). The multiplier acts as a signed 17 17-bit multiplier for this instruction, with the MSB of both operands forced to 0. The p-scaler shifter at the output of the PREG always invokes sign-extension on the PREG, when the PM bits are set to 112 (right-shift-by-6 mode). Therefore, you should not use this shift mode if you want unsigned products. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. The MPYU instruction is particularly useful for computing multiple-precision products, such as multiplying two 32-bit numbers to yield a 64-bit product. MPYU is a TREG0, PREG, and multiply instruction (see Table 67).

Words

6-175

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

MPYU DAT16 ;(DP = 4)

Before Instruction Data Memory 210h TREG0 PREG FFFFh FFFFh 1h Data Memory 210h TREG0 PREG After Instruction FFFFh FFFFh FFFE 0001h

Example 2

MPYU *,AR6
Before Instruction ARP AR5 Data Memory 210h TREG0 PREG 5 210h FFFFh FFFFh 1h ARP AR5 Data Memory 210h TREG0 PREG After Instruction 6 210h FFFFh FFFFh FFFE 0001h

6-176

Syntax Operands Opcode Execution

NEG None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 0

(PC) + 1 PC (ACC) 1 ACC If (ACC) 0: 0 C If (ACC) = 0: 1 C

Status Bits Description

Affected by: OVM

Affects: C and OV

The contents of the accumulator (ACC) are replaced with its arithmetic complement (2s complement). If the contents of the ACC are not 0, the C bit is cleared; if the contents of the ACC are 0, the C bit is set. When taking the 2s complement of 8000 0000h, the OV bit is set and: if the OVM bit is set, the ACC is replaced with 7FFF FFFFh; if the OVM bit is cleared, the ACC is replaced with 8000 0000h. NEG is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example 1

NEG ;(OVM = X)
Before Instruction ACC X C X OV FFFF F228h ACC 0 C X OV After Instruction 0DD8h

6-177

Example 2

NEG ;(OVM = 0)
Before Instruction ACC X C X OV 8000 0000h ACC 0 C 1 OV After Instruction 8000 0000h

Example 3

NEG ;(OVM = 1)
Before Instruction ACC X C X OV 8000 0000h ACC 0 C 1 OV After Instruction 7FFF FFFFh

6-178

Syntax Operands Opcode

NMI None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 1 3 0 2 0 1 1 0 0

Execution

(PC) + 1 stack 24h PC 1 INTM

Status Bits

Not affected by: INTM

Affects: INTM

Description

The current program counter (PC) is incremented and pushed onto the stack. The nonmaskable interrupt vector located at 24h is loaded into the PC. Execution continues at this address. Interrupts are globally disabled (INTM bit is set). The NMI instruction has the same affect as a hardware nonmaskable interrupt. Automatic context save is not performed. NMI is a branch and call instruction (see Table 68).

Words Cycles

1 The NMI instruction is not repeatable.

Cycles for a Single Instruction ROM 4 DARAM 4 SARAM 4 External Memory 4+3p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example

NMI ;Control is passed to program memory location 24h ;and PC+1 is pushed onto the stack.

6-179

Syntax Operands Opcode

NOP None
15 1 14 0 13 0 12 0 11 1 10 0 9 1 8 1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

Execution Status Bits Description

(PC) + 1 PC None affected. No operation is performed. The NOP instruction affects only the program counter (PC). You can use the NOP instruction to create pipeline and execution delays. NOP is a control instruction (see Table 610).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

NOP ;No operation is performed

6-180

Syntax Operands Opcode

NORM {ind} ind: {* *+ * *0+ *0 *BR0+ *BR0}

15 1 14 0 13 1 12 0 11 0 10 0 9 0 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC If (ACC) = 0: TC 1 Else: If (ACC(31)) XOR (ACC(30)) = 0: TC 0 (ACC) 2 ACC Modify current AR as specified Else: TC 1

Status Bits Description

Affects: TC
The signed number contained in the accumulator (ACC) is normalized. Normalizing a fixed-point number separates the number into a mantissa and an exponent by finding the magnitude of the sign-extended number. ACC bit 31 is exclusive-ORed (XOR) with ACC bit 30 to determine if bit 30 is part of the magnitude or part of the sign extension. If the bits are the same, then they are both sign bits, and the ACC is shifted left to eliminate the extra sign bit. If the result of the XOR operation is true, the TC bit is set; otherwise, the TC bit is cleared. The current AR is modified as specified to generate the magnitude of the exponent. It is assumed that the current AR is initialized before normalization begins. The default modification of the current AR is an increment. Multiple executions of the NORM instruction may be required to completely normalize a 32-bit number in the ACC. Although using NORM with RPT does not cause execution of NORM to fall out of the repeat loop automatically when the normalization is complete, no operation is performed for the remainder of the repeat loop. The NORM instruction functions on both positive and negative 2s-complement numbers. NORM is an accumulator memory reference instruction (see Table 64).
6-181

The NORM instruction executes the auxiliary register operation during the execution phase of the pipeline. Therefore, the auxiliary register used in the NORM instruction should not be used by an auxiliary register instruction in the next two instruction words immediately following the NORM instruction. Also, the auxiliary register pointer (ARP) should not be modified by the next two words.

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example 1

NORM *+
Before Instruction ARP AR2 ACC X TC 2 00h FFFF F001h ARP AR2 ACC 0 TC After Instruction 2 01h 0FFF E002h

Example 2

31-bit normalization:
MAR LAR NORM BCND *,AR1 AR1,#0h *+ LOOP,NTC ;Use AR1 to store the exponent. ;Clear out exponent counter. ;One bit is normalized. ;If TC = 0, magnitude not found yet.

LOOP

Example 3

15-bit normalization:
MAR*,AR1 ;Use AR1 to store the exponent. LAR AR1,#0Fh ;Initialize exponent counter. RPT #14 ;15bit normalization specified (yielding ;a 4bit exponent and 16bit mantissa). NORM * ;NORM automatically stops shifting when ;first significant magnitude bit is found, ;performing NOPs for the remainder of the ;repeat loops

6-182

The method in Example 2 normalizes a 32-bit number and yields a 5-bit exponent magnitude. The method in Example 3 normalizes a 16-bit number and yields a 4-bit magnitude. If the number requires only a small amount of normalization, the Example 2 method may be preferable to the Example 3 method because the loop in Example 2 runs only until normalization is complete; Example 3 always executes all 15 cycles of the repeat loop. Specifically, Example 2 is more efficient if the number requires three or fewer shifts. If the number requires six or more shifts, Example 3 is more efficient. Note: The NORM instruction can be used without a specified operand. In that case, any comments on the same line as the instruction are interpreted as the operand. If the first character is an asterisk (*), then the instruction is assembled as NORM * with no auxiliary register modification taking place upon execution. Therefore, TI recommends that you replace the NORM instructions with NORM *+ when you want the default increment modification.

6-183

Syntax Operands

Direct: Indirect:

OPL [#lk ], dma OPL [#lk ], {ind} [,ARn ]

0 dma 127 lk: 16-bit constant 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing with long immediate not specified
15 0 14 1 13 0 12 1 11 1 10 0 9 0 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing with long immediate not specified

15 0 14 1 13 0 12 1 11 1 10 0 9 0 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Direct addressing with long immediate specified

15 0 14 1 13 0 12 1 11 1 10 1 9 8 7 6 0 1 0 16-Bit Constant 5 4 3 2 dma 1 0

Indirect addressing with long immediate specified

15 0 14 1 13 0 12 1 11 1 10 1 9 0 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

16-Bit Constant

Execution

Long immediate not specified: (PC) + 1 PC (dma) OR (DBMR) dma Long immediate specified: (PC) +2 PC (dma) OR lk dma

Status Bits Description

Affects: TC
If a long immediate constant is specified, the constant is ORed with the contents of the data memory address (dma). If a constant is not specified, the contents of the dma are ORed with the contents of the dynamic bit manipulation register (DBMR). In both cases, the result is written directly back to the dma and the contents of the accumulator (ACC) are unaffected. If the result of the OR operation is 0, the TC bit is set; otherwise, the TC bit is cleared. OPL is a parallel logic unit (PLU) instruction (see Table 66).

Words

1 2

(Long immediate not specified) (Long immediate specified)

6-184

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 2+2d DARAM 1 1 2+2d SARAM 1 1, 3 2+2d External Memory 1+p 1+p 5+2d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n 2n2 4n2+2nd DARAM n 2n2 4n2+2nd SARAM n 2n2, 2n+1 4n2+2nd External Memory n+p 2n2+p 4n+1+2nd+p

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate specified) Operand DARAM SARAM External ROM 2 2 3+2d DARAM 2 2 3+2d SARAM 2 2 3+2d External Memory 2+2p 2+2p 6+2d+2p

Cycles for a Repeat (RPT) Execution (long immediate specified) Operand DARAM SARAM External ROM n+1 2n1 4n1+2nd DARAM n+1 2n1 4n1+2nd SARAM n+1 2n1, 2n+2 4n1+2nd External Memory n+1+2p 2n1+2p 4n+2+2nd+2p

If the operand and the code are in the same SARAM block

6-185

Example 1

OPL DAT10 ;(DP=6)

Before Instruction DBMR Data Memory 30Ah FFF0h 0001h DBMR Data Memory 30Ah After Instruction FFF0h FFF1h

Example 2

OPL #0FFFh,DAT10 ;(DP=6)

Before Instruction Data Memory 30Ah 0001h Data Memory 30Ah After Instruction 0FFFh

Example 3

OPL *,AR6
Before Instruction ARP AR3 DBMR Data Memory 300h 3 300h 00F0h 000Fh ARP AR3 DBMR Data Memory 300h After Instruction 6 300h 00F0h 00FFh

Example 4

OPL #1111h,*,AR3
Before Instruction ARP AR6 Data Memory 306h 6 306h 0Eh ARP AR6 Data Memory 306h After Instruction 3 306h 111Fh

6-186

Syntax

Direct: Indirect: Long immediate:

OR dma OR {ind} [,ARn ] OR #lk [,shift ]

Operands

0 dma 127 0n7 lk: 16-bit constant 0 shift 16 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 0 14 1 13 1 12 0 11 1 10 1 9 0 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 1 10 1 9 0 8 1 7 1 6 5 4 3 2 See Section 5.2 1 0

Long immediate addressing with shift

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 0 4 0 3 2 1 SHFT 0

16-Bit Constant
See Table 61 on page 6-2.

Long immediate addressing with shift of 16

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 1 6 0 5 0 4 0 3 0 2 0 1 1 0 0

16-Bit Constant
See Table 61 on page 6-2.

Execution

Direct or indirect addressing: (PC) + 1 PC (ACC(150)) OR (dma) ACC(150) (ACC(3116)) ACC(3116) Long immediate addressing: (PC) + 2 PC (ACC) OR (lk  2shift ) ACC

Status Bits

Does not affect: C Not affected by: SXM

Long immediate addressing

6-187

Description

If a long immediate constant is specified, the constant is shifted, as defined by the shift code, and zero-extended on both ends and is ORed with the contents of the accumulator (ACC). The result is stored in the ACC. If a constant is not specified, the contents of the data memory address (dma) are ORed with the contents of the accumulator low byte (ACCL). The result is stored in the ACCL and the contents of the accumulator high byte (ACCH) are unaffected. OR is an accumulator memory reference instruction (see Table 64).

Words

1 2

(Direct or indirect addressing) (Long immediate addressing)

Cycles

For the long immediate addressing modes, the OR instruction is not repeatable.
Cycles for a Single Instruction (direct or indirect addressing) Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing) Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate addressing) ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

6-188

Example 1

OR DAT8 ;(DP = 8)
Before Instruction Data Memory 408h ACC X C F000h 0010 0002h Data Memory 408h ACC X C After Instruction F000h 0010 F002h

Example 2

OR *,AR0
Before Instruction ARP AR1 Data Memory 300h ACC X C 1 300h 1111h 222h ARP AR1 Data Memory 300h ACC X C After Instruction 0 300h 1111h 1333h

Example 3

OR #08111h,8
Before Instruction ACC X C 00FF 0000h ACC X C After Instruction 00FF 1100h

6-189

Syntax Operands Opcode

ORB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 1 0 1

Execution

(PC) + 1 PC (ACC) OR (ACCB) ACC None affected. The contents of the accumulator (ACC) are ORed with the contents of the accumulator buffer (ACCB). The result is stored in the ACC and the contents of the ACCB are unaffected. ORB is an accumulator memory reference instruction (see Table 64).

Status Bits Description

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

ORB
Before Instruction ACC ACCB X C 5555 5555h 0000 0002h ACC ACCB X C After Instruction 5555 5557h 0000 0002h

6-190

Syntax

Direct: Indirect:

OUT dma , PA OUT {ind}, PA [,ARn ]

Operands

0 dma 127 0n7 0 port address PA 65535 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 0 14 0 13 0 12 0 11 1 10 1 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

16-Bit Constant

Indirect addressing
15 0 14 0 13 0 12 0 11 1 10 1 9 0 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

16-Bit Constant

Execution

(PC) + 2 PC While (repeat counter) 0 Port address address bus A15A0 (dma) data bus D15D0 Port address + 1 Port address (repeat counter 1) (repeat counter) (dma) Port address None affected. A 16-bit value from the data memory address (dma) is written to the specified I/O port. The IS line goes low to indicate an I/O access, and the STRB, R/W, and READY timings are the same as for an external data memory write. While port addresses 50h5Fh are memory-mapped (see subsection 9.1.1, Memory-Mapped Peripheral Registers and I/O Ports); the other port addresses are not. You can use the RPT instruction with the OUT instruction to write consecutive words in data memory to I/O space. The number of words to be moved is one greater than the number contained in the repeat counter register (RPTC) at the beginning of the instruction. When used with the RPT instruction, the OUT instruction becomes a single-cycle instruction, once the RPT pipeline is started, and the port address is incremented after each access. OUT is an I/O and data memory operation instruction (see Table 69).

Status Bits Description

Words

2
6-191

Cycles
Cycles for a Single Instruction Operand Source: DARAM Source: SARAM Source: External ROM 3+iodst 3+iodst 3+dsrc +iodst DARAM 3+iodst 3+iodst 3+dsrc +iodst SARAM 3+iodst 3+iodst , 4+iodst 3+dsrc +iodst External Memory 5+iodst +2pcode 5+iodst +2pcode 6+dsrc +iodst +2pcode

If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand Source: DARAM Source: SARAM Source: External ROM 3n+niodst 3n+niodst 5n2+ndsrc +niodst DARAM 3n+niodst 3n+niodst 5n2+ndsrc + +niodst SARAM 3n+niodst 3n+niodst , 3n+1+niodst 5n2+ndsrc +niodst External Memory 3n+3+niodst +2pcode 3n+3+niodst +2pcode 5n+1+ndsrc +niodst +2pcode

If the source operand and the code are in the same SARAM block

Example 1

OUT DAT0,57h ;(DP = 4) Output data word stored in data memory ;location 200h to peripheral on I/O port 57h. OUT *,PA15 ;Output data word referenced by current auxiliary ;register to peripheral on port address 15 ;(i.e., I/O port 5Fh).

Example 2

6-192

Syntax Operands Opcode

PAC None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 1

Execution

(PC) + 1 PC (shifted PREG) ACC

Status Bits Description

Affected by: PM
The contents of the product register (PREG) are shifted, as defined by the PM bits, and loaded into the accumulator (ACC). PAC is a TREG0, PREG, and multiply instruction (see Table 67).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

PAC ;(PM = 0)
Before Instruction PREG ACC X C 144h 23h PREG ACC X C After Instruction 144h 144h

6-193

Syntax Operands Opcode

POP None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 1 3 0 2 0 1 1 0 0

Execution

(PC) + 1 PC (TOS) ACC(150) 0 ACC(3116) Pop stack one level None affected. The contents of the top of the stack (TOS) are copied to the accumulator low byte (ACCL). The stack is popped one level after the contents are copied. The accumulator high byte (ACCH) is zero-filled. The hardware stack is last-in, first-out with eight locations. Any time a pop occurs, every stack value is copied to the next higher stack location, and the top value is removed from the stack. After a pop, the bottom two stack words have the same value. Because each stack value is copied, if more than seven stack pops (POP, POPD, RET, RETC, RETE, or RETI instructions) occur before any pushes occur, all levels of the stack contain the same value. No provision exists to check stack underflow. POP is a control instruction (see Table 610).

Status Bits Description

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

6-194

Example

POP
Before Instruction ACC Stack X C 82h 45h 16h 7h 33h 42h 56h 37h 61h ACC Stack X C After Instruction 45h 16h 7h 33h 42h 56h 37h 61h 61h

6-195

Syntax Operands

Direct: Indirect:

POPD dma POPD {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 1 14 0 13 0 12 0 11 1 10 0 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 1 14 0 13 0 12 0 11 1 10 0 9 1 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(PC) + 1 PC (TOS) dma Pop stack one level None affected. The contents of the top of the stack (TOS) are copied to the data memory address (dma). The values are popped one level in the lower seven locations of the stack. The value in the lowest stack location is unaffected. See the POP instruction, page 6-194, for more information. POPD is a control instruction (see Table 610).

Status Bits Description

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 2+d DARAM 1 1 2+d SARAM 1 1, 2 2+d External Memory 1+p 1+p 4+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n 2n+nd DARAM n n 2n+nd SARAM n n, n+2 2n+nd External Memory n+p n+p 2n+2+nd+p

If the operand and the code are in the same SARAM block

6-196

Example 1

POPD DAT10 ;(DP = 8)

Before Instruction Data Memory 40Ah Stack 55h 92h 72h 8h 44h 81h 75h 32h AAh Data Memory 40Ah Stack After Instruction 92h 72h 8h 44h 81h 75h 32h AAh AAh

Example 2

POPD *+,AR1
Before Instruction ARP AR0 Data Memory 300h Stack 0 300h 55h 92h 72h 8h 44h 81h 75h 32h AAh ARP AR0 Data Memory 300h Stack After Instruction 1 301h 92h 72h 8h 44h 81h 75h 32h AAh AAh

6-197

Syntax Operands

Direct: Indirect:

PSHD dma PSHD {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 1 11 0 10 1 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 1 11 0 10 1 9 1 8 0 7 1 6 5 4 3 2 See Section 5.2 1 0

Execution

(dma) TOS (PC) + 1 PC Push all stack locations down one level None affected. The contents of the data memory address (dma) are copied to the top of the stack (TOS). The values are pushed down one level in the lower seven locations of the stack. The value in the lowest stack location is lost. See the PUSH instruction, page 6-200, for more information. PSHD is a control instruction (see Table 610).

Status Bits Description

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

6-198

Example 1

PSHD DAT127 ;(DP = 3)

Before Instruction Data Memory 1FFh Stack 65h 2h 33h 78h 99h 42h 50h 0h 0h Data Memory 1FFh Stack After Instruction 65h 65h 2h 33h 78h 99h 42h 50h 0h

Example 2

PSHD *,AR1
Before Instruction ARP AR0 Data Memory 1FFh Stack 0 1FFh 12h 2h 33h 78h 99h 42h 50h 0h 0h ARP AR0 Data Memory 1FFh Stack After Instruction 1 1FFh 12h 12h 2h 33h 78h 99h 42h 50h 0h

6-199

Syntax Operands Opcode

PUSH None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 1 3 1 2 1 1 0 0 0

Execution

(PC) + 1 PC Push all stack locations down one level ACC(150) TOS None affected. The values are pushed down one level in the lower seven locations of the stack. The contents of the accumulator low byte (ACCL) are copied to the top of the stack (TOS). The values on the stack are pushed down before the ACC value is copied. The hardware stack is last-in, first-out with eight locations. If more than eight pushes (CALA, CALL, CC, INTR, NMI, PSHD, PUSH, or TRAP instructions) occur before a pop, the first data values written are lost with each succeeding push. PUSH is a control instruction (see Table 610).

Status Bits Description

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

6-200

Example

PUSH
Before Instruction ACC Stack X C 7h 2h 5h 3h 0h 12h 86h 54h 3Fh ACC Stack X C After Instruction 7h 7h 2h 5h 3h 0h 12h 86h 54h

6-201

Syntax Operands Opcode

RET None
15 1 14 1 13 1 12 0 11 1 10 1 9 1 8 1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

Execution

(TOS) PC Pop stack one level None affected. The contents of the top of the stack (TOS) are copied to the program counter (PC). The stack is popped one level after the contents are copied. The RET instruction is used with the CALA, CALL, and CC instructions for subroutines. RET is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

1 The RET instruction is not repeatable.

Cycles for a Single Instruction ROM 4 DARAM 4 SARAM 4 External Memory 4+3p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example

RET
Before Instruction PC Stack 96h 37h 45h 75h 21h 3Fh 45h 6Eh 6Eh PC Stack After Instruction 37h 45h 75h 21h 3Fh 45h 6Eh 6Eh 6Eh

6-202

Syntax Operands

RETC cond [, cond1 ] [,...] Conditions: ACC = 0 ACC 0 ACC < 0 ACC 0 ACC > 0 ACC 0 C=0 C=1 OV = 0 OV = 1 BIO low TC = 0 TC = 1 Unconditional
12 0 11 1 10 1 9 8 TP 7

EQ NEQ LT LEQ GT GEQ NC C NOV OV BIO NTC TC UNC

6 5 ZLVC 4 3 2 1 ZLVC 0

Opcode

15 1

14 1

13 1

See Table 61 on page 6-2.

Execution

If (condition(s)): (TOS) PC Pop stack one level Else, continue None affected. If the specified conditions are met, the contents of the top of the stack (TOS) are copied to the program counter (PC). The stack is popped one level after the contents are copied. Not all combinations of the conditions are meaningful. If the specified conditions are not met, control is passed to the next instruction. RETC is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

1 The RETC instruction is not repeatable.

Cycles for a Single Instruction Condition True False ROM 4 2 DARAM 4 2 SARAM 4 2 External Memory 4+3p 2+p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

6-203

Example

RETC GEQ,NOV ;A return, RET, is executed if the ;accummulator contents are positive and the ;OV bit is a zero.

6-204

Syntax Operands

RETCD cond [, cond1 ] [,...] Conditions: ACC = 0 ACC 0 ACC < 0 ACC 0 ACC > 0 ACC 0 C=0 C=1 OV = 0 OV = 1 BIO low TC = 0 TC = 1 Unconditional
12 1 11 1 10 1 9 8 TP 7

EQ NEQ LT LEQ GT GEQ NC C NOV OV BIO NTC TC UNC

6 5 ZLVC 4 3 2 1 ZLVC 0

Opcode

15 1

14 1

13 1

See Table 61 on page 6-2.

Execution

If (condition(s)): (TOS) PC Pop stack one level Else, continue None affected. The one 2-word instruction or two 1-word instructions following the RETCD instruction are fetched from program memory and executed before the execution of the return. The two instruction words following the RETCD instruction have no effect on the conditions being tested. After the instructions are executed if the specified conditions are met, the contents of the top of the stack (TOS) are copied to the program counter (PC). The stack is popped one level after the contents are copied. Not all combinations of the conditions are meaningful. If the specified conditions are not met, control is passed to the next instruction. RETCD is a branch and call instruction (see Table 68).

Status Bits Description

Words Cycles

1 The RETCD instruction is not repeatable.

Cycles for a Single Instruction ROM 2 DARAM 2 SARAM 2 External Memory 2+p

6-205

Example

RETCD C ;A return, RET, is executed if the carry MAR *,4 ;bit is set. The two instructions following LAR AR3,#1h ;the return instruction are executed ;before the return is taken.

6-206

Syntax Operands Opcode Execution Status Bits Description

RETD None
15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

(TOS) PC Pop stack one level None affected. The one 2-word instruction or two 1-word instructions following the RETD instruction are fetched from program memory and executed before the execution of the return. After the instructions are executed the contents of the top of the stack (TOS) are copied to the program counter (PC). The stack is popped one level after the contents are copied. RETD is a branch and call instruction (see Table 68).

Words Cycles

1 The RETD instruction is not repeatable.

Cycles for a Single Instruction ROM 2 DARAM 2 SARAM 2 External Memory 2+p

Example

RETD MAR *,4 LACC #1h

Before Instruction PC ARP ACC Stack 96h 0 0h 37h 45h 75h 21h 3Fh 45h 6Eh 6Eh PC ARP ACC Stack After Instruction 37h 4 01h 45h 75h 21h 3Fh 45h 6Eh 6Eh 6Eh

6-207

Syntax Operands Opcode Execution

RETE None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 1 3 1 2 0 1 1 0 0

(TOS) PC Pop stack one level 0 INTM

Status Bits Description

Affects: ARB, ARP, AVIS, BRAF, C, CNF, DP, HM, INTM, MP/MC, NDX, OV, OVLY, OVM, PM, RAM, SXM, TC, TRM, and XF
The contents of the top of the stack (TOS) are copied to the program counter (PC). The stack is popped one level after the contents are copied. The RETE instruction automatically clears the INTM bit and pops the shadow register values (see the RETI description, page 6-209). The RETE instruction is the equivalent of clearing the INTM bit and executing a RETI instruction. RETE is a branch and call instruction (see Table 68).

Words Cycles

1 The RETE instruction is not repeatable.

Cycles for a Single Instruction ROM 4 DARAM 4 SARAM 4 External Memory 4+3p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example

RETE
Before Instruction PC ST0 Stack 96h xx6xh 37h 45h 75h 21h 3Fh 45h 6Eh 6Eh PC ST0 Stack After Instruction 37h xx4xh 45h 75h 21h 3Fh 45h 6Eh 6Eh 6Eh

6-208

Syntax Operands Opcode Execution Status Bits

RETI None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 1 3 1 2 0 1 0 0 0

(TOS) PC Pop stack one level

Affects: ARB, ARP, AVIS, BRAF, C, CNF, DP, HM, MP/MC, NDX, OV, OVLY, OVM, PM, RAM, SXM, TC, TRM, and XF

Does not affect: INTM

Description

The contents of the top of the stack (TOS) are copied to the program counter (PC). The values in the shadow registers (stored when an interrupt was taken) are returned to their corresponding strategic registers. The following registers are shadowed: ACC, ACCB, ARCR, INDX, PMST, PREG, ST0, ST1, TREG0, TREG1, and TREG2. The INTM bit in ST0 and the XF bit in ST1 are not saved or restored to or from the shadow registers during an interrupt service routine (ISR). RETI is a branch and call instruction (see Table 68).

Words Cycles

1 The RETI instruction is not repeatable.

Cycles for a Single Instruction ROM 4 DARAM 4 SARAM 4 External Memory 4+3p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example

RETI
Before Instruction PC Stack 96h 37h 45h 75h 21h 3Fh 45h 6Eh 6Eh PC Stack After Instruction 37h 45h 75h 21h 3Fh 45h 6Eh 6Eh 6Eh

6-209

Syntax Operands Opcode

ROL None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 1 2 1 1 0 0 0

Execution

(PC) + 1 PC C ACC(0) (ACC(31)) C (ACC(300)) ACC(311)

Status Bits

Not affected by: SXM

Affects: C

Description

The contents of the accumulator (ACC) are rotated left 1 bit. The value of the C bit is shifted into the LSB of the ACC. The MSB of the original ACC is shifted into the C bit.
(1)

C (2)

MSB

ACC

LSB

ROL is an accumulator memory reference instruction (see Table 64). Words Cycles
ROM 1

1
Cycles for a Single Instruction DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

ROL
Before Instruction ACC 0 C B000 1234h ACC 1 C After Instruction 6000 2468h

6-210

Syntax Operands Opcode Execution

ROLB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 0 2 1 1 0 0 0

(PC) + 1 PC C ACCB(0) (ACCB(300)) ACCB(311) (ACCB(31)) ACC(0) (ACC(300)) ACC(311) (ACC(31)) C

Status Bits Description

Not affected by: SXM

Affects: C

The ROLB instruction causes a 65-bit rotation. The contents of both the accumulator (ACC) and accumulator buffer (ACCB) are rotated left 1 bit. The value of the C bit is shifted into the LSB of the ACCB. The MSB of the original ACCB is shifted into the LSB of the ACC. The MSB of the original ACC is shifted into the C bit.
(1)

C (3)

MSB

ACC

LSB (2)

MSB

ACCB

LSB

ROLB is an accumulator memory reference instruction (see Table 64). Words Cycles
ROM 1

1
Cycles for a Single Instruction DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

ROLB
Before Instruction ACC ACCB 1 C 0808 0808h FFFF FFFEh ACC ACCB 0 C After Instruction 1010 1011h FFFF FFFDh

6-211

Syntax Operands Opcode

ROR None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 1 2 1 1 0 0 1

Execution

(PC) + 1 PC C ACC(31) (ACC(0)) C (ACC(311)) ACC(300)

Status Bits

Not affected by: SXM

Affects: C

Description

The contents of the accumulator (ACC) are rotated right 1 bit. The value of the C bit is shifted into the MSB of the ACC. The LSB of the original ACC is shifted into the C bit.
C (1) MSB ACC LSB

(2)

ROR is an accumulator memory reference instruction (see Table 64). Words Cycles
ROM 1

1
Cycle Timings for a Single Instruction DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

ROR
Before Instruction ACC 0 C B000 1235h ACC 1 C After Instruction 5800 091Ah

6-212

Syntax Operands Opcode Execution

RORB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 0 2 1 1 0 0 1

(PC) + 1 PC C ACC(31) (ACC(311)) ACC(300) (ACC(0)) ACCB(31) (ACCB(311)) ACCB(300) (ACCB(0)) C

Status Bits Description

Not affected by: SXM

Affects: C

The RORB instruction causes a 65-bit rotation. The contents of both the accumulator (ACC) and accumulator buffer (ACCB) are rotated right 1 bit. The value of the C bit is shifted into the MSB of the ACC. The LSB of the original ACC is shifted into the MSB of the ACCB. The LSB of the original ACCB is shifted into the C bit.
C (1) MSB ACC LSB (2) MSB ACCB LSB

(3)

RORB is an accumulator memory reference instruction (see Table 64). Words Cycles
ROM 1

1
Cycles for a Single Instruction DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

RORB
Before Instruction ACC ACCB 1 C 0808 0808h FFFF FFFEh ACC ACCB 0 C After Instruction 8404 0404h 7FFF FFFFh

6-213

Syntax

Direct: Indirect: Short immediate: Long immediate:

RPT dma RPT {ind} [,ARn ] RPT #k RPT #lk

Operands

0 dma 127 0n7 0 k 255 0 lk 65535 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 0 14 0 13 0 12 0 11 1 10 0 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 0 13 0 12 0 11 1 10 0 9 1 8 1 7 1 6 5 4 3 2 1 See Section 5.2 0

Short immediate addressing

15 1 14 0 13 1 12 1 11 1 10 0 9 1 8 1 7 6 5 4 3 2 1 0 8-Bit Constant

Long immediate addressing

15 1 14 0 13 1 12 1 11 1 10 1 9 8 7 6 1 0 1 1 16-Bit Constant 5 0 4 0 3 0 2 1 1 0 0 0

Execution

Direct or indirect addressing: (PC) + 1 PC (dma) RPTC Short immediate addressing: (PC) + 1 PC k RPTC Long immediate addressing: (PC) + 2 PC lk RPTC

Status Bits Description

None affected. The contents of the data memory address (dma), an 8-bit constant, or a 16-bit constant are loaded into the repeat counter register (RPTC). The instruction following the RPT instruction is repeated n times, where n is one more than the initial value of the RPTC.

6-214

Since the RPTC cannot be saved during a context switch, repeat loops are regarded as multicycle instructions and are not interruptible. However, the processor can halt a repeat loop in response to an external HOLD signal. The execution restarts when HOLD/HOLDA are deasserted. The RPTC is cleared on a device reset. The RPT instruction is especially useful for block moves, multiply-accumulates, normalization, and other functions. RPT is a control instruction (see Table 610). Words Cycles 1 2 (Direct, indirect, or short immediate addressing) (Long immediate addressing)

The RPT instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing) Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (immediate addressing) ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

Example 1

RPT DAT127 ;(DP = 31)

Before Instruction Data Memory 0FFFh RPTC 0Ch 0h Data Memory 0FFFh RPTC After Instruction 0Ch 0Ch

Example 2

RPT *,AR1
Before Instruction ARP AR0 Data Memory 300h RPTC 0 300h 0FFFh 0h ARP AR0 Data Memory 300h RPTC After Instruction 1 300h 0FFFh 0FFFh

6-215

Example 3

RPT #1 ;Repeat next instruction 2 times.

Before Instruction RPTC 0h RPTC After Instruction 1h

Example 4

RPT #1111h ;Repeat next instruction 4370 times.

Before Instruction RPTC 0h RPTC After Instruction 1111h

6-216

Syntax Operands Opcode

RPTB pma 0 pma 65535

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 7 6 5 0 1 1 0 16-Bit Constant 4 0 3 0 2 1 1 1 0 0

Execution

1 BRAF (PC) + 2 PASR pma PAER

Status Bits

Affected by: BRAF

Affects: BRAF

Description

A block of instructions to be repeated a number of times is specified by the memory-mapped block repeat counter register (BRCR) without any penalty for looping. The BRCR must be loaded before execution of an RPTB instruction. When the RPTB instruction is executed, the BRAF bit is set, the block repeat program address start register (PASR) is loaded with the contents of the program counter (PC) + 2, and the block repeat program address end register (PAER) is loaded with the program memory address (pma). Block repeat can be deactivated by clearing the BRAF bit. The number of loop iterations is given as (BRCR) + 1. The RPTB instruction is interruptible. However, RPTB instructions cannot be nested unless the BRAF bit is properly set and the BRCR, PAER, and PASR are appropriately saved and restored. Single-instruction repeat loops (RPT and RPTZ) can be included as part of RPTB blocks. Note: The repeat block must contain at least 3 instruction words for proper operation. RPTB is a control instruction (see Table 610).

Words

6-217

Cycles

The RPTB instruction is not repeatable.

Cycles for a Single Instruction ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

Example

SPLK #iterations_minus_1,BRCR RPTB end_block 1 LACC DAT1 ADD DAT2 SACL DAT1 end_block

;initialize BRCR

6-218

Syntax Operands Opcode

RPTZ #lk 0 lk 65535

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 7 6 5 0 1 1 0 16-Bit Constant 4 0 3 0 2 1 1 0 0 1

Execution

0 ACC 0 PREG (PC) + 1 PC lk RPTC None affected. The contents of the accumulator (ACC) and product register (PREG) are cleared. The 16-bit constant, lk, is loaded into the repeat counter register (RPTC). The instruction following the RPTZ instruction is repeated lk + 1 times. The RPTZ instruction is equivalent to the following instruction sequence:
MPY #0 PAC RPT #<lk>

Status Bits Description

RPTZ is a control instruction (see Table 610). Words Cycles 2 The RPTZ instruction is not repeatable.
Cycles for a Single Instruction ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

Example

RPTZ #7FFh ;Zero product register and accumulator. MACD pma,*+ ;Repeat MACD 2048 times.

6-219

Syntax Operands Opcode

SACB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 1 0 0

Execution

(PC) + 1 PC (ACC) ACCB None affected. The contents of the accumulator (ACC) are copied to the accumulator buffer (ACCB). The contents of the ACC are unaffected. SACB is an accumulator memory reference instruction (see Table 64).

Status Bits Description

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

SACB
Before Instruction ACC ACCB 7C63 8421h 5h ACC ACCB After Instruction 7C63 8421h 7C63 8421h

6-220

Syntax Operands

Direct: Indirect:

SACH dma [,shift2 ] SACH {ind} [,shift2[,ARn ] ]

0 dma 127 0n7 0 shift2 7 (defaults to 0) ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 1 14 0 13 0 12 1 11 1 10 9 8 SHF 7 0 6 5 4 3 dma 2 1 0

Opcode

See Table 61 on page 6-2.

Indirect addressing
15 1 14 0 13 0 12 1 11 1 10 9 8 SHF 7 1 6 5 4 3 2 1 See Section 5.2 0

See Table 61 on page 6-2.

Execution Status Bits Description

(PC) + 1 PC (ACC)  2shift2 dma

Not affected by: SXM

The contents of the accumulator (ACC) are shifted left from 0 to 7 bits, as defined by the shift code, and the high-order bits are stored in the data memory address (dma). During shifting, the high-order bits are lost. The contents of the ACC are unaffected. SACH is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 2+d DARAM 1 1 2+d SARAM 1 1, 2 2+d External Memory 1+p 1+p 4+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n 2n+nd DARAM n n 2n+nd SARAM n n, n+2 2n+nd External Memory n+p n+p 2n+2+nd+p

If the operand and the code are in the same SARAM block

6-221

Example 1

SACH DAT10,1 ;(DP = 4)

Before Instruction ACC Data Memory 20Ah X C 0420 8001h ACC Data Memory 20Ah X C After Instruction 0420 8001h

0h

0841h

Example 2

SACH *+,0,AR2
Before Instruction ARP AR1 ACC Data Memory 300h X C 0h Data Memory 300h 1 300h 0420 8001h ARP AR1 ACC X C 0420h After Instruction 2 301h 0420 8001h

6-222

Syntax Operands

Direct: Indirect:

SACL dma [,shift2 ] SACL {ind} [,shift2[,ARn ] ]

0 dma 127 0n7 0 shift2 7 (defaults to 0) ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 1 14 0 13 0 12 1 11 0 10 9 8 SHF 7 0 6 5 4 3 dma 2 1 0

Opcode

See Table 61 on page 6-2.

Indirect addressing
15 1 14 0 13 0 12 1 11 0 10 9 8 SHF 7 1 6 5 4 3 2 1 See Section 5.2 0

See Table 61 on page 6-2.

Execution Status Bits Description

(PC) + 1 PC (ACC(150))  2shift2 dma

Not affected by: SXM

The contents of the accumulator low byte (ACCL) are shifted left from 0 to 7 bits, as defined by the shift code, and stored in the data memory address (dma). During shifting, the low-order bits are zero-filled and the high-order bits are lost. The contents of the ACC are unaffected. SACL is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 2+d DARAM 1 1 2+d SARAM 1 1, 2 2+d External Memory 1+p 1+p 4+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n 2n+nd DARAM n n 2n+nd SARAM n n, n+2 2n+nd External Memory n+p n+p 2n+2+nd+p

If the operand and the code are in the same SARAM block

6-223

Example 1

SACL DAT11,1 ;(DP = 4)

Before Instruction ACC Data Memory 20Bh X C 7C63 8421h ACC Data Memory 20Bh X C After Instruction 7C63 8421h

05h

0842h

Example 2

SACL *,0,AR7
Before Instruction ARP AR6 ACC Data Memory 300h X C 05h Data Memory 300h 6 300h 00FF 8421h ARP AR6 ACC X C 8421h After Instruction 7 300h 00FF 8421h

6-224

Syntax Operands

Direct: Indirect:

SAMM dma SAMM {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 1 14 0 13 0 12 0 11 1 10 0 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 1 14 0 13 0 12 0 11 1 10 0 9 0 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution Status Bits Description

(PC) + 1 PC (ACC(150)) dma(07) None affected. The contents of the accumulator low byte (ACCL) are copied to the addressed memory-mapped register. The 9 MSBs of the data memory address are cleared, regardless of the current value of the data memory page pointer (DP) bits or the upper 9 bits of the current AR. The SAMM instruction allows the ACC to be stored to any memory location on data memory page 0 without modifying the DP bits. SAMM is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction Operand MMR MMPORT ROM 1 2+iodst DARAM 1 2+iodst SARAM 1 2+iodst External Memory 1+p 4+iodst

Add one more cycle if source is a peripheral memory-mapped register access

Cycles for a Repeat (RPT) Execution Operand MMR MMPORT ROM n 2+niodst DARAM n 2+niodst SARAM n 2+niodst External Memory n+p 2n+2+p+p niodst

Add n more cycles if source is a peripheral memory-mapped register access

6-225

Example 1

SAMM PRD ;(DP = 6)

Before Instruction ACC PRD Data Memory 325h 80h 05h 0Fh PRD Data Memory 325h ACC After Instruction 80h 80h 0Fh

Example 2

SAMM *,AR2 ;(BMAR = 1Fh)

Before Instruction ARP AR7 ACC BMAR Data Memory 31Fh 7 31Fh 080h 0h 11h ARP AR7 ACC BMAR Data Memory 31Fh After Instruction 2 31Fh 080h 080h 11h

6-226

Syntax

Direct: Indirect:

SAR ARx, dma SAR ARx,{ind} [,ARn ]

Operands

0 dma 127 0x7 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 1 14 0 13 0 12 0 11 0 10 9 8 ARX 7 0 6 5 4 3 2 dma 1 0

Opcode

See Table 61 on page 6-2.

Indirect addressing
15 1 14 0 13 0 12 0 11 0 10 9 8 ARX 7 1 6 5 4 3 2 See Section 5.2 1 0

See Table 61 on page 6-2.

Execution

(PC) + 1 PC (AR) dma

Status Bits Description

Affected by: NDX

The contents of the auxiliary register (AR) are stored in the data memory address (dma). When the contents of the current AR are modified in the indirect addressing mode, the SAR instruction stores the value of the AR contents before it is incremented, decremented, or indexed by the contents of the index register (INDX). You can maintain software compatibility with the C2x by clearing the NDX bit. This causes any C2x instruction that loads AR0 to load the auxiliary register compare register (ARCR) and INDX also, maintaining C5x object-code compatibility with the C2x. The SAR and LAR (load auxiliary register) instructions can be used to store and load the ARs during subroutine calls and interrupts. If an AR is not being used for indirect addressing, LAR and SAR enable the register to be used as an additional storage register, especially for swapping values between data memory locations without affecting the contents of the accumulator (ACC). SAR is an auxiliary registers and data memory page pointer instruction (see Table 65).

Words

1
6-227

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 2+d DARAM 1 1 2+d SARAM 1 1, 2 2+d External Memory 1+p 1+p 4+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n 2n+nd DARAM n n 2n+nd SARAM n n, n+2 2n+nd External Memory n+p n+p 2n+2+nd+p

If the operand and the code are in the same SARAM block

Example 1

SAR AR0,DAT30 ;(DP = 6)

Before Instruction AR0 Data Memory 31Eh 37h 18h AR0 Data Memory 31Eh After Instruction 37h 37h

Example 2

SAR AR0,*+
Before Instruction AR0 Data Memory 401h 401h 0h AR0 Data Memory 401h After Instruction 402h 401h

6-228

Syntax Operands Opcode

SATH None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 1 3 1 2 0 1 1 0 0

Execution

(PC) + 1 PC 16  (TREG1(4)) count (ACC) right-shifted by count ACC

Status Bits

Affected by: SXM

Does not affect: C

Description

The SATH instruction, in conjunction with the SATL instruction, allows for a 2-cycle 0- to 31-bit shift right. The contents of the accumulator (ACC) are barrel-shifted right 16 bits as defined by bit 4 of TREG1. If bit 4 of TREG1 is set, the contents of the ACC are barrel-shifted right by 16 bits. If bit 4 of TREG1 is cleared, the contents of the ACC are unaffected. If the SXM bit is cleared, the high-order bits are zero-filled; if the SXM bit is set, the high-order bits of the ACC are filled with copies of ACC bit 31. The C bit is unaffected. SATH is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example 1

SATH ;(SXM = 0)
Before Instruction ACC TREG1 X C FFFF 0000h xx1xh ACC TREG1 X C After Instruction 0000 FFFFh xx1xh

6-229

Example 2

SATH ;(SXM = 1)
Before Instruction ACC TREG1 X C FFFF 0000h xx1xh ACC TREG1 X C After Instruction FFFF FFFFh xx1xh

6-230

Syntax Operands Opcode Execution

SATL None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 1 3 1 2 0 1 1 0 1

(PC) + 1 PC (TREG1(30)) count (ACC) right-shifted by count ACC

Status Bits Description

Affected by: SXM

Does not affect: C

The SATL instruction, in conjunction with the SATH instruction, allows for a 2-cycle 0- to 31-bit shift right. The contents of the accumulator (ACC) are barrel-shifted right 0 to 15 bits as defined by the 4 LSBs of TREG1. If the SXM bit is cleared, the high-order bits are zero-filled; if the SXM bit is set, the high-order bits of the ACC are filled with copies of ACC bit 31. The C bit is unaffected. SATL is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example 1

SATL ;(SXM = 0)
Before Instruction ACC TREG1 X C FFFF 0000h x2h ACC TREG1 X C After Instruction 3FFF C000h x2h

Example 2

SATL ;(SXM = 1)
Before Instruction ACC TREG1 X C FFFF 0000h x2h ACC TREG1 X C After Instruction FFFF C000h x2h

6-231

Syntax Operands Opcode

SBB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 1 2 0 1 0 0 0

Execution

(PC) + 1 PC (ACC) (ACCB) ACC

Status Bits Description

Affects: C
The contents of the accumulator buffer (ACCB) are subtracted from the contents of the accumulator (ACC). The result is stored in the ACC and the contents of the ACCB are unaffected. The C bit is cleared, if the result of the subtraction generates a borrow; otherwise, the C bit is set. SBB is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

SBB
Before Instruction ACC ACCB X C 2000 0000h 1000 0000h ACC ACCB 1 C After Instruction 1000 0000h 1000 0000h

6-232

Syntax Operands Opcode Execution Status Bits Description

SBBB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 1 2 0 1 0 0 1

(PC) + 1 PC (ACC) (ACCB) (logical inversion of C) ACC

Affects: C
The contents of the accumulator buffer (ACCB) and the logical inversion of the C bit are subtracted from the contents of the accumulator (ACC). The result is stored in the ACC and the contents of the ACCB are unaffected. The C bit is cleared, if the result of the subtraction generates a borrow; otherwise, the C bit is set. SBBB is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example 1

SBBB
Before Instruction ACC ACCB 1 C 2000 0000h 1000 0000h ACC ACCB 1 C After Instruction 1000 0000h 1000 0000h

Example 2

SBBB
Before Instruction ACC ACCB 0 C 0009 8012h 0009 8010h ACC ACCB 1 C After Instruction 01h 0009 8010h

6-233

Syntax Operands Opcode

SBRK #k 0 k 255
15 0 14 1 13 1 12 1 11 1 10 1 9 0 8 0 7 6 5 4 3 2 8-Bit Constant 1 0

Execution

(PC) + 1 PC (current AR) 8-bit positive constant current AR None affected. The 8-bit immediate value, right-justified, is subtracted from the current auxiliary register (AR). The result is stored in the current AR. The subtraction takes place in the auxiliary register arithmetic unit (ARAU), with the immediate value treated as a 8-bit positive integer. SBRK is an auxiliary registers and data memory page pointer instruction (see Table 65).

Status Bits Description

Words Cycles

1 The SBRK instruction is not repeatable.

Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Example

SBRK #0FFh
Before Instruction ARP AR7 7 0h ARP AR7 After Instruction 7 FF01h

6-234

Syntax Operands Opcode

SETC control bit

control bit : {C, CNF, HM, INTM, OVM, SXM, TC, XF}
SETC OVM (Set overflow mode)
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 0 2 0 1 1 0 1

SETC SXM (Set sign extension mode)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 0 2 1 1 1 0 1

SETC HM (Set hold mode)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 1 2 0 1 0 0 1

SETC TC (Set test/control)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 1 2 0 1 1 0 1

SETC C (Set carry)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 1 2 1 1 1 0 1

SETC XF (Set external flag pin)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 1 2 1 1 0 0 1

SETC CNF (Set configuration control)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 0 2 1 1 0 0 1

SETC INTM (Set interrupt mode)

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 0 3 0 2 0 1 0 0 1

Execution Status Bits Description

(PC) + 1 PC 1 control bit Affects selected control bit. The specified control bit is set. The LST instruction can also be used to load ST0 and ST1. See Section 4.4, Status and Control Registers, for more information on each control bit. SETC is a control instruction (see Table 610).
6-235

An IDLE instruction must not follow a SETC INTM instruction; otherwise, an unmasked interrupt may take the device out of idle before the INTM bit is set.

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

SETC TC ;TC is bit 11 of ST1

Before Instruction ST1 x1xxh ST1 After Instruction x9xxh

6-236

Syntax Operands Opcode

SFL None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 1 2 0 1 0 0 1

Execution

(PC) + 1 PC (ACC(31)) C (ACC(300)) ACC(311) 0 ACC(0)

Status Bits

Not affected by: SXM

Affects: C

Description

The contents of the accumulator (ACC) are shifted left 1 bit. The MSB of the ACC is shifted into the C bit. The LSB of the ACC is filled with a 0. The SFL instruction, unlike the SFR instruction, is unaffected by the SXM bit.
C (1) MSB ACC LSB (2)

SFL is an accumulator memory reference instruction (see Table 64). Words Cycles
ROM 1

1
Cycles for a Single Instruction DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

SFL
Before Instruction ACC X C B000 1234h ACC 1 C After Instruction 6000 2468h

6-237

Syntax Operands Opcode Execution

SFLB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 0 2 1 1 1 0 0

(PC) + 1 PC 0 ACCB(0) (ACCB(300)) ACCB(311) (ACCB(31)) ACC(0) (ACC(300)) ACC(311) (ACC(31) C

Status Bits Description

Not affected by: SXM

Affects: C

The contents of both the accumulator (ACC) and accumulator buffer (ACCB) are shifted left 1 bit. The LSB of the ACCB is filled with a 0, and the MSB of the ACCB is shifted into the LSB of the ACC. The MSB of the ACC is shifted into the C bit. The SFLB instruction, unlike the SFRB instruction, is unaffected by the SXM bit.
C (3) MSB ACC LSB (2) MSB ACCB LSB (1)

SFLB is an accumulator memory reference instruction (see Table 64). Words Cycles
ROM 1

1
Cycles for a Single Instruction DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

SFLB
Before Instruction ACC ACCB X C B000 1234h B000 1234h ACC ACCB 1 C After Instruction 6000 2469h 6000 2468h

6-238

Syntax Operands Opcode Execution

SFR None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 1 2 0 1 1 0 0

(PC) + 1 PC If SXM = 0: 0 ACC(31) If SXM = 1 (ACC(31)) ACC(31) (ACC(311)) ACC(300) (ACC(0)) C

Status Bits Description

Affected by: SXM

Affects: C

The contents of the accumulator (ACC) are shifted right 1 bit. The type of shift is determined by the SXM bit. If the SXM bit is cleared, the SFR instruction produces a logic right shift. The MSB of the ACC is filled with a 0. The LSB of the ACC is shifted into the C bit. 0
MSB (1) ACC LSB (2) C

If the SXM bit is set, the SFR instruction produces an arithmetic right shift. The MSB (sign bit) of the ACC is unchanged and is copied into ACC bit 30. The LSB of the ACC is shifted into the C bit.

MSB (1)

ACC

LSB (2)

SFR is an accumulator memory reference instruction (see Table 64). Words Cycles
ROM 1

1
Cycles for a Single Instruction DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

6-239

Example 1

SFR ;(SXM = 0)
Before Instruction ACC X C B000 1234h ACC 0 C After Instruction 5800 091Ah

Example 2

SFR ;(SXM = 1)
Before Instruction ACC X C B000 1234h ACC 0 C After Instruction D800 091Ah

6-240

Syntax Operands Opcode

SFRB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 0 2 1 1 1 0 1

Execution

(PC) + 1 PC If SXM=0: 0 ACC(31) If SXM=1: (ACC(31)) ACC(31) (ACC(311)) ACC(300) (ACC(0)) ACCB (31) (ACCB(311)) ACCB(300) (ACCB(0)) C

Status Bits

Affected by: SXM

Affects: C

Description

The contents of both the accumulator (ACC) and accumulator buffer (ACCB) are shifted right 1 bit. The type of shift is determined by the SXM bit. If the SXM bit is cleared, the SFR instruction produces a logic right shift. The MSB of the ACC is filled with a 0. The LSB of the ACC is shifted into the MSB of the ACCB. The LSB of the ACCB is shifted into the C bit. 0
MSB (1) ACC LSB (2) MSB ACCB LSB (3) C

If the SXM bit is set, the SFR instruction produces an arithmetic right shift. The MSB (sign bit) of the ACC is unchanged and is copied into ACC bit 30. The LSB of the ACC is shifted into the MSB of the ACCB. The LSB of the ACCB is shifted into the C bit.

MSB (1)

ACC

LSB (2)

MSB

ACCB

LSB (3)

SFRB is an accumulator memory reference instruction (see Table 64). Words 1

6-241

Cycles
ROM 1

Cycles for a Single Instruction DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example 1

SFRB ;(SXM = 0)
Before Instruction ACC ACCB X C B000 1235h B000 1234h ACC ACCB 0 C After Instruction 5800 091Ah D800 091Ah

Example 2

SFRB ;(SXM = 1)
Before Instruction ACC ACCB X C B000 1234h B000 1234h ACC ACCB 0 C After Instruction D800 091Ah 5800 091Ah

6-242

Syntax

Direct: Indirect:

SMMR dma, #addr SMMR {ind}, #addr [,ARn ]

Operands

0 addr 65535 0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 0 14 0 13 0 12 0 11 1 10 0 9 8 7 6 0 1 0 16-Bit Constant 5 4 3 2 dma 1 0

Opcode

Indirect addressing
15 0 14 0 13 0 12 0 11 1 10 0 9 0 8 1 7 1 6 5 4 3 2 1 See Section 5.2 0

16-Bit Constant

Execution

PFC MCS (PC) + 2 PC lk PFC While (repeat counter 0): (src, specified by lower 7 bits of dma) (dst, addressed by PFC) (PFC) + 1 PFC (repeat counter) 1 repeat counter MCS PFC None affected. The memory-mapped register value pointed at by the lower 7 bits of the data memory address (dma) is stored to the data memory location addressed by the 16-bit source address, #addr. The 9 MSBs of the dma are cleared, regardless of the current value of the data memory page pointer (DP) bits or the upper 9 bits of the current AR. The SMMR instruction allows any memory location on data memory page 0 to be stored anywhere in data memory without modifying the DP bits. When using the SMMR instruction with the RPT instruction, the destination address, #addr, is incremented after every memory-mapped store operation. SMMR is an I/O and data memory operation instruction (see Table 69).

Status Bits Description

Words

2
6-243

Cycles
Cycles for a Single Instruction Operand Destination: DARAM Source: MMR Destination: SARAM Source: MMR Destination: External Source: MMR Destination: DARAM Source: MMPORT Destination: SARAM Source: MMPORT Destination: External Source: MMPORT ROM 2 2 3+ddst 3+iosrc 3+iosrc 4+iosrc +ddst DARAM 2 2 3+ddst 3+iosrc 3+iosrc 4+iosrc +ddst SARAM 2 2, 3 3+ddst 3+iosrc 3+iosrc , 4+iosrc 4+iosrc +ddst External Memory 2+2pcode 2+2pcode 5+ddst +2pcode 4+iosrc +2pcode 3+iosrc +2pcode 6+iosrc +ddst +2pcode

If the destination operand and the code are in the same SARAM block Add one more cycle for peripheral memory-mapped register access.

Cycles for a Repeat (RPT) Execution Operand Destination: DARAM Source: MMR Destination: SARAM Source: MMR Destination: External Source: MMR Destination: DARAM Source: MMPORT Destination: SARAM Source: MMPORT Destination: External Source: MMPORT ROM 2n 2n 3n+nddst 2n+niosrc 2n+niosrc 5n2+nddst +niosrc DARAM 2n 2n 3n+nddst 2n+niosrc 2n+niosrc 5n2+nddst +niosrc SARAM 2n 2n, 2n+2 3n+nddst 2n+niosrc 2n+niosrc , 2n+2+niosrc 5n2+nddst +niosrc External Memory 2n+2pcode 2n+2pcode 3n+3+nddst +2pcode 2n+1+niosrc +2pcode 2n+1+niosrc +2pcode 5n+1+nddst +niosrc +2pcode

If the destination operand and the code are in the same SARAM block Add n more cycles for peripheral memory-mapped register access.

6-244

Example 1

SMMR CBCR,#307h ;(DP = 6, CBCR = 1Eh)

Before Instruction Data Memory 307h CBCR 1376h 5555h Data Memory 307h CBCR After Instruction 5555h 5555h

Example 2

SMMR *,#307h,AR6 ;(CBCR = 1Eh)

Before Instruction ARP AR6 Data Memory 307h CBCR 6 F01Eh 1376h 5555h ARP AR6 Data Memory 307h CBCR After Instruction 6 F01Eh 5555h 5555h

6-245

Syntax Operands Opcode

SPAC None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 1 1 0 0 1

Execution

(PC) + 1 PC (ACC) (shifted PREG) ACC

Status Bits

Affected by: OVM and PM

Not affected by: SXM

Affects: C and OV

Description

The contents of the product register (PREG) are shifted, as defined by the PM bits, and subtracted from the contents of the accumulator (ACC). The result is stored in the ACC. The C bit is cleared, if the result of the subtraction generates a borrow; otherwise, the C bit is set. The SPAC instruction is not affected by the SXM bit and the PREG is always sign extended. The SPAC instruction is a subset of the LTS, MPYS, and SQRS instructions. SPAC is a TREG0, PREG, and multiply instruction (see Table 67).

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

SPAC ;(PM = 0)
Before Instruction PREG ACC X C 1000 0000h 7000 0000h PREG ACC 1 C After Instruction 1000 0000h 6000 0000h

6-246

Syntax Operands

Direct: Indirect:

SPH dma SPH {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 1 14 0 13 0 12 0 11 1 10 1 9 0 8 1 7 0 6 5 4 3 2 dma 1 0

Opcode

Indirect addressing
15 1 14 0 13 0 12 0 11 1 10 1 9 0 8 1 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution Status Bits Description

(PC) + 1 PC (PREG shifter output (3116)) dma

Affected by: PM
The contents of the product register (PREG) high byte are shifted, as defined by the PM bits, and stored in the data memory address (dma). The contents of the PREG and the accumulator (ACC) are unaffected. When the right-shiftby-6 mode (PM is set to 112) is selected, high-order bits are sign extended. When left shifts are selected, low-order bits are filled from the PREG low byte. SPH is a TREG0, PREG, and multiply instruction (see Table 67).

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 2+d DARAM 1 1 2+d SARAM 1 1, 2 2+d External Memory 1+p 1+p 4+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n 2n+nd DARAM n n 2n+nd SARAM n n, n+2 2n+nd External Memory n+p n+p 2n+2+nd+p

If the operand and the code are in the same SARAM block

6-247

Example 1

SPH DAT3 ;(DP = 4, PM = 0)

Before Instruction PREG 203h FE07 9844h 4567h PREG 203h After Instruction FE07 9844h FE07h

Example 2

SPH *,AR7 ;(PM = 2)

Before Instruction ARP AR6 PREG Data Memory 203h 6 203h FE07 9844h 4567h ARP AR6 PREG Data Memory 203h After Instruction 7 203h FE07 9844h E079h

6-248

Syntax Operands

Direct: Indirect:

SPL dma SPL {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 1 14 0 13 0 12 0 11 1 10 1 9 0 8 0 7 0 6 5 4 3 2 dma 1 0

Opcode

Indirect addressing
15 1 14 0 13 0 12 0 11 1 10 1 9 0 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution Status Bits Description

(PC) + 1 PC (PREG shifter output (150)) dma

Affected by: PM
The contents of the product register (PREG) low byte are shifted, as defined by the PM bits, and stored in the data memory address (dma). The contents of the PREG and the accumulator (ACC) are unaffected. When the right-shiftby-6 mode (PM is set to 112) is selected, high-order bits are filled from the PREG high byte. When left shifts are selected, low-order bits are zero-filled. SPL is a TREG0, PREG, and multiply instruction (see Table 67).

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 2+d DARAM 1 1 2+d SARAM 1 1, 2 2+d External Memory 1+p 1+p 4+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n 2n+nd DARAM n n 2n+nd SARAM n n, n+2 2n+nd External Memory n+p n+p 2n+2+nd+p

If the operand and the code are in the same SARAM block

6-249

Example 1

SPL DAT5 ;(DP = 1, PM = 2)

Before Instruction PREG Data Memory 205h FE07 9844h 4567h PREG Data Memory 205h After Instruction FE07 9844h 8440h

Example 2

SPL *,AR3 ;(PM = 0)

Before Instruction ARP AR2 PREG Data Memory 205h 2 205h FE07 9844h 4567h ARP AR2 PREG Data Memory 205h After Instruction 3 205h FE07 9844h 9844h

6-250

Syntax Operands

Direct: Indirect:

SPLK #lk, dma SPLK #lk, {ind} [,ARn ]

0 dma 127 0n7 lk: 16-bit constant ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 1 14 0 13 1 12 0 11 1 10 1 9 1 8 7 6 0 0 16-Bit Constant 5 4 3 2 dma 1 0

Opcode

Indirect addressing
15 1 14 0 13 1 12 0 11 1 10 1 9 1 8 7 6 0 1 16-Bit Constant 5 4 3 2 1 See Section 5.2 0

Execution Status Bits Description

(PC) + 2 PC lk dma None affected. The 16-bit constant is stored into the data memory address (dma). The parallel logic unit (PLU) supports this bit manipulation independently of the arithmetic logic unit (ALU), so the contents of the accumulator (ACC) are unaffected. SPLK is a parallel logic unit (PLU) instruction (see Table 66).

Words Cycles

2 The SPLK instruction is not repeatable.

Cycles for a Single Instruction Operand DARAM SARAM External ROM 2 2 3+d DARAM 2 2 3+d SARAM 2 2, 3 3+d External Memory 2+2p 2+2p 5+d+2p

If the operand and the code are in the same SARAM block

Example 1

SPLK #7FFFh,DAT3 ;(DP = 6)

Before Instruction Data Memory 303h FE07h Data Memory 303h After Instruction 7FFFh

Example 2

SPLK #1111h,*+,AR4
Before Instruction ARP AR0 Data Memory 300h 0 300h ARP AR0

Data Memory 07h 6-251 300h

Syntax Operands Opcode

SPM constant 0 constant 3

15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 PM

See Table 61 on page 6-2.

Execution Status Bits Description

(PC) + 1 PC Constant PM

Not affected by: SXM

Affects: PM

The two low-order bits of the instruction word are copied into the product shift mode (PM) bits of ST1. The PM bits control the product register (PREG) output p-scaler shifter. The p-scaler shifter can shift the PREG output either 1 or 4 bits to the left or 6 bits to the right. The PM bit combinations and their meanings are shown below:
PM Field 00 01 10 11 Action Output is not shifted Output is left-shifted 1 bit and LSB is zero filled Output is left-shifted 4 bits and 4 LSBs are zero filled Output is right-shifted 6 bits, sign extended and 6 LSBs are lost

The left shifts allow the product to be justified for fractional arithmetic. The right shift by 6 accommodates up to 128 multiply-accumulate processes without overflow occurring. The PM bits may also be loaded by an LST #1 instruction (page 6-135). SPM is a TREG0, PREG, and multiply instruction (see Table 67). Words Cycles 1 The SPM instruction is not repeatable.
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Example

SPM 3 ;Product register shift mode 3 is selected, causing ;all subsequent transfers from the product register ;to the ALU to be shifted to the right six places.

6-252

Syntax

Direct: Indirect:

SQRA dma SQRA {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 0 12 1 11 0 10 0 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 0 12 1 11 0 10 0 9 1 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution

(PC) + 1 PC (ACC) + (shifted PREG) ACC (dma) TREG0 (dma)  (dma) PREG If TRM = 0: (dma) TREG1 (dma) TREG2

Status Bits

Affected by: OVM, PM, and TRM

Affects: C and OV

Description

The contents of the product register (PREG) are shifted, as defined by the PM bits, and added to the contents of the accumulator (ACC). The result is stored in the ACC. The contents of the data memory address (dma) are loaded into TREG0 and squared. The result is stored in PREG. The C bit is set, if the result of the addition generates a carry; otherwise, the C bit is cleared. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. SQRA is a TREG0, PREG, and multiply instruction (see Table 67).

Words

1
6-253

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

SQRA DAT30 ;(DP = 6, PM = 0)

Before Instruction Data Memory 31Eh TREG0 PREG ACC X C 0Fh 3h 12Ch 1F4h Data Memory 31Eh TREG0 PREG ACC 0 C After Instruction 0Fh 0Fh 0E1h 320h

Example 2

SQRA *,AR4 ;(PM = 0)

Before Instruction ARP AR3 Data Memory 31Eh TREG0 PREG ACC X C 3 31Eh 0Fh 3h 12Ch 1F4h ARP AR3 Data Memory 31Eh TREG0 PREG ACC 0 C After Instruction 4 31Eh 0Fh 0Fh 0E1h 320h

6-254

Syntax

Direct: Indirect:

SQRS dma SQRS {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 0 12 1 11 0 10 0 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 0 12 1 11 0 10 0 9 1 8 1 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution

(PC) + 1 PC (ACC) (shifted PREG) ACC (dma) TREG0 (dma)  (dma) PREG If TRM = 0: (dma) TREG1 (dma) TREG2

Status Bits

Affected by: OVM, PM, and TRM

Affects: C and OV

Description

The contents of the product register (PREG) are shifted, as defined by the PM bits, and subtracted from the contents of the accumulator (ACC). The result is stored in the ACC. The contents of the data memory address (dma) are loaded into TREG0 and squared. The result is stored in PREG. The C bit is cleared, if the result of the subtraction generates a borrow; otherwise, the C bit is set. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs, maintaining C5x object-code compatibility with the C2x. The TREGs are memory-mapped registers and can be read and written with any instruction that accesses data memory. TREG1 has only 5 bits, and TREG2 has only 4 bits. SQRS is a TREG0, PREG, and multiply instruction (see Table 67).

Words

1
6-255

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

SQRS DAT9 ;(DP = 6, PM = 0)

Before Instruction Data Memory 309h TREG0 PREG ACC X C 08h 1124h 190h 1450h Data Memory 309h TREG0 PREG ACC 1 C After Instruction 08h 08h 40h 12C0h

Example 2

SQRS *,AR5 ;(PM = 0)

Before Instruction ARP AR3 Data Memory 309h TREG0 PREG ACC X C 3 309h 08h 1124h 190h 1450h ARP AR3 Data Memory 309h TREG0 PREG ACC 1 C After Instruction 5 309h 08h 08h 40h 12C0h

6-256

Syntax

Direct: Indirect:

SST #m, dma SST #m, {ind} [,ARn ]

Operands

0 dma 127 m = 0 or 1 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing for SST#0
15 1 14 0 13 0 12 0 11 1 10 1 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing for SST#0

15 1 14 0 13 0 12 0 11 1 10 1 9 1 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

Direct addressing for SST#1

15 1 14 0 13 0 12 0 11 1 10 1 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Indirect addressing for SST#1

15 1 14 0 13 0 12 0 11 1 10 1 9 1 8 1 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution

(PC) + 1 PC (STm) dma None affected. The contents of the status register STm are stored in the data memory address (dma). In the direct addressing mode, status register STm is always stored in data memory page 0, regardless of the value of the data memory page pointer (DP) bits. The processor automatically forces the data memory page to 0, and the specific location within that data page is defined by the instruction. The DP bits are not physically modified. This allows storage of the DP bits in the data memory on interrupts, etc., in the direct addressing mode without having to change the DP. In the indirect addressing mode, the dma is obtained from the selected auxiliary register (see the LST instruction, page 6-135, for more information). In the indirect addressing mode, any page in data memory may be accessed. SST is a control instruction (see Table 610). Status registers ST0 and ST1 are defined in Section 4.4, Status and Control Registers.

Status Bits Description

Words

1
6-257

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 2+d DARAM 1 1 2+d SARAM 1 1, 2 2+d External Memory 1+p 1+p 4+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n 2n+nd DARAM n n 2n+nd SARAM n n, n+2 2n+nd External Memory n+p n+p 2n+2+nd+p

If the operand and the code are in the same SARAM block

Example 1

SST #0,DAT96 ;(DP = 6)

Before Instruction ST0 Data Memory 60h A408h 0Ah ST0 Data Memory 60h After Instruction A408h A408h

Example 2

SST #1,*,AR7
Before Instruction ARP AR0 ST1 Data Memory 300h 0 300h 2580h 0h ARP AR0 ST1 Data Memory 300h After Instruction 7 300h 2580h 2580h

6-258

Syntax

Direct: Indirect: Short immediate: Long immediate:

SUB dma [,shift ] SUB {ind} [,shift [,ARn ] ] SUB #k SUB #lk [,shift ]

Operands

0 dma 127 0 shift 16 (defaults to 0) 0n7 0 k 255 32768 lk 32767 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing with shift
15 0 14 0 13 1 12 1 11 10 9 SHFT 8 7 0 6 5 4 3 dma 2 1 0

Opcode

See Table 61 on page 6-2.

Indirect addressing with shift

15 0 14 0 13 1 12 1 11 10 9 SHFT 8 7 1 6 5 4 3 2 1 See Section 5.2 0

See Table 61 on page 6-2.

Direct addressing with shift of 16

15 0 14 1 13 1 12 0 11 0 10 1 9 0 8 1 7 0 6 5 4 3 dma 2 1 0

Indirect addressing with shift of 16

15 0 14 1 13 1 12 0 11 0 10 1 9 0 8 1 7 1 6 5 4 3 2 1 See Section 5.2 0

Short immediate addressing

15 1 14 0 13 1 12 1 11 1 10 0 9 1 8 0 7 6 5 4 3 2 8-Bit Constant 1 0

Long immediate addressing with shift

15 1 14 0 13 1 12 1 11 1 10 1 9 8 7 6 1 1 1 0 16-Bit Constant 5 1 4 0 3 2 1 SHFT 0

See Table 61 on page 6-2.

Execution

Direct or indirect addressing: (PC) + 1 PC (ACC) ((dma)  2shift ) ACC

6-259

Short immediate addressing: (PC) + 1 PC (ACC) k ACC Long immediate addressing: (PC) + 2 PC (ACC) (lk  2shift ) ACC Status Bits

Affected by: OVM and SXM OVM OVM and SXM

Affects: C and OV C and OV C and OV

Direct or indirect addressing Short immediate addressing Long immediate addressing

Description

If direct, indirect, or long immediate addressing is used, the contents of the data memory address (dma) or a 16-bit constant are shifted left, as defined by the shift code, and subtracted from the contents of the accumulator (ACC). The result is stored in the ACC. During shifting, the accumulator low byte (ACCL) is zero-filled. If the SXM bit is cleared, the high-order bits of the ACC are zero-filled; if the SXM bit is set, the high-order bits of the ACC are signextended. Note that when the auxiliary register pointer (ARP) is updated during indirect addressing, you must specify a shift operand. If you dont want a shift, you must enter a 0 for this operand. For example:
SUB*+,0,AR0

If short immediate addressing is used, an 8-bit positive constant is subtracted from the contents of the ACC. The result is stored in the ACC. In this mode, no shift value may be specified and the subtraction is unaffected by the SXM bit. The C bit is cleared, if the result of the subtraction generates a borrow; otherwise, the C bit is set. If a 16-bit shift is specified with the SUB instruction, the C bit is cleared only if the result of the subtraction generates a borrow; otherwise, the C bit is unaffected. SUB is an accumulator memory reference instruction (see Table 64). Words 1 2 (Direct, indirect, or short immediate) (Long immediate)

6-260

Cycles

For the short and long immediate addressing modes, the SUB instruction is not repeatable.
Cycles for a Single Instruction (direct or indirect addressing) Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing) Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing) ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Single Instruction (long immediate addressing) ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

Example 1

SUB DAT80 ;(DP = 8, SXM=0)

Before Instruction Data Memory 450h ACC X C 11h 24h Data Memory 450h ACC 1 C After Instruction 11h 13h

6-261

Example 2

SUB *,1,AR0 ;(SXM = 0)

Before Instruction ARP Data Memory AR7 301h ACC X C 7 301h 04h 09h ARP Data Memory AR7 301h ACC 1 C After Instruction 0 300h 04h 01h

Example 3

SUB #8h ;(SXM = 1)

Before Instruction ACC X C 07h ACC 0 C After Instruction FFFF FFFFh

Example 4

SUB #0FFFh,4 ;(SXM = 0)

Before Instruction ACC X C FFFFh ACC 1 C After Instruction 0Fh

6-262

Syntax

Direct: Indirect:

SUBB dma SUBB {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 0 11 0 10 1 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 0 10 1 9 0 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution

(PC) + 1 PC (ACC) (dma) (logical inversion of C) ACC

Status Bits

Affected by: OVM

Not affected by: SXM

Affects: C and OV

Description

The contents of the data memory address (dma) and the logical inversion of the C bit are subtracted from the contents of the accumulator (ACC) with sign extension suppressed. The result is stored in the ACC. The C bit is cleared, if the result of the subtraction generates a borrow; otherwise, the C bit is set. The SUBB instruction can be used in performing multiple-precision arithmetic. SUBB is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

6-263

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

SUBB DAT5 ;(DP = 8)

Before Instruction Data Memory 405h ACC 0 C 06h 06h Data Memory 405h ACC 0 C After Instruction 06h FFFF FFFFh

Example 2

SUBB *
Before Instruction ARP AR6 301h ACC 1 C 6 301h 02h 04h ARP AR6 301h ACC 1 C After Instruction 6 301h 02h 02h

In Example 1, the C bit is 0 from the result of a previous subtract instruction that performed a borrow. The operation performed was 6 6 (1) = 1, generating another borrow (C = 0) in the process. In Example 2, no borrow was previously generated (C = 1), and the result from the subtract instruction does not generate a borrow.

6-264

Syntax Operands

Direct: Indirect:

SUBC dma SUBC {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 0 13 0 12 0 11 1 10 0 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 0 13 0 12 0 11 1 10 0 9 1 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution

(PC) + 1 PC (ACC) ((dma)  215 ) ALU output If ALU output 0: (ALU output)  2 + 1 ACC Else: (ACC)  2 ACC

Status Bits Description

Not affected by: OVM (no saturation) and SXM

Affects: C and OV

The SUBC instruction performs conditional subtraction, which may be used for division. The 16-bit dividend is stored in the accumulator low byte (ACCL) and the accumulator high byte (ACCH) is zero-filled. The divisor is in data memory. The SUBC instruction is executed 16 times for 16-bit division. After completion of the last SUBC instruction, the quotient of the division is in the ACCL and the remainder is in the ACCH. The SUBC instruction assumes that the divisor and the dividend are both positive. The divisor is not sign extended. The dividend, in the ACCL, must initially be positive (bit 31 must be 0) and must remain positive following the ACC shift, which occurs in the first portion of the SUBC execution. If the 16-bit dividend contains fewer than 16 significant bits, the dividend may be placed in the ACC and shifted left by the number of leading nonsignificant zeroes. The number of SUBC executions is reduced from 16 by that number. One leading zero is always significant. The SUBC instruction affects the OV bit, but is not affected by the OVM bit, and therefore the ACC does not saturate upon positive or negative overflows when executing this instruction. The C bit is cleared, if the result of the subtraction generates a borrow; otherwise, the C bit is set. SUBC is an accumulator memory reference instruction (see Table 64).
6-265

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

SUBC DAT2 ;(DP = 6)

Before Instruction Data Memory 302h ACC X C 01h 04h Data Memory 302h ACC 0 C After Instruction 01h 08h

Example 2

RPT #15 SUBC *

Before Instruction ARP AR3 Data Memory 1000h ACC X C 3 1000h 07h 41h ARP AR3 Data Memory 1000h ACC 1 C After Instruction 3 1000h 07h 20009h

6-266

Syntax

Direct: Indirect:

SUBS dma SUBS {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 0 11 0 10 1 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 0 10 1 9 1 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution

(PC) + 1 PC (ACC) (dma) ACC (dma) is an unsigned16-bit number

Status Bits

Affected by: OVM

Not affected by: SXM

Affects: C and OV

Description

The contents of the data memory address (dma) are subtracted from the contents of the accumulator (ACC) with sign extension suppressed. The result is stored in the ACC. The data is treated as a 16-bit unsigned number, regardless of the SXM bit. The contents of the ACC are treated as a signed number. The C bit is cleared, if the result of the subtraction generates a borrow; otherwise, the C bit is set. The SUBS instruction produces the same results as a SUB instruction (page 6-259) with the SXM bit cleared and a shift count of 0. SUBS is an accumulator memory reference instruction (see Table 64).

Words

6-267

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

SUBS DAT2 ;(DP = 16, SXM = 1)

Before Instruction Data Memory 802h ACC X C F003h F105h Data Memory 802h ACC 1 C After Instruction F003h 102h

Example 2

SUBS * ;(SXM = 1)
Before Instruction ARP AR0 Data Memory 310h ACC X C 0 310h F003h 0FFF F105h ARP AR0 Data Memory 310h ACC 1 C After Instruction 0 310h F003h 0FFF 0102h

6-268

Syntax

Direct: Indirect:

SUBT dma SUBT {ind} [,ARn ]

Operands

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 0 11 0 10 1 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 0 10 1 9 1 8 1 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution

(PC) + 1 PC (ACC) ((dma)  2TREG1(30) ) (ACC) If SXM = 1: (dma) is sign-extended If SXM = 0: (dma) is not sign-extended

Status Bits

Affected by: OVM, SXM, and TRM

Affects: C and OV

Description

The contents of the data memory address (dma) are shifted left from 0 to 15 bits, as defined by the 4 LSBs of TREG1, and subtracted from the contents of the accumulator (ACC). The result is stored in the ACC. Sign extension on the dma value is controlled by the SXM bit. The C bit is cleared, if the result of the subtraction generates a borrow; otherwise, the C bit is set. You can maintain software compatibility with the C2x by clearing the TRM bit. This causes any C2x instruction that loads TREG0 to write to all three TREGs. Subsequent calls to the SUBT instruction will shift the value by the TREG1 value (which is the same as TREG0), maintaining C5x object-code compatibility with the C2x. SUBT is an accumulator memory reference instruction (see Table 64).

Words

6-269

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Example 1

SUBT DAT127 ;(DP = 4)

Before Instruction Data Memory 2FFh TREG1 ACC X C 06h 08h FDA5h Data Memory 2FFh TREG1 ACC 1 C After Instruction 06h 08h F7A5h

Example 2

SUBT *
Before Instruction ARP AR1 Data Memory 800h TREG1 ACC X C 1 800h 01h 08h 0h ARP AR1 Data Memory 800h TREG1 ACC 0 C After Instruction 1 800h 01h 08h FFFF FF00h

6-270

Syntax Operands

Direct: Indirect:

TBLR dma TBLR {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 1 14 0 13 1 12 0 11 0 10 1 9 1 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 1 14 0 13 1 12 0 11 0 10 1 9 1 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution

(PC) + 1 PC (PFC) MCS (ACC(150)) PFC If (repeat counter) 0: (pma, addressed by PFC) dma Modify current AR and ARP as specified (PFC) + 1 PFC (repeat counter) 1 repeat counter Else: (pma, addressed by PFC) dma Modify current AR and ARP as specified (MCS) PFC

Status Bits Description

None affected. The contents of the program memory address (pma) are transferred to the data memory address (dma). The pma is specified by the contents of the accumulator low byte (ACCL) and the dma is specified by the instruction. A read from program memory is followed by a write to data memory to complete the instruction. When used with the RPT instruction, the TBLR instruction becomes a single-cycle instruction, once the RPT pipeline is started, and the program counter (PC) that contains the contents of the ACCL is incremented once each cycle. TBLR is an I/O and data memory operation instruction (see Table 69).

Words

6-271

Cycles
Cycles for a Single Instruction Operand Source: DARAM/ROM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM/ROM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM/ROM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM 3 3 3+psrc 3 3 3+psrc 4+ddst 4+ddst 4+psrc +ddst DARAM 3 3 3+psrc 3 3 3+psrc 4+ddst 4+ddst 4+psrc +ddst SARAM 3 3 3+psrc 3, 4 3, 4 3+psrc , 4+psrc 4+ddst 4+ddst 4+psrc +ddst External Memory 3+pcode 3+pcode 3+psrc +pcode 3+pcode 3+pcode 3+psrc +pcode 6+ddst +pcode 6+ddst +pcode 6+psrc +ddst +pcode

If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand Source: DARAM/ROM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM/ROM Destination: SARAM ROM n+2 n+2 n+2+npsrc n+2 DARAM n+2 n+2 n+2+npsrc n+2 SARAM n+2 n+2 n+2+npsrc n+2, n+4 External Memory n+2+pcode n+2+pcode n+2+npsrc +pcode n+2+pcode

If the destination operand and the code are in the same SARAM block If both the source and the destination operands are in the same SARAM block If both operands and the code are in the same SARAM block

6-272

Cycles for a Repeat (RPT) Execution (Continued) Operand Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM/ROM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM n+2, 2n n+2+npsrc 2n+2+nddst 2n+2+nddst 4n+npsrc +nddst DARAM n+2, 2n n+2+npsrc 2n+2+nddst 2n+2+nddst 4n+npsrc +nddst SARAM n+2, 2n, 2n+2 n+2+npsrc , n+4+npsrc 2n+2+nddst 2n+2+nddst 4n+npsrc +nddst External Memory n+2+pcode , 2n n+2+npsrc +pcode 2n+4+nddst +pcode 2n+4+nddst +pcode 4n+2+npsrc +nddst +pcode

If the destination operand and the code are in the same SARAM block If both the source and the destination operands are in the same SARAM block If both operands and the code are in the same SARAM block

Example 1

TBLR DAT6 ;(DP = 4)

Before Instruction ACC Program Memory 23h Data Memory 206h 23h 306h 75h ACC Program Memory 23h Data Memory 206h After Instruction 23h 306h 306h

Example 2

TBLR *,AR7
Before Instruction ARP AR0 ACC Program Memory 24h Data Memory 300h 0 300h 24h 307h 75h ARP AR0 ACC Program Memory 24h Data Memory 300h After Instruction 7 300h 24h 307h 307h

6-273

Syntax Operands

Direct: Indirect:

TBLW dma TBLW {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 1 14 0 13 1 12 0 11 0 10 1 9 1 8 1 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 1 14 0 13 1 12 0 11 0 10 1 9 1 8 1 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution

(PC) + 1 PC (PFC) MCS (ACC(150)) PFC If (repeat counter) 0: (dma, addressed by PFC) pma Modify current AR and ARP as specified (PFC) + 1 PFC (repeat counter) 1 repeat counter Else: (dma, addressed by PFC) pma Modify current AR and ARP as specified (MCS) PFC

Status Bits Description

None affected. The contents of the data memory address (dma) are transferred to the program memory address (pma). The dma is specified by the instruction and the pma is specified by the contents of the accumulator low byte (ACCL). A read from data memory is followed by a write to program memory to complete the instruction. When used with the RPT instruction, the TBLW instruction becomes a single-cycle instruction, once the RPT pipeline is started, and the program counter (PC) that contains the contents of the ACCL is incremented once each cycle. TBLW is an I/O and data memory operation instruction (see Table 69).

Words

6-274

Cycles
Cycles for a Single Instruction Operand Source: DARAM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM 3 3 3+dsrc 3 3 3+dsrc 4+pdst 4+pdst 4+dsrc +pdst DARAM 3 3 3+dsrc 3 3 3+dsrc 4+pdst 4+pdst 4+dsrc +pdst SARAM 3 3 3+dsrc 3, 4 3, 4 3+dsrc , 4+dsrc 4+pdst 4+pdst 4+dsrc +pdst External Memory 3+pcode 3+pcode 3+dsrc +pcode 3+pcode 3+pcode 3+dsrc +pcode 5+pdst +pcode 5+pdst +pcode 5+dsrc +pdst +pcode

If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand Source: DARAM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM Destination: SARAM ROM n+2 n+2 n+2+ndsrc n+2 DARAM n+2 n+2 n+2+ndsrc n+2 SARAM n+2 n+2 n+2+ndsrc n+2, n+3 External Memory n+2+pcode n+2+pcode n+2+ndsrc +pcode n+2+pcode

If the destination operand and the code are in the same SARAM block If both the source and the destination operands are in the same SARAM block If both operands and the code are in the same SARAM block

6-275

Cycles for a Repeat (RPT) Execution (Continued) Operand Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM Destination: External Source: SARAM Destination: External Source: External Destination: External ROM n+2, 2n n+2+ndsrc DARAM n+2, 2n n+2+ndsrc SARAM n+2, 2n, 2n+1 n+2+ndsrc , n+3+ndsrc 2n+2+npdst 2n+2+npdst 4n+ndsrc +npdst External Memory n+2+pcode , 2n n+2+ndsrc +pcode

2n+2+npdst 2n+2+npdst 4n+ndsrc +npdst

2n+2+npdst 2n+2+npdst 4n+ndsrc +npdst

2n+3+npdst +pcode 2n+3+npdst +pcode 4n+1+ndsrc +npdst +pcode

If the destination operand and the code are in the same SARAM block If both the source and the destination operands are in the same SARAM block If both operands and the code are in the same SARAM block

Example 1

TBLW DAT5 ;(DP = 32)

Before Instruction ACC Data Memory 1005h Program Memory 257h 257h 4339h 306h ACC Data Memory 1005h Program Memory 257h After Instruction 257h 4339h 4399h

Example 2

TBLW *
Before Instruction ARP AR6 ACC Data Memory 1006h Program Memory 258h 6 1006h 258h 4340h 307h ARP AR6 ACC Data Memory 1006h Program Memory 258h After Instruction 6 1006h 258h 4340h 4340h

6-276

Syntax Operands Opcode

TRAP None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 1 3 0 2 0 1 0 0 1

Execution

(PC) + 1 stack 22h PC

Status Bits

Not affected by: INTM

Does not affect: INTM

Description

A software interrupt that transfers program control to program memory location 22h. The current program counter (PC) is incremented and pushed onto the stack. The address 22h is loaded into the PC. The instruction at address 22h may contain a branch instruction to transfer control to the TRAP routine. Placing the PC onto the stack enables a return instruction to pop the return address (pointing to the instruction after the TRAP) from the stack. The TRAP instruction is not maskable. TRAP is a branch and call instruction (see Table 68).

Words Cycles

1 The TRAP instruction is not repeatable.

Cycles for a Single Instruction ROM 4 DARAM 4 SARAM 4 External Memory 4+3p

The C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example

TRAP ;Control is passed to program memory location 22h and ;PC + 1 is pushed onto the stack.

6-277

Syntax Operands

XC n ,cond [,cond1 ] [,...] n = 1 or 2 Conditions: ACC = 0 ACC 0 ACC < 0 ACC 0 ACC > 0 ACC 0 C=0 C=1 OV = 0 OV = 1 TC = 0 TC = 1 BIO low Unconditional
11 0 10 1 9 8 TP 7

EQ NEQ LT LEQ GT GEQ NC C NOV OV NTC TC BIO UNC

6 5 ZLVC 4 3 2 1 ZLVC 0

Opcode

15 1

14 1

13 12 1 N

See Table 61 on page 6-2.

Operand (n) value 1 2

Opcode (N) value 0 1

Execution

If (condition(s)): next n instructions executed Else: execute NOPs for next n instructions None affected. If n = 1 and the conditions are met, the 1-word instruction following the XC instruction executes. If n = 2 and the conditions are met, the one 2-word instruction or two 1-word instructions following the XC instruction execute. Not all combinations of the conditions are meaningful. The XC instruction and the two instruction words following the XC are uninterruptible. If the conditions are not met, one or two NOPs are executed. Conditions tested are sampled one full cycle before the XC is executed. Therefore, if the instruction prior to the XC is a single-cycle instruction, its execution will not affect the condition of the XC. If the instruction prior to the XC does affect the condition being tested, interrupt operation with the XC can cause undesired results. XC is a branch and call instruction (see Table 68).

Status Bits Description

6-278

Words Cycles

1 The XC instruction is not repeatable.

Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Example

XC 1,LEQ,C MAR *+ ADD DAT100

If the contents of the accumulator are less than or equal to 0 and the C bit is set, the ARP is modified prior to the execution of the ADD instruction.

6-279

Syntax

Direct: Indirect: Long immediate:

XOR dma XOR {ind} [,ARn ] XOR #lk, [,shift ]

Operands

0 dma 127 0n7 lk: 16-bit constant 0 shift 16 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing
15 0 14 1 13 1 12 0 11 1 10 1 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 1 10 1 9 0 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

Long immediate addressing with shift

15 1 14 0 13 1 12 1 11 1 10 1 9 8 7 6 1 1 1 1 16-Bit Constant 5 0 4 1 3 2 1 SHFT 0

See Table 61 on page 6-2.

Long immediate addressing with shift of 16

15 1 14 0 13 1 12 1 11 1 10 1 9 8 7 6 1 0 1 0 16-Bit Constant 5 0 4 0 3 0 2 0 1 1 0 1

Execution

Direct or indirect addressing: (PC) + 1 PC (ACC(150)) XOR (dma) ACC(150) (ACC(3116)) ACC(3116) Long immediate addressing: (PC) + 2 PC (ACC(310)) XOR (lk  2shift ) ACC(310)

Status Bits

Does not affect: C Not affected by: SXM

Long immediate addressing

6-280

Description

If a long immediate constant is specified, the constant is shifted left, as defined by the shift code, and zero-extended on both ends and is exclusive-ORed with the contents of the accumulator (ACC). The result is stored in the ACC. If a constant is not specified, the contents of the data memory address (dma) are exclusive-ORed with the contents of the accumulator low byte (ACCL). The result is stored in the ACCL and the contents of the accumulator high byte (ACCH) are unaffected. XOR is an accumulator memory reference instruction (see Table 64).

Words

1 2

(Direct or indirect addressing) (Long immediate addressing)

Cycles

For the long immediate addressing modes, the XOR instruction is not repeatable.
Cycles for a Single Instruction (direct or indirect addressing) Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing) Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate addressing) ROM 2 DARAM 2 SARAM 2 External Memory 2+2p

6-281

Example 1

XOR DAT127 ;(DP = 511)

Before Instruction Data Memory FFFFh ACC X C F0F0h 1234 5678h Data Memory FFFFh ACC X C After Instruction F0F0h 1234 A688h

Example 2

XOR *+,AR0
Before Instruction ARP AR7 Data Memory 300h ACC X C 7 300h FFFFh 1234 F0F0h ARP AR7 Data Memory 300h ACC X C After Instruction 0 301h FFFFh 1234 0F0Fh

Example 3

XOR #0F0F0h,4
Before Instruction ACC X C 1111 1010h ACC X C After Instruction 111E 1F10h

6-282

Syntax Operands Opcode

XORB None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 1 2 0 1 1 0 0

Execution

(PC) + 1 PC (ACC) XOR (ACCB) ACC None affected. The contents of the accumulator (ACC) are exclusive-ORed with the contents of the accumulator buffer (ACCB). The result is stored in the ACC and the contents of the ACCB are unaffected. XORB is an accumulator memory reference instruction (see Table 64).

Status Bits Description

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

XORB
Before Instruction ACCB ACC F0F0 F0F0h FFFF 0000h ACCB ACC After Instruction F0F0 F0F0h 0F0F F0F0h

6-283

Syntax Operands

Direct: Indirect:

XPL [#lk,] dma XPL [#lk,] {ind} [,ARn ]

0 dma 127 lk: 16-bit constant 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing with long immediate not specified
15 0 14 1 13 0 12 1 11 1 10 0 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing with long immediate not specified

15 0 14 1 13 0 12 1 11 1 10 0 9 0 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

Direct addressing with long immediate specified

15 0 14 1 13 0 12 1 11 1 10 1 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

16-Bit Constant

Indirect addressing with long immediate specified

15 0 14 1 13 0 12 1 11 1 10 1 9 0 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

16-Bit Constant

Execution

Long immediate not specified: (PC) + 1 PC (dma) XOR (DBMR) dma Long immediate specified: (PC) + 2 PC (dma) XOR lk dma

Status Bits Description

Affects: TC
If a long immediate constant is specified, the constant is exclusive-ORed with the contents of the data memory address (dma). If a constant is not specified, the contents of the dma are exclusive-ORed with the contents of the dynamic bit manipulation register (DBMR). In both cases, the result is written directly back to the dma. The contents of the accumulator (ACC) are unaffected. If the result of the XOR operation is 0, the TC bit is set; otherwise, the TC bit is cleared. XPL is a parallel logic unit (PLU) instruction (see Table 66).

Words

1 2

(Long immediate not specified) (Long immediate specified)

6-284

Cycles
Operand DARAM SARAM External

Cycles for a Single Instruction ROM 1 1 2+2d DARAM 1 1 2+2d SARAM 1 1, 3 2+2d External Memory 1+p 1+p 5+2d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n 2n2 4n2+2nd DARAM n 2n2 4n2+2nd SARAM n 2n2, 2n+1 4n2+2nd External Memory n+p 2n2+p 4n+1+2nd+p

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate specified) Operand DARAM SARAM External ROM 2 2 3+2d DARAM 2 2 3+2d SARAM 2 2 3+2d External Memory 2+2p 2+2p 6+2d+2p

Cycles for a Repeat (RPT) Execution (long immediate specified) Operand DARAM SARAM External ROM n+1 2n1 4n1+2nd DARAM n+1 2n1 4n1+2nd SARAM n+1 2n1, 2n+2 4n1+2nd External Memory n+1+2p 2n1+2p 4n+2+2nd+2p

If the operand and the code are in the same SARAM block

6-285

Example 1

XPL #100h,DAT60 ;(DP = 0)

Before Instruction Data Memory 60h 01h Data Memory 60h After Instruction 101h

Example 2

XPL DAT60 ;(DP=0)

Before Instruction DBMR Data Memory 60h FFFFh 0101h DBMR Data Memory 60h After Instruction FFFFh FEFEh

Example 3

XPL #1000h,*,AR6
Before Instruction ARP AR0 Data Memory 300h 0 300h FF00h ARP AR0 Data Memory 300h After Instruction 6 300h EF00h

Example 4

XPL *,AR0
Before Instruction ARP AR6 DBMR Data Memory 301h 6 301h FF00h EF00h ARP AR6 DBMR Data Memory 301h After Instruction 0 300h FF00h 1000h

6-286

Syntax Operands

Direct: Indirect:

ZALR dma ZALR {ind} [,ARn ]

0 dma 127 0n7 ind: {* *+ * *0+ *0 *BR0+ *BR0} Direct addressing

15 0 14 1 13 1 12 0 11 1 10 0 9 0 8 0 7 0 6 5 4 3 dma 2 1 0

Opcode

Indirect addressing
15 0 14 1 13 1 12 0 11 1 10 0 9 0 8 0 7 1 6 5 4 3 2 1 See Section 5.2 0

Execution

(PC) + 1 PC 8000h ACC(150) (dma) ACC(3116)

Status Bits Description

Does not affect: C

The contents of the data memory address (dma) are loaded into the accumulator high byte (ACCH). The ZALR instruction rounds the value by adding 1/2 LSB; that is, the 15 low-order bits (bits 014) of the accumulator low byte (ACCL) are cleared, and ACCL bit 15 is set. ZALR is an accumulator memory reference instruction (see Table 64).

Words Cycles

1
Cycles for a Single Instruction Operand DARAM SARAM External ROM 1 1 1+d DARAM 1 1 1+d SARAM 1 1, 2 1+d External Memory 1+p 1+p 2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution Operand DARAM SARAM External ROM n n n+nd DARAM n n n+nd SARAM n n, n+1 n+nd External Memory n+p n+p n+1+p+nd

If the operand and the code are in the same SARAM block

6-287

Example 1

ZALR DAT3 ;(DP = 32)

Before Instruction Data Memory 1003h ACC X C 3F01h 0077 FFFFh Data Memory 1003h ACC X C After Instruction 3F01h 3F01 8000h

Example 2

ZALR *,AR4
Before Instruction ARP AR7 Data Memory FF00h ACC X C 7 FF00h E0E0h 0010 7777h ARP AR7 Data Memory FF00h ACC X C After Instruction 4 FEFFh E0E0h E0E0 8000h

6-288

Syntax Operands Opcode

ZAP None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 1 3 1 2 0 1 0 0 1

Execution

(PC) + 1 PC 0 ACC 0 PREG None affected. The contents of the accumulator (ACC) and product register (PREG) are cleared. The ZAP instruction speeds up the preparation for a repeat multiply/ accumulate. ZAP is an accumulator memory reference instruction (see Table 64).

Status Bits Description

Words Cycles

1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

ZAP
Before Instruction PREG ACC 3F01 1111h 77FF FF77h PREG ACC After Instruction 0000 0000h 0000 0000h

6-289

Syntax Operands Opcode

ZPR None
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 1 3 1 2 0 1 0 0 0

Execution

(PC) + 1 PC 0 PREG None affected. The contents of the product register (PREG) are cleared. ZPR is a TREG0, PREG, and multiply instruction (see Table 67). 1
Cycles for a Single Instruction ROM 1 DARAM 1 SARAM 1 External Memory 1+p

Status Bits Description

Words Cycles

Cycles for a Repeat (RPT) Execution ROM n DARAM n SARAM n External Memory n+p

Example

ZPR
Before Instruction PREG 3F01 1111h PREG After Instruction 0000 0000h

6-290

Chapter 7

Pipeline

In the operation of the pipeline, the instruction fetch, decode, operand read, and execute operations are independent, which allows overall instruction executions to overlap.

Topic
7.1 7.2 7.3

Page
Pipeline Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Pipeline Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24

Pipeline

7-1

Pipeline Structure

7.1 Pipeline Structure

The four phases of the C5x pipeline structure and their functions are as follows: 1) Fetch (F) This phase fetches the instruction words from memory and updates the program counter (PC). 2) Decode (D) This phase decodes the instruction word and performs address generation and ARAU updates of auxiliary registers. 3) Read (R) This phase reads operands from memory, if required. If the instruction uses indirect addressing mode, it will read the memory location pointed at by the ARP before the update of the previous decode phase. 4) Execute (E) This phase performs any specify operation, and, if required, writes results of a previous operation to memory. Figure 71 illustrates the operation of the four-level pipeline for single-word single-cycle instruction executing with no wait state. This is perfect overlapping in the pipeline, where all four phases operate in parallel. When more than one pipeline stage requires processing on the same resource, such as memory and CPU registers, a pipeline conflict occurs. Since there is no priority between these four phases, you can get unexpected results when pipeline conflict occurs. Therefore, you should avoid any conflict between these four phases in order to get the correct results.

Figure 71. Four Level Pipeline Operation

CLKIN Fetch (F) Decode (D) Read (R) Execute (E) N N1 N2 N3 N+1 N N1 N2 N+2 N+1 N N1 N+3 N+2 N+1 N

Fully loaded pipeline

7-2

Pipeline Operation

7.2 Pipeline Operation

The pipeline is essentially invisible to the user except in some cases, such as auxiliary register updates, memory-mapped accesses of the CPU registers, the NORM instruction, and memory configuration commands. Furthermore, the pipeline operation is not protected. The user has to understand the pipeline operation to avoid the pipeline conflict by arranging the code. The following sections show how the pipeline operation and how the pipeline conflict affect the result.

7.2.1

Normal Pipeline Operation

Example 71 shows the pipeline operation of a 1-word instruction and Example 72 shows the pipeline operation of a 2-word instruction.

1-Word Instruction Example 71. Pipeline Operation of 1-Word Instruction

ADD SAMM MPY SQRA . . . *+ TREG0 *+ *+, AR2

Table 71. Pipeline Operation of 1-Word Instruction

Pipeline operation Cycle 1 2 3 4 5 6 7 PC F D R E ARP 6 ADD SAMM MPY SQRA ADD SAMM MPY SQRA ADD SAMM MPY SQRA 6 6 6 2 X X AR6 60h 61h 61h 62h 63h XX XX TREG0 XX XX XX XX 30h 30h 06h PREG XX XX XX XX XX 90h 24h ACC 20h 20h 20h 30h 30h 30h C0h

[SAMM] ADD [MPY] [SQRA] SAMM MPY SQRA

Pipeline

7-3

Pipeline Operation

Assume memory locations 60h = 10h, 61h = 3h, and 62h = 6h. The following is the condition of the pipeline for each cycle. Cycle 1: Cycle 2: F) Fetch the ADD instruction and update PC to next instruction. F) Fetch the SAMM instruction and update PC. D) Decode the ADD instruction, generate address, and update AR6. Cycle 3: F) Fetch the MPY instruction and update PC. D) Decode the SAMM instruction, no address generate, and no ARAU update. R) Read data from memory location 60h (10h) which is the location pointed at by AR6 before the update of cycle 2. Cycle 4: F) Fetch the SQRA instruction and update PC. D) Decode the MPY instruction and update AR6. R) No operand read for the SAMM instruction. E) Add data read in cycle 3 (10h) to data in ACC (20h) and store result in ACC (ACC = 30h). Cycle 5: F) Fetch the next instruction and update PC. D) Decode the SQRA instruction, and update AR6 and ARP. R) Read data from data memory location 61h (3h) which is the location pointed at by AR6 before the update of cycle 4. E) Store data in ACC to TREG0 (TREG0 = 30h). Cycle 6: F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 5. R) Read data from data memory location 62h (6h) which is the location pointed at by AR6 before the update of cycle 5. E) Multiply data in TREG0 (30h) with data read in cycle 5 (3h) and store result in PREG (PREG = 90h). Cycle 7: F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 6. R) Depends on the instruction fetched in cycle 5. E) Add data in ACC (30h) to data in PREG (90h) and store result in ACC (ACC = C0h). Store data read in cycle 6 (6h) to TREG0. Square data in TREG0 (6h) and store result in PREG (PREG = 24h).
7-4

Pipeline Operation

2-Word Instruction Example 72. Pipeline Operation of 2-Word Instruction

LACC ADD SACL . . . *+ #1000h *+, 0, AR2

Table 72. Pipeline Operation of 2-Word Instruction

Pipeline operation Cycle 1 2 3 4 5 6 7 PC [ADD] [1000h] [SACL] F LACC ADD 1000h SACL LACC ADD dummy SACL LACC ADD dummy SACL LACC ADD dummy SACL D R E ARP 1 1 1 1 2 X X AR1 60h 61h 61h 61h 62h XX XX ACC 20h 20h 20h 10h 1010h 1010h 1010h [61] 3h 3h 3h 3h 3h 3h 1010h

Assume memory location 60h = 10h and 61h = 3h. The following is the condition of the pipeline for each cycle. Cycle 1: Cycle 2: F) Fetch the LACC instruction and update PC to next instruction. F) Fetch the ADD instruction and update PC. D) Decode the LACC instruction and update AR1. Cycle 3: F) Fetch the second word 1000h and update PC. D) Decode the ADD instruction and no ARAU update. R) Read data from data memory location 60h (10h) which is the location pointed at by AR1 before the update of cycle 2. Cycle 4: F) Fetch the SACL instruction and update PC. D) Dummy operation (previous fetch phase is an operand). R) No operand read for the ADD instruction. E) Load ACC with data read in cycle 3 (ACC = 10h).
Pipeline
7-5

Pipeline Operation

Cycle 5:

F) Fetch the next instruction and update PC. D) Decode the SACL instruction, and update AR1 and ARP. R) Dummy operation (operand fetch on fetch phase). E) Add 1000h to data in ACC (10h) and store result in ACC (ACC = 1010h).

Cycle 6:

F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 5. R) No operand read for the SACL instruction. E) Dummy operation (operand fetch on fetch phase).

Cycle 7:

F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 6. R) Depends on the instruction fetched in cycle 5. E) Store data in ACC (1010h) to data memory location 61h which is the location pointed at by AR1 before the update of cycle 5.

7.2.2

Pipeline Operation on Branch and Subroutine Call

Since the pipeline is 4-levels deep, normally any branch, subroutine call, or return from subroutine instruction (Table 68 on page 6-17) takes 4 cycles to flush the pipeline. The conditional branch (BCND) instruction also takes 4 cycles, when the condition is true. Following are examples that show the pipeline operations of the conditional branch, subroutine call, and return from subroutine instructions.

Branch Taken Example 73. Pipeline Operation with Branch Taken

ADD BCND ADD SUB SACL LBL SUB . . . *+ LBL, NEQ *+ #1 *+,0,AR2 *+

; Branch if ACC 0

7-6

Pipeline Operation

Table 73. Pipeline Operation with Branch Taken

Pipeline operation Cycle 1 2 3 4 5 6 7 8 9 PC [BCND] [LBL] [ADD] [SUB] LBL F ADD BCND LBL ADD SUB SUB ADD BCND dummy dummy dummy SUB ADD BCND dummy dummy dummy SUB ADD BCND dummy dummy dummy SUB D R E ARP 1 1 1 1 1 1 1 X X AR1 60h 61h 61h 61h 61h 61h 62h XX XX ACC 20h 20h 20h 30h 30h 30h 30h 30h 2Dh

Assume memory location 60h = 10h and 61h = 3h. The following is the condition of the pipeline for each cycle. Cycle 1: Cycle 2: F) Fetch the ADD instruction and update PC to next instruction. F) Fetch the BCND instruction and update PC. D) Decode the ADD instruction and update AR1. Cycle 3: F) Fetch the second word LBL and update PC. D) Decode the BCND instruction and no ARAU update. R) Read data from data memory location 60h (10h) which is the location pointed at by AR1 before the update of cycle 2. Cycle 4: F) Fetch the ADD instruction and update PC. D) Dummy operation (previous fetch phase is an operand). R) No operand read for the BCND instruction. E) Add data read in cycle 3 (10h) to data in ACC (20h) and store result in ACC (ACC = 30h). The PC update and decode (D) phase on cycle 5 depends on the execute (E) phase result of the BCND instruction. Since the condition is true, the PC will update to point to the destination address and a dummy operation will be inserted in the decode (D) phase to flush the pipeline. Cycle 5: F) Fetch the SUB instruction and update PC. Since the condition is true, the operand of BCND (LBL) will copy to PC. D) Dummy operation (flush the pipeline).
Pipeline
7-7

Pipeline Operation

R) Dummy operation (operand fetch on fetch phase). E) Conditional testing. Cycle 6: F) Fetch the SUB instruction and update PC. D) Dummy operation (flush the pipeline). R) Dummy operation (flush the pipeline). E) Dummy operation (operand fetch on fetch phase). Cycle 7: F) Fetch the next instruction and update PC. D) Decode the SUB instruction and update AR1. R) Dummy operation (flush the pipeline). E) Dummy operation (flush the pipeline). Cycle 8: F) Fetch the next instruction and update PC. D) Decode the instruction in cycle 7. R) Read data from data memory location 61h (3h) which is the location pointed at by AR1 before the update of cycle 7. E) Dummy operation (flush the pipeline). Cycle 9: F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 8. R) Depends on the instruction fetched in cycle 7. E) Subtract data read in cycle 8 (3h) from data in ACC (30h) and store result in ACC (ACC = 2Dh).

7-8

Pipeline Operation

Branch Not Taken Example 74. Pipeline Operation with Branch Not Taken
ADD BCND ADD SUB SACL . . LBL SUB . . *+ LBL, EQ *+ #1 *+,0,AR2

;Branch if ACC = 0

*+

Table 74. Pipeline Operation with Branch Not Taken

Pipeline operation Cycle 1 2 3 4 5 6 7 8 9 PC [BCND] [LBL] [ADD] [SUB] SACL F ADD BCND LBL ADD SUB SACL ADD BCND dummy ADD SUB SACL ADD BCND dummy ADD SUB SACL ADD BCND dummy ADD SUB SACL D R E ARP 1 1 1 1 1 1 2 X X AR1 60h 61h 61h 61h 62h 62h 63h XX XX ACC 20h 20h 20h 30h 30h 30h 33h 32h 32h [62h] 9h 9h 9h 9h 9h 9h 9h 9h 32h

Assume memory location 60h = 10h, 61h = 3h, and 62h = 9h. The following is the condition of the pipeline for each cycle. Cycle 1: Cycle 2: F) Fetch the ADD instruction and update PC to next instruction. F) Fetch the BCND instruction and update PC. D) Decode the ADD instruction and update AR1. Cycle 3: F) Fetch the second word LBL and update PC. D) Decode the BCND instruction and no ARAU update. R) Read data from data memory location 60h (10h) which is the location pointed at by AR1 before the update of cycle 2.
Pipeline
7-9

Pipeline Operation

Cycle 4:

F) Fetch the ADD instruction and update PC. D) Dummy operation (previous fetch phase is an operand). R) No operand read for the BCND instruction. E) Add data read in cycle 3 (10h) to data in ACC (20h) and store result in ACC (ACC = 30h).

The PC update and decode (D) phase on cycle 5 depends on the execute (E) phase result of the BCND instruction. Since the condition is false, the PC will update to point to the next instruction and BCND will be treated as 2-word instruction. Cycle 5: F) Fetch the SUB instruction and update PC. D) Decode the ADD instruction and update AR1. R) Dummy operation (operand fetch on fetch phase). E) Conditional testing. Cycle 6: F) Fetch the SACL instruction and update PC. D) Decode the SUB instruction and no ARAU update. R) Read data from data memory location 61h (3h) which is the location pointed at by AR1 before the update of cycle 5. E) Dummy operation (operand fetch on fetch phase). Cycle 7: F) Fetch the next instruction and update PC. D) Decode the SACL instruction, and update AR1 and ARP. R) No operand read for the SUB instruction. E) Add data read in cycle 6 (3h) to data in ACC (30h) and store result in ACC (ACC = 33h). Cycle 8: F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 7. R) No operand read for the SACL instruction. E) Subtract 1h from data in ACC (33h) and store result in ACC (ACC = 32h). Cycle 9: F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 8. R) Depends on the instruction fetched in cycle 7. E) Store data in ACC (32h) to data memory location 62h which is the location pointed at by AR1 before the update of cycle 7.
7-10

Pipeline Operation

Subroutine Call and Return Example 75. Pipeline Operation with Subroutine Call and Return
ADD CALL ADD SUB SACL . . LBL SUBB RET NOP NOP NOP . . *+ LBL *+ #1 *+,0,AR2

*+

Table 75. Pipeline Operation with Subroutine Call and Return

Pipeline operation Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PC [CALL] [LBL] [ADD] [SUB] LBL [RET] [NOP] [NOP] [NOP] [ADD] [SUB] [SACL] F ADD CALL LBL ADD SUB SUBB RET NOP NOP NOP ADD SUB SACL ADD CALL dummy dummy dummy SUBB RET dummy dummy dummy ADD SUB SACL ADD CALL dummy dummy dummy SUBB RET dummy dummy dummy ADD SUB SACL ADD CALL dummy dummy dummy SUBB RET dummy dummy dummy ADD SUB SACL D R E ARP 1 1 1 1 1 1 1 1 1 1 1 1 1 2 XX XX AR1 60h 61h 61h 61h 61h 61h 62h 62h 62h 62h 62h 63h 63h 64h XX XX ACC 20h 20h 20h 30h 30h 30h 30h 30h 2Dh 2Dh 2Dh 2Dh 2Dh 36h 35h 35h TOS XX XX XX XX [ADD] [ADD] [ADD] [ADD] [ADD] XX XX XX XX XX XX XX [63h] XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX 35h

Pipeline

7-11

Pipeline Operation

Assume memory location 60h = 10h, 61h = 3h, and 62h = 9h. The following is the condition of the pipeline for each cycle. Cycle 1: Cycle 2: F) Fetch the ADD instruction and update PC to next instruction. F) Fetch the CALL instruction and update PC. D) Decode the ADD instruction and update AR1. Cycle 3: F) Fetch the second word LBL and update PC. D) Decode the CALL instruction and no ARAU update. R) Read data from data memory location 60h (10h) which is the location pointed at by AR1 before the update of cycle 2. Cycle 4: F) Fetch the ADD instruction and update PC. D) Dummy operation (previous fetch phase is an operand). R) No operand read for the CALL instruction. E) Add data read in cycle 3 (10h) to data in ACC (20h) and store result in ACC (ACC = 30h). Cycle 5: F) Fetch the SUB instruction. PC will modify during the execution (E) phase. D) Dummy operation (flush the pipeline). R) Dummy operation (operand fetch on fetch phase). E) Push the address of ADD on top of stack (TOS). Update PC equal to LBL (ready to enter the subroutine). Cycle 6: F) Fetch the SUBB instruction and update PC. D) Dummy operation (flush the pipeline). R) Dummy operation (flush the pipeline). E) Dummy operation (operand fetch on fetch phase). Cycle 7: F) Fetch the RET instruction and update PC. D) Decode the SUBB instruction and update AR1. R) Dummy operation (flush the pipeline). E) Dummy operation (flush the pipeline). Cycle 8: F) Fetch the NOP instruction and update PC. D) Decode the RET instruction and no ARAU update. R) Read data from data memory location 61h (3h) which is the location pointed at by AR1 before the update of cycle 7. E) Dummy operation (flush the pipeline).
7-12

Pipeline Operation

Cycle 9:

F) Fetch the NOP instruction and update PC. D) Dummy operation (flush the pipeline). R) No operand read for the RET instruction. E) Subtract data read in cycle 8 (3h) from data in ACC (30h) and store result in ACC (ACC = 2Dh).

Cycle 10: F) Fetch the NOP instruction. PC will modify during the execute (E) phase. D) Dummy operation (flush the pipeline). R) Dummy operation (flush the pipeline). E) Pop the address from TOS to PC (ready to return from subroutine). Cycle 11: F) Fetch the ADD instruction and update PC. D) Dummy operation (flush the pipeline). R) Dummy operation (flush the pipeline). E) Dummy operation (flush the pipeline). Cycle 12: F) Fetch the SUB instruction and update PC. D) Decode the ADD instruction and update AR1. R) Dummy operation (flush the pipeline). E) Dummy operation (flush the pipeline). Cycle 13: F) Fetch the SACL instruction and update PC. D) Decode the SUB instruction and no ARAU update. R) Read data from data memory location 62h (9h) which is the location pointed at by AR1 before the update of cycle 12. E) Dummy operation (flush the pipeline). Cycle 14: F) Fetch the next instruction and update PC. D) Decode the SACL instruction, and update AR1 and ARP. R) No operand read for the SUB instruction. E) Add data read in cycle 13 (9h) to data in ACC (2Dh) and store result in ACC (ACC = 36h). Cycle 15: F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 14. R) No operand read for the SACL instruction. E) Subtract 1h from data in ACC (36h) and store result in ACC (ACC = 35h).
Pipeline
7-13

Pipeline Operation

Cycle 16: F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 15. R) Depends on the instruction fetched in cycle 14. E) Store data in ACC (35h) to data memory location 63h which is the location pointed at by AR1 before the update of cycle 14.

7.2.3

Pipeline Operation on ARAU Memory-Mapped Registers

Auxiliary register arithmetic unit (ARAU) updates of the ARs occur during the decode (D) phase of the pipeline. This allows the address to be generated before the operand read (R) phase. However, memory-mapped accesses (for example, SAMM, LMMR, SACL, or SPLK) to the ARs occur in the execute (E) phase of the pipeline. Therefore, the use of ARs for the next two instructions after a memory-mapped load of the AR is prohibited. This means that the next two instructions after a memory-mapped load of the AR should not use this AR. Modifications to the index register (INDX) and auxiliary register compare register (ARCR) also occur in the execute (E) phase of the pipeline. Therefore, any AR updates using the INDX or the ARCR must take place at least two cycles after a load of these registers. Example 76, Example 77, and Example 78 show the effects of a memory-mapped write to an auxiliary register.

Example 76. Pipeline Operation with ARx Load

LAR AR2,#67h LACC #64h SAMM AR2 LACC * ADD * . .

7-14

Pipeline Operation

Table 76. Pipeline Operation with ARx Load

Pipeline operation Cycle 1 2 3 4 5 6 7 8 9 PC [LACC] [#64h] [SAMM] [LACC] [ADD] LAR LACC 64h SAMM LACC ADD LAR LACC dummy SAMM LACC ADD LAR LACC dummy SAMM LACC ADD LAR LACC dummy SAMM LACC ADD F D R E ARP 2 2 2 2 2 2 2 2 2 AR2 XX XX XX 67h 67h 66h 64h 64h 64h ACC XX XX XX XX 64h 64h 64h 50h 90h

Assume memory location 65h = 30h, 66h = 40h, and 67h = 50h. The following is the condition of the pipeline for each cycle. Cycle 1: Cycle 2: F) Fetch the LAR instruction and update PC to next instruction. F) Fetch the LACC instruction and update PC. D) Decode the LAR instruction and no ARAU update. Cycle 3: F) Fetch the second word 64h and update PC. D) Decode the LACC instruction and no ARAU update. R) No operand read for the LAR instruction. Cycle 4: F) Fetch the SAMM instruction and update PC. D) Dummy operation (previous fetch phase is an operand). R) No operand read for the LACC instruction. E) Load AR2 with 67h. Cycle 5: F) Fetch the LACC instruction and update PC. D) Decode the SAMM instruction and no ARAU update. R) Dummy operation (operand fetch on fetch phase). E) Load ACC with 64h. Cycle 6: F) Fetch the ADD instruction and update PC. D) Decode the LACC instruction and update AR2. R) No operand read for the SAMM instruction. E) Dummy operation (operand fetch on fetch phase).
Pipeline
7-15

Pipeline Operation

Cycle 7:

F) Fetch the next instruction and update PC. D) Decode the ADD instruction and update AR2. R) Read data from data memory location 67h (50h) which is the location pointed at by AR2 before the update of cycle 6. E) Store data in ACC (64h) to AR2. This conflicts with decode (D) phase.

Cycle 8:

F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 7. R) Read data from data memory location 66h (40h) which is the location pointed at by AR2 before the update of cycle 7. E) Load ACC with data read in cycle 7 (ACC = 50h).

Cycle 9:

F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 8. R) Depends on the instruction fetched in cycle 7. E) Add data read in cycle 8 (40h) to data in ACC (50h) and store result in ACC (ACC = 90h).

Example 77. Pipeline Operation with ARx Load and NOP Instruction
LAR AR2,#67h LACC #64h SAMM AR2 LACC * NOP ADD * . .

7-16

Pipeline Operation

Table 77. Pipeline Operation with ARx Load and NOP Instruction
Pipeline operation Cycle 1 2 3 4 5 6 7 8 9 10 PC [LACC] [#64h] [SAMM] [LACC] [NOP] [ADD] LAR LACC 64h SAMM LACC NOP ADD LAR LACC dummy SAMM LACC dummy ADD LAR LACC dummy SAMM LACC dummy ADD LAR LACC dummy SAMM LACC dummy ADD F D R E ARP 2 2 2 2 2 2 2 2 2 2 AR2 XX XX XX 67h 67h 66h 64h 63h 63h 63h ACC XX XX XX XX 64h 64h 64h 64h 50h 70h

Assume memory location 63h = 10h, 64h = 20h, 65h = 30h, 66h = 40h, and 67h = 50h. The following is the condition of the pipeline for each cycle. Cycle 1: Cycle 2: F) Fetch the LAR instruction and update PC to next instruction. F) Fetch the LACC instruction and update PC. D) Decode the LAR instruction and no ARAU update. Cycle 3: F) Fetch the second word 64h and update PC. D) Decode the LACC instruction and no ARAU update. R) No operand read for the LAR instruction. Cycle 4: F) Fetch the SAMM instruction and update PC. D) Dummy operation (previous fetch (F) phase is an operand). R) No operand read for the LACC instruction. E) Load AR2 with 67h. Cycle 5: F) Fetch the LACC instruction and update PC. D) Decode the SAMM instruction and no ARAU update. R) Dummy operation (operand fetch on fetch phase). E) Load ACC with 64h.
Pipeline
7-17

Pipeline Operation

Cycle 6:

F) Fetch the NOP instruction and update PC. D) Decode the LACC instruction and update AR2. R) No operand read for the SAMM instruction. E) Dummy operation (operand fetch on fetch phase).

Cycle 7:

F) Fetch the ADD instruction and update PC. D) Dummy operation (flush the pipeline). R) Read data from data memory location 67h (50h) which is the location pointed at by AR2 before the update of cycle 6. E) Store data in ACC to AR2 (AR2 = 64h).

Cycle 8:

F) Fetch the next instruction and update PC. D) Decode the ADD instruction and update AR2. R) Dummy operation (flush the pipeline). E) Load ACC with data read in cycle 7 (ACC = 50h).

Cycle 9:

F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 8. R) Read data from data memory location 64h (20h) which is the location pointed at by AR2 before the update of cycle 8. E) Dummy operation (flush the pipeline).

Cycle 10: F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 9. R) Depends on the instruction fetched in cycle 8. E) Add data read in cycle 9 (20h) to data in ACC (50h) and store result in ACC (ACC = 70h).

Example 78. Pipeline Operation with ARx Load and NOP Instructions
LAR AR2,#67h LACC #64h SAMM AR2 NOP NOP LACC * ADD * . .

7-18

Pipeline Operation

Table 78. Pipeline Operation with ARx Load and NOP Instructions
Pipeline operation Cycle 1 2 3 4 5 6 7 8 9 10 11 PC [LACC] [#64h] [SAMM] [NOP] [NOP] [LACC] [ADD] LAR LACC 64h SAMM NOP NOP LACC ADD LAR LACC dummy SAMM dummy dummy LACC ADD LAR LACC dummy SAMM dummy dummy LACC ADD LAR LACC dummy SAMM dummy dummy LACC ADD F D R E ARP 2 2 2 2 2 2 2 2 2 2 2 AR2 XX XX XX 67h 67h 67h 64h 63h 62h 62h 62h ACC XX XX XX XX 64h 64h 64h 64h 64h 20h 30h

Assume memory location 63h = 10h, 64h = 20h, 65h = 30h, 66h = 40h, and 67h = 50h. The following is the condition of the pipeline for each cycle. Cycle 1: Cycle 2: F) Fetch the LAR instruction and update PC to next instruction. F) Fetch the LACC instruction and update PC. D) Decode the LAR instruction and no ARAU update. Cycle 3: F) Fetch the second word 64h and update PC. D) Decode the LACC instruction and no ARAU update. R) No operand read for the LAR instruction. Cycle 4: F) Fetch the SAMM instruction and update PC. D) Dummy operation (previous fetch (F) phase is an operand). R) No operand read for the LACC instruction. E) Load AR2 with 67h. Cycle 5: F) Fetch the NOP instruction and update PC. D) Decode the SAMM instruction and no ARAU update. R) Dummy operation (operand fetch on fetch phase). E) Load ACC with 64h.
Pipeline
7-19

Pipeline Operation

Cycle 6:

F) Fetch the NOP instruction and update PC. D) Dummy operation (flush the pipeline). R) No operand read for the SAMM instruction. E) Dummy operation (operand fetch on fetch phase).

Cycle 7:

F) Fetch the LACC instruction and update PC. D) Dummy operation (flush the pipeline). R) Dummy operation (flush the pipeline). E) Store data in ACC to AR2 (AR2 = 64h).

Cycle 8:

F) Fetch the ADD instruction and update PC. D) Decode the LACC instruction and update AR2. R) Dummy operation (flush the pipeline). E) Dummy operation (flush the pipeline).

Cycle 9:

F) Fetch the next instruction and update PC. D) Decode the ADD instruction and update AR2. R) Read data from data memory location 64h (20h) which is the location pointed at by AR2 before the update of cycle 8. E) Dummy operation (flush the pipeline).

Cycle 10: F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 9. R) Read data from data memory location 63h (10h) which is the location pointed at by AR2 before the update of cycle 9. E) Load ACC with data read in cycle 9 (ACC = 20h). Cycle 11: F) Fetch the next instruction and update PC. D) Decode the instruction fetched in cycle 10. R) Depends on the instruction fetched in cycle 9. E) Add data read in cycle 10 (10h) to data in ACC (20h) and store result in ACC (ACC = 30h).

7-20

Pipeline Operation

7.2.4

Pipeline Operation on External Memory Conflict

Since the C5x only has one set of external address and data buses, a bus conflict occurs between instruction fetch (F), operand read (R), and execute (E) write phases if both program and data memory are external. While the bus conflict is occurring, a dummy operation can be inserted to eliminate the bus conflict. Example 79 shows pipeline operation with a bus conflict and a dummy operation. In Example 79, assume there is no bus conflict between the LACC instruction and the previous instructions. In the operand read (R) phase of LACC, a bus conflict occurs with the fetch of SACL. Therefore, a dummy fetch operation is inserted. In the next fetch (F) phase, the SACL has a bus conflict with the ADD operand read (R) phase. Therefore, the fetch of SACL is delayed again one cycle. Two dummy instruction fetches are inserted between ADD and SACL due to this delay. A similar situation occurred in the execute (E) phase of SACL. Since external memory writes take 3 cycles, during the execution of SACL any instruction fetch or operand read access on the external bus will be delayed for 3 cycles.

Example 79. Pipeline Operation with External Bus Conflicts

LACC ADD SACL NOP . . *+ *+ *+, AR2

Table 79. Pipeline Operation with External Bus Conflicts

Pipeline operation Cycle 1 2 3 4 5 6 7 8 9 PC [ADD] [SACL] [SACL] [SACL] NOP F LACC ADD dummy dummy SACL NOP LACC ADD dummy dummy SACL dummy LACC ADD dummy dummy SACL dummy LACC ADD dummy dummy SACL dummy D R E ARP 1 1 1 1 1 2 2 2 2 AR1 800h 801h 802h 802h 802h 803h 803h 803h 803h AR2 803h 803h 803h 803h 803h 803h 802h 802h 802h ACC XX XX XX 10h 13h 13h 13h 13h 13h [802h] FFh FFh FFh FFh FFh FFh FFh 13h 13h

Pipeline

7-21

Pipeline Operation

Assume memory location 800h = 10h, 801h = 3h, 802h = FFh, and 803h = 6h. The following is the condition of the pipeline for each cycle. Cycle 1: Cycle 2: F) Fetch the LACC instruction and update PC to next instruction. F) Fetch the ADD instruction and update PC. D) Decode the LACC instruction and update AR1. Cycle 3: F) Since the read (R) phase occupies the external bus, insert a dummy operation and no update on PC. D) Decode the ADD instruction and update AR1. R) External data read for the LACC instruction from data memory location 800h (10h) which is the location pointed at by AR1 before the update of cycle 2. Cycle 4: F) Since the read (R) phase occupies the external bus, insert a dummy operation and no update on PC. D) Dummy operation from previous fetch phase. R) External data read for the ADD instruction from data memory location 801h (3h) which is the location pointed at by AR1 before the update of cycle 3. E) Load ACC with data read in cycle 3 (ACC = 10h). Cycle 5: F) Fetch the SACL instruction and update PC. D) Dummy operation from previous fetch phase. R) Dummy operation from previous decode phase. E) Add data read in cycle 4 (3h) to data in ACC (10h) and store result in ACC (ACC = 13h). Cycle 6: F) Fetch the NOP instruction and update PC. D) Decode the SACL instruction, and update ARP and AR1. R) Dummy operation from previous decode (D) phase. E) Dummy operation from previous read (R) phase. Cycle 7: F) Fetch the next instruction and update PC. D) Dummy operation (flush the pipeline). R) No operand read for the SACL instruction. E) Dummy operation from previous read (R) phase. Cycle 8: F) Since the execute (E) phase occupies the external bus and takes 3 cycles for an external write, insert a dummy operation in the next 3 fetch (F) phases and no update on PC. D) Decode instruction fetched in cycle 7.
7-22

Pipeline Operation

R) Dummy operation (flush the pipeline). E) Store data in ACC (13h) to external data memory location 802h which is the location pointed at by AR1 before the update of cycle 6. Cycle 9: F) Dummy operation and no update on PC. D) Dummy operation from previous fetch (F) phase. R) Depends on the instruction fetched in cycle 7. E) Dummy operation (flush the pipeline).

Pipeline

7-23

Pipeline Latency

7.3 Pipeline Latency

Memory-mapped registers are accessed by C5x instructions in the decode (D) and operand fetch (F) phases of the pipeline. The pipeline operation previously described requires writes to memory-mapped registers, however, latency occurs while accessing and writing to the registers. Table 710 outlines the latency required between an instruction that writes to the register via its memory-mapped address and the access of that register by subsequent instructions. Note that all direct accesses to the registers that do not use memory-mapped addressing (such as all C2x-compatible instructions: LAR, LT) are pipeline-protected (stalled) and, therefore, do not cause any latency. The current AR is affected by the NORM instruction during its execute (E) phase of the pipeline. Similar pipeline management, as described above, works in this case. The -p option of the assembler detects an AR update or store (SAR) directly after a NORM instruction and inserts NOP instructions automatically to maintain source-code compatibility with the C2x.

Table 710. Latencies Required

Register ARx ARCR BMAR CBCR CBER CBSR CWSR GREG INDX IOWSR PDWSR PMST ST1 TREG1 TREG2 Description Auxiliary registers 07 Auxiliary register compare register Block move address register Circular buffer control register Circular buffer end registers 1 and 2 Circular buffer start registers 1 and 2 Wait-state control register Global memory allocation register Index register I/O port wait-state register Program/data wait-state register Processor mode status register Configuration control (CNF) bit in ST1 Dynamic shift count Dynamic bit address Words 2 2 1 2 2 2 1 1 2 1 1 2 2 1 1 Affects Next word uses previous value; second word update gets over written Next 2 words use previous value Next 1 word uses previous value Next 2 words cannot be end of buffer Next 2 words cannot be end of buffer Next 2 words use previous value Next 1 word uses previous modes Next 1 word uses previous map Next 2 words use previous value Next 1 word uses previous count Next 1 word uses previous count Next 2 words use previous map Next 2 words use previous map Next 1 word uses old shift count Next 1 word uses old bit address

7-24

Pipeline Latency

The C5x core CPU supports reconfiguration of memory segments (internal and external) during the execute (E) phase of the pipeline. Therefore, before an instruction utilizes the new configuration, at least two instruction words should follow the instruction that reconfigures memory. In the following example, assume the current AR = 0200h and RAMB0 (0) = 1.
CLRC LACC ADD CNF #01234h * ;Map RAM B0 to data space. ;ACC = 00001234. ;ACC = 00001235.

Notice the use of the LACC #01234h to fill the 2-word requirement. Because a long-immediate operand is used, this is a 2-word instruction and, therefore, meets the requirement. This also applies to memory configurations controlled by the PMST.

If the main code is running in the B0 block (CNF = 1) and an interrupt service routine not in B0 changes CNF to 0, a RETE will not restore CNF in time to fetch the next instruction from the B0 block. Therefore, in the interrupt service routine, the CNF bit should be set at least 2 words before the RETE.

Pipeline

7-25

Chapter 8

Memory
The total memory address range of the C5x devices is 224K 16-bit words. The memory space is divided into four individually-selectable memory segments:
-

64K-word program 64K-word local data 64K-word input/output (I/O) ports 32K-word global data

Their parallel architecture lets the C5x devices perform three concurrent memory operations in any given machine cycle: fetching an instruction, reading an operand, and writing an operand. This chapter discusses C5x memory configuration and operation.

Topic
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9

Page
Memory Space Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Local Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Global Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 Input/Output (I/O) Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26 Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 External Parallel Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39

8.10 Software Wait-State Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42

8-1

Memory Space Overview

8.1 Memory Space Overview

The C5x design is based on the enhanced Harvard architecture, which has multiple memory spaces that can be accessed on two parallel buses. This makes it possible to access both program and data simultaneously. The two parallel buses are the program bus (PB) and data read bus (DB). Each bus accesses different memory spaces for different aspects of the device operation. The C5x memory is organized into four individually selectable spaces: program memory, local data memory, global data memory, and I/O ports. These memory spaces compose an address range of 224K words. Within any of these spaces, RAM, ROM, EPROM, EEPROM, or memory-mapped peripherals can reside either on- or off-chip. The 64K-word program space contains the instructions to be executed. The 64K-word local data space stores data used by the instructions. The 32K-word global data space can share data with other processors within the system or can serve as additional data space. The 64K-word I/O port space interfaces to external memory-mapped peripherals and can also serve as extra data storage space. Within a given machine cycle, the ALU can execute as many as three concurrent memory operations. The large on-chip memory of the C5x devices enhances system performance and integration. This on-chip memory includes ROM in program space, singleaccess RAM (SARAM) in program and/or data space, and dual-access RAM (DARAM) in program and/or data space. The amount and types of memory available on each device are listed in Table 11. All C5x devices have 1056 words of DARAM configured in three blocks and mapped at the same addresses: block 0 (B0) has 512 words at address 0100h02FFh in local data memory or FE00hFFFFh in program space; block 1 (B1) has 512 words at address 0300h04FFh in local data memory; and block 2 (B2) has 32 words at address 0060h007Fh in local data memory. The DARAM can be read from and written to in the same machine cycle. The C5x devices have different sizes of SARAM (see Table 11) which is divided into 2K-word and 1K-word blocks that are contiguous in program or data memory space. The SARAM requires a full machine cycle to perform a read or a write. However, the CPU can read or write one block while accessing another block during the same machine cycle. The C5x devices have different sizes of ROM in program space (see Table 11 on page 1-6). This ROM could be maskable ROM or boot ROM. The boot ROM resides in program space at address 0000h and includes a device test (for internal use) and boot code. The maskable ROM is also located in the lowest block of program memory. The ROM is enabled or disabled by the state
8-2

Memory Space Overview

of the MP/MC pin control input at reset, or by manipulating the MP/MC bit in the processor mode status register (PMST) after reset. The C50 (Figure 81) includes 2K words of boot ROM, 9K words program/ data SARAM, and 1056 words of DARAM. The boot ROM resides in program space at address range 0000h07FFh. The 9K words of SARAM can be mapped into program or data space and reside at address range 0800h2BFFh in either space. The C51 (Figure 82) removes the 2K-word boot ROM from program memory space and replaces 8K words of program/data SARAM with an 8K-word block of maskable ROM. The C51 also includes 1K word of program/data SARAM and 1056 words of DARAM. The 8K words of ROM reside in program space at address range 0000h1FFFh. The 1K word of SARAM can be mapped into data space (address range 0800h0BFFh), program space (address range 2000h23FFh), or both spaces. The C52 (Figure 83) includes 4K words of maskable ROM and 1056 words of DARAM. No program/data SARAM is available on the C52. The 4K words of ROM reside in program space at address range 0000h0FFFh. The C53 and C53S (Figure 84) include 16K words of maskable ROM, 3K words of program/data SARAM, and 1056 words of DARAM. The 16K words of ROM reside in program space at address range 0000h3FFFh. The 3K words of SARAM can be mapped into data space (address range 080013FFh), program space (address range 4000h4BFFh), or both spaces. The LC56 and LC57 (Figure 85) include 32K words of maskable ROM, 6K words of program/data SARAM, and 1056 words of DARAM. The 32K words of ROM reside in program space at address range 0000h7FFFh. The 6K words of SARAM can be mapped into data space (address range 08001FFFh), program space (address range 8000h97FFh), or both spaces. The C57S (Figure 86) includes 2K words of boot ROM, 6K words of program/ data SARAM, and 1056 words of DARAM. The boot ROM resides in program space at address range 0000h07FFh. The 6K words of SARAM can be mapped into data space (address range 08001FFFh), program space (address range 8000h97FFh), or both spaces.

Memory

8-3

Memory Space Overview

Figure 81. C50 Memory Map

Program 0000h 0040h Interrupt vectors Off-chip 0000h If MP/MC = 0, (Microcomputer mode) 2K-word on-chip ROM 0060h 0080h 0100h Data Memory-mapped registers On-chip DARAM B2

0800h

9K-word On-chip SARAM (RAM bit = 1) Off-chip (RAM bit = 0)

0300h 0500h

FE00h FFFFh

Figure 82. C51 Memory Map

Program 0000h 0040h Interrupt vectors 0000h If MP/MC = 0, (Microcomputer mode) 8K-word on-chip ROM 0060h 0080h 0100h

2000h

1K-word On-chip SARAM (RAM bit = 1) Off-chip (RAM bit = 0)

0300h 0500h

2400h

Off-chip

0800h

FE00h FFFFh

0C00h

On-chip DARAM B0 (CNF = 1) Off-chip (CNF = 0)

FFFFh

MP/MC = 1 (Microprocessor mode)

8-4

Off-chip On-chip DARAM B0 (CNF = 1) Off-chip (CNF = 0) MP/MC = 1 (Microprocessor mode)

2C00h

0800h

2C00h

FFFFh

Off-chip

Reserved On-chip DARAM B0 (CNF = 0) Reserved (CNF = 1) On-chip DARAM B1 Reserved 9K-word On-chip SARAM (OVLY = 1) Off-chip (OVLY = 0) Off-chip Data Memory-mapped registers On-chip DARAM B2 Reserved On-chip DARAM B0 (CN F= 0) Reserved (CNF = 1) On-chip DARAM B1 Reserved 1K-word On-chip SARAM (OVLY = 1) Off-chip (OVLY = 0) Off-chip

Memory Space Overview

Figure 83. C52 Memory Map

Program 0000h 0040h Interrupt vectors Off-chip 0000h If MP/MC = 0, (Microcomputer mode) 4K-word on-chip ROM 0060h 0080h 0100h Data Memory-mapped registers On-chip DARAM B2 Reserved

1000h

0300h 0500h

Off-chip

0800h

FE00h FFFFh

On-chip DARAM B0 (CNF = 1) Off-chip (CNF = 0)

FFFFh

MP/MC = 1 (Microprocessor mode)

Figure 84. C53 and C53S Memory Map

Program 0000h 0040h Interrupt vectors Off-chip

0000h If MP/MC = 0, (Microcomputer mode) 16K-word on-chip ROM 0060h 0080h 0100h

4000h

3K-word On-chip SARAM (RAM bit = 1) Off-chip (RAM bit = 0)

0300h 0500h

4C00h

Off-chip

0800h

FE00h FFFFh

1400h

On-chip DARAM B0 (CNF = 1) Off-chip (CNF = 0)

FFFFh

MP/MC = 1 (Microprocessor mode)

On-chip DARAM B0 (CNF = 0) Reserved (CNF = 1) On-chip DARAM B1 Reserved Off-chip Data Memory-mapped registers On-chip DARAM B2 Reserved

On-chip DARAM B0 (CNF = 0) Reserved (CNF = 1) On-chip DARAM B1 Reserved

3K-word On-chip SARAM (OVLY = 1) Off-chip (OVLY = 0) Off-chip

Memory

8-5

Memory Space Overview

Figure 85. LC56 and LC57 Memory Map

Program 0000h 0040h Interrupt vectors Off-chip 0000h If MP/MC = 0, (Microcomputer mode) 32K-word on-chip ROM 0060h 0080h 0100h Data Memory-mapped registers On-chip DARAM B2

8000h

6K-word On-chip SARAM (RAM bit = 1) Off-chip (RAM bit = 0)

0300h 0500h

FE00h FFFFh

Figure 86. C57S Memory Map

Program 0000h 0040h Interrupt vectors Reserved 0000h If MP/MC = 0, (Microcomputer mode) 2K-word on-chip ROM 0060h 0080h 0100h

8000h

6K-word On-chip SARAM (RAM bit = 1) Off-chip (RAM bit = 0)

0300h 0500h

9800h

Off-chip

0800h

FE00h FFFFh

2000h

On-chip DARAM B0 (CNF = 1) Off-chip (CNF = 0)

FFFFh

MP/MC = 1 (Microprocessor mode)

8-6

Off-chip On-chip DARAM B0 (CNF = 1) Off-chip (CNF = 0) MP/MC = 1 (Microprocessor mode)

9800h

0800h

2000h

FFFFh

Reserved On-chip DARAM B0 (CNF = 0) Reserved (CNF = 1) On-chip DARAM B1 Reserved 6K-word On-chip SARAM (OVLY = 1) Off-chip (OVLY = 0) Off-chip Data Memory-mapped registers On-chip DARAM B2 Reserved On-chip DARAM B0 (CNF = 0) Reserved (CNF = 1) On-chip DARAM B1 Reserved 6K-word On-chip SARAM (OVLY = 1) Off-chip (OVLY = 0) Off-chip

Program Memory

8.2 Program Memory

The program memory space addresses up to 64K 16-bit words and includes on-chip ROM in program space, SARAM (except in C52) in program and/or data space, and DARAM in program and/or data space. The amount and types of memory available on each device are listed in Table 11 on page 1-6. Software can configure these memory cells to reside inside (on-chip) or outside (off-chip) of the program address map. When the memory cells are mapped into program space, the C5x automatically accesses them when it addresses within their bounds. When the CALU generates an address outside these bounds, the C5x automatically generates an external (off-chip) access. These are the advantages of operating from internal (on-chip) memory: 1) Higher performance because no wait states are required for slower external memories. 2) Lower cost than external memory. 3) Lower power than external memory. The advantage of operating from external (off-chip) memory is the ability to access a larger address space.

8.2.1

Program Memory Configurability

The program memory can reside both on- and off-chip. At reset, the C5x device configuration is set by the level on the MP/MC pin. If this pin is high, the device is configured as a microprocessor, and the on-chip ROM is not addressed. If this pin is low, the device is configured as a microcomputer, and the on-chip ROM is enabled. The C5x devices fetch their reset vector in program memory at address location 0000h; so, if the device is operating as a microcomputer, it starts running from on-chip ROM. If the device is operating as a microprocessor, it starts running from off-chip memory. Once the program is running, the device configuration can be changed by setting or clearing the MP/MC bit in the PMST. Note that the MP/MC pin is sampled only at reset. The following instruction removes the ROM from program space by setting the MP/MC bit in the PMST to 1:
OPL#8,PMST ;Remove boot ROM from program space.

Code can be submitted to be masked into the on-chip ROM for C51, C52, C53, C56, and C57 devices. The process-masked ROM cell requires ROM codes to be submitted to Texas Instruments for implementation in the device, as detailed in Appendix F, Submitting ROM Codes to TI.
Memory
8-7

Program Memory

At reset, the SARAM and the 512-word DARAM block B0 are not resident in program space. You make the SARAM resident in program space by setting the RAM bit in the PMST. When the RAM bit is set, the RAM cells become addressable in program space. You make the DARAM block B0 resident in program space (address range FE00hFFFFh) by setting the CNF bit in the ST1. The following instructions map the SARAM and DARAM blocks into program space by setting the appropriate bit in the registers:
OPL SETC #010h,PMST CNF ;Map C5x single-access memory ;in program space. ;Map B0 to program space.

Table 81 through Table 86 show program memory configurations available on the C5x devices. Note that all addresses are specified in hexadecimal.

Table 81. C50 Program Memory Configuration

Bit values RAM 0 0 1 1 0 0 1 1 CNF 0 0 0 0 1 1 1 1 MP/MC 0 1 0 1 0 1 0 1 ROM (2K-words) 000007FF Off-chip SARAM (9K-words) Off-chip Off-chip DARAM B0 (512-words) Off-chip Off-chip Off-chip Off-chip Off-Chip 0800FFFF 0000FFFF 000007FF Off-chip 08002BFF 08002BFF Off-chip Off-chip 2C00FFFF 000007FF, 2C00FFFF 0800FDFF 0000FDFF 000007FF Off-chip FE00FFFF FE00FFFF FE00FFFF FE00FFFF 000007FF Off-chip 08002BFF 08002BFF 2C00FDFF 000007FF, 2C00FDFF 8-8


Legend:

Table 83. C52 Program Memory Configuration

Table 82. C51 Program Memory Configuration

CNF

CNF

Bit values

Bit values

RAM

RAM

Dont care condition

MP/MC

MP/MC

Off-chip

00000FFF

Off-chip

00000FFF

ROM (4K-words)

Off-chip

00001FFF

Off-chip

00001FFF

Off-chip

00001FFF

Off-chip

00001FFF

ROM (8K-words)

None

None

None

None

SARAM

200023FF

200023FF

Off-chip

Off-chip

200023FF

200023FF

Off-chip

Off-chip

SARAM (1K-words)

FE00FFFF

FE00FFFF

Off-chip

Off-chip

DARAM B0 (512-words)

FE00FFFF

FE00FFFF

FE00FFFF

FE00FFFF

Off-chip

Off-chip

Off-chip

Off-chip

DARAM B0 (512-words)

Memory
0000FDFF 1000FDFF 0000FFFF 1000FFFF Off-Chip 00001FFF, 2400FDFF 2400FDFF 0000FDFF 2000FDFF 00001FFF, 2400FFFF 2400FFFF 0000FFFF 2000FFFF Off-Chip

Program Memory

8-9


Program Memory

8-10

Table 85. LC56 and LC57 Program Memory Configuration

Table 84. C53 and C53S Program Memory Configuration

CNF

CNF

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

Bit values

Bit values

RAM

RAM

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

MP/MC

MP/MC

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

Off-chip Off-chip Off-chip Off-chip Off-chip Off-chip Off-chip Off-chip

00007FFF 00007FFF 00007FFF 00007FFF 00003FFF 00003FFF 00003FFF 00003FFF

ROM (32K-words)

ROM (16K-words)

800097FF 800097FF Off-chip Off-chip 800097FF 800097FF Off-chip Off-chip Off-chip Off-chip Off-chip Off-chip

SARAM (6K-words)

40004BFF

40004BFF

40004BFF

40004BFF

SARAM (3K-words)

FE00FFFF FE00FFFF FE00FFFF FE00FFFF Off-chip Off-chip Off-chip Off-chip FE00FFFF FE00FFFF FE00FFFF FE00FFFF Off-chip Off-chip Off-chip Off-chip

DARAM B0 (512-words)

DARAM B0 (512-words)

00007FFF, 9800FDFF 9800FDFF 0000FDFF 8000FDFF 00007FFF, 9800FFFF 9800FFFF 0000FFFF 8000FFFF Off-Chip Off-Chip 0000FFFF 4000FFFF 0000FDFF 4000FDFF

00003FFF, 4C00FDFF 4C00FDFF 00003FFF, 4C00FFFF 4C00FFFF

Program Memory

Table 86. C57S Program Memory Configuration

Bit values RAM 0 0 1 1 0 0 1 1 CNF 0 0 0 0 1 1 1 1 MP/MC 0 1 0 1 0 1 0 1 ROM (2K-words) 000007FF Off-chip SARAM (6K-words) Off-chip Off-chip DARAM B0 (512-words) Off-chip Off-chip Off-chip Off-chip Off-Chip 8000FFFF 0000FFFF 9800FFFF 000007FF Off-chip 800097FF 800097FF Off-chip Off-chip 00007FFF, 9800FFFF 000007FF Off-chip FE00FFFF FE00FFFF FE00FFFF FE00FFFF 8000FDFF 0000FDFF 9800FDFF 00007FFF, 9800FDFF 000007FF Off-chip 800097FF 800097FF

8.2.2

Program Memory Address Map

The interrupt vectors are addressed in program space. These vectors are soft meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes code at the vector location. Two words are reserved at each vector location for a branch instruction to the appropriate interrupt service routine (ISR). Table 87 lists the interrupt vector addresses after reset. At reset, the interrupt vector is mapped absolutely to address 0000h in program space. However, the interrupt vector can be remapped to the beginning of any 2K-word page in program space after reset. To do this, load the interrupt vector pointer (IPTR) bits in the PMST with the appropriate 2K-word page boundary address. After IPTR is loaded, any user interrupt vector is mapped to the new 2K-word page. For example:
OPL#05800h,PMST ;Remap vectors to start at 5800h.

In this example, the interrupt vectors move to off-chip program space beginning at address 5800h. Any subsequent interrupt (except for a reset) will fetch its interrupt vector from that new location. For example, if, after loading the IPTR, an INT2 occurs, the interrupt service routine vector will be fetched from address 5804h in program space as opposed to address 0004h. This feature lets you move the desired vectors out of the boot ROM and then remove the ROM from the memory map. Once the system code is booted into the system from the boot-loader code resident in ROM, the application reloads the IPTR
Memory
8-11


RINT2 on C52; BRNT on C56/C57 XINT2 on C52; BXNT on C56/C57

8-12

Program Memory

Table 87. C5x Interrupt Vector Addresses

RS

NMI

TRAP

HINT

INT4

TXNT

TRNT{

XINT

RINT

TINT

INT3

INT2

INT1

Name

4063 3839 2633 2023 Dec 36 34 24 18 16 14 12 10 8 6 4 2 0

Location

with a value pointing to the new vectors. In the above example, the OPL instruction is used to modify the IPTR bits in the PMST. This example assumes that the IPTR bits are currently cleared. To assure that the correct value for IPTR is set, the bits must be cleared before this instruction is executed.

The reset vector can not be remapped, because reset loads the IPTR with 0. Therefore, the reset vector will always be fetched at location 0000h in program memory. In addition, for the C51 and C53, 100 words are reserved in the on-chip ROM for device-testing purposes. Application code written to be implemented in on-chip ROM must reserve these 100 words at the top of the ROM addresses.

Note:

1A21

283F 2627 1417 Hex 24 22 18 12 10 C E A 8 6 4 2 0

1 (highest)

Priority

N/A N/A N/A N/A N/A 10 11 2 9 8 7 6 5 4 3

Software interrupts Reserved HINT (C57 only) Reserved Function

Reserved for emulation and test Nonmaskable interrupt Internal timer interrupt Software trap instruction External user interrupt #4 External user interrupt #3 External user interrupt #2 External user interrupt #1 TDM port transmit interrupt TDM port receive interrupt Serial port transmit interrupt Serial port receive interrupt

External nonmaskable reset signal

Program Memory

8.2.3

Program Memory Addressing

The program memory space contains the code for applications. It can also hold table information and immediate operands. The program memory is accessed only by the PAB. The address for this bus is generated by the PC when instructions and long immediate operands are accessed. The PAB can also be loaded with long immediate, low accumulator, or registered addresses for block transfers, multiply/accumulates, and table read/writes. The C5x fetches instructions by putting the PC on the PAB and reading the appropriate location in program memory. While the read is executing, the PC is incremented for the next fetch. If there is a program address discontinuity (for example, branch, call, return, interrupt, or block repeat), the appropriate address is loaded into the PC. The PC is also loaded when operands are fetched from program memory, which occurs when the device reads from (TBLR) or writes to (TBLW) tables, when it transfers data to (BLPD) or from (BLDP) data space, or when it uses the program bus to fetch a second multiplicand (MAC, MACD, MADS, and MADD). See Section 4.1, Program Counter (PC), on page 4-2. The data used as instruction operands is obtained in one of the following addressing modes:
-

The direct addressing mode The indirect addressing mode The short immediate addressing mode The long immediate addressing mode The dedicated-register addressing mode The memory-mapped register addressing mode

Refer to Chapter 5, Addressing Modes, for a discussion about the addressing modes.

Address Visibility
The address visibility (AVIS) feature can trace the address flow of a program externally and can be used for debugging during program development. It is enabled after reset and can be disabled by setting the AVIS bit in the PMST and enable it by clearing the AVIS bit. The address visibility mode sends the program address out to the address pins of the device, even when on-chip program memory is addressed. Note that the memory control signals (PS, RD, etc.) are not active in this mode.
Memory
8-13

Program Memory

Instruction addresses can be externally clocked with the falling edge of the instruction acquisition (IAQ) pin (refer to the TMS320C5x data sheet for IAQ timings). These instruction addresses include both words of a 2-word instruction but do not include block transfers, table reads, or multiply/accumulate operands. The address visibility mode also allows a specific interrupt trap to be decoded in conjunction with the interrupt acknowledge (IACK) pin. While IACK is low, address pins A1A4 can be decoded to identify which interrupt is being acknowledged (refer to the TMS320C5x data sheet for IACK timings). Once the system is debugged, you can disable the address visibility mode by setting the AVIS bit. Disabling the address visibility mode lowers the power consumption of the device and the RF noise of the system. Note that if the processor is running while HOLDA is active (HM = 0), the program address is not available at the address pins, regardless of the address visibility mode.

8.2.4

Program Memory Protection Feature

The program memory protection feature prevents an instruction fetched from off-chip memory from reading or writing on-chip program memory. The pipeline controller tracks instructions fetched from off-chip memory, and, if the operand address resides in on-chip program space, the instruction reads invalid data off the bus. The protection feature implements these limitations:
- Instructions fetched from off-chip memory cannot read or write on-chip

single-access and read-only program memory.

- Instructions fetched from DARAM block B0 cannot read or write on-chip

single-access and read-only program memory.

- Coefficients for off-chip multiply/accumulate instructions cannot reside in

on-chip single-access and read-only program memory.

- The on-chip single-access memory cannot be mapped to program space. - The on-chip single-access memory cannot be mapped to data space. - External DMA cannot be used. - The emulator cannot access on-chip program memory. - The program memory address range that corresponds to the on-chip

single-access RAM is not available for external memory. This feature can be used with the on-chip ROM to secure program code that is stored in external (off-chip) memory. The ROM code can include a decryption algorithm that takes encrypted off-chip code, decrypts it, and stores the routine in on-chip single-access program RAM. This process-mask option, like the ROM, must be submitted to Texas Instruments for implementation.
8-14

Local Data Memory

8.3 Local Data Memory

The local data memory space on the C5x addresses up to 64K 16-bit words. All the C5x devices have 1056 words of DARAM but different sizes of SARAM. The amount and types of memory available on each device are listed in Table 11 on page 1-6. You can use software to configure these memory cells to reside inside (on-chip) or outside (off-chip) of the local data address map. When the memory cells are mapped into local data space, the C5x automatically accesses them when it addresses within their bounds. When the CALU generates an address outside these bounds, the C5x automatically generates an external (off-chip) access. These are the advantages of operating from internal (on-chip) memory: 1) Higher performance because no wait states are required for slower external memories. 2) Higher performance because of more efficient pipeline operation. 3) Lower cost than external memory. 4) Lower power than external memory. The advantage of operating from external (off-chip) memory is the ability to access a larger address space.

8.3.1

Local Data Memory Configurability

The local data memory can reside both on- and off-chip. At reset, the C5x device configuration maps the 1056 words of DARAM into local data space. DARAM block B0 can be reconfigured into program space by setting the CNF bit in ST1. SARAM can be mapped into data space by setting the OVLY bit in the PMST. Table 88 through Table 812 show local data memory configurations available on the C5x devices. Note that all locations in the address range 0000h0800h that are not mapped into on-chip memory are on-chip reserved locations. Address range 0000h004Fh contains on-chip memory-mapped registers, and address range 0050h005Fh contains the memory-mapped I/O ports. Note that all addresses are specified in hexadecimal.

Memory

8-15


8-16

Legend:

Table 810. C52 Local Data Memory Configuration Table 89. C51 Local Data Memory Configuration
CNF Bit values 1 1 0 0 1 1 OVLY 1 0 1 0 1 0 Registers (96-words) 0000005F 0000005F 0000005F 0000005F 0000005F 0000005F 0060007F 0060007F 0060007F 0060007F DARAM B2 (32-words) 0060007F 0060007F Reserved Reserved 010002FF 010002FF DARAM B0 (512-words) Reserved Reserved 030004FF 030004FF 030004FF 030004FF DARAM B1 (512-words) 030004FF 030004FF 08000BFF Off-chip 08000BFF Off-chip SARAM (1K-words) 08002BFF Off-chip 0C00FFFF 0800FFFF 0C00FFFF 0800FFFF Off-Chip 2C00FFFF 0800FFFF

Local Data Memory

Table 811. C53 and C53S Local Data Memory Configuration

Table 88. C50 Local Data Memory Configuration

CNF

CNF

CNF

Bit values

Bit values

Bit values

1 1 0 0 1 0 0 0

OVLY

OVLY

OVLY

1 0 1 0 1 0

Registers (96-words)

Registers (96-words)

Registers (96-words)

0000005F 0000005F 0000005F 0000005F 0000005F 0000005F 0000005F 0000005F

Dont care condition

0060007F 0060007F 0060007F 0060007F 0060007F 0060007F 0060007F 0060007F

DARAM B2 (32-words)

DARAM B2 (32-words)

DARAM B2 (32-words)

Reserved Reserved Reserved

010002FF

010002FF

DARAM B0 (512-words)

010002FF

DARAM B0 (512-words)

010002FF

010002FF

DARAM B0 (512-words)

030004FF 030004FF 030004FF 030004FF 030004FF 030004FF 030004FF 030004FF

DARAM B1 (512-words)

DARAM B1 (512-words)

DARAM B1 (512-words)

080013FF Off-chip Off-chip None None Off-chip 080013FF SARAM

SARAM (3K-words)

08002BFF

SARAM (9K-words)

1400FFFF 0800FFFF 1400FFFF 0800FFFF Off-Chip Off-Chip Off-Chip 0800FFFF 0800FFFF 0800FFFF

2C00FFFF

Local Data Memory

Table 812. LC56, LC57, and C57S Local Data Memory Configuration

Bit values CNF 0 0 1 1 OVLY 0 1 0 1 Registers (96-words) DARAM B2 (32-words) 0060007F 0060007F 0060007F 0060007F DARAM B0 (512-words) 010002FF 010002FF Reserved Reserved DARAM B1 (512-words) 030004FF 030004FF 030004FF 030004FF SARAM (6K-words) Off-chip Off-Chip 0000005F 0000005F 0000005F 0000005F 0800FFFF 2000FFFF 0800FFFF 2000FFFF 08001FFF Off-chip 08001FFF

8.3.2

Local Data Memory Address Map

The 64K words of local data memory space include the memory-mapped registers for the device. The memory-mapped registers reside in data page 0. Data page 0 has five sections of register banks: CPU registers, peripheral registers, test/emulation reserved area, I/O space, and scratch-pad RAM. Table 813 lists the addresses of data page 0.
- The 28 CPU registers can be accessed with zero wait states. Some of

these registers can be accessed through paths other than the data bus for example, auxiliary registers can be loaded by the auxiliary register arithmetic unit (ARAU) by using the LAR instruction.
- The peripheral registers are the control and data registers used in the pe-

ripheral circuits. These registers reside on a dedicated peripheral bus structure called the TI Bus. They require one wait state when accessed.
- The test/emulation reserved area is used by the test and emulation sys-

tems for special information transfers. Writing to the test/emulation reserved area can cause the device to change its operational mode and, therefore, affect the operation of the application.

- The I/O space provides access to 16 words of I/O space (other than IN and

OUT instructions) via the more extensive addressing modes available within the data space. For example, the SAMM instruction can write to an I/O memory-mapped port as an OUT instruction does. The external interface functions as if an OUT instruction occurred (IS active). Port addresses reside off-chip and are subject to external wait states. They are also affected by the on-chip software wait-state generator, like any other nonmemory-mapped I/O port.
Memory
8-17


8-18

Local Data Memory

Table 813. Data Page 0 Address Map CPU Registers

Dec

03

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4

Address

Hex

03

1A 19 18 17 16 15 14 13 12 10 11 D C E B A F 9 8 7 6 5 4

CBSR1 ARCR INDX AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 PAER PASR BRCR RPTC PMST IFR IMR Name DBMR TREG2 TREG1 TREG0 GREG

- The 32-word scratch-pad RAM of DARAM block B2 can be used to hold

overhead variables so that the larger blocks of RAM are not fragmented. This RAM block supports dual-access operations and can be addressed via the memory-mapped addressing mode or any data memory addressing mode.

Circular buffer 1 start register Index register Reserved Description Auxiliary register 7 Auxiliary register 6 Auxiliary register 5 Auxiliary register 4 Auxiliary register 3 Auxiliary register 2 Auxiliary register 1 Auxiliary register 0 Block repeat counter register Repeat counter register Interrupt flag register Interrupt mask register

Auxiliary register compare register Dynamic bit manipulation register Processor mode status register Global memory allocation register

Temporary register 2 (used as bit pointer in dynamic bit test) Temporary register 1 (used for dynamic shift count) Temporary register 0 (used for multiplicand) Block repeat program address end register Block repeat program address start register

Local Data Memory

Table 813. Data Page 0 Address Map CPU Registers (Continued)
Address Dec 27 28 29 30 31 Hex 1B Name Description CBER1 CBSR2 CBER2 CBCR Circular buffer 1 end register 1C 1D 1E 1F Circular buffer 2 start register Circular buffer 2 end register Circular buffer control register Block move address register BMAR 3235 3642 4347 4855 5679 8095 2023 Memory-mapped serial port registers 242A Memory-mapped peripheral registers Reserved for test/emulation 2B2F 3037 Memory-mapped serial port registers Reserved 384F 505F 607F Memory-mapped I/O ports 96127 Scratch-pad RAM (DARAM block B2)
See subsection 9.1.1, Memory-Mapped Peripheral Registers and I/O Ports, on page 9-2

8.3.3

Local Data Memory Addressing

The local data space address generation is controlled by the decode of the current instruction. Local data memory is read via data address bus 1 (DAB) on instructions with only one data memory operand and via program address bus (PAB) on instructions with a second data memory operand. An instruction operand is provided to the CALU as described in subsection 8.2.3 on page 8-13. However, data memory addresses are generated in one of the following ways:
-

The direct addressing mode The indirect addressing mode The long immediate operand addressing mode The dedicated-register addressing mode The memory-mapped register addressing mode

Refer to Chapter 5, Addressing Modes, for a discussion about the addressing modes.

Memory

8-19

Global Data Memory

8.4 Global Data Memory

For multiprocessing applications, the C5x devices can allocate global data memory space and communicate with that space via the BR (bus request) and READY control signals. This capability can be used to extend the data memory address map by overlaying the address space. Since global memory is shared by more than one processor, access to it must be arbitrated. When global memory is used, the processors address space is divided into local and global sections. The local section is used by the processor to perform its individual function, and the global section is used to communicate with other processors. This implementation facilitates shared data multiprocessing in which data is transferred between two or more processors. Unlike a direct memory access (DMA) between two processors, reading or writing global memory does not require that one of the processors be halted.

8.4.1

Global Data Memory Configurability

The global memory allocation register (GREG) specifies part of the C5x data memory as global external memory. The 8-bit GREG is memory-mapped to data memory address location 05h and is connected to the eight LSBs of the internal data bus. The upper eight bits of location 05h are unused and are read as 1s. The contents of GREG determine the size (between 256 and 32K words) of the global memory space. The legal values of GREG and the corresponding local and global memory spaces are listed in Table 814. Note: In Table 814 all addresses are specified in hexadecimal; values in GREG other than those listed will lead to fragmented memory maps and should be avoided.

8.4.2

Global Data Memory Addressing

When a data memory address, either direct or indirect, corresponds to a global data memory address (as defined by GREG), BR is asserted low with DS to indicate that the C5x device is starting a global memory access. External logic then arbitrates for control of the global memory, asserting READY when the C5x device has control. The length of the memory cycle is controlled by the READY signal. In addition, the software wait-state generators can be used to extend the access times for slower, external memories. The wait-state generators corresponding to the overlapped memory address space in local data space generate the wait states for the corresponding addresses in global data memory space.

8-20


Table 814. Global Data Memory Configurations
Legend:

1111 1111

1111 1110

1111 1100

1111 1000

1111 0000

1110 0000

1100 0000

1000 0000

0000 00XX

GREG value

Dont care condition

0000FEFF

0000FDFF

0000FBFF

0000F7FF

0000EFFF

0000DFFF

0000BFFF

00007FFF

0000FFFF

Range

Local Memory

65 280

65 024

64 512

63 488

61 440

57 344

49 152

32 768

65 536

# Words

FF00FFFF

FE00FFFF

FC00FFFF

F800FFFF

F000FFFF

E000FFFF

C000FFFF

8000FFFF

Range

Global Memory

Memory
256 512 1024 2048 4096 8192 16 384 32 768 0

Global Data Memory

# Words

8-21

Input/Output (I/O) Space

8.5 Input/Output (I/O) Space

The C5x devices support an I/O address space of 64K 16-bit parallel input and output (I/O) ports. The I/O ports allow access to peripherals typically used in DSP applications such as codecs, digital-to-analog (D/A) converters, and analog-to-digital (A/D) converters. This section discusses addressing I/O ports and interfacing I/O ports to external devices.

8.5.1

Addressing I/O Ports

Access to external parallel I/O ports is multiplexed over the same address and data bus for program/data memory accesses. All 64K I/O ports can be accessed via the IN and OUT instructions, as shown in the following example:
IN DAT7,0FFFEh ;Read data to data memory from external ;device on port 65534. OUTDAT7,0FFFFh ;Write data from data memory to external ;device on port 65535.

Sixteen of the 64K I/O ports are memory-mapped to data memory address locations 50h5Fh. The I/O ports can be accessed by using the IN and OUT instructions or any instruction that reads or writes a location in data memory space. See Section 9.6, Parallel I/O Ports, on page 9-22. The access times to I/O ports can be modified through the software wait-state registers (IOWSR and CWSR). The BIG bit in the CWSR determines how the I/O space is partitioned. See Section 9.4, Software-Programmable Wait-State Generators, on page 9-13.

8-22

Direct Memory Access (DMA)

8.6 Direct Memory Access (DMA)

The C5x supports multiprocessing designs that require direct memory access (DMA) of external memory or of on-chip single-access RAM. The DMA feature can be used for multiprocessing by temporarily halting the execution of one or more processors to allow another processor to read from or write to local offchip memory or on-chip single-access RAM. External memory access can be controlled via the HOLD and HOLDA signals and on-chip RAM access via the HOLD, HOLDA, R/W, STRB, BR, and IAQ signals.

8.6.1

DMA in a Master-Slave Configuration

Multiprocessing systems typically utilize a master-slave configuration. The master may initialize a slave by downloading a program into the slaves program memory space and/or may provide the slave with the necessary data by using external memory to complete a task. In a typical C5x DMA scheme, the master may be a general-purpose CPU, another C5x, or even an A/D converter. A simple C5x master-slave configuration is shown in Figure 87.

Figure 87. Direct Memory Access Using a Master-Slave Configuration

C5x (Master) C5x (Slave)

XF BIO

HOLD HOLDA XF BIO Buffer and Logic A15A0 D15D0

INT1INT4 IACK A15A0 D15D0 R/W

Master Data Memory (RAM)

Master Program Memory (ROM)

Slave Program Memory (RAM)

Slave Data Memory (RAM)

The C5x master device takes complete control of the slaves external memory by asserting the slaves HOLD low via the masters external flag (XF) pin. This causes the slave to place its address, data, and control lines in a high-impedance state. When the master gains control of the slaves buses, the slave asserts HOLDA. This signal may be tied to the master BIO pin. The slaves XF pin can indicate to the master when the slave has finished performing its task and needs to be reprogrammed or requires additional data to continue processing. In a multiple-slave configuration, priority of each slaves task can be determined by
Memory
8-23

Direct Memory Access (DMA)

connecting the slaves XF signals to the appropriate INT1INT4 pin on the master device. The external bus interface of the slave device is put in high-impedance mode when its HOLDA signal is asserted. Once HOLDA goes active, the IAQ pin does not indicate an instruction acquisition. While the HOLDA is active and the CPU is in hold mode (HM = 0), the CPU continues running code from internal memory (internal ROM or single/dual access RAM). If the CPU is not in hold mode (HM = 1), the CPU halts internal execution. See Section 4.9, Reset, on page 4-45 for interaction between HOLD, RS, and external interrupts.

8.6.2

External DMA
The C5x also provides access of the on-chip single-access RAM by external devices through a mechanism called external DMA. External DMA requires the following signals: A(150) BR D(150) HOLD HOLDA IAQ R/W STRB Address inputs when HOLDA and BR are low. Bus request signal externally driven low in hold mode to indicate a request for access. DMA data. External request for control of address, data, and control lines. Indication to external circuitry that the memory address, data, and control lines are in high impedance, allowing external access. Acknowledge BR request for access while HOLDA is low. Read/write signal indicates the data bus direction for DMA reads (high) and DMA writes (low). When IAQ and HOLDA are low, STRB selects the memory access and determines its duration.

To access the C5x on-chip SARAM, a master processor must control the C5x device. The master processor initiates a DMA transfer by asserting the C5x device HOLD low. The C5x responds by asserting HOLDA. The master gains control of the C5x bus and access to the SARAM by asserting BR low. The C5x responds by asserting IAQ low to acknowledge the access. Once access is granted, the master drives the R/W signal to indicate the direction of the transfer. On a DMA write, the master must drive the address and data lines for a write. On a DMA read, the master must drive the address lines and latch the data. Each memory access (read or write) is selected when STRB is low. External access wait states are added by extending the STRB signal. The address decode of the DMA access includes only address lines A13A0 (A14 and A15 are ignored). Table 815 lists the address ranges during DMA access, effectively overlaying address lines A13A0.
8-24

Direct Memory Access (DMA)

Table 815. Address Ranges for On-Chip Single-Access RAM During External DMA

Device C50 SARAM (words) 9K Address Bus Hex Address Ranges 00002BFF 40006BFF A15A14 ignored, A13A0 used 8000ABFF C000EBFF 000003FF 400043FF 800083FF C51 1K A15A14 ignored, A13A10 must be 0, A9A0 used C000C3FF 00000BFF 40004BFF 80008BFF C53 3K A15A14 ignored, A13A12 must be 0, A11A0 used C000CBFF 000017FF 400057FF 800097FF LC56 6K A15A14 ignored, A13 must be 0, A12A0 used C000D7FF 000017FF 400057FF 800097FF C57S/ LC57 6K A15A14 ignored, A13 must be 0, A12A0 used C000D7FF

DMA access to on-chip single-access RAM is not supported if the device is in concurrent hold mode (HM = 0).

Using DMA on a C50 and writing to address 01h affects the second memory location of the SARAM. Furthermore, writing to address 4001h on a C50 is equivalent to writing to addresses 01h, 8001h, and C001h, since address lines A14 and A15 are ignored. Note that the external parallel interface signals are asynchronously disabled during reset; therefore, external DMA is not supported during reset.
Memory
8-25

Memory Management

8.7 Memory Management

The C5x programmable memory map can vary for each application. Instructions are provided for integrating the device memory into the system memory map. The amount and types of memory available on each device are listed in Table 11 on page 1-6. Examples of moving and configuring memory are given in this section.

8.7.1

Memory-to-Memory Moves
The following instructions for data and program block moves, word transfers, and the data move function efficiently utilize C5x memory spaces.
- Data and program block move instructions J J J

BLDD instruction moves a block within data memory BLDP instruction moves a block from data memory to program memory BLPD instruction moves a block from program memory to data memory

- Data and program word transfer instructions J J

The table read (TBLR) instruction reads words from program memory into data memory The table write (TBLW) instruction writes words from data memory to program memory

- Data move (DMOV) instruction allows access to data and operation on

that data simultaneously in the same cycle. For block move instructions, one address is derived from the data address generator, while the other is derived from a long immediate constant or from the BMAR. When used with the repeat instructions (RPT and RPTZ), these instructions efficiently perform block moves from on-chip or off-chip memory. The DMOV function, implemented in on-chip data RAM, is equivalent to that of the C2x. DMOV copies a word from the currently addressed data memory location in on-chip RAM to the next-higher location, while the data from the addressed location is being operated upon in the same cycle (for example, by the CALU). An ARAU operation can also be performed in the same cycle when the indirect addressing mode is used. The DMOV function can implement algorithms that use the z 1 delay operation, such as convolution and digital filtering, in which data is passed through a time window.
8-26

Memory Management

The DMOV function is most efficient when operating in dual-access on-chip RAM. When operating in single-access RAM, DMOV requires an additional cycle. The DMOV function is contiguous across the boundary of dual-access on-chip RAM blocks B0 and B1. The DMOV function is used by these instructions:
- LTD load TREG0 and accumulate product with data move - MACD multiply and accumulate with data move - MADD multiply and accumulate with data move and coefficient address

contained in BMAR Note: The DMOV operation cannot be performed on external data memory.

8.7.2

Memory Block Moves

The C5x devices can address a large amount of off-chip memory but are limited in the amount of on-chip memory. Several instructions can move blocks of data from slower off-chip memories to on-chip memory for faster program execution. In addition, data can be transferred from on-chip to off-chip memory for storage or multiprocessor applications.

8.7.2.1

Moving Data With the BLDD Instruction

The BLDD instruction transfers data in the following ways:
-

From external data memory to external data memory From external data memory to internal data memory From internal data memory to internal data memory From internal data memory to external data memory

Example 81 illustrates how to use the BLDD instruction to move external data (for example, a table of coefficients) to internal DARAM block B1.

Example 81. Moving External Data to Internal Data Memory With the BLDD Instruction
* * This routine uses the BLDD instruction to move external data memory to * internal data memory. * MOVED LACC #8000h SAMM BMAR ;BMAR contains source address in data memory LAR AR7,#300h ;AR7 contains dest. address in data memory MAR *,AR7 ;ARP = AR7 RPT #511 ;Move 512 values from data memory to data memory block B1 BLDD BMAR,*+ RET

Memory

8-27

Memory Management

8.7.2.2

Moving Data From Data Memory to Program Memory

The BLDP and TBLW instructions transfer data to program memory in the following ways:
-

From external data memory to external program memory From external data memory to internal program memory From internal data memory to internal program memory From internal data memory to external program memory

For systems with external data memory but no external program memory, you can use the BLDP instruction to move additional blocks of code into internal program memory. Example 82 illustrates how to use the BLDP instruction to move external data to internal program memory. You can also use the TBLW instruction to transfer data memory to program memory. The TBLW instruction differs from the BLDP instruction in that the accumulator contains the destination program memory address. This lets you specify a calculated, rather than predetermined, location of a block of data in program memory. Example 83 illustrates how to use the TBLW instruction to move external data to internal program memory.

Example 82. Moving External Data to Internal Program Memory With the BLDP Instruction
* * This routine uses the BLDP instruction to move external data memory to * internal program memory. This instruction could be used to boot load a * program to the on chip program RAM from external data memory. * MOVEDP LACC #2000h SAMM BMAR ;BMAR contains dest. address in program memory (C51) LAR AR7,#0F000h ;AR7 contains source address in data memory MAR *,AR7 ;ARP=AR7 RPT #1023 ;Move 1k values from data memory to program memory BLDP *+ RET

8-28

Memory Management

Example 83. Moving External Data to Internal Program Memory With the TBLW Instruction
* * This routine uses the TBLW instruction to move data memory to program memory. * The calling routine must contain the destination program memory address in * the accumulator. * TABLEW LAR AR4,#300h ;AR4 contains source address in data memory MAR *,AR4 ;ARP = AR4 RPT #511 ;Move 512 values from data memory to program memory TBLW *+ ;Accumulator contains dest. address of program memory RET

8.7.2.3

Moving Data From Program Memory to Data Memory

The BLPD and TBLR instructions transfer program data to data memory in the following ways:
-

From external program memory to external data memory From external program memory to internal data memory From internal program memory to internal data memory From internal program memory to external data memory

When no external data memory is available, program memory may contain necessary coefficient tables that should be loaded into internal data memory. Example 84 illustrates how to use the BLPD instruction to move external program memory to internal DARAM block B1. You can also use the TBLR instruction to transfer program data to data memory. The TBLR instruction differs from the BLPD instruction in that the accumulator contains the source program memory address. This lets you specify a calculated, rather than predetermined, location of a block of data in program memory. Example 85 illustrates how to use the TBLR instruction to move external program to internal DARAM block B1.

Memory

8-29

Memory Management

Example 84. Moving External Program to Internal Data Memory With the BLPD Instruction
* * This routine uses the BLPD instruction to move external program memory to * internal data memory. This routine is useful for loading a coefficient * table stored in external program memory to data memory when no external * data memory is available. * MOVEPD LAR AR7,#300h ;AR7 contains dest. address in data memory MAR *,AR7 ;ARP=AR7 RPT #127 ;Move 128 values from program memory to data block B1 BLPD #0FD00h,*+ RET

Example 85. Moving External Program to Internal Data Memory With the TBLR Instruction
* * This routine uses the TBLR instruction to move external program memory to * internal data memory. The calling routine must contain the source program * memory address in the accumulator. * TABLER LAR AR3,#300h ;AR3 contains dest. address in data memory MAR *,AR3 ;ARP=AR3 RPT #127 ;Move 128 values from program memory to data block B1 TBLR *+ ;Accumulator contains external program memory address RET

8-30

Memory Management

8.7.2.4

Moving Data From Data Memory to I/O Space With the LMMR Instruction
The LMMR instruction can be used to transfer data from external or internal data memory to an external I/O port. Example 86 illustrates how to use the LMMR instruction to move data from internal data memory to a memorymapped I/O port.

Example 86. Moving Data From Internal Data Memory to I/O Space With the LMMR Instruction
* * This routine uses the LMMR instruction to move data from internal data memory * to a memory-mapped I/O port. Note that 16 I/O ports are mapped in data * page 0 of the C5x memory map. * OUTPUT: LDP #0 ;DP=0 RPT #63 ;Move 64 values from a table beginning at 800h in data LMMR 50h,#800h ;memory to port 50h. Source address is incremented RET

8.7.2.5

Moving Data From I/O Space to Data Memory With the SMMR Instruction
The SMMR instruction can be used to transfer data from an external I/O port to external or internal data memory. Example 87 illustrates how to use the SMMR instruction to move data from a memory-mapped I/O port to internal data memory.

Example 87. Moving Data from I/O Space to Internal Data Memory With the SMMR Instruction
* * This routine uses the SMMR instruction to move * I/O port to internal data memory. Note that 16 * page 0 of the C5x memory map. * INPUT: LDP #0 :DP=0 RPT #511 ;Move 512 values from SMMR 51h,#800h ;800h in data memory. RET

data from a memory-mapped I/O ports are mapped in data

port 51h to table beginning at Dest. address is incremented

Memory

8-31

Boot Loader

8.8 Boot Loader

Several of the C5x devices include a boot loader program contained in the on-chip ROM (see Appendix G, Development Support and Part Order Information, for part numbering nomenclature). The main function of the boot loader is to transfer code from an external source to the program memory at power-up. This can be done in several different ways, depending on the system requirements. For some applications, a serial interface is appropriate. If the code is already stored in nonvolatile memory (ROM), a parallel interface is more appropriate. If the MP/MC pin of the C5x is sampled low during a hardware reset, program execution begins at address location 0000h of the on-chip ROM. This location contains a branch instruction to the start of the boot-loader program. The onchip ROM is factory programmed with the boot-loader program. The bootloader program sets up the CPU status registers before initiating the boot load:
- Interrupts are globally disabled (INTM = 1). - On-chip DARAM block B0 is mapped into program space (CNF = 1). - On-chip SARAM block is mapped into program space (RAM = 1, OVLY = 0). - Entire program and data memory spaces are enabled with seven wait

states.
- 32K words of global data memory are enabled initially in data spaces

8000h to FFFFh. After the code transfer is complete, the global memory is disabled before control is transferred to the destination address in program memory. Note that both DARAM and SARAM memory blocks are enabled in program memory space; this allows you to transfer code to on-chip program memory. The boot-loader program reads global data memory location FFFFh by driving the bus request (BR) and data strobe (DS) pins low. The lower 8 bits of the word at address FFFFh specify the boot mode; the higher 8 bits are ignored by the boot loader. Figure 88 lists the available boot mode options and the corresponding values for the boot routine selection word.

8-32

Boot Loader

Figure 88. Boot Routine Selection Word

15 8 7 4 3 0

At Address FFFFh 8-bit serial mode 16-bit serial mode 8-bit parallel I/O mode 16-bit parallel I/O mode 8-bit parallel EPROM mode 16-bit parallel EPROM mode Warm boot

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Legend: X = SRC = ADDR =

XXXX XXXX XXXX XXXX SRC SRC ADDR

0000 0100 1000 1100 01 10 11

Dont care condition 6-bit page address for parallel EPROM modes 6-bit page address for warm boot mode

8.8.1

HPI Boot Mode (C57 only)

In HPI boot mode, the boot-loader program first verifies if the host port interface (HPI) boot mode is selected. To select the HPI boot mode, connect the HINT pin to the INT3 pin; this sets the INT3 bit in the interrupt flag register (IFR) when the HINT pin is asserted low. The boot loader asserts HINT low, waits for 10 CLKOUT1 cycles, and reads the INT3 bit. If the INT3 bit is set (indicating an INT3 interrupt is pending), the boot loader transfers program control to the start address (8800h in program space) of the on-chip HPI RAM and starts executing user code from there. If the INT3 bit is not set (indicating that HINT is not connected to INT3), the boot loader skips the HPI boot mode and reads the boot routine selection word (Figure 88) at global data memory location FFFFh to identify the boot mode. If the HPI boot mode is selected, the host must download code to the HPI RAM before it brings the C5x out of reset. Note that the boot loader keeps HPI in the shared-access mode (SMOD = 1) during the entire boot loading operation. Once HINT is asserted low by the boot loader, HINT remains low until a host controller (if any) clears HINT by writing to the host port interface control register (HPIC). Instead of connecting the HINT pin to the INT3 pin, you can send a valid interrupt to the INT3 pin within 30 CLKOUT1 cycles after the C5x fetches the reset vector. For C5x reset vector fetch timing specifications, refer to the TMS320C5x data sheet.
Memory
8-33

Boot Loader

An alternative to the HPI boot mode is the warm boot mode described in subsection 8.8.5 on page 8-37. The warm boot mode may be preferred to the HPI boot mode, if it is not convenient to connect the HINT pin to the INT3 pin or if the program has already been transferred to program memory.

8.8.2

Serial Boot Mode

To select the serial boot mode, the serial port control register (SPC) is set to 00F8h for a16-bit word transfer or to 00FCh for an 8-bit word transfer. See subsection 9.7.1, Serial Port Interface Registers, on page 9-24 for a description of each SPC bit. The external flag (XF) pin signals that the C5x is ready to respond to the serial port receive section. The XF pin is set high at reset and is driven low to initiate reception. No frame sync pulses should appear on the FSR pin before XF goes low. The receive clock must be supplied by an external device to the C5x.

8.8.2.1

16-Bit Word Serial Transfer

If the 16-bit word transfer is selected (Figure 89), the first 16-bit word received by the device from the serial port specifies the destination address (Destination16) of code in program memory. The next 16-bit word specifies the length (Length16) of the actual code that follows. These two 16-bit words are followed by N number of code words to be transferred to program memory. Note that the number of 16-bit words specified by the parameter N does not include the first two 16-bit words received (Destination16 and Length16). After the specified number of code words are transferred to program memory, the C5x branches to the destination address. The length N is defined as: length N = number of 16-bit words 1

Figure 89. 16-Bit Word Transfer

15

Legend:

Destination16 Length16 Code Word(N)16

16-bit destination address 16-bit word that specifies the length of the code (N) that follows N number of 16-bit words to be transferred

8.8.2.2

8-Bit Word Serial Transfer

If the 8-bit word transfer is selected (Figure 810), a higher-order byte and a lower-order byte form a 16-bit word. The first 16-bit word received by the device from the serial port specifies the destination address (Destinationh and Destinationl) of code in program memory. The next 16-bit word specifies the

8-34

Boot Loader

length (Lengthh and Lengthl) of the actual code that follows. These two 16-bit words are followed by N number of code words to be transferred to program memory. Note that the number of 16-bit words specified by the parameter N does not include the first four bytes (first two 16-bit words) received (Destination and Length). After the specified number of code words are transferred to program memory, the C5x branches to the destination address. The length N is defined as: length N = number of 16-bit words 1 or length N = (number of bytes to be transferred 2 ) 1

Figure 810. 8-Bit Word Transfer

7

Legend:

Destinationh Destinationl Lengthh Lengthl Code Word(N)h Code Word(N)l

High byte of destination address Low byte of destination address High byte that specifies the length of the code (N) that follows Low byte that specifies the length of the code (N) that follows High byte of N number of 16-bit words to be transferred Low byte of N number of 16-bit words to be transferred

8.8.3

Parallel EPROM Boot Mode

The parallel EPROM boot mode is used only when code is stored in EPROMs (8-bit or 16-bit wide). The code is transferred from global data memory (starting at the source address) to program memory (starting at the destination address). The six MSBs of the source address are specified by the SRC field of the boot routine selection word (Figure 88 on page 8-33). A 16-bit source address is defined by this SRC field as shown in Figure 811. The C5x transfers control to the source address after disabling global data memory.

Figure 811.16-Bit Source Address for Parallel EPROM Boot Mode

15 10 9 0

SRC

Source address
Legend: SRC = 6-bit page address

8.8.3.1

16-Bit Word Parallel Transfer

If the 16-bit word parallel boot mode is selected (Figure 89 on page 8-34), boot code will be read in 16-bit words starting at the source address. The
Memory
8-35

Boot Loader

source address is incremented by 1 after every read operation. The first 16-bit word read from the source address specifies the destination address (Destination16) of code in program memory. The next 16-bit word specifies the length (Length16) of the actual code that follows. These two 16-bit words are followed by N number of code words to be transferred to program memory. Note that the number of 16-bit words specified by the parameter N does not include the first two 16-bit words received (Destination16 and Length16). After the specified number of code words are transferred to program memory, the C5x branches to the destination address. The length N is defined as: length N = number of 16-bit words 1 Note that there is at least a 4-instruction-cycle delay between a read from the EPROM and a write to the destination address. This delay ensures that if the destination is in external memory (for example, fast SRAM), there is enough time to turn off the source memory (for example, EPROM) before the write operation is performed.

8.8.3.2

8-Bit Word Parallel Transfer

If the 8-bit word parallel boot mode is selected (Figure 810 on page 8-35), two consecutive memory locations (starting at the source address) are read to form a 16-bit word. The high-order byte of the 16-bit word is followed by the low-order byte. Data is read from the lower eight data lines, ignoring the higher byte on the data bus. The first 16-bit word specifies the destination address (Destinationh and Destinationl) of code in program memory. The next 16-bit word specifies the length (Lengthh and Lengthl) of the actual code that follows. These two 16-bit words are followed by N number of code words to be transferred to program memory. Note that the number of 16-bit words specified by the parameter N does not include the first four bytes (first two 16-bit words) received (Destination and Length). After the specified number of code words are transferred to program memory, the C5x branches to the destination address. The length N is defined as: length N = number of 16-bit words 1 or length N = (number of bytes to be transferred 2 ) 1 Note that there is at least a 4-instruction-cycle delay between a read from the EPROM and a write to the destination address. This delay ensures that if the destination is in external memory (for example, fast SRAM), there is enough time to turn off the source memory (for example, EPROM) before the write operation is performed.

8-36

Boot Loader

8.8.4

Parallel I/O Boot Mode

The parallel I/O boot mode asynchronously transfers code from the I/O port at address 50h to internal or external program memory. Each word can be 16 bits or 8 bits long. The C5x communicates with the external device via the BIO and XF lines. This allows a slow host processor to communicate easily with the C5x by polling/driving the BIO and XF lines. The handshake protocol shown in Figure 812 on page 8-37 must be used to successfully transfer each word via I/O port 50h. If the 8-bit boot mode is selected, two consecutive 8-bit words are read to form a 16-bit word. The high-order byte of the 16-bit word is followed by the loworder byte. Data is read from the lower eight data lines of I/O port 50h, ignoring the higher byte on the data bus. For both the 8-bit and 16-bit parallel I/O boot modes, refer to subsection 8.8.3, Parallel EPROM Boot Mode, for the description of destination and length code words. Note that there is at least a 4-instruction-cycle delay between the XF rising edge and a write operation to the destination address. This delay ensures that if the destination is in external memory (for example, fast SRAM), the host processor has enough time to turn off the data buffers before the write operation is performed. The C5x accesses the external bus only when XF is high.

Figure 812. Handshake Protocol

BIO

XF

Host request data transmit

C5x ready to receive

Host data valid

C5x acknowledges data received

1-word transfer

Next word transfer

8.8.5

Warm Boot Mode

In a warm boot, the boot loader runs but does not move any code. Control is simply transferred to the entry address. The warm boot mode can be used if the program has already been transferred to internal or external memory by
Memory
8-37

Boot Loader

other means (for example, HPI or external DMA) or if only a warm device reset is required. The six MSBs of the entry address are specified by the ADDR field of the boot routine selection word (Figure 88 on page 8-33). A 16-bit entry address is defined by this ADDR field as shown in Figure 813. The C5x transfers control to the entry address after disabling global data memory. For C57 devices, the warm boot mode can be used instead of the HPI boot mode to transfer control to the on-chip HPI RAM.

Figure 813. 16-Bit Entry Address for Warm Boot Mode

15 10 9 0

ADDR

0 Entry address

Legend:

ADDR = 6-bit page address

8-38

External Parallel Interface Operation

8.9 External Parallel Interface Operation

All bus cycles comprise integral numbers of CLKOUT1 cycles. One CLKOUT1 cycle is defined to be from one falling edge of CLKOUT1 to the next falling edge of CLKOUT1. For full-speed, 0-wait-state operation, reads require one cycle. A write immediately preceded by a read or immediately followed by a read requires three cycles. Refer to Figure 814 on page 8-40, Figure 815 on page 8-41, and Figure 816 on page 8-41 for timings for both read and write cycles. For read cycles, STRB goes low and ADDRESS becomes valid with the falling edge of CLKOUT1. For 0-wait-state read cycles, the RD signal goes low with the rising edge of CLKOUT1 and then goes high at the next falling edge of CLKOUT1. For 1-wait-state (multicycle) read cycles, the RD stays low but goes high with the falling edge of CLKOUT1 before the next cycle, even if the cycles are contiguous. Read data is sampled at the rising edge of RD. The R/W signal goes high at least one half cycle of CLKOUT1 before any read cycle; for contiguous read cycles, STRB stays low. At the end of a read cycle or sequence of reads, STRB and RD go high on the falling edge of CLKOUT1. Write cycles always have at least one inactive (pad) cycle of CLKOUT1 before and after the actual write operation, including contiguous writes. This allows a smooth transition between the write and any adjacent bus operations or other writes. For this pad cycle, STRB and WE are always high. The R/W signal always changes state on the rising edge of CLKOUT1 during the pad cycle before and after a write or series of writes. This prevents bus contention during a transition between read and write operations. Note that for a series of writes, R/W stays low. Timing of valid addresses for writes differs, depending on what activities occur before and after the write. Between writes, and for the first and last write in a series, ADDRESS becomes valid on the rising edge of CLKOUT1. If a read immediately follows a write or series of writes, ADDRESS becomes valid for that read cycle one half cycle of CLKOUT1 early that is, on the rising edge, rather than on the falling edge, of CLKOUT1. This is an exception to the usual read cycle address timing. For the actual write operation, STRB and WE both go low on the falling edge of CLKOUT1 and stay low until the next falling edge of CLKOUT1 (for 0-waitstate write cycles). For 1-wait-state (multicycle) writes, STRB and WE remain low but go high again on the falling edge of CLKOUT1 at the beginning of the pad cycle. Write data is driven approximately at the falling edge of STRB and WE and is held for approximately one half cycle of CLKOUT1 after STRB and WE go high (refer to the TMS320C5x data sheet for actual timing specifications).
Memory
8-39

External Parallel Interface Operation

Transitions on the external parallel interface control outputs (CLKOUT1, STRB, WE, and RD) are all initiated by the same two internal clocks. Since these signals also use the same output buffer circuitry, they all switch within close tolerances of each other, as specified in the TMS320C5x data sheet. Transitions on the address bus and other related outputs (IS, PS, DS, R/W, and BR) are initiated by the same internal signals that cause transitions on the control outputs; however, the internal device logic that generates these outputs is different from the circuitry used for the control outputs. Therefore, transitions on the address bus and related outputs typically occur later than control-line transitions. Timings of control outputs with respect to CLKOUT1 are specified in the TMS320C5x data sheet. Address timings with respect to CLKOUT1 can be derived from address timings for control signals and control signal timings for CLKOUT1. For example, the delay from CLKOUT1 falling to address bus valid at the beginning of a read cycle is calculated as: [H (address setup to RD)] + maximum positive RD to CLKOUT1 skew (refer to the TMS320C5x data sheet for specific timing values) Other interface timings with respect to CLKOUT1 can be calculated in the same manner.

Figure 814. External Interface Operation for Read-Read-Write (Zero Wait States)
CLKOUT1 ADDRESS DATA R/W RD WE IS,DS,PS STRB 1-cycle Read 3-cycle Write Read Read Write Data

1-cycle Read

8-40

External Parallel Interface Operation

Figure 815. External Interface Operation for Write-Write-Read (Zero Wait States)
CLKOUT1 ADDRESS DATA R/W RD WE IS,DS,PS STRB 2-cycle Write 1-cycle Read 3-cycle Write Write Data Write Data Read

Figure 816. External Interface Operation for Read-Write (One Wait State)
CLKOUT1 ADDRESS DATA R/W RD WE IS,PS,DS STRB READY 2-cycle Read with one READY generated wait state 4-cycle Write with one READY generated wait state Read Write Data

Memory

8-41

Software Wait-State Generation

8.10 Software Wait-State Generation

The software-programmable wait-state generators can be used to extend external bus cycles by up to seven machine cycles. All external reads require at least one machine cycle, while all external writes require at least two machine cycles. However, as shown in Figure 814 and Figure 815, an external write immediately followed or immediately preceded by an external read cycle requires three cycles. This provides a convenient way for interfacing external devices that do not satisfy the full-speed access-time requirements of the C5x. The C5x can generate wait states to extend the memory read/write cycles by software-programmable wait-state generators or by an interface with the hardware READY line. The software-programmable wait-state generators can only generate up to seven wait states. External devices requiring more than seven wait states can use the hardware READY line to generate the wait states. Note that if the on-chip wait-state generator is used to add wait states for external accesses, the number of CLKOUT1 cycles required for writes is not effected until two or more wait states are specified, contrary to wait states generated with the external READY input. Table 816 shows the number of cycles required for the different types of external device accesses.

Table 816. Number of CLKOUT1 Cycles Per Access for Various Numbers of Wait States
Number of CLKOUT1 Cycles Number N mber of Wait States 0 1 2 3 Hardware Wait State Read 1 2 3 4 Write 2n + 1 3n + 1 4n + 1 5n + 1 Software Wait State Read 1 2 3 4 Write 2n + 1 2n + 1 3n + 1 4n + 1

Where n is the number of consecutive write cycles.

Also, note that the external READY input is sampled only after the internal software wait states are completed. Therefore, if the READY input is driven low before the completion of the internal software wait states, no wait states are added to the external memory access until the specified number of software wait states is completed. Wait states are only added if the READY input is still low after the software wait states are completed. Additionally, it should be noted that the READY input is not an asynchronous input and input setup and hold times for this signal as specified in the TMS320C5x data sheet must be met or significant device malfunction will result.
8-42

Chapter 9

On-Chip Peripherals
The on-chip peripheral interfaces connected to the C5x CPU include the divide-by-one clock, timer, software-programmable wait-state generators, general purpose I/O pins, parallel I/O ports, serial ports, and host port interface. These peripherals are controlled through registers that reside in the memory map. The serial ports and timer are synchronized to the processor via interrupts.

Topic
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9

Page
Peripheral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Software-Programmable Wait-State Generators . . . . . . . . . . . . . . . . 9-13 General-Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 Buffered Serial Port (BSP) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-53 Time-Division Multiplexed (TDM) Serial Port Interface . . . . . . . . . . . 9-74

9.10 Host Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-87

On-Chip Peripherals

9-1

Peripheral Control

9.1 Peripheral Control

Peripheral circuits are operated and controlled through access of memorymapped control and data registers. The operation of the serial ports and the timer is synchronized to the processor via interrupts or through interrupt polling. Setting and clearing bits can enable, disable, initialize, and dynamically reconfigure the peripherals. Data is transferred to and from the peripherals through memory-mapped data registers. When a peripheral is not in use, the internal clocks can be shut off from that peripheral, allowing for lower power consumption when the device is in normal run mode or idle mode.

9.1.1

Memory-Mapped Peripheral Registers and I/O Ports

There are 28 processor registers, 17 peripheral registers, and 16 I/O ports mapped into the data memory space. Table 91 lists the memory-mapped registers and I/O ports of the C5x. Note that all writes to memory-mapped peripheral registers (but not processor registers or memory-mapped I/O ports) require one additional CLKOUT1 cycle.

Table 91. Data Page 0 Address Map Peripheral Registers and I/O Ports

9-2

Address Dec 03 Hex 03 Name Description Reserved 431 41F Memory-mapped processor registers (see subsection 8.3.2, Local Data Memory Address Map, on page 8-17). Data receive register 32 33 34 35 36 37 38 39 40 41 42 20 21 22 23 24 25 26 27 28 29 DRR DXR SPC Data transmit register Serial port control register Reserved TIM Timer counter register Timer period register PRD TCR Timer control register Reserved PDWSR IOWSR CWSR Program/data wait-state register I/O port wait-state register Wait-state control register 2A


Table 91. Data Page 0 Address Map Peripheral Registers and I/O Ports (Continued)
5679 4347 Dec 89 88 87 86 85 84 83 82 81 80 55 54 53 52 51 50 49 48 Address 2B2F 384F Hex 59 58 57 56 55 54 53 52 51 50 37 36 35 34 33 32 31 30 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 BKR ARR BKX TRAD AXR TRTA SPCE TCSR BSPC TSPC BDXR TDXR BDRR TRCV Name Description I/O port 59h I/O port 58h I/O port 57h I/O port 56h I/O port 55h I/O port 54h I/O port 53h I/O port 52h I/O port 51h I/O port 50h Reserved BSP receive buffer size register BSP address receive register BSP transmit buffer size register TDM receive address register BSP address transmit register TDM receive/transmit address register BSP control extension register TDM channel select register BSP control register TDM serial port control register BSP data transmit register TDM data transmit register BSP data receive register TDM data receive register Reserved for test/emulation

On-Chip Peripherals

Peripheral Control

9-3

Peripheral Control

Table 91. Data Page 0 Address Map Peripheral Registers and I/O Ports (Continued)

9.1.2

External Interrupts

9-4

Address Dec 90 91 92 93 94 95 Hex 5A 5B Name Description I/O port 5Ah PA10 PA11 I/O port 5Bh 5C 5D 5E 5F PA12 PA13 PA14 PA15 I/O port 5Ch I/O port 5Dh I/O port 5Eh I/O port 5Fh 96127 607F Scratch-pad RAM (DARAM B2)

The C5x has four external, maskable user interrupts (INT4INT1) that external devices can use to interrupt the processor, and one external nonmaskable interrupt (NMI). Internal interrupts are generated by the timer (TINT), the serial port (RINT, XINT, TRNT, TXNT, BRNT, and BXNT), the host port (HINT), and the software interrupt instructions (TRAP, NMI and INTR). Interrupt priorities are set so that reset (RS) has the highest priority and INT4 has the lowest priority. The NMI has the second highest priority. For further information regarding interrupt operation, see Section 4.8, Interrupts, on page 4-36. Interrupts may be asynchronously triggered. In the functional logic organization for INT4INT1, shown in Figure 91, the external interrupt INTn is synchronized to the core via a five flip-flop synchronizer. The actual implementation of the interrupt circuits is similar to this logic implementation. If a 1-1-0-0-0 sequence on five consecutive CLKOUT1 cycles is detected, a 1 is loaded into the interrupt flag register (IFR).

Peripheral Control

Figure 91. External Interrupt Logic Diagram

RS

RS

SETC INTM

CLRC INTM From Data Bus

From Data Bus

Q D IMR

R S

INTM Priority Decode INTn D Q Q D Q Q D Q Q D Q Q D Q Q R S CLKOUT Q IFR to PC Interrupt Processor Interrupt Active IACK

Machine State

The C5x devices sample the external interrupt pins multiple times to avoid noise-generated interrupts. To detect an active interrupt, the C5x must sample the signal low on at least three consecutive machine cycles. Once an interrupt is detected, the C5x must sample the signal high on at least two consecutive machine cycles to be able to detect another interrupt. The external interrupt pins are sampled on the rising edge of CLKOUT1. If the external interrupts are running asynchronously, the pulses should be stretched to guarantee three consecutive low samples. Note that if the CPU is in IDLE2 mode, an interrupt input must be high for at least four CLKOUT1 cycles and low for a minimum of five CLKOUT1 cycles to be properly recognized. If the INTM bit and mask register are properly enabled, the interrupt signal is accepted by the processor. INTM is set and the appropriate IFR bit is cleared when the INTR instruction is jammed into the pipeline, and then after three CLKOUT1 cycles, IACK is generated (see Figure 49 on page 4-44). NMI uses the same logic as for INT1INT4, except that NMI is not affected by the status of the interrupt mask register (IMR) or the INTM bit.

On-Chip Peripherals

9-5

Peripheral Control

9.1.3

Peripheral Reset
A number of actions occur when the C5x is reset. Section 4.9, Reset, on page 4-45 describes the events that occur when the C5x is reset. On a device reset, the central processing unit (CPU) sends an SRESET signal to the peripheral circuits. The SRESET signal affects the peripheral circuits in the following ways: 1) The two software wait-state registers (IOWSR and PDWSR) are set to FFFFh, causing all external accesses to occur with seven wait states. The CWSR is loaded with 0Fh. 2) The FO bits of the SPC and TSPC/BSPC are cleared, which selects a word length of 16 bits for each serial port. 3) The FSM bits of the SPC and TSPC/BSPC are cleared. The FSM bit must be set for operation with frame sync pulses. 4) The TXM bits of the SPC and TSPC/BSPC are cleared, which configures the FSX and TFSX pins as inputs. 5) The SPC and TSPC/BSPC are loaded with 0y00h, where the two MSBs of y are 102 and the two LSBs of y reflect the current levels on the transmit and receive clock pins of the respective port. 6) The TIM and PRD are loaded with FFFFh. The TDDR and TSS fields of the TCR are cleared and the timer starts. 7) On the HPI, HINT and SMOD are cleared while in reset, and then set after reset goes high. Refer to Section 4.9 for further details of reset operation.

9-6

Clock Generator

9.2 Clock Generator

The C5x clock generator consists of an internal oscillator and a phase lock loop (PLL) circuit that provides the flexibility for the system designer to select the clock source. The clock generator is driven by a crystal resonator circuit or by an external clock source.

9.2.1

Standard Clock Options (C50, C51, C52, C53, and C53S only)
Table 92 lists the standard clock options available. When the internal divideby-2 option is selected, the internal oscillator is enabled by connecting a crystal across the X1 and X2/CLKIN pins. The frequency of CLKOUT1 is one-half the crystal oscillating frequency. When the external divide-by-2 option is selected, the external clock source is connected directly to the X2/CLKIN pin and the X1 pin is unconnected. The external frequency is divided by two to generate the internal machine cycle. When the PLL option is selected, the external clock source is connected directly to the CLKIN2 pin, the X1 pin is disconnected from VDD, and the X2/CLKIN pin is connected to VDD. For the C50, C51, C53, and C53S, the external frequency is multiplied by one to generate the internal machine cycle. For the C52, the external frequency is multiplied by two to generate the internal machine cycle.

Table 92. Standard Clock Options (C50, C51, C52, C53, and C53S only)

CLKMD1 0 0 1 CLKMD2 0 1 0 Clock Mode External divide-by-2 option with internal oscillator disabled. Reserved for test purposes. PLL clock generator option. - For C50, C51, C53, and C53S: multiply-by-1 option - For C52: multiply-by-2 option External divide-by-2 option or internal divide-by-2 option with an external crystal. 1 1

On-Chip Peripherals

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Clock Generator

9.2.2

PLL Clock Options (LC56, C57S, and LC57 only)

Table 93 lists the PLL clock options available. The PLL circuit provides the capability to supply lower external frequency sources than the machine cycle rate of the CPU. This is a desirable feature because it reduces a systems highfrequency noise that is due to a high-speed switching clock. When the PLL option is selected, the external clock source is connected directly to the X2/CLKIN pin. The PLL has a maximum operating frequency of 28.6 MHz (on a 35-ns C5x device). The PLL requires a transitory locking time which is specified in the TMS320C5x data sheet. When the device is in idle2 power-down mode or in stop mode, the PLL stops; in idle power-down mode, the PLL continues operating. See the TMS320C5x data sheet for more information on the external input frequency specification. Note that the clock mode should not be reconfigured with the clock mode pins during the normal operation. During the idle2 mode, the clock mode can be reconfigured after CLKOUT1 settling high.

Table 93. PLL Clock Options (LC56, C57S, and LC57 only)

9-8

CLKMD1 0 0 0 0 1 1 1 1 CLKMD2 0 0 1 1 0 0 1 1 CLKMD3 0 1 0 1 0 1 0 1 Clock Mode PLL multiply-by-3 option External divide-by-2 option with internal oscillator disabled PLL multiply-by-4 option PLL multiply-by-2 option PLL multiply-by-5 option PLL multiply-by-1 option PLL multiply-by-9 option External divide-by-2 option or internal divideby-2 option with an internal oscillator enabled

Timer

9.3 Timer
The timer is an on-chip down counter that can be used to periodically generate CPU interrupts. Figure 92 shows a logical block diagram of the timer. The timer is driven by a prescaler which is decremented by 1 at every CLKOUT1 cycle. A timer interrupt (TINT) is generated each time the counter decrements to 0. The timer provides a convenient means of performing periodic I/O or other functions. When the timer is stopped (TSS = 1), the internal clocks to the timer are shut off, allowing the circuit to run in a low-power mode of operation.

Figure 92. Timer Block Diagram

SRESET TRB

PRD

TDDR

TIM Borrow

PSC Borrow

CLKOUT1 TSS

TINT TOUT

9.3.1

Timer Registers
The timer operation is controlled via the timer control register (TCR), the timer counter register (TIM), and the timer period register (PRD). Figure 93 shows and Table 94 describes the TCR bit fields.

On-Chip Peripherals

9-9

Timer

Figure 93. Timer Control Register (TCR) Diagram

1512 11 10 96 5 4 30 Reserved Soft Free PSC TRB TSS TDDR

Table 94. Timer Control Register (TCR) Bit Summary

Bit 1512 11

Name Reserved Soft

Reset value 0

Function These bits are reserved and are always read as 0. This bit is used in conjunction with the Free bit to determine the state of the timer when a halt is encountered. When the Free bit is cleared, the Soft bit selects the emulation mode. Soft = 0 Soft = 1 The timer stops immediately. The timer stops after decrementing to zero.

10

Free

This bit is used in conjunction with the Soft bit to determine the state of the timer when a halt is encountered. When the Free bit is cleared, the Soft bit selects the emulation mode. Free = 0 Free = 1 The Soft bit selects the timer mode. The timer runs free regardless of the Soft bit.

96

PSC

Timer prescaler counter bits. These bits specify the count for the on-chip timer. When the PSC is decremented past 0 or the timer is reset, the PSC is loaded with the contents of the TDDR, and the TIM is decremented. Timer reload bit. This bit resets the on-chip timer. When the TRB is set, the TIM is loaded with the value in the PRD and the PSC is loaded with the value in the TDDR. The TRB is always read as a 0. Timer stop status bit. This bit stops or starts the on-chip timer. At reset, the TSS bit is cleared and the timer immediately starts timing.Note that due to timer logic implementation, two successive writes of one to the TSS bit are required to properly stop the timer. TSS = 0 TSS = 1 The timer is started. The timer is stopped.

TRB

TSS

30

TDDR

0000

Timer divide-down register bits. These bits specify the timer divide-down ratio (period) for the on-chip timer. When the PSC bits are decremented past 0, the PSC is loaded with the contents of the TDDR.

9-10

Timer

9.3.2

Timer Operation
When the PSC decrements to 0 or when the timer is reset by setting the TRB bit, the contents of the TDDR are loaded into the PSC and the TIM is decremented. When the TIM decrements to 0 or when the timer is reset by setting the TRB bit, the contents of the PRD are loaded into the TIM. The TRB bit is always read as 0. When a 1 is written to the TRB, the timer is reset, but TRB is still read as 0. Note: The current value in the timer can be read by reading the TIM; the PSC can be read by reading the TCR. Because it takes two instructions to read both registers, there may be a change between the two reads as the counter decrements. Therefore, when making precise timing measurements, it may be more accurate to stop the timer to read these two values. Due to timer logic implementation, two instructions are also required to properly stop the timer; therefore, two successive writes of one to the TSS bit should be made when the timer must be stopped. The timer interrupt (TINT) rate is given by: TINT rate + 1 t c(C) u v + t c(C) 1 (TDDR ) 1) (PRD ) 1)

where tc(C) is the period of CLKOUT1, u is the sum of the TDDR contents + 1, and v is the sum of the PRD contents + 1. The TINT rate equals the CLKOUT1 frequency divided by two independent factors. The two divisors are implemented with a down counter and period register (see Figure 92 on page 9-9) in each stage. The PSC and TDDR fields of the TCR are used for the first stage and the TIM and PRD are used for the second stage. Each time a down counter (PSC or TIM) decrements to 0, a borrow is generated on the next CLKOUT1 cycle, and the down counter is reloaded with the contents of its corresponding period register (TDDR or PRD). The output of the second stage is the TINT signal sent to the CPU and to the timer output (TOUT) pin. The width of the borrow pulse that appears on the output of the second stage equals tc(C). The timer can be used to generate a sample clock for an analog interface. Example 91 uses the timer to generate a sample rate of 50 kHz. Consider an analog-to-digital converter operating at this sample rate. Example 92 shows a typical interrupt service routine (ISR).
On-Chip Peripherals
9-11

Timer

Example 91. Code Initialization for Generating a 50-kHz Clock Signal

*Clkin frequency = 20 MHz, timer is running at 10 MHz. * LDP #0 SPLK #199,PRD ;Load timer period for 20 us period. OPL #8,IMR ;Set timer interrupt mask bit SPLK #20h,TCR ;reload and start timer. SPLK #1000b,IFR ;Clear any pending timer interrupts. CLRC INTM ;global interrupt enable. *

Example 92. Interrupt Service Routine for a 50-kHz Sample Rate

*50 kHz sample rate A/D interrupt service routine * TIMER_ISR MAR *,AR3 ;Use auxiliary register reserved for ;timer ISR. IN *,14 ;Read A/D. RETE ;Reenable interrupts and return. *

9-12

Software-Programmable Wait-State Generators

9.4 Software-Programmable Wait-State Generators

The software-programmable wait-state generators can extend external bus cycles by up to seven machine cycles. This operation provides a convenient means to interface the C5x to external devices that do not satisfy the fullspeed access-time requirement of the C5x. Devices that require more than seven wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generators are shut off; shutting off the internal clocks allows this circuitry to run with lower power consumption. Note: The wait-state generators affect external accesses only. Two 16-bit wait-state registers and a 5-bit control register control the softwareprogrammable wait-state generators. Each of the three external spaces (program, data, and I/O spaces) has an assigned field in a software wait-state register.

9.4.1

Program/Data Wait-State Register (PDWSR)

The program and data memory spaces each consist of 64K word addresses. You can view each 64K-word space as being composed of four 16K-word blocks. Each 16K-word block in program and data space is associated with a 2-bit wait-state field in the PDWSR, as shown in Figure 94 and listed in Table 95. The value of the 2-bit field in PDWSR specifies the number of wait states to be inserted for each access in the given address range. At reset, the PDWSR is set to FFFFh.

Figure 94. Program/Data Wait-State Register (PDWSR) Diagram (C50, C51, and C52 only)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data 4 Data 3 Data 2 Data 1 Program 4 Program 3 Program 2 Program 1

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Software-Programmable Wait-State Generators

Table 95. Program/Data Wait-State Register (PDWSR) Address Ranges (C50, C51, and C52 only)

Figure 95. Program/Data Wait-State Register (PDWSR) Diagram (C53S, LC56, and C57 only)

159

Reserved

Table 96. Program/Data Wait-State Register (PDWSR) Address Ranges (C53S, LC56, and C57 only)
Wait-State Field Bits 159 86 53 20 Space Hex Address Range

9-14

PDWSR Bits 1514 1312 1110 98 76 54 32 10 Memory Space Data 4 Data 3 Data 2 Data 1 Hex Address Range C000FFFF 8000BFFF 40007FFF 00003FFF Program 4 Program 3 Program 2 Program 1 C000FFFF 8000BFFF 40007FFF 00003FFF 86 I/O 53 Data

The C53S, LC56, and C57 implement a simpler version of the software wait states. Program, data, and I/O space wait states are specified by a single waitstate value. All external addresses in each space may be independently set from 0 to 7 wait states by the 3-bit wait-state field in the PDWSR, as shown in Figure 95 and listed in Table 96.

20

Program

Reserved I/O 0000FFFF 0000FFFF 0000FFFF Data Program

Software-Programmable Wait-State Generators

Note that if the on-chip wait-state generator is used to add wait states for external accesses, the number of CLKOUT1 cycles required for writes is not effected until two or more wait states are specified, contrary to wait states generated with the external READY input. Table 97 shows the number of cycles required for the different types of external device accesses. Also, note that the external READY input is sampled only after the internal software wait states are completed. Therefore, if the READY input is driven low before the completion of the internal software wait states, no wait states are added to the external memory access until the specified number of software wait states is completed. Wait states are only added if the READY input is still low after the software wait states are completed. Additionally, it should be noted that the READY input is not an asynchronous input and input setup and hold times for this signal as specified in the TMS320C5x data sheet must be met or significant device malfunction will result.

Table 97. Number of CLKOUT1 Cycles per Access for Various Numbers of Wait States
Number of CLKOUT1 Cycles Hardware Wait State Number of Wait States 0 1 2 3 Read 1 2 3 4 Write 2n + 1 3n + 1 4n + 1 5n + 1 Software Wait State Read 1 2 3 4 Write 2n + 1 2n + 1 3n + 1 4n + 1

Where n is the number of consecutive write cycles.

On-Chip Peripherals

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Software-Programmable Wait-State Generators

9.4.2

I/O Wait-State Register (IOWSR)

The I/O space consists of 64K word addresses. The IOWSR, shown in Figure 96, can be mapped in either of two ways, as specified by the BIG bit in the wait-state control register (CWSR). The value of the 2-bit field in IOWSR specifies the number of wait states to be inserted for each access in the given port or address range (Table 98). At reset, the IOWSR is set to FFFFh. If the BIG bit is cleared, each of eight pairs of memory-mapped I/O ports is associated with a 2-bit wait-state field in IOWSR. The value of the 2-bit field in IOWSR specifies the number of wait states to be inserted for each access in the given port. The entire I/O space is configured with wait states on 2-word boundaries (that is, port 0/1, port 10/11, and port 20/21 all have the same number of wait states). This configuration provides maximum flexibility when I/O bus-cycles access peripherals such as D/A and A/D devices. If the BIG bit is set, the 64K-word space is divided into eight 8K-word blocks. Each 8K-word block in I/O space is associated with a 2-bit wait-state field in the IOWSR. The value of the 2-bit field in IOWSR specifies the number of wait states to be inserted for each access in the given address range.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I/O 8 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1

Figure 96. I/O Port Wait-State Register (IOWSR) Diagram

Table 98. I/O Port Wait-State Register (IOWSR) Address Ranges

Wait-State Field Bits 01 23 45 67 89 I/O Space I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8

Ports/Hex Address Range

BIG = 0

BIG = 1

Port 0/1, port 10/11, etc.

00001FFF 20003FFF 40005FFF 60007FFF 80009FFF

Port 2/3, port 12/13, etc. Port 4/5, port 14/15, etc. Port 6/7, port 16/17, etc. Port 8/9, port 18/19, etc.

1011

Port 0A/0B, port 1A/1B, etc.

A000BFFF

1213 1415

Port 0C/0D, Port 1C/1D, etc. Port 0E/0F, Port 1E/1F, etc.

C000DFFF E000FFFF

9-16

Software-Programmable Wait-State Generators

9.4.3

Wait-State Control Register (CWSR)

The CWSR allows you to select one of two mappings of the IOWSR and one of two mappings between 2-bit wait-state fields and the number of wait states for the corresponding space in the PDWSR and IOWSR. The CWSR bit fields are shown in Figure 97 and described in Table 99. If a bit is cleared, the number of wait states for external accesses in that space is equal to the waitstate field value. If a bit is set, the number of wait states for external accesses in that space is determined by the wait-state field values listed in Table 910. Always program the CWSR before configuring the PDWSR and IOWSR to avoid configuring memory with too few wait states during the set-up of waitstate registers.

Figure 97. Wait-State Control Register (CWSR) Diagram

155 4 3 2 1 0 Reserved BIG I/O High I/O Low D P

Table 99. Wait-State Control Register (CWSR) Bit Summary

Bit Name Reset value 0 0 Function These bits are reserved. This bit specifies how the IOWSR is mapped. BIG = 0 BIG = 1 3 I/O High 1 The IOWSR is divided into eight pairs of I/O ports with a 2-bit wait-state field assigned to each pair of ports. The I/O space is divided into eight 8K-word blocks with a 2-bit wait-state field assigned to each block.

155 Reserved 4 BIG

This bit is used in conjunction with the 2-bit wait-state field in the IOWSR to determine the number of wait states for the I/O space upper half (I/O 5I/O 8). See Table 910 for the wait state configurations. I/O High = 0 I/O High = 1 The number of wait states assigned to the I/O space upper half is 0, 1, 2, or 3. The number of wait states assigned to the I/O space upper half is 0, 1, 3, or 7.

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Software-Programmable Wait-State Generators

Table 99. Wait-State Control Register (CWSR) Bit Summary (Continued)

Bit 2 Name I/O Low Reset value 1 Function This bit is used in conjunction with the 2-bit wait-state field in the IOWSR to determine the number of wait states for the I/O space lower half (I/O 1I/O 4). See Table 910 for the wait state configurations. I/O Low = 0 I/O Low = 1 1 D 1 The number of wait states assigned to the I/O space lower half is 0, 1, 2, or 3. The number of wait states assigned to the I/O space lower half is 0, 1, 3, or 7.

Data memory space bit. This bit is used in conjunction with the 2-bit wait-state field in the PDWSR to determine the number of wait states for the data memory space. See Table 910 for the wait state configurations. D=0 D=1 The number of wait states assigned to the data memory space is 0, 1, 2, or 3. The number of wait states assigned to the data memory space is 0, 1, 3, or 7.

Program memory space bit. This bit is used in conjunction with the 2-bit wait-state field in the PDWSR to determine the number of wait states for the program memory space. See Table 910 for the wait state configurations. P=0 P=1 The number of wait states assigned to the program memory space is 0, 1, 2, or 3. The number of wait states assigned to the program memory space is 0, 1, 3, or 7.

Table 910. Wait-State Field Values and Number of Wait States as a Function of CWSR Bits 03

9-18

Wait-State Field of PDWSR or IOWSR 00 01 10 11 No. of Wait States (CWSR Bit 03 = 0) 0 1 2 3 No. of Wait States (CWSR Bit 03 = 1) 0 1 3 7
This bit field corresponds to the wait-state field bits in Figure 94 and Figure 96.

Software-Programmable Wait-State Generators

9.4.4

Logic for External Program Space

Figure 98 shows a block diagram of the wait-state generator logic for external program space. When an external program access is decoded, the appropriate field of the PDWSR is loaded into the counter. If the field is not 0002, a notready signal is sent to the CPU. The not-ready condition is maintained until the counter decrements to 0 and the external READY line is set high. The external READY and the wait-state READY are ORed to generate the CPU WAIT signal. The READY line is sampled at the rising edge of CLKOUT1. Note: The external READY line is sampled only at the last cycle of an external access if the on-chip wait-state generator is used to insert software wait states.

Figure 98. Software-Programmable Wait-State Generator Block Diagram

CPU PDWSR 01 23 45 67 C5x

PSEL A14 A15

G A B 2-to-4 Decoder

CYCLE

3-Bit Counter Carry

WAIT

READY

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9-19

External Logic

Y0 Y1 Y2 Y3

General-Purpose I/O Pins

9.5 General-Purpose I/O Pins

The C5x has two general-purpose pins that are software controlled. The branch control input (BIO) pin and the external flag output (XF) pin. For detailed timing specifications of BIO and XF signals, refer to the TMS320C5x data sheet.

9.5.1

Branch Control Input (BIO)

The BIO pin monitors peripheral device status especially as an alternative to an interrupt when time-critical loops must not be disturbed. A branch can be conditionally executed dependent upon the state of the BIO input. The timing diagram, shown in Figure 99, shows the BIO operation (refer to the TMS320C5x data sheet for actual timing specifications). This timing diagram is for a sequence of single-cycle, signal-word instructions located in external memory. When used with the XC instruction, the BIO condition is tested during the decode (second) phase of the pipeline; all other instructions (BCND, BCNDD, CC, CCD, RETC, and RETCD), test BIO during the execute (fourth) phase of the pipeline.

Figure 99. BIO Timing Diagram

CLKOUT1 Setup BIO Pulse width

Hold

9-20

General-Purpose I/O Pins

9.5.2

External Flag Output (XF)

The XF pin signals to external devices via software. It is set high by the SETC XF instruction and reset low by the CLRC XF instruction. XF is set high at device reset. Figure 910 shows the relationship between the time the SETC or CLRC instruction is fetched, and the time the XF pin is set or reset (refer to the TMS320C5x data sheet for actual timing specifications). The timing diagram is for a sequence of single-cycle, single-word instructions located in external memory. Actual timing can vary with different instruction sequences.

Figure 910. XF Timing Diagram

CLKOUT1 SETC XF/CLRC XF FETCH XF Delay

On-Chip Peripherals

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Parallel I/O Ports

9.6 Parallel I/O Ports

The C5x has 64K parallel I/O ports. Sixteen of the 64K I/O ports are memorymapped in data page 0 as listed in Table 91 on page 9-2. You can access the 64K I/O ports using the IN and OUT instructions or any instruction that reads or writes a location in data memory space. Accesses to memorymapped I/O space are distinguished from program and data accesses by the IS signal going low; the DS signal is not active, even though the I/O port is actually accessed through data space. The following example shows how to use direct addressing to access an I/O device on port 51h:
SACL 51h ;(DP = 0) Store accumulator to external ;device on port 81.

The RD signal can be used in conjunction with chip-select logic to generate an output enable signal for an external peripheral. The WE signal can be used in conjunction with chip-select logic to generate a write enable signal for an external peripheral. Figure 911 shows a typical I/O port interface circuitry. The decode section can be simplified if fewer I/O ports are used.

Figure 911.I/O Port Interface Circuitry

+5 V IS A3 A0 A1 A2

G1 G2A G2B A B C AS138

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7

CS Input Device OE WE

RD WE Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 AS138 Port 8 Port 9 Port A Port B Port C Port D Port E Port F

Output Device CS

TMS320C5x

G1 G2A G2B A B C

9-22

Serial Port Interface

9.7 Serial Port Interface

Several C5x devices implement a variety of types of flexible serial port interfaces. These serial port interfaces provide full duplex, bidirectional, communication with serial devices such as codecs, serial analog to digital (A/D) converters, and other serial systems. The serial port interface signals are directly compatible with many industry-standard codecs and other serial devices. The serial port may also be used for interprocessor communication in multiprocessing applications (the time-division multiplexed (TDM) serial port is especially optimized for multiprocessing). Three different types of serial port interfaces are available on C5x devices. The basic standard serial port interface (SP) is implemented on all C5x devices. The TDM serial port interface is implemented on the C50, C51, and C53 devices. The C56 and C57 devices include the buffered serial port (BSP), which implements an automatic buffering feature that greatly reduces CPU overhead required in handling serial data transfers. See Table 11 on page 1-6 for information about features included in various C5x devices. The BSP operates in either autobuffering or nonbuffered mode. When operated in nonbuffered (or standard) mode, the BSP functions the same as the basic standard serial port (except where specifically indicated) and is described in this section. The TDM serial port operates in either TDM or non-TDM mode. When operated in non-TDM (or standard) mode, the TDM serial port also functions the same as the basic standard serial port and is described in this section. The BSP also implements several enhanced features in standard mode, and these features, as well as operation of the BSP in autobuffering mode, are described in Section 9.8, Buffered Serial Port (BSP) Interface, on page 9-53. Therefore, when using the C56 or C57 devices, Section 9.8 should be consulted. Operation of the TDM serial port in TDM mode is described in Section 9.9, Time-Division Multiplexed (TDM) Serial Port Interface, on page 9-74. Note that the BSP and TDM serial ports initialize to a standard serial port compatible mode upon reset. In all C5x serial ports, both receive and transmit operations are double-buffered, thus allowing a continuous communications stream with either 8- or 16-bit data packets. The continuous mode provides operation that, once initiated, requires no further frame synchronization pulses (FSR and FSX) when transmitting at maximum packet frequency. The serial ports are fully static and thus will function at arbitrarily low clocking frequencies. The maximum operating frequency for the standard serial port of one-fourth of CLKOUT1 (5M bps at 50 ns, 7.14M bps at 35 ns) is achieved when using internal serial port clocks. The maximum operating frequency for the BSP is CLKOUT1. When the serial
On-Chip Peripherals
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Serial Port Interface

ports are in reset, the device may be configured to turn off the internal serial port clocks, allowing the device to run in a lower power mode of operation.

9.7.1

Serial Port Interface Registers

The serial port operates through the three memory-mapped registers (SPC, DXR, and DRR) and two other registers (RSR and XSR) that are not directly accessible to the program, but are used in the implementation of the doublebuffering capability. These five registers are listed in Table 911.

9-24

Address 0020h 0021h 0022h Register DRR DXR SPC Description Data receive register Data transmit register Serial port control register Receive shift register RSR XSR Data transmit shift register - Data receive register (DRR). The 16-bit memory-mapped data receive

Table 911. Serial Port Registers

register (DRR) holds the incoming serial data from the RSR to be written to the data bus. At reset, the DRR is cleared.

- Data transmit register (DXR). The 16-bit memory-mapped data transmit

register (DXR) holds the outgoing serial data from the data bus to be loaded in the XSR. At reset, the DXR is cleared.
- Serial port control register (SPC). The 16-bit memory-mapped serial port

control register (SPC) contains the mode control and status bits of the serial port.
- Data receive shift register (RSR). The 16-bit data receive shift register

(RSR) holds the incoming serial data from the serial data receive (DR) pin and controls the transfer of the data to the DRR.
- Data transmit shift register (XSR). The 16-bit data transmit shift register

(XSR) controls the transfer of the outgoing data from the DXR and holds the data to be transmitted on the serial data transmit (DX) pin. During normal serial port operation, the DXR is typically loaded with data to be transmitted on the serial port by the executing program, and its contents read automatically by the serial port logic to be sent out when a transmission is initiated. The DRR is loaded automatically by the serial port logic with data received on the serial port and read by the executing program to retrieve the received data.

Serial Port Interface

At times during normal serial port operation, however, it may be desirable for a program to perform other operations with the memory-mapped serial port registers besides simply writing to DXR and reading from DRR. On the SP, the DXR and DRR may be read or written at any time regardless of whether the serial port is in reset or not. On the BSP, access to these registers is restricted; the DRR can only be read, and the DXR can only be written when autobuffering is disabled (see subsection 9.8.2, Autobuffering Unit (ABU) Operation, on page 9-60). The DRR can only be written when the BSP is in reset. The DXR can be read at any time. Note, however, that on both the SP and the BSP, care should be exercised when reading or writing to these registers during normal operation. With the DRR, since, as mentioned previously, this register is written automatically by the serial port logic when data is received, if a write to DRR is performed, subsequent reads may not yield the result written if a serial port receive occurs after the write but before the read is performed. With the DXR, care should be exercised when this register is written, since if previously written contents intended for transmission have not yet been sent, these contents will be overwritten and the original data lost. As mentioned previously, the DXR can be read at any time. Alternatively, DXR and DRR may also serve as general purpose storage if they are not required for serial port use. If these registers are to be used for general purpose storage, the transmit and/or receive sections of the serial port should be disabled either by tying off (by pulling up or down, whichever is appropriate) external input pins which could spuriously cause serial port transfers, or by putting the port in reset.

9.7.2

Serial Port Interface Operation

This section describes operation of the basic standard serial port interface, which includes operation of the TDM and BSP serial ports when configured in standard mode. Table 912 lists the pins used in serial port operation. Figure 912 shows these pins for two C5x serial ports connected for a oneway transfer from device 0 to device 1. Only three signals are required to connect from a serial port transmitter to a receiver for data transmission. The transmitted serial data signal (DX) sends the actual data. The transmit frame synchronization signal (FSX) initiates the transfer (at the beginning of the packet), and the transmit clock signal (CLKX) clocks the bit transfer. The corresponding pins on the receive device are DR, FSR and CLKR, respectively.
On-Chip Peripherals
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Serial Port Interface

Table 912. Serial Port Pins

Figure 912. One-Way Serial Port Transfer

C5x Device 0

9-26

Pin Description CLKR CLKX DR DX Receive clock signal Transmit clock signal Received serial data signal Transmitted serial data signal FSR FSX Receive framing synchronization signal Transmit frame synchronization signal C5x Device 1 DX FSX CLKX DR FSR CLKR

Figure 913 shows how the pins and registers are configured in the serial port logic and how the double-buffering is implemented. Transmit data is written to the DXR, while received data is read from the DRR. A transmit is initiated by writing data to the DXR, which copies the data to the XSR when the XSR is empty (when the last word has been transmitted serially, that is, driven on the DX pin). The XSR manages shifting the data to the DX pin, thus allowing another write to DXR as soon as the DXR-to-XSR copy is completed. During transmits, upon completion of the DXR-to-XSR copy, a 0-to-1 transition occurs on the transmit ready (XRDY) bit in the SPC. This 0-to-1 transition generates a serial port transmit interrupt (XINT) that signals that the DXR is ready to be reloaded. See Section 4.8, Interrupts, on page 4-36 and subsection 9.1.2, External Interrupts, on page 9-4 for more information on C5x interrupts.

Serial Port Interface

Figure 913. Serial Port Interface Block Diagram

Data Bus 16 (Load) Load Control Logic 16 DXR (16) 16 Load Control Logic RSR (16) (Clear) Byte/Word Counter (Clock) (Clear) (Clock) Byte/Word Counter (Load) XINT on DXR-XSR transfer

DRR (16) 16 RINT on RSR-DRR transfer

XSR (16)

FSR DR

FSX DX

CLKR CLKX

The process is similar in the receiver. Data from the DR pin is shifted into the RSR, which is then copied into the DRR from which it may be read. Upon completion of the RSR-to-DRR copy, a 0-to-1 transition occurs on the receive ready (RRDY) bit in the SPC. This 0-to-1 transition generates a serial port receive interrupt (RINT). Thus, the serial port is double-buffered because data can be transferred to or from DXR or DRR while another transmit or receive is being performed. Note that transfer timing is synchronized by the frame sync pulse in burst mode (discussed in more detail in subsection 9.7.4, Burst Mode Transmit and Receive Operations, on page 9-37).

9.7.3

Setting the Serial Port Configuration

The SPC contains control bits which configure the operation of the serial port. The SPC bit fields are shown in Figure 914 and described in Table 913. Note that seven bits in the SPC are read only and the remaining nine bits are read/write.

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Figure 914. Serial Port Control Register (SPC) Diagram

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Free
R/W

Soft RSRFULL XSREMPTY XRDY RRDY

R/W R R R R

IN1
R

IN0 RRST XRST TXM MCM FSM

R R/W R/W R/W R/W R/W

FO

DLB
R/W

Res
R

R/W

Note:

R = Read, W = Write

Table 913. Serial Port Control Register (SPC) Bit Summary

Bit Name 15 Free Reset Value 0 Function This bit is used in conjunction with the Soft bit to determine the state of the serial port clock when a halt is encountered. See Table 914 on page 9-37 for the serial port clock configurations. Free = 0 Free = 1 14 Soft 0 The Soft bit selects the emulation mode. The serial port clock runs free regardless of the Soft bit.

This bit is used in conjunction with the Free bit to determine the state of the serial port clock when a halt is encountered. When the Free bit is cleared to 0, the Soft bit selects the emulation mode. See Table 914 on page 9-37 for the serial port clock configurations. Soft = 0 Soft = 1 The serial port clock stops immediately, thus aborting any transmission. The clock stops after completion of the current transmission.

13

RSRFULL

Receive Shift Register Full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when RSR is full and DRR has not been read since the last RSR-to-DRR transfer. On the SP, when FSM = 1, the occurrence of a frame sync pulse on FSR qualifies the generation of RSRFULL = 1. When FSM = 0, and on the BSP, only the basic two conditions apply; that is, RSRFULL goes high without waiting for an FSR pulse. RSRFULL = 0 Any one of the following three events clears the RSRFULL bit to 0: reading DRR, resetting the receiver (RRST bit to 0), or resetting the device. The port has recognized an overrun. When RSRFULL = 1, the receiver halts and waits for DRR to be read, and any data sent on DR is lost. On the SP, the data in RSR is preserved; on the BSP, the contents of RSR are lost.

RSRFULL = 1

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Table 913. Serial Port Control Register (SPC) Bit Summary (Continued)
Bit Name 12 XSREMPTY Reset Value 0 Function Transmit Shift Register Empty. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when XSR is empty and DXR has not been loaded since the last DXR-to-XSR transfer. XSREMPTY = 0 Any one of the following three events clears the XSREMPTY bit to 0: underflow has occurred, resetting the transmitter (XRST bit to 0), or resetting the device. On the SP, XSREMPTY is deactivated (set to 1) directly as a result of writing to DXR; on the BSP, XSREMPTY is only deactivated after DXR is loaded followed by the occurrence of an FSX pulse.

XSREMPTY = 1

11

XRDY

Transmit Ready. A transition from 0 to 1 of the XRDY bit indicates that the DXR contents have been copied to XSR and that DXR is ready to be loaded with a new data word. A transmit interrupt (XINT) is generated upon the transition. This bit can be polled in software instead of using serial port interrupts. Note that on the SP, XRDY is generated directly as a result of writing to DXR; while on the BSP, XRDY is only generated after DXR is loaded followed by the occurrence of an FSX pulse. At reset or serial port transmitter reset (XRST = 0), the XRDY bit is set to 1. Receive Ready. A transition from 0 to 1 of the RRDY bit indicates that the RSR contents have been copied to the DRR and that the data can be read. A receive interrupt (RINT) is generated upon the transition. This bit can be polled in software instead of using serial port interrupts. At reset or serial port receiver reset (RRST = 0), the RRDY bit is cleared to 0. Input 1. This bit allows the CLKX pin to be used as a bit input. IN1 reflects the current level of the CLKX pin of the device. When CLKX switches levels, there is a latency of between 0.5 and 1.5 CLKOUT1 cycles before the new CLKX value is represented in the SPC. Input 0. This bit allows the CLKR pin to be used as a bit input. IN0 reflects the current level of the CLKR pin of the device. When CLKR switches levels, there is a latency of between 0.5 and 1.5 CLKOUT1 cycles before the new CLKR value is represented in the SPC. Receive Reset. This signal resets and enables the receiver. When a 0 is written to the RRST bit, activity in the receiver halts. RRST = 0 RRST = 1 The serial port receiver is reset. Writing a 0 to RRST clears the RSRFULL and RRDY bits to 0. The serial port receiver is enabled.

10

RRDY

IN1

IN0

RRST

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Table 913. Serial Port Control Register (SPC) Bit Summary (Continued)
Bit Name 6 XRST Reset Value 0 Function Transmitter Reset. This signal is used to reset and enable the transmitter. When a 0 is written to the XRST bit, activity in the transmitter halts. When the XRDY bit is 0, writing a 0 to XRST generates a transmit interrupt (XINT). XRST = 0 The serial port transmitter is reset. Writing a 0 to XRST clears the XSREMPTY bit to 0 and sets the XRDY bit to 1. The serial port transmitter is enabled.

XRST = 1 5 TXM 0

Transmit Mode. This bit configures the FSX pin as an input (TXM = 0) or as an output (TXM = 1). TXM = 0

External frame sync. The transmitter idles until a frame sync pulse is supplied on the FSX pin. Internal frame sync. Frame sync pulses are generated internally when data is transferred from the DXR to XSR to initiate data transfers. The internally generated framing signal is synchronous with respect to CLKX.

TXM = 1

MCM

Clock Mode. This bit specifies the clock source for CLKX. MCM = 0 MCM = 1 CLKX is taken from the CLKX pin. CLKX is driven by an on-chip clock source. For the SP and the BSP in standard mode, this on-chip clock source is at a frequency of one-fourth of CLKOUT1. The BSP also allows the option of generating clock frequencies at additional ratios of CLKOUT1. For a detailed description of this feature, see Section 9.8, Buffered Serial Port (BSP) Interface, on page 9-53. Note that if MCM = 1 and DLB = 1, a CLKR signal is also supplied by the internal source.

FSM

Frame Sync Mode. This bit specifies whether frame synchronization pulses (FSX and FSR) are required after the initial frame sync pulse for serial port operation. See subsection 9.7.2, Serial Port Interface Operation, on page 9-25 for more details on the frame sync signals. FSM = 0

Continuous mode. Frame sync pulses are not required after the initial frame sync pulse, but they are not ignored; therefore, improperly timed frame syncs may cause errors in serial transfers. See subsection 9.7.6, Serial Port Interface Exception Conditions, on page 9-46 for information about serial port operation under various exception conditions. Burst mode. A frame sync pulse is required on FSX/FSR for the transmission/reception of each word.

FSM = 1

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Table 913. Serial Port Control Register (SPC) Bit Summary (Continued)
Bit Name 2 FO Reset Value 0 Function Format. This bit specifies the word length of the serial port transmitter and receiver. FO = 0 FO = 1 The data is transmitted and/or received as 16-bit words. The data is transferred as 8-bit bytes. The data is transferred with the MSB first. The BSP also allows the capability of 10and 12-bit transfers. For a detailed description of this feature, see Section 9.8, Buffered Serial Port (BSP) Interface, on page 9-53.

DLB

Digital Loopback Mode. This bit can be used to put the serial port in digital loopback mode. DLB = 0 DLB = 1 The digital loopback mode is disabled. The DR, FSR, and CLKR signals are taken from their respective device pins. The digital loopback mode is enabled. The DR and FSR signals are connected to DX and FSX, respectively, through multiplexers, as shown in Figure 915(a) and (b) on page 9-32. Additionally, CLKR is driven by CLKX if MCM = 1. If DLB = 1 and MCM = 0, CLKR is taken from the CLKR pin of the device. This configuration allows CLKX and CLKR to be tied together externally and supplied by a common external clock source. The logic diagram for CLKR is shown in Figure 915(c) on page 9-32. Note also that in DLB mode, the FSX and DX signals appear on the device pins, but FSR and DR do not. Either internal or external FSX signals may be used in DLB mode, as defined by the TXM bit.

Res

Reserved. Always read as a 0 in the serial port. This bit performs a function in the TDM serial port discussed in Section 9.9, Time-Division-Multiplexed (TDM) Serial Port Interface, on page 9-74.

Reserved Bit
Bit 0 is reserved and is read as 0, although it performs a function in the TDM serial port (discussed in Section 9.9, Time-Division-Multiplexed (TDM) Serial Port Interface, on page 9-74).

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DLB Bit
The DLB (bit 1) selects digital loopback mode, which allows testing of serial port code with a single C5x device. When DLB = 1, DR and FSR are connected to DX and FSX, respectively, through multiplexers, as shown in Figure 915. When in loopback mode, CLKR is driven by CLKX if on-chip serial port clock generation is selected (MCM = 1), but if MCM = 0, then CLKR is driven by the external CLKR signal. This allows for the capability of external serial port clock generation in digital loopback mode. If DLB = 0, then normal operation occurs where DR, FSR, and CLKR are all taken from their respective pins.

Figure 915. Receiver Signal MUXes

(a) DR 0 MUX FSR 0 MUX (b)

DR (internal) (c)

FSR (internal)

DX

1 CLKR DLB MUX 0

FSX

1 DLB

CLKR (internal)

CLKX

1 DLB MCM

FO Bit
The FO (bit 2) specifies whether data is transmitted as 16-bit words (FO = 0) or 8-bit bytes (FO = 1). Note that in the latter case, only the lower byte of whatever is written to DXR is transmitted, and the lower byte of data read from DRR is what was received. To transmit a whole 16-bit word in 8-bit mode, two writes to DXR are necessary, with the appropriate shifts of the value because the upper eight bits written to DXR are ignored. Similarly, to receive a whole 16-bit word in 8-bit mode, two reads from DRR are required, with the appropriate shifts of the value. In the SP, the upper eight bits of DRR are indeterminate in 8-bit receptions; in the BSP, the unused bits of DRR are sign-extended. Additionally, in the BSP, transfers of 10- and 12-bit words are provided for additional flexibility. For a detailed description of this feature, refer to Section 9.8, Buffered Serial Port (BSP) Interface, on page 9-53.
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FSM Bit
The FSM (bit 3) specifies whether or not frame sync pulses are required in consecutive serial port transmits. If FSM = 1, a frame sync must be present for every transfer, although FSX may be either externally or internally generated depending on TXM. This mode is referred to as burst mode, because there are normally periods of inactivity on the serial port between transmits. The frequency with which serial port transmissions occur is called packet frequency, and data packets can be 8, 10, 12, or 16 bits long. Therefore, as packet frequency increases, it reaches a maximum that occurs when the time, in serial port clock cycles, from one packet to the next, is equal to the number of bits being transferred. If transmission occurs at the maximum rate for multiple transfers in a row, however, frame sync essentially becomes redundant. Note that frame sync actually becomes redundant in burst mode only at maximum packet frequency with FSX configured as an output (TXM = 1). When FSX is an input (TXM = 0), its presence is required for transmissions to occur. FSM = 0 selects the continuous mode of operation which requires only an initial frame sync pulse as long as a write to DXR (for transmit), or a read from DRR (for receive), is executed during each transfer. Note that when FSM = 0, frame sync pulses are not required, but they are not ignored, therefore, improperly timed frame syncs may cause errors in serial transfers. The timing of burst and continuous modes is discussed in detail in subsections 9.7.4, 9.7.5, and 9.7.6.

MCM Bit
The serial port clock source is set by MCM (bit 4). If MCM = 0, CLKX is configured as an input and thus accepts an external clock. If MCM = 1, then CLKX is configured as an output, and is driven by an internal clock source. For the SP, and the BSP operating in standard mode, this on-chip clock is at a frequency of one-fourth of CLKOUT1. The BSP also allows the option of generating clock frequencies at additional ratios of CLKOUT1. For a detailed description of this feature, refer to Section 9.8, Buffered Serial Port (BSP) Interface, on page 9-53. Note that the CLKR pin is always configured as an input.

TXM Bit
The transmit frame synchronization pulse source is set by TXM (bit 5). Like MCM, if TXM = 1, FSX is configured as an output and generates a pulse at the beginning of every transmit. If TXM = 0, FSX is configured as an input, and accepts an external frame sync signal. Note that the FSR pin is always configured as an input.
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XRST and RRST Bits

The serial port transmitter and receiver are reset with XRST (bit 6) and RRST (bit 7). These signals are active low, so that if XRST = RRST = 0, the serial port is in a reset state. To reset and reconfigure the serial port, a total of two writes to the SPC are required.
- The first write to the SPC should: J write a 0 to the XRST and RRST bits J write the desired configuration to the remainder of the bits. - The second write to the SPC should: J write 1 to the XRST and RRST bits J resend the desired configuration to the remainder of the bits.

The second write takes the serial port out of reset. Note that the transmitter and receiver may be reset individually if desired. When a 0 is written to XRST or RRST, activity in the corresponding section of the serial port stops. This minimizes the switching and allows the device to operate with lower power consumption. When XRST = RRST = MCM = 0, power requirements are further reduced since CLKX is no longer driven as an output. Note that in IDLE2 mode, SP operation halts as with other parts of the C5x device. On the BSP, however, if the external serial port clock is being used, operation continues after an IDLE2 is executed. This allows power savings to still be realized in IDLE2 mode, while still maintaining operation of critical serial port functions if necessary (see Section 9.8, Buffered Serial Port (BSP) Interface, on page 9-53 for further information about BSP operation). It should also be noted that, on the SP, the serial port may be taken out of reset at any time. Depending on the timing of exiting reset, however, a frame sync pulse may be missed. On the BSP, for receive and transmit with external frame sync, a setup of at least one CLKOUT1 cycle plus 1/2 serial port clock cycle is required prior to FSX being sampled active in standard mode. In autobuffering mode, additional setup is required (see Section 9.8, Buffered Serial Port (BSP) Interface, on page 9-53 for further information about BSP initialization timing requirements).

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IN0 and IN1 Bits

IN0 (bit 8) and IN1 (bit 9) allow the CLKR and CLKX pins to be used as bit inputs. IN0 and IN1 reflect the current states of the CLKR and CLKX pins. The data on these pins can be sampled by reading the SPC. This can be accomplished using the BIT instruction (page 6-63), BITT instruction (page 6-65), or PLU instructions (Table 66 on page 6-14). Note that there is a latency of between 0.5 and 1.5 CLKOUT1 cycles in duration from CLKR/CLKX switching to the new CLKR/CLKX value being available in the SPC. Note that even if the serial port is reset, IN0 and IN1 can still be used as bit inputs, and DRR and DXR as general-purpose registers.

RRDY and XRDY Bits

Bits 1013 in the SPC are read-only status bits that indicate various states of serial port operation. Writes and reads of the serial port may be synchronized by polling RRDY (bit 10) and XRDY (bit 11), or by using the interrupts that they generate. A transition from 0 to 1 of the RRDY bit indicates that the RSR contents have been copied to the DRR and that the received data may be read. A receive interrupt (RINT) is generated upon this transition. A transition from 0 to 1 of the XRDY bit indicates that the DXR contents have been copied to XSR and that DXR is ready to be loaded with a new data word. A transmit interrupt (XINT) is generated upon this transition. Polling XRDY and RRDY in software may either substitute for or complement the use of serial port interrupts (both polling and interrupts may be used together if so desired). Note that with external FSX, on the SP, XSR is loaded directly as a result of loading DXR, while on the BSP, XSR is not loaded until an FSX occurs.

XSREMPTY Bit
The XSREMPTY (bit 12) indicates whether the transmitter has experienced underflow. XSREMPTY is an active low bit; therefore, when XSREMPTY = 0, an underflow has occurred. Any one of the following three conditions causes XSREMPTY to become active (XSREMPTY = 0):
- DXR has not been loaded since the last DXR-to-XSR transfer, and XSR

empties (the actual transition of XSREMPTY occurs after the last bit has been shifted out of XSR),
- or the transmitter is reset (XRST = 0), - or the C5x device is reset (RS = 0).

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When XSREMPTY = 0, the transmitter halts and stops driving DX (the DX pin is in a high-impedance state) until the next frame sync pulse. Note that underflow does not constitute an error condition in the burst mode, although it does in the continuous mode (error conditions are further discussed in subsection 9.7.6, Serial Port Interface Exception Conditions, on page 9-46). The following condition causes XSREMPTY to become inactive (XSREMPTY = 1):
- A write to DXR occurs on the SP, or on the BSP a write to DXR occurs fol-

lowed by an FSX pulse (see subsection 9.7.4, Burst Mode Transmit and Receive Operations, on page 9-37 for further information about transmit timing).

RSRFULL Bit
The RSRFULL (bit 13) indicates whether the receiver has experienced overrun. RSRFULL is an active high bit; therefore, when RSRFULL = 1, RSR is full. In burst mode (FSM = 1), all three of the following must occur to cause RSRFULL to become active (RSRFULL = 1):
- The DRR has not been read since the last RSR-to-DRR transfer, - RSR is full, - and a frame sync pulse appears on FSR.

In continuous mode (FSM = 0), and on the BSP, only the first two conditions are necessary to set RSRFULL:
- The DRR has not been read since the last RSR-to-DRR transfer - and RSR is full.

Therefore, in continuous mode, and on the BSP, RSRFULL occurs after the last bit has been received. When RSRFULL = 1, the receiver halts and waits for the DRR to be read, and any data sent on DR is lost. On the SP, the data in RSR is preserved; on the BSP, the RSR contents are lost. Any one of the following three conditions causes RSRFULL to become inactive (RSRFULL = 0):
- The DRR is read, - or the serial port is reset (RRST = 0), - or the C5x device is reset (RS = 0). 9-36

Serial Port Interface

Soft and Free Bits

Soft (bit 14) and Free (bit 15) are special emulation bits that determine the state of the serial port clock when a breakpoint is encountered in the high-level language debugger. If the Free bit is set to 1, then upon a software breakpoint, the clock continues to run (free runs) and data is still shifted out. When Free = 1, the Soft bit is a dont care. If the Free bit is cleared to 0, then the Soft bit takes effect. If the Soft bit is cleared to 0, then the clock stops immediately, thus aborting any transmission. If the Soft bit is set to 1 and a transmission is in progress, the transmission continues until completion of the transfer, and then the clock halts. These options are listed in Table 914. The receive side functions in a similar fashion. Note that if an option other than immediate stop (Soft = Free = 0) is chosen, the receiver continues running and an overflow error is possible. The default value for these bits is immediate stop.

Table 914. Serial Port Clock Configuration

Free 0 0 1
Note:

Soft 0 1 X

Serial Port Clock Configuration Immediate stop, clocks are stopped. (Reset values) Transmitter stops after completion of word. Receiver is not affected. Free run.

X = Dont care

9.7.4

Burst Mode Transmit and Receive Operations

In burst mode operation, there are periods of serial port inactivity between packet transmits. The data packet is marked by the frame sync pulse occurring on FSX (see Figure 916). On the transmit device, the transfer is initiated by a write to DXR. The value in DXR is then transferred to XSR, and, upon a frame sync pulse on FSX (generated internally or externally depending on TXM), the value in XSR is shifted out and driven on the DX pin. Note that on the SP, the DXR to XSR transfer occurs on the second rising edge of CLKX after DXR is loaded, while on the BSP this transfer does not occur until an FSX occurs, when FSX is external. When FSX is internal on the BSP, the DXR to XSR transfer and generation of FSX occur directly after loading DXR. On both the SP and the BSP, once XSR is loaded with the value from DXR, XRDY goes high, generating a transmit interrupt (XINT) and setting XSREMPTY to a 1.
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Figure 916. Burst Mode Serial Port Transmit Operation

CLKX FSX (TXM = 1) DX (FO = 1) XRDY (SP) XINT (SP) XSREMPTY (SP) XRDY (BSP) XINT (BSP) XSREMPTY (BSP) A1 MSB A2 A3 A4 A5 A6 A7 A8 LSB B1

DXR loaded XSR loaded (SP)

XSR loaded (BSP)

DXR reloaded

XSR reloaded (SP)

XSR reloaded (BSP)

Note that in both the SP and the BSP, DXR to XSR transfers occur only if the XSR is empty and the DXR has been loaded since the last DXR to XSR transfer. If DXR is reloaded before the old DXR contents have been transferred to XSR, the previous DXR contents are overwritten. Accordingly, unless overwriting DXR is intended, the DXR should only be loaded if XRDY = 1. This is assured if DXR writes are made only in response to a transmit interrupt or polling XRDY. It should be noted that in the following discussions, the timings are slightly different for internally (TXM = 1, FSX is an output) and externally (TXM = 0, FSX is an input) generated frame syncs. This distinction is made because in the former case, the frame sync pulse is generated by the transmitting device as a direct result of a write to DXR. In the latter case, there is no such direct effect. Instead, the transmitting device must write to DXR and wait for an externally generated frame sync. If internal frame sync pulse generation is selected (TXM = 1), a frame sync pulse is generated on the second rising edge of CLKX following a write to DXR. For externally generated frame syncs, the events described here will occur as soon as a properly timed frame sync pulse occurs (see the data sheet for detailed serial port interface timings).
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On the next rising edge of CLKX after FSX goes high, the first data bit (MSB first) is driven on the DX pin. Thus, if the frame sync pulse is generated internally (TXM = 1), there is a 2-CLKX cycle latency (approximately) after DXR is loaded, before the data is driven on the line. If frame sync is externally generated, data transmission is delayed indefinitely after a DXR load until the FSX pulse occurs (this is described in further detail later in this subsection). With the falling edge of frame sync, the rest of the bits are shifted out. When all the bits are transferred, DX enters a high-impedance state. At the end of each transmission, if DXR was not reloaded when XINT was generated, XSREMPTY becomes active (low) at this point, indicating underflow. With externally generated frame sync, if XSREMPTY is active and a frame sync pulse is generated, any old data in the DXR is transmitted. This is explained in detail in subsection 9.7.6, Serial Port Interface Exception Conditions, on page 9-46. Note that the first data bit transferred could have variable length if frame sync is generated externally and does not fall within one CLKX cycle (this is illustrated in Figure 917). Internally generated frame syncs are assured by C5x timings to be one CLKX cycle in duration.

Figure 917. Serial Port Transmit With Long FSX Pulse

CLKX

FSX

DX

MSB

MSB-1

MSB-2

Serial port transmit with external frame sync pulses is similar to that with internal frame sync, with the exception that transfers do not actually begin until the external frame sync occurs. If the external frame sync occurs many CLKX cycles after DXR is loaded, however, the double buffer is filled and frozen until frame sync appears. On the SP (Figure 918), when the delayed frame sync occurs, A is transmitted on DX; after the transmit, a DXR-to-XSR copy of B occurs, XINT is generated, and again, the transmitter remains frozen until the next frame sync. When frame sync finally occurs, B is transmitted on DX. Note that when B is loaded into DXR, a DXR-to-XSR copy of B does not occur immediately because A has not been transmitted, and no XINT is generated. Any subsequent writes to DXR before the next delayed frame sync occurs overwrite B in the DXR.
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Figure 918. Burst Mode Serial Port Transmit Operation With Delayed Frame Sync in External Frame Sync Mode (SP)
CLKX FSX (TXM = 0) DX (F0 = 1) XRDY (SP) XINT (SP) XSREMPTY (SP) A1 MSB A7 A8 LSB B1 B2

DXR loaded with A

XSR loaded with A

DXR loaded with B

XSR loaded with B

On the BSP (Figure 919), since DXR was reloaded with B shortly after being loaded with A when the delayed frame sync finally occurs, B is transmitted on DX. After the transmit, the transmitter remains frozen until the next frame sync. When frame sync finally occurs, B is again transmitted on DX. Note that when B is loaded into DXR, a DXR-to-XSR copy of B does not occur immediately since the BSP requires a frame sync to initiate transmitting. Any subsequent writes to DXR before the next delayed frame sync occurs overwrite B in the DXR.

Figure 919. Burst Mode Serial Port Transmit Operation With Delayed Frame Sync in External Frame Sync Mode (BSP)
CLKX FSX (TXM = 0) DX (F0 = 1) XRDY (BSP) XINT (BSP) XSREMPTY (BSP) B1 MSB B7 B8 LSB B1 B2

DXR loaded with A

DXR loaded with B

XSR loaded with B

XSR loaded with B

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During a receive operation, shifting into RSR begins on the falling edge of the CLKR cycle after frame sync has gone low (as shown in Figure 920). Then, as the last data bit is being received, the contents of the RSR are transferred to the DRR on the falling edge of CLKR, and RRDY goes high, generating a receive interrupt (RINT).

Figure 920. Burst Mode Serial Port Receive Operation

CLKR FSR DR (FO = 1) RRDY RINT A1 MSB A2 A3 A4 A5 A6 A7 A8 LSB B1 B2

DRR Loaded From RSR

DRR Read

If the DRR from a previous receive has not been read, and another word is received, no more bits can be accepted without causing data corruption since DRR and RSR are both full. In this case, the RSRFULL bit is set indicating this condition. On the SP, this occurs with the next FSR; on the BSP, RSRFULL is set on the falling edge of CLKR during the last bit received. RSRFULL timing on both the SP and BSP is shown in Figure 921.

Figure 921. Burst Mode Serial Port Receive Overrun

CLKR FSR DR RRDY RINT RSRFULL(SP) RSRFULL(BSP) A1 MSB A8 LSB B1 MSB B8 LSB C1 MSB C2 C3 C4 C5

DRR loaded with A

Read A from DRR

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Unlike transmit underflow, overrun (RSRFULL = 1) constitutes an actual error condition. While DRR contents are preserved in overrun, its occurrence can often result in loss of other received data. Overrun is handled differently on the SP and on the BSP. On the SP, the contents of RSR are preserved on overrun, but since RSRFULL is not set to 1 until the next FSR occurs after the overflowing reception, incoming data usually begins being lost as soon as RSRFULL is set. Data loss can only be avoided if RSRFULL is polled in software and the DRR is read immediately after RSRFULL is set to 1. This is normally possible only if the CLKR frequency is slow with respect to CLKOUT1, since RSRFULL is set on the falling edge of CLKR during FSR, and data begins being received on the following rising edge of CLKR. The time available for polling RSRFULL and reading the DRR to avoid data loss is, therefore, only half of one CLKR cycle. On the BSP, RSRFULL is set on the last valid bit received, but the contents of RSR are never transferred to DRR, therefore, the complete transferred word in RSR is lost. If the DRR is read (clearing RSRFULL) before the next FSR occurs, subsequent transfers can be received properly. Overrun and various other serial port exception conditions such as the occurrence of frame sync during a receive are discussed in further detail in subsection 9.7.6, Serial Port Interface Exception Conditions, on page 9-46. If the serial port receiver is provided with FSR pulses significantly longer than one CLKR cycle, timing of data reception is effected in a similar fashion as with long FSX pulses. With long FSR pulses, however, the reception of all bits, including the first one, is simply delayed until FSR goes low. Serial port receive operation with a long FSR pulse is illustrated in Figure 922.

Figure 922. Serial Port Receive With Long FSR pulse

CLKR

FSR

DR

MSB

MSB-1

MSB-2

Note that if the packet transmit frequency is increased, the inactivity period between the data packets for adjacent transfers decreases to zero. This corresponds to a minimum period between frame sync pulses (equivalent to 8 or 16 CLKX/R cycles, depending on FO) that corresponds to a maximum packet frequency at which the serial port may operate. At maximum packet frequency, transmit timing is a compressed version of Figure 916, as shown in Figure 923.
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Figure 923. Burst Mode Serial Port Transmit at Maximum Packet Frequency
CLKX FSX (TXM = 1) DX (FO = 1) XRDY (SP) XINT (SP) XRDY (BSP) XINT (BSP)
A7 A8 B1 MSB B2 B3 B4 B5 B6 B7 B8 LSB C1 C2 C3 C4

DXR loaded XSR loaded (SP)

XSR loaded (BSP)

DXR reloaded

XSR reloaded (SP)

XSR reloaded (BSP)

At maximum packet frequency, the data bits in consecutive packets are transmitted contiguously with no inactivity between bits. The frame sync pulse overlaps the last bit transmitted in the previous packet. Maximum packet frequency receive timing is similar and is shown in Figure 924.

Figure 924. Burst Mode Serial Port Receive at Maximum Packet-Frequency

CLKR FSR DR (FO = 1) RRDY RINT A8 B1 MSB B2 B3 B4 B5 B6 B7 B8 LSB C1 C2 C3 C4 C5

DRR loaded from RSR

DRR read

DRR loaded from RSR

DRR read

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As shown in Figure 923 and Figure 924, with the transfer of multiple data packets at maximum packet frequency in burst mode, packets are transmitted at a constant rate, and the serial port clock provides sufficient timing information for the transfer, which permits a continuous stream of data. Therefore, the frame sync pulses are essentially redundant. Theoretically, then, only an initial frame sync signal is required to initiate the multipacket transfer. The C5x does support operation of the serial port in this fashion, referred to as continuous mode, which is selected by clearing the FSM bit in the SPC to 0. Continuous mode serial port operation is described in detail in subsection 9.7.5, Continuous Mode Transmit and Receive Operations.

9.7.5

Continuous Mode Transmit and Receive Operations

In continuous mode, a frame sync on FSX/FSR is not necessary for consecutive packet transfers at maximum packet frequency after the initial pulse. Continuous mode is selected by setting FSM = 0. Note that when FSM = 0, frame sync pulses are not required, but they are not ignored, therefore, improperly timed frame syncs may cause errors in serial transfers. Serial port operation under various error conditions is described in detail in subsection 9.7.6, Serial Port Interface Exception Conditions, on page 9-46. In continuous mode transmission, one frame sync is generated following the first DXR load, and no further frame syncs are generated. As long as DXR is reloaded once every transmission, continuous transfers are maintained. Failing to update DXR causes the serial port to halt, as in the burst mode case (XSREMPTY becomes asserted, etc). If DXR is reloaded after a halt, the device begins continuous mode transmission again and generates a single FSX, assuming that internal frame sync generation is selected. The distinction between internal and external frame syncs for continuous mode is similar to that of burst mode, as discussed in subsection 9.7.4, Burst Mode Transmit and Receive Operations. If frame sync is externally generated (TXM = 0), then when DXR is loaded, the appearance of the frame sync pulse initiates continuous mode transmission. Continuous mode transmission may be discontinued (and burst mode resumed) only by reconfiguring and resetting the serial port (see subsection 9.7.2, Serial Port Interface Operation, on page 9-25). Simply changing the FSM bit during transmit or halt will not properly switch to burst mode. Continuous mode transmit timing, shown in Figure 925, is similar to maximum packet frequency transmission in burst mode as shown in Figure 923. The major difference is the lack of a frame sync pulse after the initial one. As long as DXR is updated once per transmission, this mode will continue. Overwrites to DXR behave just as in burst mode; the last data written will be

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transmitted. XSR operation is the same as in burst mode. A new external FSX pulse will abort the present transmission, cause one data packet to be lost, and initiate a new continuous mode transmit. This is explained in more detail in subsection 9.7.6, Serial Port Interface Exception Conditions, on page 9-46.

Figure 925. Continuous Mode Serial Port Transmit

CLKX FSX (TXM = 1) DX (FO = 1) XRDY (SP) XINT (SP) XRDY (BSP) XINT (BSP) A1 MSB A2 A3 A4 A5 A6 A7 A8 LSB B1 B2 B3 B4

DXR loaded XSR loaded (SP)

XSR loaded (BSP)

DXR reloaded

XSR reloaded (BSP) XSR reloaded (SP)

Continuous mode reception is similar to the transmit operation. After the initial frame sync pulse on FSR, no further frame syncs are required. This mode will continue as long as DRR is read every transmission. If DRR is not read by the end of the next transfer, the receiver will halt, and RSRFULL is set, indicating overrun. See subsection 9.7.6, Serial Port Interface Exception Conditions, on page 9-46. Overrun in continuous mode effects the SP and the BSP differently. On the SP, once overrun has occurred, reading DRR will restart continuous mode at the next word/byte boundary after DRR is read; no new FSR pulse is required. On the BSP, continuous mode reception does not resume until DRR is read and an FSR occurs. Continuous mode reception may only be discontinued by reconfiguring and resetting the serial port. Simply changing the FSM bit during a reception or halt will not properly switch to burst mode. Continuous mode receive timing is shown in Figure 926.
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Figure 926. Continuous Mode Serial Port Receive

CLKR FSR DR (FO = 1) RRDY RINT A1 MSB A2 A3 A4 A5 A6 A7 A8 LSB B1 B2 B3 B4 B5

DRR loaded from RSR

DRR read

Figure 926 shows only one frame sync pulse; otherwise, it is similar to Figure 924. If a pulse occurs on FSR during a transfer (an error), then the receive operation is aborted, one packet is lost, and a new receive cycle is begun. This is discussed in more detail in subsection 9.7.2, Serial Port Interface Operation, on page 9-25 and in subsection 9.7.6, Serial Port Interface Exception Conditions.

9.7.6

Serial Port Interface Exception Conditions

Exception (or error) conditions result from an unexpected event occurring on the serial port. These conditions are operational aberrations such as overrun, underflow, or a frame sync pulse during a transfer. Understanding how the serial port handles these errors and the state it acquires during these error conditions is important for efficient use of the serial port. Because the error conditions differ slightly in burst and continuous modes, they are discussed separately.

Burst Mode
In burst mode, one type of error condition (presented in subsection 9.7.2, Serial Port Interface Operation) is receive overrun, indicated by the RSRFULL flag. This flag is set when the device has not read incoming data and more data is being sent. If this condition occurs, the processor halts serial port receives until DRR is read. Thus, any further data sent may be lost. Overrun is handled differently on the SP and on the BSP. On the SP, the contents of RSR are preserved on overrun, but since RSRFULL is not set to 1 until the next FSR occurs after the overflowing reception, incoming data usually begins being lost as soon as RSRFULL is set. Data loss can only be avoided if RSRFULL is polled in software and the DRR is read immediately after
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RSRFULL is set to 1. This is normally possible only if the CLKR frequency is slow with respect to CLKOUT1, since RSRFULL is set on the falling edge of CLKR during FSR, and data begins being received on the following rising edge of CLKR. The time available for polling RSRFULL and reading the DRR to avoid data loss is, therefore, only half of one CLKR cycle. On the BSP, RSRFULL is set on the last valid bit received, but the contents of RSR are never transferred to DRR, therefore, the complete transferred word in RSR is lost. If the DRR is read (clearing RSRFULL) before the next FSR occurs, subsequent transfers can be received properly. Another type of receive error is caused if frame sync occurs during a receive (that is, data is being shifted into RSR from DR). If this happens, the present receive is aborted and a new one begins. Thus, the data that was being loaded into RSR is lost, but the data in DRR is not (no RSR-to-DRR copy occurs). Burst mode serial port receiver behavior under normal and error conditions for the SP is shown in Figure 927 and for the BSP is shown in Figure 928.

Figure 927. SP Receiver Functional Operation (Burst Mode)

FSR pulse occurs

Receive in progress ?

No

Is RSRFULL set ? Yes

No

Is RSR full ?

No

Start new data receive

Yes Abort receive. Start next reception. (No RSR to DRR, thus, 1 word lost)

Yes Set RSRFULL=1

Ignore FSR pulse

Figure 928. BSP Receiver Functional Operation (Burst Mode)

FSR pulse occurs

Receive in progress ?

No

Is RSRFULL set ? Yes Ignore FSR pulse

No

Start new data receive

Yes Abort receive. Start next reception. (No RSR to DRR, thus, 1 word lost)

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Transmitter exception conditions in burst mode may occur for several possible reasons. Underflow, which is described in subsection 9.7.3, Setting the Serial Port Configuration, on page 9-27 is an exception condition that may occur in burst mode, however, underflow is not normally considered an error. An exception condition that causes errors in transmitted data occurs when frame sync pulses occur at inappropriate times during a transfer. If a transmit is in progress (that is, XSR data is being driven on DX) when a frame sync pulse occurs, the transmission is aborted, and the data in XSR is lost. Then, whatever data is in DXR at the time of the frame sync pulse is transferred to XSR (DXR-to-XSR copy) and is transmitted. Note, however, that in this case an XINT is generated only if the DXR has been written to since the last transmit. Also, if XSREMPTY is active and a frame sync pulse occurs, the old data in DXR is shifted out. Figure 929 summarizes serial port transmit behavior under error and nonerror conditions. Note that if an FSX occurs when no transmit is in progress, and DXR has been reloaded since the last transmit, the DXR-toXSR copy and generation of transmit interrupt occur at this point only on the BSP. On the SP, these two events occur at the time the DXR was reloaded.

Figure 929. SP/BSP Transmitter Functional Operation (Burst Mode)

FSX pulse occurs

Transmit in progress?

No

New DXR since last transmit ?

No

XSREMPTY is low, DXR-to-XSR copy occurs. No transmit interrupt. Start transmit.

Yes Abort transmit

Yes DXR-to-XSR copy (BSP only). Transmit interrupt (BSP only). Start transmit.

New DXR written since last transmit ?

No

DXR-to-XSR copy. No transmit interrupt. Start transmit.

Yes DXR-to-XSR copy. Transmit interrupt. Start transmit (1 word is lost).

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Continuous Mode
In continuous mode, errors take on a broader meaning, since data transfer is intended to occur at all times. Thus, underflow (XSREMPTY = 0) constitutes an error in continuous mode because data will not be transmitted. As in burst mode, overrun (RSRFULL = 1) is also an error, and in continuous mode, both overrun and underflow cause the serial port receive or transmit sections, respectively, to halt (see subsection 9.7.3, Setting the Serial Port Configuration, on page 9-27 for a description of these conditions). Fortunately, underflow and overrun errors may not be catastrophic; they can often be corrected simply by reading DRR or writing to DXR. The SP and the BSP are affected differently when overrun occurs in continuous mode. In the SP, when DRR is read to deactivate RSRFULL, a frame sync pulse is not required in order to resume continuous mode operation. The receiver keeps track of the transfer word boundary, even though it is not receiving data. Therefore, when the RSRFULL flag is deactivated by a read from DRR, the receiver begins reading from the correct bit. On the BSP, since an FSR pulse is required to restart continuous reception, this also reestablishes the proper bit alignment, in addition to restarting reception. Figure 930 shows receiver functional operation in continuous mode.

Figure 930. SP/BSP Receiver Functional Operation (Continuous Mode)

FSR pulse occurs Ignore pulse, since RSRFULL is active

Receive in progress ?

No

Yes Abort current receive. Start next reception. (No RSR-to-DRR copy; thus, current word is lost)

During a receive in continuous mode, if a frame sync pulse occurs, this causes a receive abort condition, and one packet of data is lost (this is caused because the frame sync pulse resets the RSR bit counter). The data present on DR then begins being shifted into RSR, starting again from the first bit. Note that if a frame sync occurs after deactivating the RSRFULL flag by reading DRR, but before the beginning of the next word boundary, this also creates a receive abort condition.
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Another cause for error is the appearance of extraneous frame syncs during a transmission. After the initial frame sync in continuous mode, no others are required; if an improperly timed frame sync pulse occurs during a transmit, the current transfer (that is, serially driving XSR data onto DX) is aborted, and data in XSR is lost. A new transmit cycle is initiated, and transfers continue as long as the DXR is updated once per transmission afterward. Figure 931 shows continuous mode transmitter functional operation. Note that if XSREMPTY is active in continuous mode and an external frame sync occurs, the previous DXR data is transmitted as in burst mode operation.

Figure 931. SP/BSP Transmitter Functional Operation (Continuous Mode)

FSX pulse occurs

Transmit in progress ?

No

XSREMPTY is low, DXR-to-XSR copy occurs. No transmit interrupt. Start transmit.

Yes Abort transmit

New DXR since last transmit ?

No

DXR-to-XSR copy. No transmit interrupt. Start transmit.

Yes DXR-to-XSR copy. Transmit interrupt. Start new transmit. (Current word is lost)

9.7.7

Example of Serial Port Interface Operation

The following two code examples illustrate a one-way transmit from device 0 to device 1 of an arithmetic sequence of numbers. The numbers are written in each device in a block from 9000h to B000h in data memory. Device 0 waits in a BIO loop for a ready-to-receive signal (XF) from device 1 and initializes the transfer with a value of 0. Both routines assume that the DP is cleared to 0, and that ARP = 7. Example 93 shows the code running on device 0. Only its transmit interrupt (XINT) is enabled; its transmit ISR writes the value it will send into its own memory.

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Example 93. Device 0 Transmit Code (Serial Port Interface Operation)

* Device 0 Transmit side : :

SPLK

SPLK SPLK SPLK CLRC BCND B LACL LAR SACL SACL B LACC SUB BCND LACL ADD SACL SACL RETE B

ILOOP SENDZ

SELF1 XMT_ISR

: ;Setup SPC as CLK source ;and internal frame sync #0038h, SPC ;Set TXM=MCM=FSM=1, ;TDM=DLB=FO=0. ;And put SP into reset ;(XRST=RRST=0) #00F8h, SPC ;Take SP out of reset ;Setup interrupts #0ffffh, IFR ;clear IFR #020h, IMR ;Turn on XINT INTM ;enable interrupts SENDZ, BIO ;Wait for readytoreceive ILOOP ;from other device #0 ;First transmit/write ;value is 0 AR7, #9000h ;Setup where to write * ;Write first value DXR ;Transmit first value SELF1 ;Wait for interrupts AR7 ;Check if past 0x0b000 #0B000h ;i.e. end of block END_SERP,GEQ ;Go to tight loop if so ;Add one and transmit *+ ;Load value #1 ;Add one * ;Write value DXR ;Transmit value END_SERP ;Sit in tight loop after ;block is complete.

END_SERP

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Example 94 shows the code for device 1. It sends a ready-to-receive signal (XF) to device 0. Only its receive interrupt (RINT) is enabled, and its receive ISR reads from the DRR, writes to the block, and checks to see if the end of the block has been reached.

Example 94. Device 1 Receive Code (Serial Port Interface Operation)

Device 1 Receive ;Set SP as CLK, frame ;sync receive #0008h, SPC ;Set TXM=MCM=DLB=FO=0, ;FSM=1. ;And put SP into reset ;(XRST=RRST=0) #00C8h, SPC ;Take SP out of reset ;Setup interrupts #0ffffh, IFR ;clear IFR #010h, IMR ;Turn on RINT INTM ;Enable interrupts AR7, #9000h ;Setup where to write ;received data XF ;Signal ready to receive SELF1 ;Wait for interrupts DRR *+ AR7 #0b000h END_SERP,GEQ END_SERP ;Load received value ;Write to memory block ;Check if past 0x0b000 ;i.e. end of block ;Go to tight loop if so ;Sit in tight loop after ;block is complete.

SPLK

SPLK SPLK SPLK CLRC LAR CLRC SELF1 RCV_ISR B LACL SACL LACC SUB BCND B

END_SERP

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9.8 Buffered Serial Port (BSP) Interface

The buffered serial port (BSP) is made up of a full-duplex, double-buffered serial port interface, which functions in a similar manner to the C5x standard serial port (SP), and an autobuffering unit (ABU) (see Figure 932). The SP section of the BSP is an enhanced version of the C5x standard serial port as implemented on the C50, C51, C52, and C53. The ABU is an additional section of logic which allows the SP section to read/write directly to C5x internal memory independent of the CPU. This results in a minimum overhead for serial port transfers and faster data rates. The BSP is available on the LC56, LC57, and C57S devices. The full duplex BSP serial interface provides direct communication with serial devices such as codecs, serial A/D converters, and other serial devices with a minimum of external hardware. The double-buffered BSP allows transfer of a continuous communication stream in 8-,10-,12- or 16-bit data packets. Frame synchronization pulses as well as a programmable frequency serial clock can be provided by the BSP for transmission and reception. The polarity of frame sync and clock signals are also programmable. The maximum operating frequency is CLKOUT1 (28.6M bps at 35ns, 40M bps at 25 ns). The BSP transmit section includes a pulse coded modulation (PCM) mode that allows easy interface with a PCM line. Operation of the BSP in standard (nonbuffered) mode is detailed in subsection 9.8.1 on page 9-55. The ABU has its own set of circular addressing registers, each with corresponding address generation units. Memory for transmit and receive buffers resides within a special 2K word block of C5x internal memory. This memory can also be used by the CPU as general purpose storage, however, this is the only memory block in which autobuffering can occur. Using autobuffering, word transfers occur directly between the SP section and the C5x internal memory automatically using the ABU embedded address generators. The length and starting addresses of the buffers within the 2K block are programmable, and a buffer empty/full interrupt can be generated to the CPU. Buffering can easily be halted using the autodisabling capability. ABU operation is detailed in subsection 9.8.2 on page 9-60. The BSP autobuffering capability can be separately enabled for the transmit and receive sections. When autobuffering is disabled (standard mode), data transfers with the SP section occur under software control in the same fashion as with the standard C5x serial port. In this mode, the ABU is transparent, and the WXINT and WRINT interrupts generated each time a word is transmitted or received are sent to the CPU as transmit interrupt (XINT) and receive interrupt (RINT). When autobuffering is enabled, the XINT and RINT interrupts are only generated to the CPU each time half of the buffer is transferred.
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Figure 932. BSP Block Diagram

C5x Memory Interface
DATA BUS ADDRESS BUS

11

Read

Write

C5X CPU Interface

16

Autobuffering Unit Module

Control

XRDY

RRDY BXINT BRINT

BCLKX BFSX

BDXR

SPCE

WXINT

XINT

BDX BDR

BXSR Serial Port Control Logic BRSR WRINT

Interrupt Control RINT

Interrupt Logic

BCLKR BFSR BDRR BSPC

Serial Port Interface Module

Most aspects of BSP operation are similar to that of the C5x standard serial port. Section 9.7, Serial Port Interface, on page 9-23 discusses operation of both the C5x standard serial port and the BSP in standard mode. Since standard mode BSP operation is a superset of standard SP operation, Section 9.7 should first be studied before the rest of this section is read. System considerations of BSP operation such as initialization and low power modes are discussed in subsection 9.8.3 on page 9-69.
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9.8.1

BSP Operation in Standard Mode

BSP operation in standard mode is discussed in Section 9.7, Serial Port Interface, on page 9-23. This subsection summarizes the differences between SP operation and standard mode BSP operation. The enhanced BSP features are available both in standard mode and in autobuffering mode. ABU is discussed in subsection 9.8.2 on page 9-60. Information presented in this section assumes familiarity with standard mode operation as described in Section 9.7. The BSP uses its own dedicated memory-mapped data transmit, data receive and serial port control registers (BDXR, BDRR, and BSPC). The BSP also utilizes an additional control register, the BSP control extension register (SPCE), in implementing its enhanced features and controlling the ABU. The BDRR, BDXR, and BSPC registers function similarly to their counterparts in the SP as described in Section 9.7. As with the SP, the BSP transmit and receive shift registers (BXSR and BRSR) are not directly accessible in software but facilitate the double-buffering capability. If the serial port is not being used, the BDXR and the BDRR registers can be used as general purpose registers. In this case, BFSR should be set to an inactive state to prevent a possible receive operation from being initiated. Note, however, that program access to BDXR or BDRR is limited when autobuffering is enabled for transmit or receive, respectively. BDRR can only be read, and BDXR can only be written when the ABU is disabled. BDRR can only be written when the BSP is in reset. BDXR can be read any time. The buffered serial port registers are summarized in Table 915. The ABU utilizes several additional registers which are discussed in subsection 9.8.2, Autobuffering Unit (ABU) Operation, on page 9-60.

Table 915. Buffered Serial Port Registers

Address 0030h 0031h 0032h 0033h Register BDRR BDXR BSPC SPCE Description 16-bit BSP data receive register 16-bit BSP data transmit register 16-bit BSP control register 16-bit BSP control extension register BRSR BXSR 16-bit BSP data receive shift register 16-bit BSP data transmit shift register

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9.8.1.1

Differences Between SP and BSP Operation in Standard Mode

The differences between SP and BSP operation in standard mode are discussed in detail in the standard mode serial port operation (Section 9.7 on page 9-23). These differences relate primarily to boundary conditions, however, in some systems, these differences may be significant. The differences are summarized in Table 916.

Table 916. Differences Between SP and BSP Operation in Standard Mode

Condition RSRFULL is set. SP RSRFULL is set when RSR is full and then an FSR occurs, except in continuous mode where RSRFULL is set as soon as RSR is full. RSR contents are preserved on overrun. Receive restarts as soon as DRR is read (see subsection 9.7.6, Serial Port Interface Exception Conditions, on page 9-46). No Occur when DXR is loaded. DRR and DXR can be read or written under program control at any time. Note that caution should be exercised when reads and writes of the DRR may be close in time to serial port receptions. In this case, a DRR read may not yield the result that was previously written by the program. Also note that rewrites of DXR may cause loss (and therefore non-transmission) of previously written data depending on the relative timing of the writes and FSX (see subsection 9.7.4, Burst Mode Transmit and Receive Operations, on page 9-37). CLKOUT1/2 BSP RSRFULL is set as soon as BRSR is full.

Preservation of data in RSR on overrun. Continuous mode receive restart after overrun.

BRSR contents are not preserved on overrun. Receive does not restart until BDRR is read and then a BFSR occurs. Yes Occur when when a BFSX occurs after BDXR is loaded. BDRR can only be read and BDXR can only be written when the ABU is disabled. BDRR can only be written when the BSP is in reset. BDXR can be read any time. The same precautions with regard to reads and writes to these registers apply as in SP.

Sign extension in DRR on 8-, 10-, or 12-bit transfers. XSR load, XSREMPTY clear, XRDY/XINT generation. Program accessibility to DXR and DRR.

Maximum serial port clock rate.

CLKOUT1

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Table 916. Differences Between SP and BSP Operation in Standard Mode (Continued)
Condition Initialization timing requirements. SP On the SP, the serial port may be taken out of reset at any time with respect to FSX/FSR, however, if XRST/RRST go high during or after the frame sync, the frame sync may be ignored. BSP On the BSP, exiting serial port reset under certain conditions must precede FSX timing by one CLKOUT1 cycle in standard mode and by six CLKOUT1 cycles in autobuffering mode (see subsection 9.8.3, System Considerations of BSP Operation, on page 9-69). Yes (see subsection 9.8.3, System Considerations of BSP Operation, on page 9-69).

Operates in IDLE2 mode.

No

9.8.1.2

Enhanced BSP Features

The enhanced features that the BSP offers include the capability to generate programmable rate serial port clocks, select positive or negative polarities for clock and frame sync signals, and to perform transfers of 10- and 12-bit words, in addition to the 8- and 16-bit transfers offered by the SP. Additionally, the BSP implements the capability to specify that frame sync signals be ignored until instructed otherwise, and provides a dedicated operating mode which facilitates its use with PCM interfaces. The SPCE contains the control and status bits that are used in the implementation of these enhanced BSP features and the ABU. The 10 LSBs of SPCE are dedicated to the enhanced features control, whereas the 6 MSBs are used for ABU control, which is discussed in subsection 9.8.2, Autobuffering Unit (ABU) Operation, on page 9-60. Figure 933 shows the SPCE bit positions and Table 917 summarizes the function of the SPCE bits. The value of the SPCE upon reset is 3. This results in standard mode operation compatible with the SP.

Figure 933. BSP Control Extension Register (SPCE) Diagram Serial Port Control Bits

1510 9 8 7 6 5 40 ABU control PCM
R/W

FIG

FE

CLKP
R/W

FSP
R/W

CLKDV
R/W

R/W

R/W

Note:

R = Read, W = Write

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Table 917. BSP Control Extension Register (SPCE) Bit Summary Serial Port Control Bits
Bit 1510 9 Name ABU control PCM Reset value 0 Function Reserved for autobuffering unit control (see subsection 9.8.2, Autobuffering Unit (ABU) Operation, on page 9-60). Pulse Code Modulation Mode. This control bit puts the serial port in pulse-code modulation (PCM) mode. The PCM mode only affects the transmitter. BDXR-toBXSR transfer is not affected by the PCM bit value. PCM = 0 PCM = 1 Pulse-coded modulation mode is disabled. Pulse-coded modulation mode is enabled. In PCM mode, BDXR is transmitted only if its most significant B bit is set to 0. If this bit is set to 1, BDXR is not transmitted and BDX is put in high impedance during the transmission period.

FIG

Frame Ignore. This control bit operates only in transmit continuous mode with external frame and in receive continuous mode. FIG = 0 FIG = 1 Frame sync pulses following the first frame pulse restart the transfer. Frame sync pulses following the first frame pulse that initiates a transfer operation are ignored.

FE

Format Extension. The FE bit in conjunction with FO in the SPC register (Table 913 on page 9-28) specifies the word length. When FO FE = 00, the format is 16-bit words; when FO FE = 01, the format is 10-bit words; when FO FE = 10, the format is 8-bit words; and when FO FE = 11, the format is 12-bit words. Note that for 8-, 10-, and 12-bit words, the received words are right justified and the sign bit is extended to form a 16-bit word. Words to transmit must be right justified. See Table 918 for the word length configurations. Clock Polarity. This control bit specifies when the data is sampled by the receiver and transmitter. CLKP = 0 CLKP = 1 Data is sampled by the receiver on BCLKR falling edge and sent by the transmitter on BCLKX rising edge. Data is sampled by the receiver on BCLKR rising edge and sent by the transmitter on BCLKX falling edge.

CLKP

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Table 917. BSP Control Extension Register (SPCE) Bit Summary Serial Port Control Bits (Continued)
Bit 5 Name FSP Reset value 0 Function Frame Sync Polarity. This control bit specifies whether frame sync pulses (BFSX and BFSR) are active high or low. FSP = 0 FSP = 1 40 CLKDV 00011 Frame sync pulses (BFSX and BFSR) are active high. Frame sync pulses (BFSX and BFSR) are active low.

Internal Transmit Clock Division factor. When the MCM bit of BSPC is set to 1, CLKX is driven by an on-chip source having a frequency equal to 1/(CLKDV+1) of CLKOUT. CLKDV range is 031. When CLKDV is odd or equal to 0, the CLKX duty cycle is 50%. When CLKDV is an even value (CLKDV=2p), the CLKX high and low state durations depend on CLKP. When CLKP is 0, the high state duration is p+1 cycles and the low state duration is p cycles; when CLKP is 1, the high state duration is p cycles and the low state duration is p+1 cycles.

Table 918. Buffered Serial Port Word Length Configuration

FO 0 0 1 1 FE 0 1 0 1 Buffered Serial Port Word Length Configuration 16-bit words transmitted and received. (Reset values) 10-bit words transmitted and received. 8-bit words transmitted and received. 12-bit words transmitted and received.

These enhanced features allow greater flexibility in serial port interface in a variety of areas. In particular, the frame ignore feature offers a capability which allows a mechanism for effectively compressing transferred data packets if they are not transferred in 16 bit format. This feature is used with continuous receptions and continuous transmits with external frame sync. When FIG=0, if a frame sync pulse occurs after the initial one, the transfer is restarted; when FIG=1, this frame sync is ignored. Setting FIG to 1 allows, for example, effectively achieving continuous 16-bit transfers under circumstances where frame sync pulses occur every 8-, 10- or 12-bits. Without using FIG, each transfer of less than 16 bits requires an entire 16-bit memory word, and each 16 bits transferred as two 8-bit bytes requires two memory words and two transfer operations, rather than one of each. Using FIG, therefore, can result in a significant improvement in buffer size requirement in both autobuffered and standard mode, and a significant improvement in CPU cycle overhead required to handle serial port transfers in standard mode. Figure 934 shows an example with the BSP configured in 16-bit format but with a frame sync after 8 bits.
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Figure 934. Transmit Continuous Mode with External Frame and FIG = 1 (Format is 16 bits)
CLKX/ CLKR
Frame Ignored

FSX/FSR

DX/DR RRDY

MSB

XRDY

DXR reloaded

9.8.2

Autobuffering Unit (ABU) Operation

Since ABU functionality is a superset of standard mode serial port operation, Section 9.7, Serial Port Interface, on page 9-23 and subsection 9.8.1, BSP Operation in Standard Mode, on page 9-55 should first be studied before this subsection is read. Also, note that when operating in autobuffering mode, the serial port control and status bits in BSPC and SPCE function in the same fashion as in standard mode. The ABU implements the capability to move data transferred on the serial port to and from internal C5x memory independent of CPU intervention. The ABU utilizes five memory-mapped registers: the address transmit register (AXR), the block size transmit register (BKX), the address receive register (ARR), and the block size receive register (BKR), along with the SPCE. These registers are summarized in Table 919.

9-60

Address 0033h 0034h 0035h 0036h 0037h Register SPCE AXR BKX Description 16-bit BSP control extension register 11-bit BSP address transmit register (ABU) 11-bit BSP transmit buffer size register (ABU) 11-bit BSP address receive register (ABU) ARR BKR 11-bit BSP receive buffer size register (ABU)

Table 919. Autobuffering Unit Registers

Buffered Serial Port (BSP) Interface

Figure 935 shows the block diagram of the ABU. The SPCE contains bits which control ABU operation and will be discussed in detail later in this subsection. AXR, BKX, ARR, and BKR, along with their associated circular addressing logic, allow address generation for accessing words to be transferred between the C5X internal memory and the BSP data transmit register (BDXR) and BSP data receive register (BDRR) in autobuffering mode. The address and block size registers as well as circular addressing are also discussed in detail later in this subsection. Note that the 11-bit memory mapped AXR, BKX, ARR, and BKR registers are read as 16-bit words, with the five most significant bits read as zeroes and the 11-bit register contents right justified in the least significant 11 bits. If autobuffering is not used, these registers can be used for general purpose storage of 11-bit data. The transmit and receive sections of the ABU can be enabled separately. When either section is enabled, access to its corresponding serial port data register (BDXR or BDRR) through software is limited. The BDRR can only be read, and the BDXR can only be written when the ABU is disabled. The BDRR can only be written when the BSP is in reset. The BDXR can be read any time. When either transmit or receive autobuffering is disabled, that section operates in standard mode, and its portion of the ABU is transparent. The ABU also implements the capability to generate CPU interrupts when transmit and receive buffers have been halfway or entirely filled or emptied. These interrupts take the place of the transmit and receive interrupts in standard mode operation, which are not generated in autobuffering mode. This mechanism features an autodisabling capability which can be used to automatically terminate autobuffering when either the half-of- or bottom-of-buffer boundary is crossed. These features are also described in detail later in this subsection.

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Figure 935. ABU Block Diagram

C5x Memory Interface

DATA BUS ADDRESS BUS

11

Read

Write

MUX
11 11

Autobuffering Unit Module C5X CPU Interface ABU Control

AXR
16

ARR

BKX

BKR XRDY

Control

RRDY

BXINT

BRINT

BCLKX BFSX

BDXR

SPCE WXINT BXNT

BDX BDR

BXSR BRSR

Serial Port Control Logic WRINT

Interrupt Control BRNT

Interrupt Logic

BCLKR BFSR BDRR BSPC

Serial Port Interface Module

Burst or continuous mode, as described in Section 9.7, Serial Port Interface, can be used in conjunction with the autobuffering capability. Note that due to the nature of autobuffering mode, however, if burst mode with internal frame sync is selected, this will effectively result in continuous transmission with FSX generated by the BSP at the start of each transmission.
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The internal C5X memory used for autobuffering consists of a 2K-word block of single-access memory that can be configured as data, program, or both (as with other single-access memory blocks). This memory can also be used by the CPU as general purpose storage, however, this is the only memory block in which autobuffering can occur. Since the BSP is implemented on several different TMS320 devices, the actual base address of the ABU memory may not be the same in all cases. The 2K-word block of BSP memory is lcoated at 800hFFFh in data memory or at 8000h87FFh in program memory as specified by the RAM and OVLY control bits. When the ABU is enabled, this 2K-word block of memory can still be accessed by the CPU within data and/or program spaces. Conflicts may therefore occur between the CPU and the ABU if the 2K-word block is accessed at the same time by both. If a conflict does occur, priority is given to the ABU, resulting in the CPU access being delayed by one cycle. Accordingly, the worst case situation is that a CPU access could be delayed one cycle each time the ABU accesses the memory block, that is, for every new word transmitted or received. Note that external DMA can only be performed in the 2K-word block of ABU memory when autobuffering is disabled. Also note that when on-chip program memory is secured using the ROM protection feature, the 2K-word block of ABU memory cannot be mapped to program memory. For further information regarding the ROM protection feature, refer to subsection 8.2.4, Program Memory Protection Feature, on page 8-14. When the ABU is enabled for both transmit and receive, if transmit and receive requests from the serial port interface occur at same time, the transmit request takes priority over the receive request. In this case, the transmit memory access occurs first, delaying the receive memory access by generating a wait state. When the transmit memory access is completed, the receive memory access takes place.

9.8.2.1

Autobuffering Control Register

The most-significant six bits in the SPCE constitute the ABU control register (ABUC). Some of these bits are read only, while others are read/write. Figure 936 shows the ABUC bit positions and Table 920 summarizes the function of each ABUC bit in the SPCE. The value of the SPCE upon reset is 3.

15 14 13 12 11 10 90 HALTR
R/W

Figure 936. BSP Control Extension Register (SPCE) Diagram ABU Control Bits

RH
R

BRE
R/W

HALTX
R/W

XH
R

BXE
R/W

SP control

Note:

R = Read, W = Write

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Table 920. BSP Control Extension Register (SPCE) Bit Summary ABU Control Bits
Bit 15 Name HALTR Reset value 0 Function Autobuffering Receive Halt. This control bit determines whether autobuffering receive is halted when the current half of the buffer has been received. HALTR = 0 HALTR = 1 Autobuffering continues to operate when the current half of the buffer has been received. Autobuffering is halted when the current half of the buffer has been received. When this occurs, the BRE bit is cleared to 0 and the serial port continues to operate in standard mode.

14

RH

Receive Buffer Half Received. This read-only bit indicates which half of the receive buffer has been filled. Reading RH when the RINT interrupt occurs (seen either as a program interrupt or by polling IFR) is a convenient way to identify which boundary has just been crossed. RH = 0 RH = 1 The first half of the buffer has been filled and that receptions are currently placing data in the second half of the buffer. The second half of the buffer has been filled and that receptions are currently placing data in the first half of the buffer.

13

BRE

Autobuffering Receive Enable. This control bit enables autobuffering receive. BRE = 0 BRE = 1 Autobuffering is disabled and the serial port interface operates in standard mode. Autobuffering is enabled for the receiver.

12

HALTX

Autobuffering Transmit Halt. This control bit determines whether autobuffering transmit is halted when the current half of the buffer has been transmitted. HALTX = 0 HALTX = 1 Autobuffering continues to operate when the current half of the buffer has been transmitted. Autobuffering is halted when the current half of the buffer has been transmitted. When this occurs, the BXE bit is cleared to 0 and the serial port continues to operate in standard mode.

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Table 920. BSP Control Extension Register (SPCE) Bit Summary ABU Control Bits (Continued)
Bit 11 Name XH Reset value 0 Function Transmit Buffer Half Transmitted. This read-only bit indicates which half of the transmit buffer has been transmitted. Reading XH when the XINT interrupt occurs (seen either as a program interrupt or by polling IFR) is a convenient way to identify which boundary has just been crossed. XH = 0 The first half of the buffer has been transmitted and transmissions are currently taking data from the second half of the buffer. The second half of the buffer has been transmitted and transmissions are currently taking data from the first half of the buffer.

XH = 1

10

BXE

Autobuffering Transmit Enable. This control bit enables the autobuffering transmit. BXE = 0 BXE = 1 Autobuffering is disabled and the serial port operates in standard mode. Autobuffering is enabled for the transmitter.

90

SP control

Serial Port Interface Control bits (see subsection 9.8.1.2, Enhanced BSP Features, on page 9-57).

9.8.2.2

Autobuffering Process
The autobuffering process occurs between the ABU and the 2K-word block of ABU memory. Each time a serial port transfer occurs, the data involved is automatically transferred to or from a buffer in the 2K-word block of memory under control of the ABU. During serial port transfers in autobuffering mode, interrupts are not generated with each word transferred as they are in standard mode operation. This prevents the overhead of having the CPU directly involved in each serial port transfer. Interrupts are generated to the CPU only each time one of the half-buffer boundaries is crossed. Within the 2K-word block of ABU memory, the starting address and size of the buffers allocated is programmable using the 11-bit address registers (AXR and ARR) and the 11-bit block size registers (BKX and BKR). The transmit and receive buffers can reside in independent areas, overlapping areas or the same area, which allows transmitting from a buffer while receiving into the same buffer if desired.
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The autobuffering process utilizes a circular addressing mechanism to access buffers within the 2K word block of ABU memory. This mechanism operates in the same fashion for transmit and receive. For each direction (transmit or receive), two registers specify the buffer size and the current address in the buffer. These registers are the block size and address register for transmit and receive. Each of the BK/AR register pairs fully specify the top and bottom of buffer addresses for transmit and receive. Note that this circular addressing mechanism only effects accesses into the 2K word block by the ABU. Accesses to this memory by the CPU are performed strictly according to the addressing mode(s) selected in the assembly language instructions which perform the memory access. The circular addressing mechanism automatically recirculates ABU memory accesses through the specified buffer, returning to the top of the buffer each time the bottom of the buffer is reached. The circular addressing mechanism is initialized by loading BK with the exact size of the desired buffer (as opposed to size1) and AR with a value which contains both the base address of the buffer within the 2K word block and the initial starting address within this buffer (this is explained in detail below). Often the initial starting address within the buffer is 0, indicating the start of the buffer (the top-of-buffer address), but the initial starting address may be any point within the defined buffer range. Once initialized, BK can be considered to consist of two parts; the most significant or higher part (BKH), which corresponds to the all of the most significant 0 bits of BK, and the lower part (BKL), which is the remaining bits, of which the most significant bit is a 1 and whose bit position is designated bit position N. The N bit position also defines the two parts (ARH and ARL) of the address register. The top of buffer address (TBA) is defined by the concatenation of ARH with N+1 least significant 0 bits. The bottom of buffer address (BBA) is defined by the concatenation of ARH and BKL1, and the current address within the buffer is specified by the complete contents of AR. A circular buffer of size BK must therefore start on an N-bit boundary (the N least significant bits of the address register are 0) where N is smallest integer that satisfies 2N > BK, or at the lowest address within the 2K memory block. The buffer consists of two halves, the address range for the first half is: ARH|0...0 to ARH|[(BKL >> 1) 1] and the address range for the second half is: ARH|(BKL >> 1) to ARH|(BKL1) Figure 937 illustrates all of the relationships between the defined buffer and the BK and AR registers, the bottom of circular buffer address (BBA), and the top of circular buffer address (TBA).
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Figure 937. Circular Addressing Registers

TBA ARH 00 Top of Buffer

10 ARH

N ARL

0 FIRST HALF Current location in buffer

Address register (AR) ARH 10 00 BKH N 1 BKL BBA ARH BKL Bottom of Buffer +1 SECOND HALF 0 BKL >>1 Second Half Start

Block size register (BK)

The minimum block size for an ABU buffer is two; the maximum block size is 2047, and any buffer of 2047 to 1024 words must start at a relative address of 0x0000 with respect to the base address of the 2K block of ABU memory. If either of the address registers (AXR or ARR) is loaded with a value specifying a location that is outside the range of the currently allocated buffer size as defined by BK, improper operation may result. Subsequent memory accesses will be performed starting at the location specified, despite the fact that they will be to locations which are outside the range of the desired buffer, and the AR will be incremented with each access until its contents reach the next permitted buffer start address. Any further accesses are then performed using the correct circular buffering algorithm with the new AR contents as the updated buffer start address. It should be noted that any accesses performed with improperly loaded ARs may therefore unexpectedly corrupt some memory locations. The following example illustrates some of these functional aspects of the autobuffering process. Consider a transmit buffer of size 5 (BKX = 5) and a receive buffer of size 8 (BKR = 8) as shown in Figure 938. The transmit buffer may start at any relative address that is a multiple of 8 (address 0x0000, 0x0008, 0x0010, 0x0018, ..., 0x07F8), and the receive buffer may start at any relative address that is a multiple of 16 (0x0000, 0x0010, 0x0020, ..., 0x07F0). In this
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example, the transmit buffer starts at relative address 0x0008 and the receive buffer starts at relative address 0x0010. AXR may therefore contain any value in the range 0x00080x000C and ARR may contain any value in the range 0x00100x0017. If AXR in this example had been loaded with the value 0x000D (not acceptable in a modulo 5 buffer), memory accesses would be performed and AXR incremented until it reaches address 0x0010 which is an acceptable starting address for a modulo 5 buffer. Note, however, that if this had occurred, AXR would then specify a transmit buffer starting at the same base address as the receive buffer, which may cause improper buffer operation.

Figure 938. Transmit Buffer and Receive Buffer Mapping Example

0000h

Transmit BKX = 5

0008h 000Ah 000Ch AXR

0010h Receive 0014h BKR = 8 0017h ARR

The autobuffering process is activated upon request from serial port interface when XRDY or RRDY goes high, indicating that a word has been received. The required memory access is then performed, following which an interrupt is generated if half of the defined buffer (first or second) has been processed. The RH and XH flags in the SPCE register indicate which half has been processed when the interrupt occurs.
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When autodisabling is selected (HALTX or HALTR bit is set), then when the next half (first or second) buffer boundary is encountered, the autobuffering enable bit in the SPCE (BXE or BRE) is cleared so that autobuffering is disabled and does not generate any further requests. When transmit autobuffering is halted, transmission of the current XSR contents and the last value loaded in DXR are completed, since these transfers have already been initiated. Therefore, when using the HALTX function, some delay will normally occur between crossing a buffer boundary and transmission actually stopping. If it is necessary to identify when transmission has actually ended, software should poll for the condition of XRDY = 1 and XSREMPTY = 0, which occurs after last bit has been transmitted. In the receiver, when using HALTR, since autobuffering is stopped when the most recent buffer boundary is crossed, future receptions may be lost, unless software begins servicing receive interrupts at this point, since BDRR is no longer being read and transferred to memory automatically by the ABU. For explanation of how the serial port operates in standard mode when DRR is not being read, refer to subsection 9.7.6, Serial Port Interface Exception Conditions, on page 9-46. The sequence of events involved in the autobuffering process is summarized as follows: 1) The ABU performs the memory access to the buffer. 2) The appropriate address register is incremented unless the bottom of buffer has been reached, in which case the address register is modified to point to the top of buffer address. 3) Generate an XINT or RINT and update XH/RH if the half buffer or bottom of buffer boundary has been crossed. 4) Autodisable the ABU if this function has been selected and if the half buffer or bottom of buffer boundary has been crossed.

9.8.3

System Considerations of BSP Operation

This subsection discusses several system-level considerations of BSP operation. These considerations include initialization timing issues, software initialization of the ABU, and power down mode operation.

9.8.3.1

Timing of Serial Port Initialization

The C5x device utilizes a fully static design, and accordingly, in both the SP and the BSP, serial port clocks need not be running between transfers or prior to initialization. Therefore, proper operation can still result if FSX/FSR occurs
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simultaneously with CLKX/CLKR starting. Regardless of whether serial port clocks have been running previously, however, the timing of serial port initialization, and most importantly, when the port is taken out of reset, can be critical for proper serial port operation. The most significant consideration of this is when the port is taken out of reset with respect to when the first frame sync pulse occurs. Initialization timing requirements differ on the SP and the BSP. On the SP, the serial port may be taken out of reset at any time with respect to FSX/FSR, however, if XRST/RRST go high during or after the frame sync, the frame sync may be ignored. In standard mode operation on the BSP for receive, and for transmit with external frame sync (TXM = 0), the BSP must be taken out of reset at least one full CLKOUT1 cycle plus 1/2 serial port clock cycle prior to the edge of the clock which detects the active frame sync pulse (whether the clock has been running previously or not) for proper operation. See Figure 939. Transmit operations with internal clock and frame sync are not subject to this requirement since frame sync is internally generated automatically (after XRST is cleared (set to 1)) when BDXR is loaded. Note, however, that if external serial port clock is used with internal frame sync, frame sync generation may be delayed depending on the timing of clearing XRST with respect to the clock. Figure 939 illustrates the standard mode BSP initialization timing requirements for the transmitter. The figure shows standard mode operation with external frame (TXM = 0) and clock (MCM = 0), active high frame sync (FSP = 0) and data samples on rising edge (CLKP = 0). In this example, if the BFSX pulse occurs during the first BCLKX, the transmission is still properly initiated.

Figure 939. Standard Mode BSP Initialization Timing

BCLKX

BFSX

BDX

1 CLKOUT1 +1/2 Serial Port clock cycle XRST

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In autobuffering mode, for receive, and transmit with external frame sync (TXM = 1), the BSP must be taken out of reset at least six CLKOUT1 cycles plus 1/2 serial port clock cycle prior to the edge of the clock which detects the active frame sync pulse (whether the clock has been running previously or not) for proper operation. This is due to the time delay for the ABU logic to be activated. See Figure 940. Transmit operations with internal clock and frame sync are not subject to this requirement since frame sync is internally generated automatically after XRST is cleared. Note, however, that if external serial port clock is used with internal frame sync, and if the clock is not running when XRST is cleared, frame sync generation may be delayed depending on the timing of clearing XRST with respect to the clock. Figure 940 illustrates autobuffering mode initialization timing requirements for the transmitter with external clock and frame sync. The figure shows standard mode operation with external frame (TXM = 0) and clock (MCM = 0), active high frame sync (FSP = 0), and data sampled on rising edge (CLKP = 0).

Figure 940. Autobuffering Mode Initialization Timing

BCLKX

BFSX

BDX

6 CLKOUT1 +1/2 Serial Port clock cycle XRST

XRDY

9.8.3.2

Software Initialization Examples

In order to start or restart BSP operation in standard mode, the same steps are performed in software as with initializing the SP (see Section 9.7, Serial Port Interface, on page 9-23), in addition to which, the SPCE register must be initialized to configure any of the enhanced features desired. To start or restart the
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BSP in autobuffering mode, a similar set of steps must also be performed, in addition to which, the autobuffering registers must be initialized. The following two code examples illustrate initializing the serial port interface for autobuffering mode operation. In both cases, the code is written assuming that transmit and receive interrupts are used to service the ABU interrupts, however, polling of the interrupt flag register (IFR) could also be used. Both the transmit and receive sections can be initialized at the same time or separately depending upon system requirements. Example 95 initializes the serial port for transmit operations only, with burst mode, external frame sync and external clock selected. The selected data format is 10 bits, with frame sync and clock polarities selected to be high true. Transmit autobuffering is enabled by setting the BXE bit in the ABUC section of SPCE, and HALTX has been set to 1, which causes transmission to halt when half of the defined buffer is transmitted. Example 96 initializes the serial port for receive operations only, with continuous mode selected. Frame sync and clock polarities are selected to be low true, data format is 16 bits, and frame ignore is selected so that two received data bytes are packed into a single received word to minimize memory requirements. Receive autobuffering is enabled by setting the BRE bit in the ABUC section of SPCE. Note that in Example 95 and Example 96, the transmit and receive interrupts used are those that the BSP occupies on the C56 and C57, the two main devices which include the BSP. However, on other devices which use the BSP, different interrupts may be used, therefore, appropriate device documentation should be consulted. Also, for both examples, it is assumed that DP has been initialized to 0 and that interrupts are disabled (INTM = 1) when entering the routines.

Example 95. Transmit Initialization in Burst Mode with External Frame Sync and External Clock (Format is 10 bits)
OPL SPLK SPLK SPLK SPLK OPL OPL CLRC #00080h,IMR ;enable transmit interrupt (XINT) #00008h,BSPC ;configure serial port SPC register ;(XRST=0) #01480h,SPCE ;configure serial port SPCE register #XTOP,AXR ;init address of buffer start in AXR #XSIZE,BKX ;init size of buffer #00080h,IFR ;clear any latched transmit interrupt #00040h,BSPC ;start transmit part (XRST=1) INTM ;enable interrupts

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Example 96. Receive Initialization in Continuous Mode (Format is 16 bits)

OPL SPLK SPLK SPLK SPLK OPL OPL CLRC

#00040h,IMR ;enable receive interrupt (RINT) #00000h,BSPC ;reset and configure serial port SPC ;(RRST=0) #02160h,SPCE ;configure serial port SPCE register #RTOP,ARR ;init pointer with top of buffer address #RSIZE,BKR ;init size of receive buffer #00040h,IFR ;clear any latched receive interrupt #0080h,BSPC ;start receive part INTM ;enable interrupts

9.8.4

BSP Operation in Power-Down Mode

The C5x offers several power down modes which allow part or all of the device to enter a dormant state and dissipate considerably less power than when running normally. Power down mode may be invoked in several ways, including either executing the IDLE/IDLE2 instructions or driving the HOLD input low with the HM status bit set to 1. The BSP, like other peripherals (timer, standard serial port), can take the CPU out of IDLE using the transmit interrupt (XINT) or receive interrupt (RINT). When in IDLE or HOLD mode, the BSP continues to operate, as is the case with the SP. When in IDLE2, unlike the SP and other on-chip peripherals which are stopped with this power-down mode, the BSP can still be operated. In standard mode, if the BSP is using external clock and frame sync while the device is in IDLE2, the port will continue to operate, and a transmit interrupt (XINT) or receive interrupt (RINT) will take the device out of IDLE2 mode if INTM = 0 before the device executes the IDLE2 instruction. With internal clock and/or frame sync, the BSP remains in IDLE2 until the CPU resumes operation. In autobuffering mode, if the BSP is using external clock and frame sync while the device is in IDLE2, a transmit/receive event will cause the internal BSP clock to be turned on for the cycles required to perform the DXR (or DRR) to memory transfer. The internal BSP clock is then turned off automatically as soon as the transfer is complete so the device will remain in IDLE2 mode. The device is awakened from IDLE2 by the ABU transmit interrupt (XINT) or receive interrupt (RINT) when the transmit/receive buffer has been halfway or entirely emptied or filled if INTM = 0 before the device executes the IDLE2 instruction.
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9.9 Time-Division Multiplexed (TDM) Serial Port Interface

The time-division multiplexed (TDM) serial port allows the C5x device to communicate serially with up to seven other devices. The TDM port, therefore, provides a simple and efficient interface for multiprocessing applications. The TDM serial port is a superset of the serial port described in Section 9.7 on page 9-23. By means of the TDM bit in the TDM serial port control register (TSPC), the port can be configured in multiprocessing mode (TDM = 1) or stand-alone mode (TDM = 0). When in stand-alone mode, the port operates as described in Section 9.7. When in multiprocessing mode, the port operates as described in this section. The port can be shut down for low power consumption via the XRST and RRST bits, as described in Section 9.7.

9.9.1

Basic Time-Division Multiplexed Operation

Time-division multiplexing is the division of time intervals into a number of subintervals, with each subinterval representing a communications channel according to a prespecified arrangement. Figure 941 shows a 4-channel TDM scheme. Note that the first time slot is labeled chan 1 (channel 1), the next chan 2 (channel 2), etc. Channel 1 is active during the first communications period and during every fourth period thereafter. The remaining three channels are interleaved in time with channel 1.

Figure 941. Time-Division Multiplexing

Full Interval (frame) Word Transfer Interval chan chan chan chan chan chan chan chan chan chan chan 1 2 3 4 1 2 3 4 1 2 3 0

time

The C5x TDM port uses eight TDM channels. Which device is to transmit and which device or devices is/are to receive for each channel may be independently specified. This results in a high degree of flexibility in interprocessor communications.

9.9.2

TDM Serial Port Interface Registers

The TDM serial port operates through six memory-mapped registers and two other register (TRSR and TXSR) that are not directly accessible to the program, but are used in the implementation of the double-buffering capability. These eight registers are listed in Table 921.

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Table 921. TDM Serial Port Registers

Address 0030h 0031h 0032h 0033h 0034h 0035h Register TRCV TDXR TSPC Description TDM data receive register TDM data transmit register TDM serial port control register TDM channel select register TCSR TRTA TDM receive/transmit address register TDM receive address register TRAD TRSR TXSR TDM data receive shift register TDM data transmit shift register - TDM data receive register (TRCV). The 16-bit TDM data receive register

(TRCV) holds the incoming TDM serial data. The TRCV has the same function as the DRR, described in Section 9.7 on page 9-23.

- TDM data transmit register (TDXR). The 16-bit TDM data transmit register

(TDXR) holds the outgoing TDM serial data. The TDXR has the same function as the DXR, described in Section 9.7 on page 9-23.
- TDM serial port control register (TSPC). The 16-bit TDM serial port control

register (TSPC) contains the mode control and status bits of the TDM serial port interface. The TSPC is identical to the SPC (Figure 914) except that bit 0 serves as the TDM mode enable control bit in the TSPC. The TDM bit configures the port in TDM mode (TDM = 1) or stand-alone mode (TDM = 0). In stand-alone mode, the port operates as a standard serial port as described in Section 9.7 on page 9-23.
- TDM channel select register (TCSR). The 16-bit TDM channel select reg-

ister (TCSR) specifies in which time slot(s) each C5x device is to transmit.
- TDM receive/transmit address register (TRTA). The 16-bit TDM receive/

transmit address register (TRTA) specifies in the eight LSBs (RA0RA7) the receive address of the C5x device and in the eight MSBs (TA0TA7) the transmit address of the C5x device.
- TDM receive address register (TRAD). The 16-bit TDM receive address

register (TRAD) contains various information regarding the status of the TDM address line (TADD).
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- TDM data receive shift register (TRSR). The 16-bit TDM data receive shift

register (TRSR) controls the storing of the data, from the input pin, to the TRCV. The TRSR has the same function as the RSR, described in Section 9.7 on page 9-23.
- TDM data transmit shift register (TXSR). The 16-bit TDM data transmit

shift register (TXSR) controls the transfer of the outgoing data from the TDXR and holds the data to be transmitted on the data-transmit (TDX) pin. The TXSR has the same function as the XSR, described in Section 9.7 on page 9-23.

9.9.3

TDM Serial Port Interface Operation

Figure 942(a) shows the C5x TDM port architecture. Up to eight devices can be placed on the four-wire serial bus. This four-wire bus consists of a conventional serial ports bus of clock, frame, and data (TCLK, TFRM, and TDAT) wires plus an additional wire (TADD) that carries the device addressing information. Note that the TDAT and TADD signals are bidirectional signals and are often driven by different devices on the bus during different time slots within a given frame of operation.

Figure 942. TDM 4-Wire Bus

(a) Device 0 Device 1 Device 7 TFRM TADD TCLK TDAT (b) TDX TDR TFSX TFSR TCLKX TCLKR TFRM TADD TCLK TDAT

C5x

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The TADD line, which is driven by a particular device for a particular time slot, determines which device(s) in the TDM configuration should execute a valid TDM receive during that time slot. This is similar to a valid serial port read operation, as described in Section 9.7, Serial Port Interface, on page 9-23, except that some corresponding TDM registers are named differently. The TDM receive register is TRCV, and the TDM receive shift register is TRSR. Data is transmitted on the bidirectional TDAT line. Note that in Figure 942(b) the device TDX and TDR pins are tied together externally to form the TDAT line. Also, note that only one device can drive the data and address line (TDAT and TADD) in a particular slot. All other devices TDAT and TADD outputs should be in the high-impedance state during that slot, which is accomplished through proper programming of the TDM port control registers (this is described in detail later in this section). Meanwhile, in that particular slot, all the devices (including the one driving that slot) sample the TDAT and TADD lines to determine if the current transmission represents valid data to be read by any one of the devices on the bus (this is also discussed in detail later in this section). When a device recognizes an address to which it is supposed to respond, a valid TDM read then occurs, the value is transferred from TRSR to the TRCV register. A receive interrupt (TRNT) is generated, which indicates that TRCV has valid receive data and can be read. All TDM port operations are synchronized by the TCLK and TFRM signals. Each of them are generated by only one device (typically the same device), referred to as the TCLK and TFRM source(s). The word master is not used here because it implies that one device controls the other, which is not the case, and TCSR must be set to prevent slot contention. Consequently, the remaining devices in the TDM configuration use these signals as inputs. Figure 942(b) shows that TCLKX and TCLKR are externally tied together to form the TCLK line. Also, TFRM and TADD originate from the TFSX and TFSR pins respectively. This is done to make the TDM serial port also easy to use in standard mode. TDM port operation is controlled by six memory-mapped registers. The layout of these registers is shown in Figure 943. The TRCV and TDXR registers have the same functions as the DRR and DXR registers respectively, described in Section 9.7, Serial Port Interface. The TSPC register is identical to the SPC register except that bit 0 serves as the TDM mode enable control bit in the TSPC. This bit configures the port in TDM mode (TDM=1) or stand-alone mode (TDM=0). In stand-alone mode, the port operates as a standard serial port as described in Section 9.7. Refer to Section 9.7, Serial Port Interface, on page 9-23 for additional information about the function of the bits in these registers.
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Figure 943. TDM Serial Port Registers Diagram

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRCV TDXR TSPC Receive Data Transmit Data IN0 X Free X Soft X X X X X XRDY RRDY X X IN1 X RRST XRST TXM MCM CH7 RA7 A7 CH6 RA6 A6 CH5 RA5 A5 CH4 RA4 A4 X 0 0 TDM TCSR TRTA CH3 RA3 A3 CH2 CH1 CH0 RA2 A2 RA1 A1 RA0 A0 TA7 X TA6 X TA5 X2 TA4 X1 TA3 X0 TA2 S2 TA1 S1 TA0 S0 TRAD Note: X=Dont care.

When TDM mode is selected, the DLB and FO bits in the TSPC are hardconfigured to 0, resulting in no access to the digital loopback mode and in a fixed word length of 16 bits (a different type of loopback is discussed in the example in subsection 9.9.6 on page 9-82). Also, the value of FSM does not affect the port when TDM=1, and the states of the underflow and overrun flags are indeterminate (subsection 9.9.5, TDM Serial Port Interface Exception Conditions, on page 9-82 explains how exceptions are handled in TDM mode). If TDM=1, changes made to the contents of the TSPC become effective upon completion of channel 7 of the current frame. Thus the TSPC value cannot be changed for the current frame; any changes made will take effect in the next frame. The source device for the TCLK and TFRM timing signals is set by the MCM and TXM bits, respectively. The TCLK source device is identified by setting the MCM bit of its TSPC register to 1. Typically, this device is the same one that supplies the TDM port clock signal TCLK. The TCLKX pin is configured as an input if MCM=0 and an output if MCM=1. In the latter case (internal C5x clock), the device whose MCM=1 supplies the clock (TCLK frequency=one fourth of CLKOUT1 frequency) for all devices on the TDM bus. The clock can be supplied by an external source if MCM=0 for all devices. TFRM can also be supplied externally if TXM=0. An external TFRM, however, must meet TDM receive timing specifications with respect to TCLK for proper operation. No more than one device should have MCM or TXM set to 1 at any given time. The specification of which device is to supply clock and framing signals is typically made only once, during system initialization. The TDM channel select register (TCSR) of a given device specifies in which time slot(s) that device is to transmit. A 1 in any one or more of bits 07 of the TCSR sets the transmitter active during the corresponding time slot. Again, a key system-level constraint is that no more than one device can transmit

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during the same time slot; devices do not check for bus contention, and slots must be consistently assigned. As in TSPC operation, a write to TCSR during a particular frame is valid only during the next frame. However, a given device can transmit in more than one slot. This is discussed in more detail in subsection 9.9.4, TDM Mode Transmit and Receive Operations, on page 9-80, with an emphasis on the utilization of TRTA, TDXR, and TCSR in this respect. The TDM receive/transmit address register (TRTA) of a given device specifies two key pieces of information. The lower half specifies the receive address of the device, while the upper half of TRTA specifies the transmit address. The receive address (RA7RA0, refer to Figure 943) is the 8-bit value that a device compares to the 8-bit value it samples on the TADD line in a particular slot to determine whether it should execute a valid TDM receive. The receive address, therefore, establishes the slots in which that device may receive, dependent on the addresses present in those slots, as specified by the transmitting devices. This process occurs on each device during every slot. The transmit address (TA7TA0, refer to Figure 943) is the address that the device drives on the TADD line during a transmit operation on an assigned slot. The transmit address establishes which receiving devices may execute a valid TDM receive on the driven data. Only one device at a time can drive a transmit address on TADD. Each processor bit-wise-logically-ANDs the value it samples on the TADD line with its receive address (RA7RA0). If this operation results in a nonzero value, then a valid TDM receive is executed on the processor(s) whose receive addresses match the transmitted address. Thus, for one device to transmit to another, there must be at least one bit in the upper half of the transmitting devices TRTA (the transmit address) with a value of 1 that matches one bit with a value of 1 in the lower half of TRTA (the receive address) of the receiving device. This method of configuration of TRTA allows one device to transmit to one or more devices, and for any one device to receive from one or more than one transmitter. This can also allow the transmitting device to control which devices receive, without the receive address on any of the devices having to be changed. The TDM receive address register (TRAD) contains various information regarding the status of the TADD line which can be polled to verify the previous values of this signal and to verify the relationship between instruction cycles and TDM port timing. Bits 1311 (X2X0) contain the current slot number value, regardless of whether a valid data receive was executed in that slot or not. This value is latched at the beginning of the slot and retained only until the end of the slot.
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Bits 108 (S02S0) hold the number of the last slot plus one (modulo eight) in which data was received (that is, if the last valid data read occurred in slot 5 in the previous frame, these bits would contain the number six). This value is latched during the TDM receive interrupt (TRNT) at the end of the slot in which the last valid data receive occurred, and maintained until the end of the next slot in which a valid receive occurs. Bits 70 (A7A0) hold the last address sampled on the TADD line, regardless of whether a valid data receive was executed or not. This value is latched halfway through each slot (so the value on the TADD may be shifted in) and maintained until halfway through the next slot, whether a valid receive is executed or not.

9.9.4

TDM Mode Transmit and Receive Operations

Figure 944 shows the timing for TDM port transfers. The TCLK and TFRM signals are generated by the timing source device. The TCLK frequency is one fourth the frequency of CLKOUT1 if generated by a C5x device. The TFRM pulse occurs every 128 TCLK cycles and is timed to coincide with bit 0 of slot 7, which is the last bit of the previous frame. The relationship of TFRM and TCLK allows 16 data bits for each of eight time slots to be driven on the TDAT line, which also permits the processor to execute a maximum of 64 instructions during each slot, assuming that a C5x internal clock is used. Beginning with slot 0 and with the MSB first, the transmitter drives 16 data bits for each slot, with each bit having a duration of one TCLK cycle, with the exception of the first bit of each slot, which lasts only half of one bit time. Note that data is both clocked onto the TDAT line by the transmitting device and sampled from the TDAT line by receiving devices on the rising edge of TCLK (see the data sheet for detailed TDM interface timings).

Figure 944. Serial Port Timing (TDM Mode)

TCLK TDAT TADD TFRM
bit 17 bit 07 bit 150 a00 bit 140 a10 bit 130 a20 bit 80 bit 70 bit 00 a70 bit 151 bit 141 a01 a11

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Simultaneous with data transfer, the transmitting device also drives the TADD line with the transmit address for each slot. This information, unlike that on TDAT, is only one byte long and is transmitted with the LSB first for the first half of the slot. During the second half of the slot (that is, the last eight TCLK periods) the TADD line is driven high. The TDM receive logic samples the TADD line only for the first eight TCLK periods, ignoring it during the second half of the slot. Therefore, the transmitting device (if not a C5x) could drive TADD high or low during that time period. Note that, like TDAT, the first TADD bit transmitted lasts for only one half of one TCLK cycle. If no device on the TDM bus is configured to transmit in a slot (that is, none of the devices has a 1 for the corresponding slot in their TCSR register), that slot is considered empty. In an empty slot, both TADD and TDAT are high impedance. This condition has the potential for spurious receives, however, because TDAT and TADD are always sampled, and a device performs a valid TDM reception if its receive address matches the address on the TADD line. To avoid spurious reads, a 1-kilohm pull-down resistor must be tied to the TADD line. This causes the TADD line to read low on empty slots. Otherwise, any noise on the TADD line that happens to match a particular receive address would result in a spurious read. If power dissipation is a concern and the resistor is not desired, then an arbitrary processor with transmit address equal to 0h can drive empty slots by writing to TDXR in those slots. Slot manipulation is explained later in this section. The 1-kilohm resistor is not required on the TDAT line. An empty TDM slot can result in the following cases: the first obvious case, as mentioned above, occurs when no device has its TCSR configured to transmit in that slot. A second more subtle case occurs when TDXR has not been loaded before a transmit slot in a particular frame. This may also happen when the TCSR contents are changed, since the actual TCSR contents are not updated until the next TFRM pulse occurs. Therefore, any subsequent change takes effect only in the next frame. The same is true for the receive address (the lower half of TRTA). The transmit address (upper half of TRTA), however, and TDXR, clearly, may be changed within the current frame for a particular slot, assuming that the slot has not yet been reached when the instruction to load the TRTA or TDXR is executed. Note that it is not necessary to load the transmit address each time TDXR is loaded; when a TDXR load occurs and a transmission begins, the current transmit address in TRTA is transmitted on TADD. The current slot number may be obtained by reading the X2X0 bits in TRAD. This affords the flexibility of reconfiguring the TDM port on a slot-by-slot basis, and even slot sharing if desired. The key to utilizing this capability is to understand the timing relationship between the instructions being executed and the
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frame/slots of the TDM port. If the TDM port is to be manipulated on a slot-byslot basis, changes must be made to appropriate registers quickly enough for the desired effect to take place at the desired time. It is also important to take into account that the TCSR and the receive address (lower half of TRTA) take effect only at the start of a new frame, while the transmit address (upper half of TRTA) and TDXR (transmit data) can take effect at the start of a new slot, as mentioned previously. Note that if the transmit address is being changed on the fly, care should be exercised not to corrupt the receive address, since both addresses are located in the TRTA register, thus maintaining the convention of allowing the transmitting device to specify which devices can receive.

9.9.5

TDM Serial Port Interface Exception Conditions

Because of the nature of the TDM architecture, with the ability for one processor to transmit in multiple slots, the concepts of overrun and underflow become indeterminate. Therefore, the overrun and underflow flags are not active in TDM mode. In the receiver, if TRCV has not been read and a valid receive operation is initiated (because of the value on TADD and the devices receive address), the present value of TRCV is overwritten; the receiver is not halted. On the other hand, if TDXR has not been updated before a transmission, the TADD or TDAT lines are not driven, and these pins remain in the high-impedance state. This mode of operation prevents spurious transmits from occurring. If a TFRM pulse occurs at an improper time during a frame, the TDM port is not able to continue functioning properly, since slot and bit numbers become ambiguous when this occurs. Only one TFRM should occur every 128 TCLK cycles. Unlike the serial port, the TDM port cannot be reinitialized with a frame sync pulse during transmission. To correct an improperly timed TFRM pulse, the TDM port must be reset.

9.9.6

Examples of TDM Serial Port Interface Operation

The following is an example of TDM serial port operation, showing the contents of some of the key device registers involved, and explaining the effect of this configuration on port operation. In this example, eight devices are connected to the TDM serial port as shown in Figure 942 on page 9-76. Table 922 shows the TADD value during each of the eight channels given the transmitter and receiver designations shown. This example shows the configuration for eight devices to communicate with each other. In this example, device 0 broadcasts to all other device addresses during slot 0. In subsequent frames, devices 17 each communicate to one other processor.

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Table 923. TDM Register Contents
Table 923 shows the TDM serial port register contents of each device that results in the scenario given in Table 922. Device 0 provides the clock and frame control signals for all channels and devices. The TCSR and TRTA contents specify which device is to transmit on a given channel and which devices are to receive.
Device 7 6 5 4 3 2 1 0 xxC9h xxC9h xxC9h xxC9h xxC9h xxC9h xxC9h xxF9h TSPC 0FE01h 4080h 2040h 1020h 0810h 0408h 0204h 0102h TRTA TCSR xx02h xx04h xx08h xx10h xx20h xx40h xx80h xx01h

Table 922. Interprocessor Communications Scenario
Channel 7 6 5 4 3 2 1 0 TADD Data 0FEh 01h 02h 04h 08h 10h 20h 40h

Time-Division Multiplexed (TDM) Serial Port Interface

Transmitter Device

On-Chip Peripherals
1 2 3 4 5 6 7 0 Receiver Device(s) 17 0 1 2 3 4 5 6

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In this example, the transmit address of a given device (the upper byte of TRTA) matches the receive address (the lower byte of TRTA) of the receiving device. Note, however, that it is not necessary for the transmit and receive addresses to match exactly; the matching operation implemented in the receiver is a bitwise AND operation. Thus, it is only necessary that one bit in the field matches for a receive to occur. The advantage of this scheme is that a transmitting device can select the device or devices to receive its transmitted data by simply changing its transmit address (as long as each devices receive address is unique, the receive address of the receiving device does not need to be changed). In the example, device 0 can transmit to any combination of the other devices by merely writing to the upper byte of TRTA. Therefore, if a transmitting device changed its TRTA to 8001h on the fly, it would transmit only to device 7. A device may also transmit to itself, because both the transmit and receive operations are executed on the rising edge of TCLK (see the data sheet for detailed TDM interface timings). To enable this type of loopback, it is necessary to use the standard TDM port interface connections as shown in Figure 942. Then, if device 0 has a TRTA of 0101h, it would transmit only to itself. Another example of TDM port operation is provided in the code sequence of Example 97 in which a one-way transmit of a sequence of values from device 0 to device 1 is shown. The values are stored in each device in a block from 4000h to 6000h in data memory. Device 0 transmits in slot 0 and has a transmit address of 01h. It waits in a BIO loop for a ready-to-receive signal (XF) from device 1, and initializes the transfer data with a value of 0. Only its transmit interrupt is enabled and its transmit ISR writes the value it will send into its own memory.

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Example 97. Device 0 Transmit Code (TDM Operation)

* Device 0 Transmit side : : : SPLK #1h, TCSR SPLK #100h, TRTA ;Setup TCSR to xmt on ;slot 0 ;Setup transmit address ;Set up TSPC as TCLK, TFRM ;source ;Set TXM=MCM=FSM=TDM=1, ;DLB=FO=0. ;And put TDM into reset ;(XRST=RRST=0) ;Take TDM out of reset ;Setup interrupts ;clear IFR ;Turn on TXNT ;enable interrupts ;Wait for readyto ;receive from other device ;First transmission/write ;value is 0. ;Setup where to write ;Write first value ;Transmit first value ;Wait for interrupts ;Check if past 0x6000 ;i.e. end of block ;Go to tight loop if so. ;Add one and transmit ;Load value ;Add one ;Write value ;Transmit value ;Sit in tight loop after ;block is complete.

SPLK #0039h, TSPC

SPLK #00F9h, TSPC SPLK #0ffffh, IFR SPLK #080h, IMR CLRC INTM TILOOP TSENDZ BCND TSENDZ, BIO B TILOOP LACL #0 LAR AR7, #4000h SACL * SACL TDXR SELF2 _ISR LACC AR7 SUB #6000h BCND END_TDMP, GEQ LACL ADD SACL SACL RETE END_TDMP B *+ #1 * TDXR END_TDMP : : : B SELF2

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Example 98 shows the code in device 1. It has a receive address of 01h and sends a ready-to-receive signal (XF) to device 0. Only its receive interrupt is enabled, and its receive ISR reads from the TRCV, writes to the block, and then checks to see if it has reached the end of the block.

Example 98. Device 1 Receive Code (TDM Operation)

*Device 1 receive side SPLK #0h, TCSR SPLK #001h, TRTA ; Setup TCSR to xmt on ; no slots ; Setup receive address ; ; ; ; ; ; ; Set TDM as TCLK, TFRM receive Set TXM=MCM=DLB=FO=0, FSM=TDM=1. And put TDM into reset (XRST=RRST=0) Take TDM out of reset

SPLK #0009h, TSPC

SPLK #00C9h, TSPC SPLK #0ffffh, IFR SPLK #040h, IMR CLRC INTM LAR AR7, #4000h CLRC XF SELF2 _ISR LACC SACL LACC SUB BCND RETE END_TDMP B TRCV *+ AR7 #6000h END_TDMP, GEQ END_TDMP B SELF2

; Setup interrupts ; clear IFR ; Mask on TRNT ; ; ; ; enable interrupts Setup where to write received data Signal ready to receive

; Wait for interrupts ; ; ; ; ; Load received value Write to memory block Check if past 0x6000 i.e. end of block Go to tight loop if so

; Sit in tight loop after ; block is complete.

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9.10 Host Port Interface

The host port interface (HPI) is an 8-bit parallel port used to interface a host device or host processor to the C5x. Information is exchanged between the C5x and the host device through on-chip C5x memory that is accessible by both the host and the C5x. The HPI is available on the LC57 and C57S devices. The HPI is designed to interface to the host device as a peripheral, with the host device as master of the interface, therefore greatly facilitating ease of access by the host. The host device communicates with the HPI through dedicated address and data registers, to which the C5x does not have direct access, and the HPI control register, using the external data and interface control signals (see Figure 945). Both the host device and the C5x have access to the HPI control register.

Figure 945. Host Port Interface Block Diagram

HD7HD0

Interface control signals

Data latch 8 8 16 16 MUX 16 MUX Address register Data Address HPI memory block HPI control logic Host port interface

HPI control register

DSP data

DSP address

On-Chip Peripherals

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The HPI provides 16-bit data to the C5x while maintaining the economical 8-bit external interface by automatically combining successive bytes transferred into 16-bit words. When the host device performs a data transfer with the HPI registers, the HPI control logic automatically performs an access to a dedicated 2K-word block of internal C5x single access RAM to complete the transaction. The C5x can then access the data within its memory space. The HPI RAM can also be used as general purpose single access data or program RAM. The HPI has two modes of operation, shared-access mode (SAM) and hostonly mode (HOM). In shared-access mode, the normal mode of operation, both the C5x and the host can access HPI memory. In this mode, asynchronous host accesses are resynchronized internally and, in the case of a conflict between a C5x and a host cycle, the host has access priority and the C5x waits one cycle. In host-only mode, only the host can access HPI memory while the C5x is in reset or in IDLE2 with all internal and even external clocks stopped. The host can therefore access the HPI RAM while the C5x is in its minimum power consumption configuration. The HPI supports high speed, back-to-back host accesses. In shared-access mode, the HPI can transfer one byte every five CLKOUT1 cycles (that is 64M bps) with the C5x running at a 40-MHz CLKOUT1. The HPI is designed so the host can take advantage of this high bandwidth and run at frequencies up to (Fd*n)/5, where Fd is the C5x CLKOUT1 frequency and n is the number of host cycles for an external access. Therefore, with a 40-MHz C5x and common values of 4 (or 3) for n, the host can run at speeds of up to 32 (or 24) MHz without requiring wait states. In the host-only mode, the HPI supports even higher speed back-to-back host accesses on the order of one byte every 50 ns (that is, 160M bps), independent of the C5x clock rate (refer to the TMS320C5x data sheet for specific detailed timing information).

9.10.1 Basic Host Port Interface Functional Description

The external HPI interface consists of the 8-bit HPI data bus and control signals that configure and control the interface. The interface can connect to a variety of host devices with little or no additional logic necessary. Figure 946 shows a simplified diagram of a connection between the HPI and a host device.

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Figure 946. Generic System Block Diagram

8 DATA HD0HD7 2 ADDRESS R/W HCNTL0/1 (address) HBIL (1st/2nd byte) HR/W HDS1 HDS2 HCS HAS Sampled by internal strobe or HAS DATA STROBE Internal strobe (controls transfer) ALE (if used) (Samples ADDRESS and R/W signals, if used) HINT READY HRDY INTERRUPT

Host device

C5x

The 8-bit data bus (HD0HD7) exchanges information with the host. Because of the 16-bit word structure of the C5x, all transfers with a host must consist of two consecutive bytes. The dedicated HBIL pin indicates whether the first or second byte is being transferred. An internal control register bit determines whether the first or second byte is placed into the most significant byte of a 16-bit word. The host must not break the first byte/second byte (HBIL low/high) sequence of an ongoing HPI access. If this sequence is broken, data can be lost, and unpredictable operation can result.

The two control inputs (HCNTL0 and HCNTL1) indicate which internal HPI register is being accessed and the type of access to the register. These inputs, along with HBIL, are commonly driven by host address bus bits or a function of these bits. Using the HCNTL0/1 inputs, the host can specify an access to the HPI control (HPIC) register, the HPI address (HPIA) register (which serves as the pointer into HPI memory), or HPI data (HPID) register. The HPID register can also be accessed with an optional automatic address increment. The autoincrement feature provides a convenient way of reading or writing to subsequent word locations. In autoincrement mode, a data read causes a postincrement of the HPIA, and a data write causes a preincrement of the HPIA. By writing to the HPIC, the host can interrupt the C5x CPU, and the HINT output can be used by the C5x to interrupt the host. The host can also acknowledge and clear HINT by writing to the HPIC.
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Table 924 summarizes the three registers that the HPI utilizes for communication between the host device and the C5x CPU and their functions.

Table 924. HPI Registers Description

Name HPIA HPIC HPID Address 0500h Description HPI address register. Directly accessible only by the host. Contains the address in the HPI memory at which the current access occurs. HPI control register. Directly accessible by either the host or by the C5x. Contains control and status bits for HPI operations. HPI data register. Directly accessible only by the host. Contains the data that was read from the HPI memory if the current access is a read, or the data that will be written to HPI memory if the current access is a write.

The two data strobes (HDS1 and HDS2), the read/write strobe (HR/W), and the address strobe (HAS) enable the HPI to interface to a variety of industrystandard host devices with little or no additional logic required. The HPI is easily interfaced to hosts with multiplexed address/data bus, separate address and data buses, one data strobe and a read/write strobe, or two separate strobes for read and write. This is described in detail later in this section. The HPI ready pin (HRDY) allows insertion of wait states for hosts that support a ready input to allow deferred completion of access cycles and have faster cycle times than the HPI can accept due to C5x operating clock rates. If HRDY, when used directly from the C5x, does not meet host timing requirements, the signal can be resynchronized using external logic if necessary. HRDY is useful when the C5x operating frequency is variable, or when the host is capable of accessing at a faster rate than the maximum shared-access mode access rate (up to the host-only mode maximum access rate). In both cases, the HRDY pin provides a convenient way to automatically (no software handshake needed) adjust the host access rate to a faster C5x clock rate or switch the HPI mode. All of these features combined allow the HPI to provide a flexible and efficient interface to a wide variety of industry-standard host devices. Also, the simplicity of the HPI interface greatly simplifies data transfers both from the host and the C5x sides of the interface. Once the interface is configured, data transfers are made with a minimum of overhead at a maximum speed.

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9.10.2 Details of Host Port Interface Operation

This subsection includes a detailed description of each HPI external interface pin function, as well as descriptions of the register and control bit functions. Logical interface timings and initialization and read/write sequences are discussed in subsection 9.10.3, Host Read/Write Access to HPI, on page 9-97. The external HPI interface signals implement a flexible interface to a variety of types of host devices. Devices with single or multiple data strobes and with or without address latch enable (ALE) signals can easily be connected to the HPI. Table 925 gives a detailed description of the function of each of the HPI external interface pins.

Table 925. HPI Signal Names and Functions
HPI Pin HAS Host Pin State Signal Function I Address latch enable (ALE) or Address strobe or unused (tied high) Address strobe input. Hosts with a multiplexed address and data bus connect HAS to their ALE pin or equivalent. HBIL, HCNTL0/1, and HR/W are then latched on HAS falling edge. When used, HAS must precede the later of HCS, HDS1, or HDS2 (see C5x data sheet for detailed HPI timing specifications). Hosts with separate address and data bus can connect HAS to a logic-1 level. In this case, HBIL, HCNTL0/1, and HR/W are latched by the later of HDS1, HDS2, or HCS falling edge while HAS stays inactive (high). HBIL Address or control lines I Byte identification input. Identifies first or second byte of transfer (but not most significant or least significant this is specified by the BOB bit in the HPIC register, described later in this section). HBIL is low for the first byte and high for the second byte. Host control inputs. Selects a host access to the HPIA register, the HPI data latches (with optional address increment), or the HPIC register. HCNTL0, HCNTL1 HCS Address or control lines Address or control lines I I Chip select. Serves as the enable input for the HPI and must be low during an access but may stay low between accesses. HCS normally precedes HDS1 and HDS2, but this signal also samples HCNTL0/1, HR/W, and HBIL if HAS is not used and HDS1 or HDS2 are already low (this is explained in further detail later in this subsection). Figure 947 on page 9-93 shows the equivalent circuit of the HCS, HDS1 and HDS2 inputs.
I: O: Z: Input Output High impedance

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Table 925. HPI Signal Names and Functions (Continued)
HPI Pin Host Pin Data bus State I/O/Z Signal Function HD7HD0 Parallel bidirectional 3-state data bus. HD7 (MSB) through HD0 (LSB) are placed in the high-impedance state when not outputting (HDSx and HCS = 1) or when EMU1/OFF is active (low). HDS1, HDS2 Read strobe and write strobe or data strobe I Data strobe inputs. Control transfer of data during host access cycles. Also, when HAS is not used, used to sample HBIL, HCNTL0/1, and HR/W when HCS is already low (which is the case in normal operation). Hosts with separate read and write strobes connect those strobes to either HDS1 or HDS2. Hosts with a single data strobe connect it to either HDS1 or HDS2, connecting the unused pin high. Regardless of HDS connections, HR/W is still required to determine direction of transfer. Because HDS1 and HDS2 are internally exclusive-NORed, hosts with a high true data strobe can connect this to one of the HDS inputs with the other HDS input connected low. Figure 947 on page 9-93 shows the equivalent circuit of the HDS1, HDS2, and HCS inputs. Host interrupt output. Controlled by the HINT bit in the HPIC. Driven high when the C5x is being reset. Placed in high impedance when EMU1/OFF is active (low). HINT Host interrupt input O/Z HRDY Asynchronous ready O/Z HPI ready output. When high, indicates that the HPI is ready for a transfer to be performed. When low, indicates that the HPI is busy completing the internal portion of the previous transaction. Placed in high impedance when EMU1/OFF is active (low). HCS enables HRDY; that is, HRDY is always high when HCS is high. HR/W Read/Write strobe, address line, or multiplexed address/data I Read/write input. Hosts must drive HR/W high to read HPI and low to write HPI. Hosts without a read/write strobe can use an address line for this function.
I: O: Z: Input Output High impedance

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Host Port Interface

The HCS input serves primarily as the enable input for the HPI, and the HDS1 and HDS2 signals control the HPI data transfer; however, the logic with which these inputs are implemented allows their functions to be interchanged if desired. If HCS is used in place of HDS1 and HDS2 to control HPI access cycles, HRDY operation is affected (since HCS enables HRDY and HRDY is always high when HCS is high). The equivalent circuit for these inputs is shown in Figure 947. The figure shows that the internal strobe signal that samples the HCNTL0/1, HBIL, and HR/W inputs (when HAS is not used) is derived from all three of the input signals, as the logic illustrates. Therefore, the latest of HDS1, HDS2, or HCS is the one which actually controls sampling of the HCNTL0/1, HBIL, and HR/W inputs. Because HDS1 and HDS2 are exclusive-NORed, both these inputs being low does not constitute an enabled condition.

Figure 947. Select Input Logic

HDS1 HDS2

Internal Strobe HCS

When using the HAS input to sample HCNTL0/1, HBIL and HR/W, this allows these signals to be removed earlier in an access cycle, therefore allowing more time to switch bus states from address to data information, facilitating interface to multiplexed address and data type buses. In this type of system, an ALE signal is often provided and would normally be the signal connected to HAS. The two control pins (HCNTL0 and HCNTL1) indicate which internal HPI register is being accessed and the type of access to the register. The states of these two pins select access to the HPI address (HPIA), HPI data (HPID), or HPI control (HPIC) registers. The HPIA register serves as the pointer into HPI memory, the HPIC contains control and status bits for the transfers, and the HPID contains the actual data transferred. Additionally, the HPID register can be accessed with an optional automatic address increment. Table 926 describes the HCNTL0/1 bit functions.

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Table 926. HPI Input Control Signals Function Selection Descriptions

HCNTL1 0 0 1 1 HCNTL0 0 1 0 1 Description Host can read or write the HPI control register, HPIC. Host can read or write the HPI data latches. HPIA is automatically postincremented each time a read is performed and preincremented each time a write is performed. Host can read or write the address register, HPIA. This register points to the HPI memory. Host can read or write the HPI data latches. HPIA is not affected.

On the C57, HPI memory is a 2K  16-bit word block of single-access RAM that can be configured to reside either from 1000h to 17FFh in data memory space or from 8800h to 8FFFh in program memory space. As with all singleaccess RAM blocks, the HPI RAM is affected by the ROM protection feature, if it is enabled. Also, the HPI memory may be located at different addresses on other C5x devices; consult the specific product documentation. From the host interface, the 2K-word block of HPI memory can conveniently be accessed at addresses 0 through 7FFh; however, the memory can also be accessed by the host starting with any HPIA values with the 11 LSBs equal to 0. For example, the first word of the HPI memory block, addressed at 1000h by the C57 in data memory space, can be accessed by the host with any of the following HPIA values: 0000h, 0800h,1000h,1800h, ... F800h. The HPI autoincrement feature provides a convenient way of accessing consecutive word locations in HPI memory. In the autoincrement mode, a data read causes a postincrement of the HPIA, and a data write causes a preincrement of the HPIA. Therefore, if a write is to be made to the first word of HPI memory with the increment option, due to the preincrement nature of the write operation, the HPIA should first be loaded with any of the following values: 07FFh, 0FFFh, 17FFh, ... FFFFh. The HPIA is a 16-bit register and all 16 bits can be written to or read from, although with a 2K-word HPI memory implementation, only the 11 LSBs of the HPIA are required to address the HPI memory. The HPIA increment and decrement affect all 16 bits of this register.

HPI Control Register Bits and Function

Four bits control HPI operation. These bits are BOB (which selects first or second byte as most significant), SMOD (which selects host or shared-access mode), and DSPINT and HINT (which can be used to generate C5x and host interrupts, respectively) and are located in the HPI control register (HPIC). A detailed description of the HPIC bit functions is presented in Table 927.
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Host Port Interface

Table 927. HPI Control Register (HPIC) Bit Descriptions

Bit Host Access Read/Write C5x Access Description BOB If BOB = 1, first byte is least significant. If BOB = 0, first byte is most significant. BOB affects both data and address transfers. Only the host can modify this bit and it is not visible to the C5x. BOB must be initialized before the first data or address register access. DSPINT Write The host processor-to-C5x interrupt. This bit can be written only by the host and is not readable by the host or the C5x. When the host writes a 1 to this bit, an interrupt is generated to the C5x. Writing a 0 to this bit has no effect. Always read as 0. When the host writes to HPIC, both bytes must write the same value. See this subsection for a detailed description of DSPINT function. This bit determines the state of the C5x HINT output, which can be used to generate an interrupt to the host. HINT = 0 upon reset, which causes the external HINT output to be inactive (high). The HINT bit can be set only by the C5x and can be cleared only by the host. The C5x writes a 1 to HINT, causing the HINT pin to go low. The HINT bit is read by the host or the C5x as a 0 when the external HINT pin is inactive (high) and as a 1 when the HINT pin is active (low). For the host to clear the interrupt, however, it must write a 1 to HINT. Writing a 0 to the HINT bit by either the host or the C5x has no effect. See this subsection for a detailed description of HINT function. HINT Read/Write Read/Write SMOD Read Read/Write If SMOD = 1, shared-access mode (SAM) is enabled: the HPI memory can be accessed by the C5x. If SMOD = 0, host-only mode (HOM) is enabled: the C5x is denied access to the entire HPI RAM block. SMOD = 0 during reset; SMOD = 1 after reset. SMOD can be modified only by the C5x but can be read by both the C5x and the host.

Because the host interface always performs transfers with 8-bit bytes and the control register is normally the first register accessed to set configuration bits and initialize the interface, the HPIC is organized on the host side as a 16-bit register with the same high and low byte contents (although access to certain bits is limited, as described previously) and with the upper bits unused on the C5x side. The control/status bits are located in the least significant four bits. The host accesses the HPIC register with the appropriate selection of HCNTL0/1, as described previously, and two consecutive byte accesses to the 8-bit HPI data bus. When the host writes to HPIC, both the first and second byte written must be the same value. The C57 accesses the HPIC at 500h in data memory space.
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Host Port Interface

The layout of the HPIC bits is shown in Figure 948 through Figure 951. In the figures for read operations, if 0 is specified, this value is always read; if X is specified, an unknown value is read. For write operations, if X is specified, any value can be written. On a host write, both bytes must be identical. Note that bits 47 and 1215 on the host side and bits 415 on the C5x side are reserved for future expansion.

Figure 948. HPIC Diagram Host Reads from HPIC

1512 X 11 10 0 9 8 74 X 3 2 0 1 0 HINT SMOD BOB HINT SMOD BOB
Note: X = Unknown value is read.

Figure 949. HPIC Diagram Host Writes to HPIC

1512 X 11 10 9 8

74 X

HINT

DSPINT

BOB

HINT DSPINT

BOB

Note:

X = Any value can be written.

Figure 950. HPIC Diagram C5x Reads From HPIC

154 X

2 0

0 0

HINT

SMOD

Note:

X = Unknown value is read.

Figure 951. HPIC Diagram C5x Writes to HPIC

154 X

HINT

SMOD

Note:

X = Any value can be written.

Because the C5x can write to the SMOD and HINT bits, and these bits are read twice on the host interface side, the first and second byte reads by the host may yield different data if the C5x changes the state of one or both of these bits in between the two read operations. The characteristics of host and C5x HPIC read/write cycles are summarized in Table 928.

Table 928. HPIC Host/C5x Read/Write Characteristics

9-96

Device Host C5x Read Write 2 bytes 16 bits 2 bytes (Both bytes must be equal) 16 bits

Host Port Interface

9.10.3 Host Read/Write Access to HPI

The host begins HPI accesses by performing the external interface portion of the cycle; that is, initializing first the HPIC register, then the HPIA register, and then writing data to or reading data from the HPID register. Writing to HPIA or HPID initiates an internal cycle that transfers the desired data between the HPID and the dedicated internal HPI memory. Because this process requires several C5x cycles, each time an HPI access is made, data written to the HPID is not written to the HPI memory until after the host access cycle, and the data read from the HPID is the data from the previous cycle. Therefore, when reading, the data obtained is the data from the location specified in the previous access, and the current access serves as the initiation of the next cycle. A similar sequence occurs for a write operation: the data written to HPID is not written to HPI memory until after the external cycle is completed. If an HPID read operation immediately follows an HPID write operation, the same data (the data written) is read. The autoincrement feature available for HPIA results in sequential accesses to HPI memory by the host being extremely efficient. During random (nonsequential) transfers or sequential accesses with a significant amount of time between them, it is possible that the C5x may have changed the contents of the location being accessed between a host read and the previous host data read/write or HPIA write access, because of the prefetch nature of internal HPI operation. If this occurs, data different from the current memory contents may be read. Therefore, in cases where this is of concern in a system, two reads from the same address or an address write prior to the read access can be made to ensure that the most recent data is read. When the host performs an external access to the HPI, there are two distinctly different types of cycles that can occur: those for which wait states are generated (the HRDY signal is active) and those without wait states. In general, when in shared-access mode (SAM), the HRDY signal is used; when in hostonly mode (HOM), HRDY is not active and remains high; however, there are exceptions to this, which will be discussed. For accesses utilizing the HRDY signal, during the time when the internal portion of the transfer is being performed (either for a read or a write), HRDY is low, indicating that another transfer cannot yet be initiated. Once the internal cycle is completed and another external cycle can begin, HRDY is driven high by the HPI. This occurs after a fixed delay following a cycle initiation (refer to the C5x data sheet for detailed timing information for HPI external interface timings). Therefore, unless back-to-back cycles are being performed, HRDY is normally high when the first byte of a cycle is transferred. The external HPI cycle using HRDY is shown in the timing diagram in Figure 952.
On-Chip Peripherals
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Host Port Interface

Figure 952. HPI Timing Diagram

Byte 1 HCNTL0/1 HR/W HBIL Valid Valid Byte 2

HCS HAS (if used) HDS1, HDS2 HD read HD write HRDY

In a typical external access, as shown in Figure 952, the cycle begins with the host driving HCNTL0/1, HR/W, HBIL and HCS, indicating specifically what type of transfer is to occur and whether the cycle is to be read or a write. Then the host asserts the HAS signal (if used) followed by one of the data strobe signals. If HRDY is not already high, it goes high when the previous internal cycle is complete, allowing data to be transferred, and the control signals are deasserted. Following the external HPI cycle, HRDY goes low and stays low for a period of approximately five CLKOUT1 cycles (refer to C5x data sheet for HPI timing information) while the C5x completes the internal HPI memory access, and then HRDY is driven high again. Note, however, HRDY is always high when HCS is high. As mentioned previously, SAM accesses generally utilize the HRDY signal. The exception to the HRDY-based interface timings when in SAM occurs when reading HPIC or HPIA or writing to HPIC (except when writing 1 to either DSPINT or HINT). In these cases, HRDY stays high; for all other SAM accesses, HRDY is active.
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Valid Valid Valid Valid

Host Port Interface

Host access cycles when in HOM have timings different from the SAM timings described previously. In HOM, the CPU is not involved (with one exception), and the access can be completed after a short, fixed delay time. The exception to this occurs when writing 1s to the DSPINT or HINT bits in HPIC. In this case, the host access takes several CPU clock cycles, and SAM timings apply. Besides the HRDY timings and a faster cycle time, HOM access cycles are logically the same as SAM access cycles. A summary of the conditions under which the HRDY signal is active (where SAM timings apply) for host accesses is shown in Table 929. When HRDY is not active (HRDY stays high), HOM timings apply. Refer to the C5x data sheet for detailed HPI timing specifications.

Table 929. Wait-State Generation Conditions

Example Access Sequences

A complete host access cycle always involves two bytes, the first with HBIL low, and the second with HBIL high. This 2-byte sequence must be followed regardless of the type of host access (HPIA, HPIC, or data access) and the host must not break the first byte/second byte (HBIL low/high) sequence of an ongoing HPI access. If this sequence is broken, data may be lost, and unpredictable operation may result. Before accessing data, the host must first initialize HPIC, in particular the BOB bit, and then HPIA (in this order, because BOB affects the HPIA access). After initializing BOB, the host can then write to HPIA with the correct byte alignment. On an HPI memory read operation, after completion of the HPIA write, the HPI memory is read and the contents at the given address are transferred to the two 8-bit data latches, the first byte data latch and the second byte data latch. Table 930 illustrates the sequence involved in initializing BOB and HPIA for an HPI memory read. In this example, BOB is set to 0 and a read is requested of the first HPI memory location (in this case 1000h), which contains FFFEh.
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Wait State Generated Writes Register HPIA Reads No HOM No SAM Yes HPIC No 1 to DSPINT/HINT Yes All other cycles No HOM No HPID HOM No SAM Yes SAM Yes

Host Port Interface

Table 930. Initialization of BOB and HPIA

Event HD 00 00 10 00 HR/W 0 0 0 0 HCNTL1/0 00 00 10 10 HBIL 0 1 0 1 HPIC 00xx HPIA xxxx xxxx latch1 xxxx xxxx xxxx xxxx FF latch2 xxxx xxxx xxxx xxxx FE Host writes HPIC, 1st byte Host writes HPIC, 2nd byte Host writes HPIA, 1st byte 0000 0000 10xx Host writes HPIA, 2nd byte 1000 1000 Internal HPI RAM read complete

In the cycle shown in Table 930, BOB and HPIA are initialized, and by loading HPIA, an internal HPI memory access is initiated. The last line of Table 930 shows the condition of the HPI after the internal RAM read is complete; that is, after some delay following the end of the host write of the second byte to HPIA, the read is completed and the data has been placed in the upper and lower byte data latches. For the host to actually retrieve this data, it must perform an additional read of HPID. During this HPID read access, the contents of the first byte data latch appears on the HD pins when HBIL is low and the content of the second byte data latch appears on the HD pins when HBIL is high. Then the address is incremented if autoincrement is selected and the memory is read again into the data latches. Note that the address autoincrement occurs between the transfers of the first and second bytes. The sequence involved in this access is shown in Table 931.

Table 931. Read Access to HPI with Autoincrement

Event HD FF HR/W 1 1 HCNTL1/0 01 01 HBIL 0 1 HPIC 0000 0000 HPIA 1000 1001 1001 latch1 FF FF latch2 FE FE Host reads data, 1st byte Host reads data, 2nd byte FE Internal HPI RAM read complete 6A BC

In the access shown in Table 931, the data obtained from reading HPID is the data from the read initiated in the previous cycle (the one shown in Table 930) and the access performed as shown in Table 931 also initiates a further read, this time at location 1001h (because autoincrement was specified in this access by setting HCNTL1/0 to 01). Also, when autoincrement is selected, the increment occurs with each 16-bit word transferred (not with each byte); therefore, as shown in Table 931, the HPIA is incremented by only 1. The last line of Table 931 indicates that after the second internal RAM read is complete, the contents of location 1001h (6ABCh) has been read and placed into the upper and lower byte data latches.

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Host Port Interface

During a write access to the HPI, the first byte data latch is overwritten by the data coming from the host while the HBIL pin is low, and the second byte data latch is overwritten by the data coming from the host while the HBIL pin is high. At the end of this write access, the data in both data latches is transferred as a 16-bit word to the HPI memory at the address specified by the HPIA register. The address is incremented prior to the memory write because autoincrement is selected. An HPI write access is illustrated in Table 932. In this example, after the internal portion of the write is completed, location 1002h of HPI RAM contains 1234h. If a read of the same address follows this write, the same data just written in the data latches (1234h) is read back.

Table 932. Write Access to HPI with Auto-Increment

Event HD 12 34 HR/W 0 0 HCNTL1/0 01 01 HBIL 0 1 HPIC 0000 0000 HPIA 1001 1002 1002 latch1 12 12 12 latch2 FE 34 34 Host writes data, 1st byte Host writes data, 2nd byte Internal HPI RAM write complete

9.10.4 DSPINT and HINT Function Operation

The host and the C5x can interrupt each other using bits in the HPIC register. This subsection presents more information about this process.

Host Device Using DSPINT to Interrupt the C5x

A C5x interrupt is generated when the host writes a 1 to the DSPINT bit in HPIC. This interrupt can be used to wake up the C5x from IDLE. The host and the C5x always read this bit as 0. A C5x write has no effect. Once a 1 is written to DSPINT by the host, a 0 need not be written before another interrupt can be generated, and writing a 0 to this bit has no effect. The host should not write a 1 to the DSPINT bit while writing to BOB or HINT, or an unwanted C5x interrupt is generated. On the C5x, the host-to-C5x interrupt vector address is 18h. This interrupt is located in bit 11 of the IMR/IFR. Since the C5x interrupt vectors can be remapped into the HPI memory, the host can instruct the C5x to execute preprogrammed functions by simply writing the start address of a function to address 19h in the HPI memory prior to interrupting the C5x with a branch instruction located at address 18h.
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Host Port Interface (C5x) Using HINT to Interrupt the Host Device
When the C5x writes a 1 to the HINT bit in HPIC, the HINT output is driven low; the HINT bit is then read as a 1 by the C5x or the host. The HINT signal can be used to interrupt the host device. The host device, after detecting the HINT interrupt line, can acknowledge and clear the C5x interrupt and the HINT bit by writing a 1 to the HINT bit. The HINT bit is cleared and then read as a 0 by the C5x or the host, and the HINT pin is driven high. If the C5x or the host writes a 0, the HINT bit remains unchanged. While accessing the SMOD bit, the C5x should not write a 1 to the HINT bit unless it also wants to interrupt the host.

9.10.5 Considerations in Changing HPI Memory Access Mode (SAM/HOM) and IDLE2 Use
The HPI host-only mode (HOM) allows the host to access HPI RAM while the C5x is in IDLE2 (that is, completely halted). Additionally, the external clock input to the C5x can be stopped for the lowest power consumption configuration. Under these conditions, random accesses can still be made without having to restart the external clock for each access and wait for its lockup time if the C5x on-chip PLL is used. The external clock need only be restarted before taking the C5x out of IDLE2. The host cannot access HPI RAM in SAM when the C5x is in IDLE2, because CPU clocks are required for access in this mode of operation. Therefore, if the host requires access to the HPI RAM while the C5x is in IDLE2, the C5x must change HPI mode to HOM before entering IDLE2. When the HPI is in HOM, the C5x can access HPIC to toggle the SMOD bit or send an interrupt to the host, but cannot access the HPI RAM block; a C5x access to the HPI RAM is disregarded in HOM. In order for the C5x to again access the HPI RAM block, HPI mode must be changed to SAM after exiting IDLE2. To select HOM, a 0 must be written to the SMOD bit in HPIC. To select SAM, a 1 must be written to SMOD. When changing between HOM and SAM, two considerations must be met for proper operation. First, the instruction immediately following the one that changes from SAM to HOM must not be an IDLE2. This is because in this case, due to the C5x pipeline and delays in the SAM to HOM mode switch, the IDLE2 takes effect before the mode switch occurs, causing the HPI to remain in SAM; therefore, no host accesses can occur. The second consideration is that when changing from HOM to SAM, the instruction immediately following the one that changes from HOM to SAM cannot read the HPI RAM block. This requirement is due to the fact that the mode has not yet changed when the HPI RAM read occurs and the RAM read is
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ignored because the mode switch has not yet occurred. HPI RAM writes are not included in this restriction because these operations occur much later in the pipeline, so it is possible to write to HPI RAM in the instruction following the one which changes from HOM to SAM. On the host side, there are no specific considerations associated with the mode changes. For example, it is possible to have a third device wake up the C5x from IDLE2 and the C5x changing to SAM upon wake-up without a software handshake with the host. The host can continue accessing while the HPI mode changes. However, if the host accesses the HPI RAM while the mode is being changed, the actual mode change will be delayed until the host access is completed. In this case, a C5x access to the HPI memory is also delayed. Table 933 illustrates the sequence of events involved in entering and exiting an IDLE2 state on the C5x when using the HPI. Throughout the process, the HPI is accessible to the host.

Table 933. Sequence of Entering and Exiting IDLE2

9.10.6 Access of HPI Memory During Reset

Host or Other Device C5x Mode HOM HOM HOM HOM C5x clock Running Running Running Switches mode to HOM Executes a NOP Executes IDLE2 instruction In IDLE2 May stop DSP clock Stopped or running Running Running Running Running Turns on DSP clock if it was stopped Sends an interrupt to DSP In IDLE2 In IDLE2 HOM HOM HOM SAM C5x wakes up from IDLE2 C5x switches mode to SAM
Sufficient wake-up time must be ensured when the C5x on-chip PLL is used.

The C5x is not operational during reset, but the host can access the HPI, allowing program or data downloads to the HPI memory. When this capability is used, it is often convenient for the host to control the C5x reset input. The sequence of events for resetting the C5x and downloading a program to HPI memory while the C5x is in reset is summarized in Table 934 and corresponds to the reset of the C5x.
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Initially, the host stops accessing the HPI at least six C5x periods before driving the C5x reset line low. The host then drives the C5x reset line low and can start accessing the HPI after a minimum of four C5x periods. The HPI mode is automatically set to HOM during reset, allowing high-speed program download. The C5x clock can even be stopped at this time; however, the clock must be running when the reset line falls and rises for proper reset operation of the C5x. Once the host has finished downloading into HPI memory, the host stops accessing the HPI and drives the C5x reset line high. At least 20 C5x periods after the reset line rising edge, the host can again begin accessing the HPI. This number of periods corresponds to the internal reset delay of the C5x. The HPI mode is automatically set to SAM upon exiting reset. On the C5x, the RAM and OVLY bits must be set to 1 after reset for the HPI memory to be mapped into C5x program and data space, as with other singleaccess RAM blocks. The host, however, can access the HPI memory regardless of the status of these two bits. Also, if the host writes a 1 to DSPINT while the C5x is in reset, the interrupt is lost when the C5x comes out of reset. The C5x warm boot can use the HPI memory and start execution from the lowest HPI address.

Table 934. HPI Operation During RESET

Host C5x Mode X C5x clock Running Running Waits 6 C5x clock periods Running Brings RESET low and waits 4 clocks Can stop C5x clock Goes into reset In reset In reset In reset In reset HOM HOM HOM HOM HOM SAM SAM Stopped or Running Stopped or Running Running Running Running Running Writes program and/or data in HPI memory Turns on DSP clock if it was stopped Brings RESET high Waits 20 C5x clock periods Can access HPI Comes out of reset Running
Sufficient wake-up time must be ensured when the C5x on-chip PLL is used.

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Appendix A Appendix A

Pinouts and Signal Descriptions

The TMS320C5x DSPs are available in a 100-pin quad flat-pack (QFP), 100-pin thin quad flat-pack (TQFP), 128-pin TQFP, 132-pin bumpered quad flat-pack (BQFP), and 144-pin TQFP packages. All packages conform to JEDEC specifications for electrical/electronic components. Refer to the figures and tables in this appendix for the pin/signal assignments of the different packages. Also, this appendix presents a table of signal definitions.

Topic
A.1 A.2 A.3 A.4 A.5 A.6 A.7

Page
100-Pin QFP Pinout (C52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 100-Pin TQFP Pinout (C51, C52, C53S, and LC56) . . . . . . . . . . . . . . A-4 128-Pin TQFP Pinout (LC57) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 132-Pin BQFP Pinout (C50, C51, and C53) . . . . . . . . . . . . . . . . . . . . . A-8 144-Pin TQFP Pinout (C57S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 100-Pin TQFP Device-Specific Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . A-12 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13

Pinouts and Signal Descriptions

A-1

100-Pin QFP Pinout (C52)

A.1 100-Pin QFP Pinout (C52)

Refer to Figure A1 and Table A1 for pin/signal assignments of the C52 in the 100-pin QFP package.

Figure A1. Pin/Signal Assignments for the C52 in 100-Pin QFP

BIO HOLD READY RS VSSI VSSI CLKX VSSI TOUT VSSC
80 79 78 77 76 75

D9 D10 D11 D12 D13 D14 D15 MP/MC VSSI D8 VDDD VSSD VSSD D7 D6 D5 D4 D3 D2 D1 D0 TMS VDDD VDDD TCK VSSD VSSD INT1 INT2 INT3 INT4 NMI DR VSSI FSR CLKR VDDA VSSA A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

TRST

EMU1/OFF EMU0 VDDC VDDC VDDI VDDI CLKOUT1 XF HOLDA NC DX VSSI FSX CLKMD2 VSSI VSSI TDO VDDC X1 X2/CLKIN CLKIN2 BR STRB R/W PS IS DS VSSC WE RD

(PJ package) (Top view)

74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A1 A2 A3 A4 A5 A6 A7 A8 A9 VDDI TDI VSSA CLKMD1

A10 A11 A12

A13

Note:

NC

These pins are not connected (reserved).

A-2

A14 A15 VDDA

100-Pin QFP Pinout (C52)

Table A1. Signal/Pin Assignments for the C52 in 100-Pin QFP

Signal A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BR BIO CLKIN2 CLKMD1 CLKMD2 CLKOUT1 CLKR CLKX D0 D1 D2 D3 D4 D5 Pin 30 31 32 33 34 35 36 37 38 39 44 45 46 47 48 49 59 90 60 43 67 74 27 84 12 11 10 9 8 7 Signal D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DR DS DX EMU0 EMU1/OFF FSR FSX HOLD HOLDA INT1 INT2 INT3 INT4 IS MP/MC NMI PS READY RD RS Pin 6 5 1 100 99 98 97 96 95 94 24 54 70 79 80 26 68 89 72 19 20 21 22 55 93 23 56 88 51 87 Signal R/W STRB TCK TDI TDO TMS TOUT TRST VDDA VDDA VDDC VDDC VDDC VDDD VDDD VDDD VDDI VDDI VDDI VSSA VSSA VSSC VSSC VSSD VSSD VSSD VSSD VSSI VSSI VSSI Pin 57 58 16 41 64 13 82 91 28 50 78 77 63 2 14 15 40 75 76 42 29 53 81 3 4 17 18 83 85 86 Signal VSSI VSSI VSSI VSSI VSSI WE X1 X2/CLKIN1 XF Pin 69 66 65 92 25 52 62 61 73 71

This pin is not connected (reserved).

Pinouts and Signal Descriptions

A-3

100-Pin TQFP Pinout (C51, C52, C53S, and LC56)

A.2 100-Pin TQFP Pinout (C51, C52, C53S, and LC56)

Refer to Figure A2 and Table A2 for pin/signal assignments of the C51, C52, C53S, and LC56 in the 100-pin TQFP package. Table A6 on page A-12 lists device-specific pin/signal assignments for the C51, C52, C53S, and LC56.

Figure A2. Pin/Signal Assignments for the C51, C52, C53S, and LC56 in 100-Pin TQFP
CLKOUT1 XF HOLDA VDDC VDDI VDDI TDO VDDC X1 X2/CLKIN CLKMD2 VSSI VSSI DS VSSC BR STRB R/W

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

EMU0 EMU1/OFF VSSC TOUT * * * * RS READY HOLD BIO TRST VSSI VSSI MP/MC D15 D14 D13 D12 D11 D10 D9 D8 VDDD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PS IS

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

(PZ package) (Top view)

WE RD VDDA A15 A14 A13 A12 A11 A10 CLKMD1 VSSA VSSA TDI VDDI A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSSA

D7 D6 D5 D4 D3 D2 D1 D0 TMS VDDD TCK VSSD VSSD

VSSD VSSD

Note:

These pins are reserved for specific devices (see Table A6 on page A-12).

A-4

VDDA

INT1

INT2 INT3 INT4 NMI

100-Pin TQFP Pinout (C51, C52, C53S, and LC56)

Table A2. Signal/Pin Assignments for the C51, C52, C53S, and LC56 in 100-Pin TQFP
Signal A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BR BIO CLKMD1 CLKMD2 CLKOUT1 D0 D1 D2 D3 D4 D5 D6 D7 D8
Legend: *

Pin 52 53 54 55 56 57 58 59 60 61 67 68 69 70 71 72 82 12 66 90 97 35 34 33 32 31 30 29 28 24

Signal D9 D10 D11 D12 D13 D14 D15 DS EMU0 EMU1/OFF HOLD HOLDA INT1 INT2 INT3 INT4 IS MP/MC NMI PS READY RD RS R/W STRB TCK TDI TDO TMS TRST

Pin 23 22 21 20 19 18 17 77 1 2 11 95 41 42 43 44 78 16 45 79 10 74 9 80 81 38 63 87 36 13

Signal VDDA VDDA VDDC VDDC VDDD VDDD VDDI VDDI VDDI
TOUT

Pin 50 73 86 100 25 37 62 98 99 4 65 64 51 3 76 26 27 39 40 14 15 88 89 75 85 84 96 5 6 7

Signal * * * * * * * * * *

Pin 8 46 47 48 49 83 91 92 93 94

VSSA VSSA VSSA VSSC VSSC VSSD VSSD VSSD VSSD VSSI VSSI VSSI VSSI WE X1 X2/CLKIN XF * * *

These pins are reserved for specific devices (see Table A6 on page A-12).

Pinouts and Signal Descriptions

A-5

128-Pin TQFP Pinout (LC57)

A.3 128-Pin TQFP Pinout (LC57)

Refer to Figure A3 and Table A3 for pin/signal assignments of the LC57 in the 128-pin TQFP package.

Figure A3. Pin/Signal Assignments for the LC57 in 128-Pin TQFP

VDDI CKLOUT1 XF HOLDA BDX DX X2/CLKIN FSX HD5 CLKMD2 HD4 VSSI CLKMD3

VDDC VDDI

VDDC X1

DS HD2 VSSC

128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97

VSSC
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

STRB

HD7 BFSX HD6

VSSI TDO

BR HD3

R/W

PS IS

HINT EMU0 EMU1/OFF VSSC VSSC TOUT BCLKX CLKX VDDC BFSR BCLKR RS READY HOLD BIO VDDC VDDC IAQ TRST VSSI VSSI MP/MC D15 D14 D13 D12 D11 D10 D9 D8 VDDD VDDD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

(PBK package) (Top view)

WE HD1 RD HD0 HRDY VDDA A15 A14 A13 A12 A11 A10 CLKMD1 VSSA VSSA TDI HDS1 HDS2 VDDI VDDI A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSSA HCS

VSSD VSSD D7 D6 D5 D4 D3 D2 D1 D0 HCNTL0 TMS

HCNTL1 VDDD

HR/W INT1

VDDD TCK

INT3 INT4 HBIL

NMI DR

BDR FSR CLKR VDDA VDDA

VSSD VSSD

A-6

INT2

HAS

128-Pin TQFP Pinout (LC57)

Table A3. Signal/Pin Assignments for the LC57 in 128-Pin TQFP

Signal A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BCLKR BCLKX BDR BDX BFSR BFSX BIO BR X2/CLKIN CLKMD1 CLKMD2 CLKMD3 CLKOUT1 CLKR Pin 67 68 69 70 71 72 73 74 75 76 85 86 87 88 89 90 11 7 59 122 10 119 15 106 108 84 115 107 125 61 Signal CLKX D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DR DS DX EMU0 EMU1/OFF FSR FSX HAS HBIL HCNTL0 HCNTL1 HCS HD0 Pin 8 42 41 40 39 38 37 36 35 30 29 28 27 26 25 24 23 58 100 121 2 3 60 117 64 56 43 45 65 93 Signal HD1 HD2 HD3 HD4 HD5 HD6 HD7 HDS1 HDS2 HINT HOLD HOLDA HRDY HR/W IAQ INT1 INT2 INT3 INT4 IS MP/MC NMI PS RD READY RS R/W STRB TCK TDI Pin 95 99 105 114 116 118 120 80 79 1 14 123 92 51 18 52 53 54 55 101 22 57 102 94 13 12 103 104 48 81 Signal TDO TMS TOUT TRST VDDC VDDA VDDA VDDA VDDC VDDC VDDC VDDC VDDD VDDD VDDD VDDD VDDI VDDI VDDI VDDI VSSA VSSA VSSA VSSC VSSC VSSC VSSC VSSD VSSD VSSD Pin 111 44 6 19 9 91 63 62 16 17 110 128 31 32 46 47 77 78 126 127 66 82 83 4 5 97 98 33 34 49 Signal VSSD VSSI VSSI VSSI VSSI WE X1 XF Pin 50 20 21 112 113 96 109 124

Pinouts and Signal Descriptions

A-7

132-Pin BQFP Pinout (C50, C51, and C53)

A.4 132-Pin BQFP Pinout (C50, C51, and C53)

Refer to Figure A4 and Table A4 for pin/signal assignments of the C50, C51, and C53 in the 132-pin BQFP package.

Figure A4. Pin/Signal Assignments for the C50, C51, and C53 in 132-Pin BQFP
TCLKR TFSR/TADD CLKX TCLKX TOUT VSSC VSSC EMU1/OFF

D8 D9 D10 D11 D12 D13 D14 D15 MP/MC VSSI VSSI TRST IAQ VDDC VDDC

READY RS

NC NC VDDD VDDD

17 16 15 14 13 12 11 10

1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116

NC NC VSSD VSSD NC D7 D6 D5 D4 D3 D2 D1 D0 TMS VDDD VDDD TCK VSSD VSSD NC INT1 INT2 INT3 INT4 NMI DR TDR FSR CLKR VDDA VDDA NC NC

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

BIO HOLD

EMU0 NC

(PQ package) (Top view)

115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84

NC NC VDDI VDDI IACK NC CLKOUT1 XF HOLDA TDX DX TFSX/TFRM FSX CLKMD2 VSSI VSSI TDO VDDC VDDC X1 X2/CLKIN CLKIN2 BR STRB R/W PS IS DS NC VSSC VSSC NC NC

VSSA VSSA NC CLKMD1

VDDA VDDA

VSSA VSSA A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 VDDI VDDI TDI

Note:

NC

These pins are not connected (reserved).

A-8

A10 A11 A12 A13 A14 A15 NC NC

RD WE

NC NC

132-Pin BQFP Pinout (C50, C51, and C53)

Table A4. Signal/Pin Assignments for the C50, C51, and C53 in 132-Pin BQFP
Signal A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BR BIO CLKIN2 CLKMD1 CLKMD2 CLKOUT1 CLKR CLKX D0 D1 D2 D3 D4 D5 Pin 55 56 57 58 59 60 61 62 63 64 72 73 74 75 76 77 94 130 95 71 103 110 46 124 30 29 28 27 26 25 Signal D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DR DS DX EMU0 EMU1/OFF FSR FSX HOLD HOLDA IACK IAQ INT1 INT2 INT3 INT4 IS MP/MC NMI PS READY Pin 24 23 13 12 11 10 9 8 7 6 43 89 106 118 119 45 104 129 108 112 1 38 39 40 41 90 5 42 91 128 Signal RD RS R/W STRB TCK TCLKR TCLKX TDI TDO TDR TDX TMS TOUT TRST TFSR/TADD TFSX/TFRM VDDC VDDC VDDA VDDA VDDA VDDA VDDC VDDC VDDD VDDD VDDD VDDD VDDI VDDI Pin 82 127 92 93 34 126 123 67 100 44 107 31 122 2 125 105 131 132 47 48 80 81 98 99 14 15 32 33 113 114 Signal VDDI VDDI VSSA VSSA VSSA VSSA VSSC VSSC VSSC VSSC VSSD VSSD VSSD VSSD VSSI VSSI VSSI VSSI WE X1 X2/CLKIN XF { { { { { { { { Pin 65 66 53 54 68 69 86 87 121 120 20 21 35 36 3 4 101 102 83 97 96 109 16 17 18 19 22 37 49 50 Signal { { {
{

Pin 51 52 70 78 79 84 85 88 111 115 116 117

{ { { { { { { {

These pins are not connected (reserved).

Pinouts and Signal Descriptions

A-9

144-Pin TQFP Pinout (C57S)

A.5 144-Pin TQFP Pinout (C57S)

Refer to Figure A5 and Table A5 for pin/signal assignments of the C57S in the 144-pin TQFP package.

Figure A5. Pin/Signal Assignments for the C57S in 144-Pin TQFP

VDDC VDDI VDDI NC CKLOUT1 XF HOLDA BDX DX HD7 BFSX HD6 FSX HD5 CLKMD2 HD4 VSSI VSSI TDO NC VDDC X1 X2/CLKIN CLKMD3 NC BR HD3 NC STRB R/W PS IS DS HD2 VSSC VSSC
121 120 119 118 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126

HINT EMU0 NC EMU1/OFF VSSC VSSC TOUT BCLKX CLKX VDDC BFSR BCLKR RS READY HOLD NC BIO VDDC VDDC IAQ TRST VSSI VSSI MP/MC D15 D14 D13 NC D12 D11 D10 D9 NC D8 VDDD VDDD

125 124 123 122

113 112 111 110 109

117 116 115 114

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

(PGE package) (Top view)

108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 61 62 63 64 65 66 67 68 69 70 71 72

WE HD1 RD HD0 HRDY VDDA A15 NC A14 A13 A12 NC A11 A10 CLKMD1 VSSA VSSA TDI HDS1 HDS2 VDDI VDDI A9 A8 A7 NC A6 A5 A4 A3 NC A2 A1 A0 VSSA HCS

49 50 51 52

53 54 55 56

Note:

NC

These pins are not connected (reserved).

A-10

VSSD V SSD D7 D6 NC D5 D4 D3 NC D2 D1 D0 HCNTL0 TMS HCNTL1 VDDD VDDD TCK VSSD VSSD NC HR/W INT1 INT2 INT3 INT4 HBIL NMI DR BDR FSR CLKR V DDA V DDA HAS NC

57 58 59 60

144-Pin TQFP Pinout (C57S)

Table A5. Signal/Pin Assignments for the C57S in 144-Pin TQFP

Signal A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BCLKR BCLKX BDR BDX BFSR BFSX BIO BR CLKMD1 CLKMD2 CLKMD3 CLKOUT1 CLKR Pin 75 76 77 79 80 81 82 84 85 86 95 96 98 99 100 102 12 8 66 137 11 134 17 119 94 130 121 140 68 Signal CLKX D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DR DS DX EMU0 EMU1/OFF FSR FSX HAS HBIL HCNTL0 HCNTL1 HCS Pin 9 48 47 46 44 43 42 40 39 34 32 31 30 29 27 26 25 65 112 136 2 4 67 132 71 63 49 51 73 Signal HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HDS1 HDS2 HINT HOLD HOLDA HRDY HR/W IAQ INT1 INT2 INT3 INT4 IS MP/MC NMI PS RD READY RS R/W STRB Pin 105 107 111 118 129 131 133 135 90 89 1 15 138 104 58 20 59 60 61 62 113 24 64 114 106 14 13 115 116 Signal TCK TDI TDO TMS TOUT TRST VDDA VDDA VDDA VDDC VDDC VDDC VDDC VDDC VDDD VDDD VDDD VDDD VDDI VDDI VDDI VDDI VSSA VSSA VSSA VSSC VSSC VSSC VSSC Pin 54 91 126 50 7 21 69 70 103 10 18 19 124 144 35 36 52 53 87 88 142 143 74 92 93 5 6 109 110 Signal VSSD VSSD VSSD VSSD VSSI VSSI VSSI VSSI WE X1 X2/CLKIN XF { { { { { { { { { { { { { { { { Pin 37 38 55 56 22 23 127 128 108 123 122 139 3 16 28 33 41 45 57 72 78 83 97 101 117 120 125 141

These pins are not connected (reserved).

Pinouts and Signal Descriptions

A-11

100-Pin TQFP Device-Specific Pinouts

A.6 100-Pin TQFP Device-Specific Pinouts

Table A6 lists device-specific pin/signal assignments for the C51, C52, C53S, and LC56 in the 100-pin TQFP package. Refer to Figure A2 on page A-4 and Table A2 on page A-5 for common pin/signal assignments of the C51, C52, C53S, and LC56.

Table A6. Device-Specific Pin/Signal Assignments for the C51, C52, C53S, and LC56 in 100-Pin TQFP
Pin 5 6} 7 8 46} 47 48} 49} 83 91} 92 93} 94 C51 TCLKX CLKX TFSR/TADD TCLKR DR TDR FSR CLKR CLKIN2 FSX TFSX/TFRM DX TDX C52 VSSI CLKX VSSI VSSI DR VSSI FSR CLKR CLKIN2 FSX VSSI DX NC C53S CLKX2 CLKX1 FSR2 CLKR2 DR1 DR2 FSR1 CLKR1 CLKIN2 FSX1 FSX2 DX1 DX2 LC56 BCLKX CLKX BFSR BCLKR DR BDR FSR CLKR CLKMD3 FSX BFSX DX BDX

Pin names beginning with B indicate signals on the buffered serial port (BSP). No change in function. NC = These pins are not connected (reserved).

A-12

Signal Descriptions

A.7 Signal Descriptions

Table A7 through Table A18 list each signal, specifies the signals operating state(s), and describes the signals function.

Table A7. Address and Data Bus Signal Descriptions

Signal A15 (MSB) A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB) D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB)
Note:

State I/O/Z

Description Parallel, bidirectional, 3-state address bus A15 (MSB) through A0 (LSB). Multiplexed to address external data/program memory or I/O. Placed in high-impedance state in hold mode or when OFF { is active (low). These signals are used as inputs for external DMA access of the on-chip single-access RAM. They become inputs while HOLDA is active low, if the BR pin is externally driven low.

I/O/Z

Parallel, bidirectional, 3-state data bus D15 (MSB) through D0 (LSB). Multiplexed to transfer data between the core CPU and external data/program memory or I/O devices. Placed in high-impedance state when not outputting, when RS or HOLD is asserted, or when OFF { is active (low). These signals are also used in external DMA access of the on-chip single-access RAM.

Input pins that are unused may be connected to VDD or to an external pullup resistor. The BR pin has an internal pullup for performing DMA to the on-chip RAM. Legend: I Input O Output Z High impedance { The OFF signal, when active (low), puts all C5x output drivers into the high-impedance state.

Pinouts and Signal Descriptions

A-13

Signal Descriptions

Table A8. Memory Control Signal Descriptions

Signal DS PS IS RD State O/Z Description Data, program, and I/O space select signals. Always high unless low level is asserted for communicating to a particular external space. Placed into a high-impedance state in hold mode or when OFF { is active (low). Read select. Indicates an active, external read cycle and may connect directly to the output enable (OE) of external devices. This signal is active on all external program, data, and I/O reads. It is placed into high-impedance state in hold mode or when OFF { is active (low). Data ready input. Indicates whether an external device is prepared for the bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. READY also indicates a bus grant to an external device after a BR (bus request) signal. Read/write signal. Indicates transfer direction during communication to an external device. Normally in read mode (high), unless low level is asserted for performing a write operation. Placed in high-impedance state in hold mode or when OFF { is active (low). R/W is also used in external DMA access of the on-chip RAM cell. While HOLDA and IAQ are active (low), this signal indicates the direction of the data bus for DMA reads (high) and writes (low). Strobe signal. Always high unless asserted low to indicate an external bus cycle. Placed in high-impedance state in the hold mode or when OFF { is active (low). STRB is also used in external DMA access of the on-chip single-access RAM. While HOLDA and IAQ are active (low), this signal is used to select the memory access. Write enable. The falling edge of this signal indicates that the device is driving the external data bus (D15D0). Data can be latched by an external device on the rising edge of WE. This signal is active on all external program, data, and I/O writes. It is placed into high-impedance state in hold mode or when OFF { is active (low).

O/Z

READY

R/W

I/O/Z

STRB

I/O/Z

WE

O/Z

Input pins that are unused may be connected to VDD or to an external pullup resistor. The BR pin has an internal pullup for performing DMA to the on-chip RAM. Legend: I Input O Output Z High impedance { The OFF signal, when active (low), puts all C5x output drivers into the high-impedance state.

Note:

A-14

Signal Descriptions

Table A9. Multiprocessing Signal Descriptions

Signal BIO BR State I I/O/Z Description Branch control input. Can be used to control a conditional branch instruction. BIO is sampled during the fetch of the conditional branch instruction. Bus request signal. Asserted during access of external global data memory space. READY is asserted to the device when the global data memory is available for the bus transaction. BR can be used to extend the data memory address space by up to 32K words. It goes into high impedance when OFF { is active (low). BR is used in external DMA access of the on-chip single-access RAM. While HOLDA is active low, BR is externally driven low to request access to the on-chip single-access RAM. Hold input. This signal is asserted to request control of the address, data, and control lines. When HOLDA is acknowledged by the C5x, these lines go to the highimpedance state. Hold acknowledge signal. Indicates to the external circuitry that the processor is in a hold state. At the same time, the address, data, and memory control lines are in a high-impedance state so that they are available to the external circuitry for access of local memory. This signal also goes into high impedance when OFF { is active (low). Interrupt acknowledge signal. Indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15A0. This signal goes into high impedance when OFF { is active (low). Instruction acquisition signal. This signal is asserted (active) when there is an instruction address on the address bus. This signal goes into high impedance when OFF { is active (low). IAQ is also used in external DMA access of the on-chip singleaccess RAM. While HOLDA is active low, IAQ acknowledges the BR request for access of the on-chip single-access RAM and stops indicating instruction acquisition. External flag output (latched software-programmable signal). This signal is set high or low by specific instructions or by loading status register 1 (ST1). XF can be used for signaling other processors in multiprocessor configurations or as a generalpurpose output pin. This signal also goes into high impedance when OFF { is active (low). This pin is set high at reset.

HOLD

HOLDA

O/Z

IACK

O/Z

IAQ

O/Z

XF

O/Z

Note:

Input pins that are unused may be connected to VDD or to an external pullup resistor. The BR pin has an internal pullup for performing DMA to the on-chip RAM. Legend: I Input O Output Z High impedance { The OFF signal, when active (low), puts all C5x output drivers into the high-impedance state.

Pinouts and Signal Descriptions

A-15

Signal Descriptions

Table A10. Initialization, Interrupt, and Reset Operations Signal Descriptions

Signal INT4 INT3 INT2 INT1 MP/MC State I Description External user interrupt inputs. Prioritized and maskable by the interrupt mask register (IMR) and interrupt mode (INTM) bit in status register 0 (ST0). Can be polled and reset via the interrupt flag register (IFR). Microprocessor/microcomputer mode select pin. If active (low) at reset (microcomputer mode), the pin causes the internal program ROM to be mapped into program memory space. In the microprocessor mode, all program memory is mapped externally. This pin is sampled only during reset, and the mode is set at reset. The mode can be overridden via the software control bit MP/MC in the PMST register. Nonmaskable interrupt. External interrupt that cannot be masked via the IMR or the INTM bit in ST0. When NMI is activated, the processor traps to the appropriate vector location. Reset input. Causes the device to terminate execution and forces the program counter to 0. When RS is brought to a high level, execution begins at location 0h of program memory. RS affects various registers and status bits.

NMI

RS

Note: Input pins that are unused may be connected to VDD or to an external pullup resistor. Legend: I Input

Table A11. Supply Signal Descriptions

Signal VDDA VDDC VDDD VDDI VSSA VSSC VSSD VSSI State S S S S S S S S Description Power supply for address bus. Power supply for memory control signals. Power supply for data bus. Power supply for inputs and internal logic. Ground for address bus. Ground for memory control signals. Ground for data bus. Ground for inputs and internal logic.

Note: Input pins that are unused may be connected to VDD or to an external pullup resistor. Legend: S Supply

A-16

Signal Descriptions

Table A12. Oscillator/Timer Signal Descriptions

Signal CLKIN2 CLKOUT1 State I O/Z Description External clock input. Divide-by-1 input clock for driving the internal machine rate. PLL clock input for C50, C51, C52, C53, and C53S. Master clock output signal. This signal cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the rising edges of this signal. This signal goes into high impedance when OFF } is active (low). Timer output. This pin issues a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT1 cycle wide. Internal oscillator output. Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, this pin should be left unconnected. This signal does not go into high impedance when OFF } is active (low). External clock input. Input pin to internal oscillator from the crystal. If the internal oscillator is not being used, a clock may be input to the device on this pin. PLL clock input for LC56, C57S, and LC57. Clock mode input. Input pin to determine clock mode. Refer to Table A13 and Table A14 for the clock options. Clock mode input. Input pin to determine clock mode. Refer to Table A13 and Table A14 for the clock options. Clock mode input. Input pin to determine clock mode. Refer to Table A14 for the clock options.

TOUT X1

O O

X2/CLKIN

CLKMD1 CLKMD2 CLKMD3

I I I

Note: Input pins that are unused may be connected to VDD or to an external pullup resistor. Legend: I Input O Output Z High impedance { This pin is not available on the LC56, C57S, and LC57 devices. } The OFF signal, when active (low), puts all C5x output drivers into the high-impedance state. This pin is not available on the C50, C51, C52, C53, and C53S devices.

Pinouts and Signal Descriptions

A-17

Signal Descriptions

Table A13. Oscillator/Timer Standard Options (C50, C51, C52, C53, and C53S Only)
Signal CLKMD1 CLKMD2 State I CLKMD1 CLKMD2 0 0
-

Clock Mode PLL disabled Internal oscillator disabled Input clock provided to X2/CLKIN pin External clock with divide-by-2 option Reserved for test purposes PLL enabled Internal oscillator disabled Input clock provided to CLKIN2 pin External clock option: For C50, C51, C53, and C53S: multiply-by-1 option For C52: multiply-by-2 option PLL disabled Internal oscillator enabled Input clock provided to X2/CLKIN pin Internal or external divide-by-2 option

0 1

1 0

Note: Input pins that are unused may be connected to VDD or to an external pullup resistor. Legend: I Input

A-18

Signal Descriptions

Table A14. Oscillator/Timer Expanded Options (LC56, C57S, and LC57 Only)
Signal CLKMD1 CLKMD2 CLKMD3 State I CLKMD1 CLKMD2 CLKMD3 0 0 0
-

Clock Mode PLL enabled Internal oscillator disabled External multiply-by-3 option Internal oscillator disabled External divide-by-2 option PLL enabled Internal oscillator disabled External multiply-by-4 option PLL enabled Internal oscillator disabled External multiply-by-2 option PLL enabled Internal oscillator disabled External multiply-by-5 option PLL enabled Internal oscillator disabled External multiply-by-1 option PLL enabled Internal oscillator disabled External multiply-by-9 option Internal oscillator enabled External/internal divide-by-2 option

0 0

0 1

1 0

Note: Input pins that are unused may be connected to VDD or to an external pullup resistor. Legend: I Input

Pinouts and Signal Descriptions

A-19

Signal Descriptions

Table A15. Serial Port Interface Signal Descriptions

Signal CLKR CLKR1 CLKR2 TCLKR State I Description Receive clock signal. External clock signal for clocking data into the data receive shift register (RSR) from the data receive pin(s): - C50, C51, or C53: pins DR or TDR. - C53S: pins DR1 or DR2. - C51, C52, LC56, C57S, or LC57: pin DR. The receive clock signal must be present during serial port transfers. If the serial port is not being used, the pin(s) can be sampled as an input via the IN0 bit in the serial port control register (SPC and/or TSPC). CLKX CLKX1 CLKX2 TCLKX I/O/Z Transmit clock signal. Clock signal for clocking data from the data transmit shift register (XSR) to the data transmit pin(s): - C50, C51, or C53: pins DX or TDX. - C53S: pins DX1 or DX2. - C51, C52, LC56, C57S, or LC57: pin DX. The clock signal can be an input if the MCM bit in the SPC (TSPC) is cleared. This pin may also be driven by the device at 1/4 the CLKOUT1 frequency when the MCM bit is set. If the serial port is not being used, the pin(s) can be sampled as an input via the IN1 bit in the SPC (and/or TSPC). The signal(s) go into high impedance when the OFF { signal is active (low). DR DR1 DR2 TDR DX DX1 DX2 TDX FSR FSR1 FSR2 TFSR/ TADD FSX FSX1 FSX2 TFSX/ TFRM I Received serial data. The RSR receives serial data through this input pin.

O/Z

Transmitted serial data. The XSR transmits serial data through this pin. This pin is placed in a high-impedance state when not transmitting and also when the OFF { signal is active (low). Receive frame synchronization. The falling edge of these pulses initiates the data receive process, beginning the clocking of the RSR. TFSR becomes an input/output (TADD) pin when the C50, C51, and the C53 are operating in TDM mode (TDM bit = 1). In TDM mode, this pin is used to output/input the address of the port. This signal goes into high impedance when OFF { is active (low). Transmit frame synchronization. The falling edge of these pulses initiates the data transmit process, beginning the clocking of the XSR. Following reset, the default operating condition of these pulses is an input. This pin can be selected by software to be an output when the TXM bit in the SPC (TSPC) is set. This signal goes into high impedance when the OFF { signal is active (low). When the C50, C51, and C53 are operating in the TDM mode (TDM bit = 1), the TFSX pin becomes TFRM (TDM frame synch).

I/O/Z

I/O/Z

Note: Input pins that are unused may be connected to VDD or to an external pullup resistor. Legend: I Input O Output Z High impedance { The OFF signal, when active (low), puts all C5x output drivers into the high-impedance state.

A-20

Signal Descriptions

Table A16. Buffered Serial Port Interface Signal Descriptions (LC56 and C57 Only)
Signal BCLKR State I Description Receive clock signal. External clock signal for clocking data into the data receive shift register (BRSR) from the data receive (BDR) pin. Data is clocked on the falling edge of BCLKR, if the CLKP bit in the BSP control extension register (SPCE) is cleared; data is clocked on the rising edge of BCLKR, if the CLKP bit is set. If the serial port is not used, this pin can be sampled as an input via the IN0 bit in the SPC. Transmit clock signal. Clock signal for clocking data from the data transmit shift register (BXSR) to the data transmit (BDX) pin. Data is clocked on the rising edge of CLKX, if the CLKP bit in the SPCE is cleared; data is clocked on the falling edge of CLKX, if the CLKP bit is set. CLKX can be an input if the MCM bit in the BSP control register (BSPC) is cleared. When the MCM bit of BSPC is set to 1, CLKX is driven by an on-chip source having a frequency equal to 1/(CLKDV+1) of CLKOUT. CLKDV value is defined in SPCE. When CLKDV is odd or equal to 0, the CLKX duty cycle is 50%. When CLKDV is an even value (CLKDV=2p), the CLKX high and low state durations depend on CLKP. When CLKP is 0, the high state duration is p+1 cycles and the low state duration is p cycles; when CLKP is 1, the high state duration is p cycles and the low state duration is p+1 cycles. Following device reset, the default operating condition of CLKX is an input. If the serial port is not used, this pin can be sampled as an input via the IN1 bit in the SPC. Received serial data. The BRSR receives serial data through this input pin. Transmitted serial data. The BXSR transmits serial data through this pin. This pin is placed in a high-impedance state when not transmitting and also when the OFF { signal is active (low). Receive frame synchronization. This signal initiates the data receive process. Upon reset, BFSR is active high. BFSR can be configured as active low by setting the FSP bit in the SPCE. Transmit frame synchronization. This signal initiates the data transmit process. Upon reset, BFSX is an input signal. BFSX can be configured as an output by setting the TXM bit in the SPC. Upon reset, BFSX is active high. BFSX can be configured as active low by setting the FSP bit in the SPCE.

BCLKX

I/O/Z

BDR BDX

I O/Z

BFSR

BFSX

I/O/Z

Note: Input pins that are unused may be connected to VDD or to an external pullup resistor. Legend: I Input O Output Z High impedance { The OFF signal, when active (low), puts all C5x output drivers into the high-impedance state.

Pinouts and Signal Descriptions

A-21

Signal Descriptions

Table A17. Host Port Interface Signal Descriptions (C57 Only)

Signal HAS State I Description Address strobe input. Hosts with a multiplexed address and data bus connect HAS to their ALE pin or equivalent. HBIL, HCNTL0/1, and HR/W are then latched on HAS falling edge. When used, HAS must precede the later of HCS, HDS1, or HDS2 (see C5x data sheet for detailed HPI timing specifications). Hosts with separate address and data bus can connect HAS to a logic-1 level. In this case, HBIL, HCNTL0/1, and HR/W are latched by the later of HDS1, HDS2, or HCS falling edge while HAS stays inactive (high). Byte identification input. Identifies first or second byte of transfer (but not most significant or least significant this is specified by the BOB bit in the HPIC register, described later in this section). HBIL is low for the first byte and high for the second byte. Control inputs. Indicates type of host access to the HPI address register (HPIA), the HPI data latches (with optional address increment), or the HPI control register (HPIC). HCNTL1 0 0 HCNTL0 0 1 Description Host can read or write the HPIC.
-

HBIL

HCNTL0 HCNTL1

Host can read or write the HPI data latches. HPIA postincremented when data is read HPIA preincremented when data is written Host can read or write the HPIA. HPIA points to the HPI memory. DSP does not have access to the HPIA.

1 HCS I

Host can read or write the HPI data latches. HPIA is not affected.

Chip select input. Serves as the enable input for the HPI and must be low during an access but may stay low between accesses. HCS normally precedes HDS1 and HDS2, but this signal also samples HCNTL0/1, HR/W, and HBIL if HAS is not used and HDS1 or HDS2 are already low. Parallel, bidirectional, 3-state data bus. HD7 (MSB) through HD0 (LSB) are placed in high-impedance state when not outputting (HDSx and HCS = 1) or when OFF { is active (low).

HD7 (MSB) HD6 HD5 HD4 HD3 HD2 HD1 HD0 (LSB)

I/O/Z

Note: Input pins that are unused may be connected to VDD or to an external pullup resistor. Legend: I Input O Output Z High impedance S Supply { The OFF signal, when active (low), puts all C5x output drivers into the high-impedance state.

A-22

Signal Descriptions

Table A17. Host Port Interface Signal Descriptions (C57 Only) (Continued)
Signal HDS1 HDS2 State I Description Data strobe input. Control transfer of data during host access cycles. Also, when HAS is not used, used to sample HBIL, HCNTL0/1, and HR/W when HCS is already low (which is the case in normal operation). Hosts with separate read and write strobes connect those strobes to either HDS1 or HDS2. Hosts with a single data strobe connect it to either HDS1 or HDS2, connecting the unused pin high. Regardless of HDS connections, HR/W is still required to determine direction of transfer. Because HDS1 and HDS2 are internally exclusive-NORed, hosts with a high true data strobe can connect this to one of the HDS inputs with the other HDS input connected low. Host interrupt. Controlled by the HINT bit in the HPIC. This pin driven high when the C5x is being reset. Placed in high impedance when OFF { is active (low). HPI ready output. When high, indicates that the HPI is ready for a transfer to be performed. When low, indicates that the HPI is busy completing the internal portion of the previous transaction. Placed in high impedance when OFF { is active (low). HCS enables HRDY; that is, HRDY is always high when HCS is high. Read/write input. Hosts must drive HR/W high to read HPI and low to write HPI. Hosts without a R/W strobe can use an address line.

HINT HRDY

O/Z O/Z

HR/W

Note: Input pins that are unused may be connected to VDD or to an external pullup resistor. Legend: I Input O Output Z High impedance S Supply { The OFF signal, when active (low), puts all C5x output drivers into the high-impedance state.

Pinouts and Signal Descriptions

A-23

Signal Descriptions

Table A18. Emulation/Testing Signal Descriptions

Signal TCK State I Description IEEE JTAG Standard 1149.1 test clock. This is normally a free-running clock signal with a 50% duty cycle. The changes on test access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. IEEE JTAG Standard 1149.1 test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. IEEE JTAG Standard 1149.1 test data output. The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when it is scanning data. This signal also goes into high impedance when OFF { is active low. IEEE JTAG Standard 1149.1 test mode select. This serial control input is clocked into the TAP controller on the rising edge of TCK. IEEE JTAG Standard 1149.1 test reset. This signal, when active high, gives the IEEE Standard 1149.1 scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the signals are ignored. Emulator pin 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system. This pin is defined as input/output via IEEE Standard 1149.1 scan. Emulator pin 1/disable all outputs. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output via IEEE Standard 1149.1 scan. When TRST is driven low, this pin is configured as OFF. The EMU1/ OFF signal, when active (low), puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Thus, for the OFF condition, the following conditions must apply for at least 2 machine cycles:
Note:

TDI TDO

I O/Z

TMS TRST

I I

EMU0

I/O/Z

EMU1/OFF

I/O/Z

TRST = low EMU0 = high EMU1/OFF = low

Input pins that are unused may be connected to VDD or to an external pullup resistor. For emulation, TRST has an internal pulldown, and TMS, TCK, and TDI have internal pullups. EMU0 and EMU1 require external pullups to support emulation. Legend: I Input O Output Z High impedance { The OFF signal, when active (low), puts all C5x output drivers into the high-impedance state.

A-24

Appendix B Appendix A

Instruction Classes and Cycles

Instructions are classified into several categories, or classes, according to cycles required. This appendix describes the instruction classes. Because a single instruction can have multiple syntaxes and types of execution, it can appear in multiple classes. The tables in this appendix show the number of cycles required for a given C5x instruction to execute in a given memory configuration when executed as a single instruction.

Topic
B.1 B.2

Page
Cycle Class-to-Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . B-2 Instruction Set-to-Cycle Class Summary . . . . . . . . . . . . . . . . . . . . . . . . B-5

Instruction Classes and Cycles

B-1

Cycle Class-to-Instruction Set Summary

B.1 Cycle Class-to-Instruction Set Summary

Table B1 provides a cycle class-to-instruction set cross reference. See Table 62 on page 6-4 for definitions of symbols and abbreviations used in the syntax expression.

Table B1. Cycle Class-to-Instruction Set Summary

Cycle class Class I Cycle class description 1 word, 1 cycle, no memory operands Mnemonic ABS, ADCB, ADD #k, ADDB, ADRK #k, ANDB, APAC, BSAR, CLRC, CMPL, CMPR, CRGT, CRLT, EXAR, IDLE, IDLE2, LACB, LACL #k, MAR, MPY #k, NEG, NOP, NORM, ORB, PAC, POP, PUSH, ROL, ROLB, ROR, RORB, SACB, SATH, SATL, SBB, SBBB, SBRK #k, SETC, SFL, SFLB, SFR, SFRB, SPAC, SPM, SUB #k, XC, XORB, ZAP, ZPR ADD, ADDC, ADDS, ADDT, AND, BIT, BITT, CPL, LACC, LACL, LACT, LPH, LT, LTA, LTP, LTS, MPY, MPYA, MPYS, MPYU, OR, PSHD, RPT, SQRA, SQRS, SUB, SUBB, SUBC, SUBS, SUBT, XOR, ZALR LAMM ADD #lk, AND #lk, LACC #lk, LAR ARn, #lk, MPY #lk, OR #lk, RPT #lk, RPTB, RPTZ #lk, SUB #lk, XOR #lk

Class IIA

1 word, 1 cycle, memory read operand

Class IIB Class III

1 word, 1 cycle, memorymapped register read 2 words, 2 cycles, longimmediate operand, no memory access, not repeatable 1 word, 1 cycle, memory write operand 1 word, 1 cycle, memorymapped register write 1 word, 1 cycle, memory read and write 2 words, 2 cycles, memory read and write 2 words, 2 cycles, memory read operand 2 words, 2 cycles, memory write operand, not repeatable

Class IVA Class IVB Class V Class VI Class VIIa Class VIIb

POPD, SACH, SACL, SAR, SPH, SPL, SST SAMM APL, DMOV, LTD, OPL, XPL APL, OPL, XPL CPL #lk SPLK

Bold typeface indicates instructions that are new for the C5x instruction set. ADD #k, ADRK #k, LACL #k, MPY #k, RPT, SBRK #k, SPM, SUB #k, and XC are not repeatable instructions.

B-2

Cycle Class-to-Instruction Set Summary

Table B1. Cycle Class-to-Instruction Set Summary (Continued)

Cycle class Class VIII Cycle class description 2 words, 4 cycles program counter discontinuity, no delayed slots, not repeatable 2 words, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable 1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 1 word, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable 2 words, 3 cycles, block data transfer, data to data space 1 word, 2 cycles, block data transfer, data to data space 2 words, 3 cycles, block data transfer, program to data space 1 word, 2 cycles, block data transfer, program to data space 1 word, 2 cycles, block data transfer, data to program space 1 word, 3 cycles, table read 1 word, 3 cycles, table write 2 words, 3 cycles, multiply accumulate 1 word, 2 cycles, multiply accumulate 2 words, 3 cycles, multiply accumulate with data move Mnemonic B, BANZ, BCND, CALL, CC

Class IX

BANZD, BCNDD, BD, CALLD, CCD

Class X

BACC, CALA, INTR, NMI, RET, RETC, RETE, RETI, TRAP

Class XI

BACCD, CALAD, RETCD, RETD

Class XII Class XIII Class XIV

BLDD BLDD BLPD

Class XV

BLPD

Class XVI

BLDP

Class XVII Class XVIII Class XIX Class XX Class XXI

TBLR TBLW MAC MADS MACD

Bold typeface indicates instructions that are new for the C5x instruction set. ADD #k, ADRK #k, LACL #k, MPY #k, RPT, SBRK #k, SPM, SUB #k, and XC are not repeatable instructions.

Instruction Classes and Cycles

B-3

Cycle Class-to-Instruction Set Summary

Table B1. Cycle Class-to-Instruction Set Summary (Continued)

Cycle class Class XXII Class XXIII Class XXIV Class XXV Class XXVI Class XXVII Class XXVIII Cycle class description 1 word, 2 cycles, multiply accumulate with data move 2 words, 2 cycles, memorymapped register load 2 words, 2 cycles, memorymapped register store 2 words, 3 cycles, output port 2 words, 2 cycles, input port 1 word, 2 cycles, pipelineprotected, memory read 1 word, 2 cycles, pipelineprotected, memory read, not repeatable 1 word, 2 cycles, no memory access, not repeatable, pipeline protected Mnemonic MADD LMMR SMMR OUT IN LAR, LDP, LST LAR ARn, #k; LDP #k

Class XXIIX

RPT #k

Bold typeface indicates instructions that are new for the C5x instruction set. ADD #k, ADRK #k, LACL #k, MPY #k, RPT, SBRK #k, SPM, SUB #k, and XC are not repeatable instructions.

B-4

Instruction Set-to-Cycle Class Summary

B.2 Instruction Set-to-Cycle Class Summary

Table B2 provides an instruction set-to-cycle class cross reference. See Table 62 on page 6-4 for definitions of symbols and abbreviations used in the syntax expression.

Table B2. Instruction Set-to-Cycle Class Summary

Mnemonic ABS ADCB ADD ADD #k ADD #lk ADDB ADDC ADDS ADDT ADRK #k AND AND #lk ANDB APAC APL APL B BACC BACCD Cycle class Class I Class I Class IIA Class I Class III Class I Class IIA Class IIA Class IIA Class I Class IIA Class III Class I Class I Class V Class VI Class VIII Class X Class XI Cycle class description 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory read operand 1 word, 1 cycle, no memory operands, not repeatable 2 words, 2 cycles, long-immediate operand, no memory access, not repeatable 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read operand 1 word, 1 cycle, no memory operands, not repeatable 1 word, 1 cycle, memory read operand 2 words, 2 cycles long-immediate operand, no memory access, not repeatable 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory read and write 2 words, 2 cycles, memory read and write 2 words, 4 cycles program counter discontinuity, no delayed slots, not repeatable 1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 1 word, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable Page 6-28 6-30 6-31 6-31 6-31 6-35 6-36 6-38 6-40 6-42 6-43 6-43 6-46 6-47 6-48 6-48 6-51 6-52 6-53

Bold typeface indicates instructions that are new for the C5x instruction set.

Instruction Classes and Cycles

B-5

Instruction Set-to-Cycle Class Summary

Table B2. Instruction Set-to-Cycle Class Summary (Continued)

Mnemonic BANZ BANZD BCND BCNDD BD BIT BITT BLDD BLDD BLDP BLPD BLPD BSAR CALA CALAD CALL CALLD CC Cycle class Class VIII Class IX Class VIII Class IX Class IX Class IIA Class IIA Class XIII Class XII Class XVI Class XV Class XIV Class I Class X Class XI Class VIII Class IX Class VIII Cycle class description 2 words, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 2 words, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable 2 words, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 2 words, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable 2 words, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read operand 1 word, 2 cycles, block data transfer, data to data space 2 words, 3 cycles, block data transfer, data to data space 1 word, 2 cycles, block data transfer, data to program space 1 word, 2 cycles, block data transfer, program to data space 2 words, 3 cycles, block data transfer, program to data space 1 word, 1 cycle, no memory operands 1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 1 word, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable 2 words, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 2 words, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable 2 words, 4 cycles, program counter discontinuity, no delayed slots, not repeatable Page 6-54 6-56 6-58 6-60 6-62 6-63 6-65 6-67 6-67 6-73 6-76 6-76 6-82 6-83 6-84 6-85 6-86 6-88

Bold typeface indicates instructions that are new for the C5x instruction set.

B-6

Instruction Set-to-Cycle Class Summary

Table B2. Instruction Set-to-Cycle Class Summary (Continued)

Mnemonic CCD CLRC CMPL CMPR CPL CPL #lk CRGT CRLT DMOV EXAR IDLE IDLE2 IN INTR LACB LACC LACC #lk LACL LACL #k LACT LAMM LAR LAR ARn, #k Cycle class Class IX Class I Class I Class I Class IIA Class VIIa Class I Class I Class V Class I Class I Class I Class XXVI Class X Class I Class IIA Class III Class IIA Class I Class IIA Class IIB Class XXVII Class XXVIII Cycle class description 2 words, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory read operand 2 words, 2 cycles, memory read operand 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory read and write 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands, not repeatable 1 word, 1 cycle, no memory operands, not repeatable 2 words, 2 cycles, input port 1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory read operand 2 words, 2 cycles, long-immediate operand, no memory access, not repeatable 1 word, 1 cycle, memory read operand 1 word, 1 cycle, no memory operands, not repeatable 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory-mapped register read 1 word, 2 cycles, pipeline-protected, memory read 1 word, 2 cycles, pipeline-protected, memory read, not repeatable Page 6-90 6-92 6-94 6-95 6-97 6-97 6-100 6-102 6-104 6-106 6-107 6-108 6-109 6-111 6-113 6-114 6-114 6-117 6-117 6-120 6-122 6-124 6-124

Bold typeface indicates instructions that are new for the C5x instruction set.

Instruction Classes and Cycles

B-7

Instruction Set-to-Cycle Class Summary

Table B2. Instruction Set-to-Cycle Class Summary (Continued)

Mnemonic LAR ARn, #lk Cycle class Class III Cycle class description 2 words, 2 cycles, long-immediate operand, no memory access, not repeatable 1 word, 2 cycles, pipeline-protected, memory read 1 word, 2 cycles, pipeline-protected, memory read, not repeatable 2 words, 2 cycles, memory-mapped register load 1 word, 1 cycle, memory read operand 1 word, 2 cycles, pipeline-protected, memory read 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read and write 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read operand 2 words, 3 cycles, multiply accumulate 2 words, 3 cycles, multiply accumulate with data move 1 word, 2 cycles, multiply accumulate with data move 1 word, 2 cycles, multiply accumulate 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory read operand 1 word, 1 cycle, no memory operands, not repeatable 2 words, 2 cycles, long-immediate operand, no memory access, not repeatable 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read operand 1 word, 1 cycle, no memory operands Page 6-124

LDP LDP #k

Class XXVII Class XXVIII

6-127 6-127

LMMR LPH LST LT LTA LTD LTP LTS MAC MACD MADD MADS MAR MPY MPY #k MPY #lk

Class XXIII Class IIA Class XXVII Class IIA Class IIA Class V Class IIA Class IIA Class XIX Class XXI Class XXII Class XX Class I Class IIA Class I Class III

6-130 6-133 6-135 6-138 6-140 6-142 6-145 6-147 6-149 6-153 6-158 6-162 6-166 6-168 6-168 6-168

MPYA MPYS MPYU NEG

Class IIA Class IIA Class IIA Class I

6-171 6-173 6-175 6-177

Bold typeface indicates instructions that are new for the C5x instruction set.

B-8

Instruction Set-to-Cycle Class Summary

Table B2. Instruction Set-to-Cycle Class Summary (Continued)

Mnemonic NMI NOP NORM OPL OPL OR OR #lk ORB OUT PAC POP POPD PSHD PUSH RET RETC RETCD RETD RETE RETI ROL Cycle class Class X Class I Class I Class V Class VI Class IIA Class III Class I Class XXV Class I Class I Class IVA Class IIA Class I Class X Class X Class XI Class XI Class X Class X Class I Cycle class description 1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory read and write 2 words, 2 cycles, memory read and write 1 word, 1 cycle, memory read operand 2 words, 2 cycles, long-immediate operand, no memory access, not repeatable 1 word, 1 cycle, no memory operands 2 words, 3 cycles, output port 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory write operand 1 word, 1 cycle, memory read operand 1 word, 1 cycle, no memory operands 1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 1 word, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable 1 word, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable 1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 1 word, 1 cycle, no memory operands Page 6-179 6-180 6-181 6-184 6-184 6-187 6-187 6-190 6-191 6-193 6-194 6-196 6-198 6-200 6-202 6-203 6-205 6-207 6-208 6-209 6-210

Bold typeface indicates instructions that are new for the C5x instruction set.

Instruction Classes and Cycles

B-9

Instruction Set-to-Cycle Class Summary

Table B2. Instruction Set-to-Cycle Class Summary (Continued)

Mnemonic ROLB ROR RORB RPT RPT #k RPT #lk RPTB RPTZ #lk SACB SACH SACL SAMM SAR SATH SATL SBB SBBB SBRK #k SETC SFL SFLB SFR SFRB SMMR Cycle class Class I Class I Class I Class IIA Class XXIX Class III Class III Class III Class I Class IVA Class IVA Class IVB Class IVA Class I Class I Class I Class I Class I Class I Class I Class I Class I Class I Class XXIV Cycle class description 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory read operand, not repeatable 1 word, 2 cycle, no memory operands, not repeatable 2 words, 2 cycles, long-immediate operand, no memory access, not repeatable 2 words, 2 cycles, long-immediate operand, no memory access, not repeatable 2 words, 2 cycles, long-immediate operand, no memory access, not repeatable 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory write operand 1 word, 1 cycle, memory write operand 1 word, 1 cycle, memory-mapped register write 1 word, 1 cycle, memory write operand 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands, not repeatable 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands 2 words, 2 cycles, memory-mapped register store Page 6-211 6-212 6-213 6-214 6-214 6-214 6-217 6-219 6-220 6-221 6-223 6-225 6-227 6-229 6-231 6-232 6-233 6-234 6-235 6-237 6-238 6-239 6-241 6-243

Bold typeface indicates instructions that are new for the C5x instruction set.

B-10

Instruction Set-to-Cycle Class Summary

Table B2. Instruction Set-to-Cycle Class Summary (Continued)

Mnemonic SPAC SPH SPL SPLK SPM SQRA SQRS SST SUB SUB #k SUB #lk SUBB SUBC SUBS SUBT TBLR TBLW TRAP XC XOR XOR #lk XORB XPL XPL Cycle class Class I Class IVA Class IVA Class VIIb Class I Class IIA Class IIA Class IVA Class IIA Class I Class III Class IIA Class IIA Class IIA Class IIA Class XVII Class XVIII Class X Class I Class IIA Class III Class I Class V Class VI Cycle class description 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory write operand 1 word, 1 cycle, memory write operand 2 words, 2 cycles, memory write operand, not repeatable 1 word, 1 cycle, no memory operands, not repeatable 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory write operand 1 word, 1 cycle, memory read operand 1 word, 1 cycle, no memory operands, not repeatable 2 words, 2 cycles, long-immediate operand, no memory access, not repeatable 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read operand 1 word, 1 cycle, memory read operand 1 word, 3 cycles, table read 1 word, 3 cycles, table write 1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable 1 word, 1 cycle, no memory operands, not repeatable 1 word, 1 cycle, memory read operand 2 words, 2 cycles, long-immediate operand, no memory access, not repeatable 1 word, 1 cycle, no memory operands 1 word, 1 cycle, memory read and write 2 words, 2 cycles, memory read and write Page 6-246 6-247 6-249 6-251 6-252 6-253 6-255 6-257 6-259 6-259 6-259 6-263 6-265 6-267 6-269 6-271 6-274 6-277 6-278 6-280 6-280 6-283 6-284 6-284

Bold typeface indicates instructions that are new for the C5x instruction set.

Instruction Classes and Cycles

B-11

Instruction Set-to-Cycle Class Summary

Table B2. Instruction Set-to-Cycle Class Summary (Continued)

Mnemonic ZALR ZAP ZPR Cycle class Class IIA Class I Class I Cycle class description 1 word, 1 cycle, memory read operand 1 word, 1 cycle, no memory operands 1 word, 1 cycle, no memory operands Page 6-287 6-289 6-290

Bold typeface indicates instructions that are new for the C5x instruction set.

B-12

Appendix C Appendix A

System Migration
This appendix contains information that is necessary to upgrade a C2x system into a C5x system. The information consists of a detailed list of the programming differences and hardware and timing differences between the two generations of TMS320 DSPs. Note that the C50, C51, and C53 have the same features with the exception of memory map; so within this appendix, any reference to C5x applies to C50, C51, and C53, unless otherwise stated.

Topic
C.1 C.2 C.3 C.4

Page
Package and Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8 On-Chip Peripheral Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11 C2x-to-C5x Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-12

System Migration

C-1

Package and Pin Layout

C.1 Package and Pin Layout

The C25 is available in both a 68-pin ceramic pin grid array (CPGA) as shown in Figure C1 and a 68-pin plastic leaded chip carrier (PLCC) as shown in Figure C2. The C5x devices are available in various packages as shown in Appendix A, Pinouts and Signal Descriptions.

Figure C1. TMS320C25 in 68-Pin CPGA

Top view 28,448 (1.120) 27,432 (1.080) 17,02 (0.670) Nom 28,448 (1.120) 27,432 (1.080)

17,02 (0.670) Nom

4,953 (0.195) 2,032 (0.080)

1,397 (0.055) Max

3,302 (0.130) 2,794 (0.110)

0,508 (0.020) 0,406 (0.016)

1,575 (0.062) Dia 1,473(0.058) 2,54 (0.100) T.P. L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 1,27 (0.050) Nom 1,524 (0.060) Nom 4 places Bottom view 2,54 (0.100) T.P.

Thermal Resistance Characteristics Parameter RJA RJC Junction-to-free-air thermal resistance Junction-to-case thermal resistance Max 36 6 Unit C/W C/W

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.

C-2

Package and Pin Layout

Figure C2. TMS320C25 in 68-Pin PLCC

1,35 (0.053) 1,19 (0.047) 45 0,25 (0.010) R Max in 3 places 24,33 (0.956) 24,13 (0.950) (see Note A)

2,79 (0.110) 2,41 (0.095) 4,50 (0.177) 4,24 (0.167)

Thermal Resistance Characteristics Parameter RJA RJC Junction-to-free-air thermal resistance Junction-to-case thermal resistance Max 46 11 Unit C/W C/W
0,51 (0.020) 0,36 (0.014) Lead Detail Notes: A. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by this dimension. B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES. 0,64 (0.025) Min

23,62 (0.930) 23,11 (0.910) (At Seating Plane) 25,27 (0.995) 25,02 (0.985) 1,27 (0.050) T.P. (See Note B) 24,33 (0.956) 24,13 (0.950) (see Note A) 1,22 (0.048) 1,07 (0.042) 0,94 (0.037) R 0,69 (0.027) Seating Plane 25,27 (0.995) 25,02 (0.985) 45 0,81 (0.032) 0,66 (0.026) 1,52 (0.060) Min

System Migration

C-3

Package and Pin Layout

When a C25 is upgraded to a C50, C51, or C53, there is minimal layout modification. The C5x signals are on the same side (except the CLKR and A0 pins), and in the same order (except the X1 and X2/CLKIN pins) as those of the C25. Figure C3 shows the pin-to-pin relationship between the C25 and the C5x devices in J-leaded chip carrier packages. The two devices are not drawn to scale. The power (VDD) and ground (VSS) signals are symmetrically positioned on the C5x so that, in conjunction with the OFF signal, the device is not damaged by inserting it in the wrong orientation. The C5x has more power and ground pins to provide higher performance and more noise immunity than the C25.

C-4

Package and Pin Layout

Figure C3. TMS320C25-to-TMS320C5x Pin/Signal Relationship

C50, C51, and C53
VDD VDD D8 D9 D10 D11 D12 D13 D14 D15 MP/MC VSS VSS TRST IAQ VDD VDD BIO HOLD READY RS TCLKR TFSR/TADD CLKX TCLKX TOUT VSS VSS EMU1/OFF EMU0
116 115 114 113 112 111 110 109 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 108 60 IACK 10 107 59 MSC 11 58 CLKOUT1 12 106 57 CLKOUT2 13 105 56 XF 14 104 55 HOLDA 15 103 54 DX 16 102 53 FSX 17 101 52 X2/CLKIN 18 100 51 X1 19 99 50 BR 20 98 49 STRB 21 97 48 R/W 22 96 47 PS 23 95 46 IS 24 45 DS 94 25 44 VSS 26 93 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 92 91 90 89 88 87 86 85 84 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132131130129128127126125124123122121120119 118 117 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

D7 D6 D5 D4 D3 D2 D1 D0 TMS VDD VDD TCK VSS VSS INT1 INT2 INT3 INT4 NMI DR TDR FSR CLKR VDD VDD

D8 D9 D10 D11 D12 D13 D14 D15 MP/MC BIO HOLD READY RS CLKR CLKX VCC VCC

VSS VSS

VDD VDD IACK CLKOUT1 XF HOLDA TDX DX TFSX/TFRM FSX CLKMD2 VSS VSS TDO VDD VDD X1 X2/CLKIN CLKIN2 BR STRB R/W PS IS DS VSS VSS

VSS D7 D6 D5 D4 D3 D2 D1 D0 SYNC INT0 INT1 INT2 VCC DR FSR A0

C25

51 52 53 54 55 56 57 58 59

CLKMD1 A10 A11 A12 A13 A14 A15

V SS V SS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 VDD VDD TDI V SS V SS

VSS A1 A2 A3 A4 A5 A6 A7 VCC A8 A9 A10 A11 A12 A13 A14 A15

Note:

Pins without callouts are unassigned (reserved).

Three C25 signals (CLKOUT2, MSC and SYNC) are not present on the C5x. Because the C5x operates with a divide-by-two clock, it can be synchronized with reset. Therefore, there is no need for the SYNC signal. With only two phases, there are no external timings that tie to the CLKOUT2 of the C25. Some of the C25-equivalent pins have additional capabilities on the C5x. The C5x supports external direct memory access of the on-chip single-access RAM block. For this reason, the following signals are now bidirectional:
System Migration
C-5

VDD VDD RD WE

Package and Pin Layout

Address lines, A0A15 Memory access strobe, STRB Read/write, R/W Bus request, BR

The C5x serial port transmit clock (CLKX) can now be configured as an output that operates at one-fourth the machine clock rate. CLKX is configured as an input by reset. The C25 CLKX pin is always an input. The C25 operates with a four-phase clock. The C25 machine rate is one-fourth the CLKIN rate. CLKOUT1 and CLKOUT2 operate at the machine rate and are 90 out of phase. The C5x operates with a two-phase clock. The C5x machine rate is one-half the CLKIN rate. In addition, the C5x offers a divide-by-one clock input feature so that the C5x machine rate equals the CLKIN rate. CLKOUT1 operates at the machine rate. Figure C4 shows both the C25 and the C5x clocking schemes.

Figure C4. TMS320C25 and TMS320C5x Clocking Schemes

C25
CLKIN CLKOUT1 CLKOUT2

C5x
CLKIN CLKOUT1

The C5x MP/MC pin is sampled only while RS is low. Changes on this pin are ignored while RS is high. The mode can be changed during execution by changing the MP/MC bit in the PMST. On the C25, any change on the MP/MC pin affects the operation of the device, regardless of the state of RS. The C5x IACK signal goes low only on the first machine cycle of the fetch of the first word of the interrupt vector. The C25 IACK goes low on each wait-state cycle, as well as on the first machine cycle, but it is valid only during CLKOUT1 low (during CLKOUT1 high, it has a specific meaning for emulator/ test operations). Figure C5 illustrates this difference.
C-6

Package and Pin Layout

Figure C5. TMS320C25 IACK Versus TMS320C5x IACK

CLKOUT1

C25
IACK

C5x
IACK

The C5x device includes some additional functions not included with the C25. These functions and associated pins are as follows:
- TDM serial port: TCLKR, TCLKX, TDR, TDX, TADD, TFRM - Emulation interface: EMU0, EMU1/OFF, IAQ, TCK, TDI, TDO, TMS,

TRST
- Timer borrow: TOUT - Divide-by-one clock: CLKIN2, CLKMD1, and CLKMD2 - Fourth external interrupt: INT4 - Nonmaskable interrupt: NMI - Read enable: RD - Write enable: WE

The C5x package also includes 12 additional power and 13 additional ground pins. These additional power and ground pins enable the device to operate at much faster speeds. Twenty pins are reserved for future C5x spinoff devices.

System Migration

C-7

Timing

C.2 Timing
The C2x and the C5x operate with some timing differences. These timing differences include aspects of the on-chip operation and the external memory interfacing. These key differences are:
- The C5x is capable of operating at two to three times the speed of a C2x. - The C2x operates with a three-deep pipeline, while the C5x operates with

a four-deep pipeline.
- The C5x external memory interface is faster and includes external inter-

face enhancements.
- Some compatible operations execute in a different number of machine

cycles.

C.2.1 Device Clock Speed

The C2x operates its machine cycles with a divide-by-four clocking scheme. The C5x uses a divide-by-two clocking scheme. This means that a C2x, operating with a 40-MHz CLKIN, executes its machine cycles within 100 ns, while the C5x, which is operating with the same CLKIN, executes its machine cycles in 50 ns. This clocking arrangement changes the way that the signals of the devices are specified. Many of the C2x timing values, given in the TMS320 Second-Generation Digital Signal Processor Data Sheet, are specified as quarter-phase (Q) + N ns. The timing values of the C5x are defined in half-phases (H).

C.2.2 Pipeline
The C2x operates with a three-deep pipeline, while the C5x operates with a four-deep pipeline. This means that anytime there is a program counter (PC) discontinuity (for example, branch, call, return, interrupt, etc.), it takes four cycles to complete with the C5x, whereas it takes three cycles on the C2x. The C5x, however, also has delayed instructions that take only two cycles to complete.

C.2.3 External Memory Interfacing

The C5x is designed to execute external memory operations with the same signals as the C2x. As mentioned above, the C5x operates at twice the instruction rate of the C2x when both operate with the same input clock. The C5x uses its software wait-state generators to compensate for this interface difference. The C5x device, operating with one software wait state, has similar memory timing to the C2x operating with no wait states. However, external writes require two cycles on the C5x devices. The exact timing of the signals differ because of the more advanced process used with the C5x.
C-8

Timing

The C5x has two additional memory interface signals to reduce the amount of external interfacing circuitries. The RD signal can be used to interface directly to the output enable pin of another device, while the WE signal can be directly connected to the write enable pin of another device. This alleviates the need of gating STRB and R/W to generate the equivalent signals.

C.2.4 Execution Cycle Times

Some of the C2x instructions require additional cycles or words to execute on the C5x. The function of these instructions is the same, but the format and pipeline execution are enhanced to operate with the C5x architecture. The IN and OUT instructions are now two-word instructions. They execute on the C5x in the same number of cycles as with the C2x, but the assembler generates a two-word instruction for the C5x. Note that the C5x IN and OUT instructions behave differently in RPT mode. See Chapter 6, Assembly Language Instructions, for details. Two words are used because the C5x can address 65 536 I/O ports; the C2x only addresses 16. The C5x can address sixteen of its I/O ports in data memory space. This allows any instruction with data-memory-addressing capability to also read or write directly to an I/O port instead of having to pass it through a temporary on-chip data memory location. For example, a value can be read directly from an external analog-to-digital (A/D) converter into the ALU via an I/O port. The modification of the three mode bits of the serial port are executed in two-cycle/two-word instructions with the C5x. However, any or all of the three bits can be modified with one instruction without affecting other bits in the register. This is done with the PLU instructions. The NORM instruction modifies the auxiliary register (AR) on the execute (fourth) phase of the pipeline, while the ARAU operations occur on the decode (second) phase. The two instructions following a NORM instruction should not use the same AR for an address. If the two instructions following NORM change the auxiliary register pointer (ARP), then the NORM update of the AR is executed on the new ARP, not the old one. See Chapter 6, Assembly Language Instructions, for NORM instruction description. The assembler supports an optional way to test for this condition and automatically compensate by adding NOP instructions to the code. This modification is made to the listing and object files and does not affect your source code.

System Migration

C-9

Timing

Unlike the C2x, the ARs are also accessible in the data address space on the C5x. This allows the ARs to be loaded with the CALU instructions for advanced-addressing modes. However, use caution when using this feature because the CALU operations write to the ARs on the execute phase of the pipeline and, therefore, are subject to the same characteristics of the NORM instruction. The assembler supports the option to flag these conflicts for resolution.

C-10

On-Chip Peripheral Interfacing

C.3 On-Chip Peripheral Interfacing

The C5x has more peripherals than the C2x; many C5x peripherals are enhancements of the C2x peripherals. The C2x has three peripheral circuits: serial port, timer, and 16 I/O ports. In addition to these peripherals, the C5x has software wait states and a divide-by-one clock. The serial port interface of the C5x has been enhanced because the CLKX pin can be configured as either an input or an output. (CLKX is always an input on the C2x.) CLKX is configured as an input upon a device reset to maintain compatibility with the C2x. The new serial port status bits are now mapped to a memory-mapped register that is used exclusively for the serial port. The serial port modes are no longer controlled via status register 1 (ST1). Therefore, serial port modes changed by using the LST1 instruction will no longer work. The mode bits must be set/reset via the serial port control register (SPC). The data transmit (DXR) and data receive (DRR) registers have been moved in the memory map from locations 1 and 0, to 33 and 32, respectively. See Section 9.7, Serial Port Interface, on page 9-23 for more details. The timer has been enhanced on the C5x to include a divide-down factor of 1 to 17 and can be stopped or reset via software. These additional features are controlled via the timer control register (TCR). Upon reset, the divide-down factor is set to 1, and the timer is enabled to maintain compatibility with the C2x. The timer (TIM) and period (PRD) registers have been moved in the memory map from locations 2 and 3, to locations 36 and 37, respectively. See Section 9.3, Timer, on page 9-9 for more details. The 16 I/O ports of the C5x are addressable in the data memory space. Any instruction that can address data memory can also address the I/O ports. This allows direct access of the I/O space by the CPU and supports bit operation in the I/O space via the PLU. The I/O space can be increased from 16 ports to 65 536 ports. However, no additional decode circuitry is necessary if only 16 ports are used. See Section 8.5, Input/Output (I/O) Space, on page 8-22 and Section 9.6, Parallel I/O Ports, on page 9-22 for more details. The C5x includes software wait-state generators that are mapped on 16K-word page sizes in the program and data memory spaces. There are also wait-state generators for the I/O ports. The I/O space wait-state generators can be mapped on 2-word or on 8K-word boundaries. These wait-state generators allow the system to be programmed for 0, 1, 2, 3, 4, or 7 wait states, eliminating the need of an off-chip interfacing circuitry. External access wait states can be extended further via the READY signal. See Section 9.4, SoftwareProgrammable Wait-State Generators, on page 9-13 for more details.
System Migration
C-11

C2x-to-C5x Instruction Set

C.4 C2x-to-C5x Instruction Set

The C5x instruction set is a superset of the C2x instruction set. The instruction set of the C2x is upward source-code compatible. This means that all of the instruction features of the C2x, implemented and code written for the C2x, can be reassembled to run on the C5x. See Chapter 6, Assembly Language Instructions, for the detailed discussion of the instruction set.

C.4.1 Overview
There are a number of new instructions on the C5x devices. These new instructions provide an advanced addressing scheme and exercise the new CPU enhancements. To simplify the description of the instruction set, a number of different instructions are combined into single new instructions with additional operand formats, such as the ADD instruction shown in Table C1.

Table C1. TMS320C2x Versus TMS320C5x for the ADD Instruction

C2x Instruction ADD ADDK ADLK ADDH *+ 0FFh 0FFFFh *+ C5x Instruction ADD ADD ADD ADD *+ #0FFh #0FFFFh *+ , 16

The IDLE instruction, when executed, stops the CPU from fetching and executing instructions until an unmasked interrupt occurs. The C2x automatically enables the interrupts globally with the execution of the IDLE instruction; this saves the extra instruction word/cycle required to execute the EINT (enable interrupts globally) instruction. Upon receipt of the interrupt, the C2x executes the interrupt vector and resumes operations. The C5x does not automatically enable the interrupts globally with its IDLE instruction. If the interrupts are not globally enabled (INTM = 1), then the CPU resumes execution at the instruction following the IDLE instruction, without taking the interrupt trap. If the interrupts are globally enabled (INTM = 0), the C5x operates like the C2x. In addition, a second low-power mode is available with the IDLE2 instruction. This mode operates the same as IDLE, except that the CPU will resume only after an external interrupt. See Chapter 6, Assembly Language Instructions, for IDLE and IDLE2 instruction details. The C5x repeat counter is 16 bits wide (the C2x repeat counter is 8 bits wide). This means that, when loading from RAM, the RPT instruction supports repeat counts up to 65 536. The assembler also allows the RPT to support a16-bit immediate repeat count. Note that RPT with long immediate addressing is, however, a two-word instruction.
C-12

C2x-to-C5x Instruction Set

C.4.2 Serial Port Control Bit Instructions

The serial port mode control bits have been moved from the status registers to the serial port control register (SPC). Because they are no longer part of the CPU registers, they no longer have direct instructions to set or clear them. The bits of the SPC can be manipulated easily with the PLU instructions (Table 66 on page 6-14). Table C2 shows the C5x serial port instructions that replace the C2x instructions (note that the data page pointer must be set to 0 to execute these new instructions).

Table C2. TMS320C2x to TMS320C5x Serial Port Instructions

C2x Instruction FORT0 FORT1 RFSM RTXM SFSM STXM C5x Instruction APL #0FFFBh, SPC OPL #4, SPC APL #0FFF7h, SPC APL #0FFDFh, SPC OPL #8, SPC OPL #020h, SPC

Any or all three of the SPC bits can be set in one execution of the OPL instruction, while any or all three of the bits can be cleared with the APL instruction. The SPC bits can be toggled with the XPL instruction. See Chapter 6, Assembly Language Instructions, for instruction details.

C.4.3 C2x-to-C5x Instruction Set Mapping

The Texas Instruments C5x assembler accepts instruction mnemonics from either the C2x or the C5x instruction set. Because the C5x instruction set is a superset of the C2x instruction set, there are some C5x instructions that do not appear in the following tables. Table C3 through Table C8 alphabetically list the maps between the C2x and C5x instruction sets within the following functional groups:
- Accumulator memory reference instructions (Table C3) - Auxiliary registers and data memory page pointer instructions (Table C4 -

on page C-15) TREG0, PREG, and multiply instructions (Table C5 on page C-16) Branch and call instructions (Table C6 on page C-17) I/O and data memory operation instructions (Table C7 on page C-18) Control instructions (Table C8 on page C-19)
System Migration
C-13

C2x-to-C5x Instruction Set

Table C3. TMS320C2x-to-TMS320C5x Accumulator Memory Reference Instructions

C2x Instruction ABS ADD ADDC ADDH ADDK ADDS ADDT ADLK AND ANDK CMPL LAC LACK LACT LALK NEG NORM OR ORK ROL ROR SACH SACL SBLK SFL SFR SUB SUBB C5x Instruction ABS ADD ADDC ADD ADD ADDS ADDT ADD AND AND CMPL LACC LACL LACT LACC NEG NORM OR OR ROL ROR SACH SACL SUBB SFL SFR SUB SUBB

There is a potential pipeline conflict with the NORM instruction. See the NORM instruction summary (page 6-181) for details.

C-14

C2x-to-C5x Instruction Set

Table C3. TMS320C2x-to-TMS320C5x Accumulator Memory Reference Instructions (Continued)

C2x Instruction SUBC SUBH SUBK SUBS SUBT XOR XORK ZAC ZALH ZALR ZALS C5x Instruction SUBC SUB SUB SUBS SUBT XOR XOR LACL LACC ZALR LACL

Table C4. TMS320C2x-to-TMS320C5x Auxiliary Registers and Data Memory Page Pointer Instructions
C2x Instruction ADRK CMPR LAR LARK LARP LDP LDPK LRLK MAR SAR SBRK C5x Instruction ADRK CMPR LAR LAR MAR LDP LDP LAR MAR SAR SBRK

System Migration

C-15

C2x-to-C5x Instruction Set

Table C5. TMS320C2x-to-TMS320C5x TREG0, PREG, and Multiply Instructions

C2x Instruction APAC LPH LT LTA LTD LTP LTS MAC MACD MPY MPYA MPYK MPYS MPYU PAC SPAC SPH SPL SPM SQRA SQRS C5x Instruction APAC LPH LT LTA LTD LTP LTS MAC MACD MPY MPYA MPY MPYS MPYU PAC SPAC SPH SPL SPM SQRA SQRS

C-16

C2x-to-C5x Instruction Set

Table C6. TMS320C2x-to-TMS320C5x Branch and Call Instructions

C2x Instruction B BACC BANZ BBNZ BBZ BC BGEZ BGZ BIOZ BLEZ BLZ BNC BNV BNZ BV BZ CALA CALL RET TRAP C5x Instruction B BACC BANZ BCND BCND BCND BCND BCND BCND BCND BCND BCND BCND BCND BCND BCND CALA CALL RET TRAP

System Migration

C-17

C2x-to-C5x Instruction Set

Table C7. TMS320C2x-to-TMS320C5x I/O and Data Memory Operation Instructions

C2x Instruction BLKD BLKP DMOV FORT IN OUT RFSM RTXM RXF SFSM STXM SXF TBLR TBLW C5x Instruction BLDD BLPD DMOV OPL APL IN OUT APL APL CLRC OPL OPL SETC TBLR TBLW

The suggested mapping requires that the data page pointer be set to 0.

C-18

C2x-to-C5x Instruction Set

Table C8. TMS320C2x-to-TMS320C5x Control Instructions

C2x Instruction BIT BITT CNFD CNFP DINT EINT IDLE LST LST1 NOP POP POPD PSHD PUSH RC RHM ROVM RPT RPTK RSXM RTC SC SHM SOVM SST SST1 SSXM STC C5x Instruction BIT BITT CLRC SETC SETC CLRC IDLE LST LST NOP POP POPD PSHD PUSH CLRC CLRC CLRC RPT RPT CLRC CLRC SETC SETC SETC SST SST SETC SETC

System Migration

C-19

Appendix D Appendix A

Design Considerations for Using XDS510 Emulator

The C5x DSPs support emulation through a dedicated emulation port. The emulation port is a superset of the IEEE JTAG standard 1149.1 and can be accessed by the XDS510 emulator. The information in this appendix supports XDS510 Cable #2563988-001 Rev B. The term JTAG, as used in this book, refers to TI scan-based emulation, which is based on the IEEE standard 1149.1. For more information concerning the IEEE standard 1149.1, contact IEEE Customer Service: Address: IEEE Customer Service 445 Hoes Lane, PO Box 1331 Piscataway, NJ 08855-1331 Phone: (800) 678IEEE in the US and Canada (908) 9811393 outside the US and Canada (908) 9819667 Telex: 833233

FAX:

Topic
D.1 D.2 D.3 D.4 D.5 D.6 D.7 D.8

Page
Cable Header and Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2 Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 Emulator Cable Pod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4 Emulator Cable Pod Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-6 Target System Test Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7 Configuring Multiple Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-8 Connections Between the Emulator and the Target System . . . . . . . D-9 Emulation Timing Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11

Design Considerations for Using XDS510 Emulator

D-1

Cable Header and Signals

D.1 Cable Header and Signals

To perform emulation with the XDS510, your target system must have a 14-pin header (two 7-pin rows) with connections as shown in Figure D1. Table D1 describes the emulation signals. Although you can use other headers, recommended parts include: Straight header, unshrouded Right-angle header, unshrouded DuPont Electronics part number 67996114 DuPont Electronics part number 68405114

Figure D1. Header Signals and Header Dimensions

TMS TDI PD (VDD) TDO TCK_RET TCK EMU0
1 3 5 7 9 11 13 2 4 6 8 10 12 14

TRST GND No pin (key) GND GND GND EMU1

Header Dimensions: Pin-to-pin spacing: 0.100 in. (X,Y) Pin width: 0.025 in. square post Pin length: 0.235 in., nominal

Table D1. XDS510 Header Signal Description

Pin 1 2 3 5 Signal TMS TRST TDI PD State O O O I Target State Description I I I O JTAG test mode select JTAG test reset JTAG test data input Presence detect. Indicates that the emulation cable is connected and that the target is powered up. PD should be tied to VDD in the target system. JTAG test data output JTAG test clock return. Test clock input to the XDS510 emulator. May be a buffered or unbuffered version of TCK. JTAG test clock. TCK is a 10-MHz clock source from the emulation cable pod. This signal can be used to drive the system test clock. Emulation pin 0 Emulation pin 1

7 9

TDO TCK_RET

I I

O O

11

TCK

13 14

EMU0 EMU1

I I

I/O I/O

D-2

Bus Protocol

D.2 Bus Protocol

The IEEE standard 1149.1 covers the requirements for JTAG bus slave devices (C5x) and provides certain rules, summarized as follows:
- The TMS and TDI inputs are sampled on the rising edge of the TCK signal

of the device.
- The TDO output is clocked from the falling edge of the TCK signal of the

device. When JTAG devices are daisy-chained together, the TDO of one device has approximately a half TCK cycle setup time before the next devices TDI signal. This timing scheme minimizes race conditions that would occur if both TDO and TDI were timed from the same TCK edge. The penalty for this timing scheme is a reduced TCK frequency. The IEEE standard 1149.1 does not provide rules for JTAG bus master (XDS510) devices. Instead, it states that it expects a bus master to provide bus slave compatible timings. The XDS510 provides timings that meet the bus slave rules and also provides an optional timing mode that allows you to run the emulation at a much higher frequency for improved performance.

Design Considerations for Using XDS510 Emulator

D-3

Emulator Cable Pod

D.3 Emulator Cable Pod

Figure D2 shows a portion of the XDS510 emulator cable pod. The functional features of the emulator pod are:
- TDO and TCK_RET can be parallel-terminated inside the pod if required

by the application. By default, these signals are not terminated.

- TCK is driven with a 74AS1034 device. Because of the high-current drive

(48 mA IOL/IOH), this signal can be parallel-terminated. If TCK is tied to TCK_RET, you can use the parallel terminator in the pod.
- TMS and TDI can be generated from the falling edge of TCK_RET, accord-

ing to the IEEE (JTAG) standard 1149.1 bus slave device timing rules. They can also be driven from the rising edge of TCK_RET, which allows a higher TCK_RET frequency. The default is to match the IEEE standard 1149.1 slave device timing rules. This is an emulator software option that can be selected when the emulator is invoked. In general, single-processor applications can benefit from the higher clock frequency. However, in multiprocessing applications, you may wish to use the IEEE standard 1149.1 bus slave timing mode to minimize emulation system timing constraints.
- TMS and TDI are series-terminated to reduce signal reflections. - A 10-MHz test clock source is provided. You can also provide your own

test clock for greater flexibility.

D-4

Emulator Cable Pod

Figure D2. Emulator Cable Pod Interface

VDD 180 JP1 270

Q 74F175 D Q 33 258 33

TDO (Pin 7)

TMS (Pin 1) TDI (Pin 3)

GND (Pins 4,6,8,10,12)

VDD 10 MHz 10 k 10 k 1034 VDD 180 JP2 270 1004 1034

TCK (Pin 11) TRST (Pin 2)

EMU0 (Pin 13) EMU1 (Pin 14)

TCK_RET (Pin 9) PD (Pin 5)

100 CL 74

NOTE: All devices are 74AS, unless otherwise specified.

Design Considerations for Using XDS510 Emulator

D-5

Emulator Cable Pod Signal Timings

D.4 Emulator Cable Pod Signal Timings

Figure D3 shows the signal timings for the emulator cable pod. Table D2 defines the timing parameters illustrated in the figure. These timing parameters are calculated from values specified in the standard data sheets for the cable pod and are for reference only. Texas Instruments does not test or guarantee these timings. The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an optional target system test clock source.

Figure D3. Emulator Cable Pod Timings

1 TCK_RET 2 TMS TDI (Default) 4 TMS TDI (Optional) 5 3 1.5 V

TDO

Table D2. Emulator Cable Pod Timing Parameters

No. 1 2 3 4 5 6 7 Paramter tTCKmin tTCKmax tTCKhighmin tTCKlowmin td(XTMXmin) td(XTMXmax) td(XTMSmin) td(XTMSmax) tsu(XTDOmin) thd(XTDOmin) Description TCK_RET period TCK_RET high pulse duration TCK_RET low pulse duration TMS/TDI valid from TCK_RET low (default timing) TMS/TDI valid from TCK_RET high (optional timing) TDO setup time to TCK_RET high TDO hold time from TCK_RET high Min 35 15 15 6 7 3 12 20 24 Max 200 Unit ns ns ns ns ns ns ns

D-6

Target System Test Clock

D.5 Target System Test Clock

Figure D4 shows an application with the system test clock generated in the target system. In this application the TCK signal is left unconnected. There are two benefits to having the target system generate the test clock: 1) You can set the test clock frequency to match your system requirements. The emulator provides only a single 10-MHz test clock. 2) You may have other devices in your system that require a test clock when the emulator is not connected.

Figure D4. Target-System Generated Test Clock

Greater than 6 inches VDD C5x EMU0 EMU1 TRST TMS TDI TDO TCK NC 13 14 2 1 3 7 11 9 Emulator header EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND System test clock GND GND GND GND GND 4 6 8 10 12 5 VDD

PD

Design Considerations for Using XDS510 Emulator

D-7

Configuring Multiple Processors

D.6 Configuring Multiple Processors

Figure D5 shows a typical daisy-chained multiprocessor configuration that meets the minimum requirements of the IEEE (JTAG) standard 1149.1. The emulation signals are buffered to isolate the processors from the emulator and provide adequate signal drive for the target system. One of the benefits of this test interface is that you can slow down the test clock to eliminate timing problems. Several key points to multiprocessor support are as follows:
- The processor TMS, TDI, TDO, and TCK signals should be buffered

through the same physical device package for better control of timing skew.
- The input buffers for TMS, TDI, and TCK should have pullup resistors con-

nected to 5 volts to hold these signals at a known value when the emulator is not connected. A pullup resistor value of 4.7 k or greater is suggested.
- Buffering EMU0 and EMU1 is optional but highly recommended to provide

isolation. These are not critical signals and do not have to be buffered through the same physical package as TMS, TCK, TDI, and TDO.

Figure D5. Multiprocessor Connections

C5x TDO TRST TMS TCK TDI EMU0 EMU1 TDO TMS TRST TCK C5x TDI EMU0 EMU1 VDD VDD Emulator header 13 14 2 1 3 7 11 9 EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND GND GND GND GND GND 4 6 8 10 12 PD 5

D-8

Connections Between the Emulator and the Target System

D.7 Connections Between the Emulator and the Target System

It is extremely important to provide high-quality signals between the emulator and the target system. You must supply the correct signal buffering, test clock inputs, and multiple processor interconnections to ensure proper emulator and target system operation. EMU0 and EMU1 are I/O pins on the C5x; however, they are only inputs to the XDS510. In general, these pins are used in multiprocessor systems to provide global run/stop operations.

D.7.1 Emulation Signals Not Buffered

If the distance between the emulation header and the target device is less than 6 inches, no buffering is necessary. Figure D6 shows the no-buffering configuration. The EMU0 and EMU1 signals must have pullup resistors connected to 5 volts to provide a signal rise time of less than 10 s. A 4.7-k resistor is suggested for most applications.

Figure D6. Emulator Connections Without Signal Buffering

Less than 6 inches VDD C5x EMU0 EMU1 TRST TMS TDI TDO TCK 13 14 2 1 3 7 11 9 Emulator header EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND GND GND GND GND GND 4 6 8 10 12 PD 5 VDD

Design Considerations for Using XDS510 Emulator

D-9

Connections Between the Emulator and the Target System

D.7.2 Emulation Signals Buffered

If the distance between the emulation header and the JTAG target device is greater than 6 inches, the emulation signals must be buffered. Figure D7 shows the buffering configuration. Emulation signals TMS, TDI, TDO, and TCK_RET are buffered through the same device package. The EMU0 and EMU1 signals must have pullup resistors connected to 5 volts to provide a signal rise time of less than 10 s. A 4.7-k resistor is suggested for most applications. To have high-quality signals (especially the processor TCK and the emulator TCK_RET signals), you may have to employ special care when routing the printed wiring board trace. You also may have to use termination resistors to match the trace impedance. The emulator pod provides optional internal parallel terminators on the TCK_RET and TDO. TMS and TDI provide fixed series termination.

Figure D7. Buffered Signals

Greater than 6 inches VDD C5x EMU0 EMU1 TRST TMS TDI TDO TCK 13 14 2 1 3 7 11 9 Emulator Header EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND GND GND GND GND GND 4 6 8 10 12 PD 5 VDD

D-10

Emulation Timing Calculations

D.8 Emulation Timing Calculations

The following are a few examples of how to calculate the emulation timings in your system. For actual target timing parameters, see the appropriate device data sheets. Assumptions:
tsu(TTMS) th(TTMS) td(TTDO) td(bufmax) td(bufmin) t(bufskew) ttckfactor Target TMS/TDI setup to TCK high Target TMS/TDI hold from TCK high Target TDO delay from TCK low Target buffer delay maximum Target buffer delay minimum Target buffer skew between two devices in the same package: [td(bufmax) td(bufmin)] 0.15 A 40/60 duty cycle clock 10 ns 5 ns 15 ns 10 ns 1 ns 1.35 ns 0.4

Given in Table D2 (page D-6):

td(XTMSmax) td(XTMX) td(XTMSmax) td(XTMXmin) XDS510 TMS/TDI delay from TCK_RET low, maximum min XDS510 TMS/TDI delay from TCK_RET low, minimum XDS510 TMS/TDI delay from TCK_RET high, maximum XDS510 TMS/TDI delay from TCK_RET high, minimum 20 ns 6 ns 24 ns 7 ns 3 ns

tsu(XTDOmin) TDO setup time to XDS510 TCK_RET high

There are two key timing paths to consider in the emulation design: 1) the TCK_RET/TMS/TDI (tprdtck_TMS) path, and 2) the TCK_RET/TDO (tprdtck_TDO) path. In each case, the worst-case path delay is calculated to determine the maximum system test clock frequency.

Design Considerations for Using XDS510 Emulator

D-11

Emulation Timing Calculations

Case 1:

Single processor, direct connection, TMS/TDI timed from TCK_RET low (default timing). tprdtck_TMS = = = = = = [t(d(XTMSmax) + tsu(TTMS)] / ttckfactor (20 ns + 10 ns) / 0 .4 75 ns (13.3 MHz) [t(d(TTDO) + tsu(XTDOmin)] / ttckfactor (15 ns + 3 ns) / 0.4 45 ns (22.2 MHz)

tprdtck_TDO

In Case 1, the TCK/TMS path is the limiting factor. Case 2: Single processor, direct connection, TMS/TDI timed from TCK_RET high (optional timing). tprdtck_TMS = = = = = = td(XTMSmax) + tsu(TTMS) (24 ns + 10 ns) 34 ns (29.4 MHz) [td(TTDO) + tsu(XTDOmin)] / ttckfactor (15 + 3) / 0.4 45 ns (22.2 MHz)

tprdtck_TDO

In Case 2, the TCK/TDO path is the limiting factor. One other thing to consider in this case is the TMS/TDI hold time. The minimum hold time for the XDS510 cable pod is 7 ns, which meets the 5-ns hold time of the target device. Case 3: Single/multiple processor, TMS/TDI buffered input; TCK_RET/TDO buffered output, TMS/TDI timed from TCK_RET high (optional timing). tprdtck_TMS = = = = = = td(XTMSmax) + tsu(TTMS) + 2 td(bufmax) 24 ns + 10 ns + 2 (10) 54 ns (18.5 MHz) [td(TTDO) + tsu(XTDOmin) + t(bufskew)] / ttckfactor (15 ns + 3 ns + 1.35 ns) / 0.4 58.4 ns (20.7 MHz)

tprdtck_TDO

In Case 3, the TCK/TMS path is the limiting factor. The hold time on TMS/TDI is also reduced by the buffer skew (1.35 ns) but still meets the minimum device hold time.
D-12

Emulation Timing Calculations

Case 4:

Single/multiprocessor, TMS/TDI/TCK buffered input; TDO buffered output, TMS/TDI timed from TCK_RET low (default timing). tprdtck_TMS = = = = = = [td(XTMSmax) + tsu(TTMS) + tbufskew] / tckfactor (24 ns + 10 ns + 1.35 ns) / 0.4 88.4 ns (11.3 MHz) [td(TTDO) + tsu(XTDOmin) + td(bufmax)] / tckfactor (15 ns + 3 ns + 10 ns) / 0.4 70 ns (14.3 MHz)

tprdtck_TDO

In Case 4, the TCK/TMS path is the limiting factor. In a multiprocessor application, it is necessary to ensure that the EMU0 and EMU1 lines can go from a logic low level to a logic high level in less than 10 s. This can be calculated as follows (remember that t = 5 RC): trise = = = 5(Rpullup Ndevices Cload_per_device) 5(4.7k 16 15pF) 5.64 s

Design Considerations for Using XDS510 Emulator

D-13

Appendix E Appendix A

Memories, Sockets, and Crystals

This appendix provides product information regarding memories and sockets that are manufactured by Texas Instruments and are compatible with the C5x. Information is also given regarding crystal frequencies, specifications, and vendors.

Topic
E.1 E.2 E.3

Page
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2 Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2 Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3

Memories, Sockets, and Crystals

E-1

Memories / Sockets Memories

E.1 Memories
This section provides product information on EPROM memories that can be interfaced with C5x processors. Refer to Digital Signal Processing Applications with the TMS320 Family for additional information on interfaces using memories and analog conversion devices. Data sheets for EPROM memories are located in the MOS Memory Data Book (literature number SMYD095): TMS27C64 TMS27C128 TMS27C256 TMS27C512 Another EPROM memory, TMS27C291/292, is described in a data sheet (literature number SMLS291).

E.2 Sockets
AMP manufactures a 132-pin quad flat pack socket for the C5x devices. There are two pieces a base (the socket itself) and a lid. The part numbers are:
- Base: AMP part number 821942-1 - Lid: AMP part number 821949-5

For additional information about TI sockets, contact the nearest TI sales office or: Texas Instruments Incorporated Connector Systems Dept, M/S 143 Attleboro, MA 02703 (617) 6995242/5269 Telex: 927708

E-2

Crystals

E.3 Crystals
This section lists the commonly used crystal frequencies (Table E1), crystal specification requirements, and the names of suitable vendors.

Table E1. Commonly Used Crystal Frequencies

Device TMS320C25 TMS320C5x Frequency 40.96 MHz 20.48 MHz 40.96 MHz

When connected across X1 and X2/CLKIN of the TMS320 processor, a crystal enables the internal oscillator. Crystal specification requirements are listed below: Load capacitance = 20 pF Series resistance = 30 ohm Power dissipation = 1 mW Vendors of crystals suitable for use with TMS320 devices are listed below: RXD, Inc. Norfolk, NB (800) 2288108 N.E.L. Frequency Controls, Inc. Burlington, WI (414) 7633591 CTS Knight, Inc. Contact the local distributor.

Memories, Sockets, and Crystals

E-3

Appendix F Appendix A

Submitting ROM Codes to TI

Texas Instruments offers a mask-programmable ROM to provide a single-chip solution to its customers. This appendix explains the benefits of the spacesaving ROM and describes the function of the TMS320 development tools.

Topic
F.1 F.2 F.3

Page
Single-Chip Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-2 TMS320 Development Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-3 Submitting TMS320 ROM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-4

Submitting ROM Codes to TI

F-1

Single-Chip Solution

F.1 Single-Chip Solution

The size of a printed circuit board is a consideration in many DSP applications. To make full use of the board space, Texas Instruments offers this ROM code option that reduces the chip count and provides a single-chip solution. This option allows you to use a code-customized processor for a specific application while taking advantage of:
-

Greater memory expansion Lower system cost Less hardware and wiring Smaller PCB

If a routine or algorithm is used often, it can be programmed into the on-chip ROM of a TMS320 DSP. TMS320 programs can also be expanded by using external memory; this reduces chip count and allows for a more flexible program memory. Multiple functions are easily implemented by a single device, thus enhancing system capabilities. TMS320 development tools are used to develop, test, refine, and finalize the algorithms. The microprocessor/microcomputer (MP/MC) mode is available on all ROM-coded TMS320 DSP devices when accesses to either on-chip or off-chip memory are required. The microprocessor mode is used to develop, test, and refine a system application. In this mode of operation, the TMS320 acts as a standard microprocessor by using external program memory. When the algorithm has been finalized, the code can be submitted to Texas Instruments for masking into the on-chip program ROM. At that time, the TMS320 becomes a microcomputer that executes customized programs from the onchip ROM. Should the code need changing or upgrading, the TMS320 can once again be used in the microprocessor mode. This shortens the fieldupgrade time and avoids the possibility of inventory obsolescence.

F-2

TMS320 Development Flow

F.2 TMS320 Development Flow

Figure F1 illustrates the procedural flow for developing and ordering TMS320 masked parts. When ordering, there is a one-time, nonrefundable charge for mask tooling. A minimum production order per year is required for any masked-ROM device. ROM codes are deleted from the Texas Instruments system one year after the final delivery.

Figure F1. TMS320 ROM Code Submittal Flowchart

Customer TMS320 design

Customer submits: TMS320 New Code Release Form Print Evaluation and Acceptance Form (PEAF) Purchase order for mask prototypes TMS320 code

Texas Instruments responds: Customer code input into TI system Code sent back to customer for verification

No

Customer approves algorithm

Yes TI produces prototypes

No

Customer approves prototypes (minimum production order required) Yes TMS320 production

Submitting ROM Codes to TI

F-3

Submitting TMS320 ROM Code

F.3 Submitting TMS320 ROM Code

The TMS320 ROM code may be submitted in one of the following forms:
-

3-1/2-inch floppy: COFF format from macro-assembler/linker (preferred) 5-1/4-inch floppy: COFF format from macro-assembler/linker Modem (BBS): COFF format from macro-assembler/linker EPROM (others): TMS27C64 PROM: TBP28S166, TBP28S86

When code is submitted to TI for masking, the code is reformatted to accommodate the TI mask-generation system. System-level verification by the customer is therefore necessary to ensure the reformatting remains transparent and does not affect the execution of the algorithm. The formatting changes involve the removal of address-relocation information (the code address begins at the base address of the ROM in the TMS320 device and progresses without gaps to the last address of the ROM) and the addition of data in the reserved locations of the ROM for device ROM test. Because these changes have been made, a checksum comparison is not a valid means of verification. With each masked-device order, the customer must sign a disclaimer that states: The units to be shipped against this order were assembled, for expediency purposes, on a prototype (that is, nonproduction qualified) manufacturing line, the reliability of which is not fully characterized. Therefore, the anticipated inherent reliability of these prototype units cannot be expressly defined. and a release that states: Any masked ROM device may be resymbolized as TI standard product and resold as though it were an unprogrammed version of the device, at the convenience of Texas Instruments. The use of the ROM-protect feature does not hold for this release statement. Additional risk and charges are involved when the ROM-protect feature is selected. Contact the nearest TI Field Sales Office for more information on procedures, leadtimes, and cost associated with the ROM-protect feature.

F-4

Appendix G Appendix A

Development Support and Part Order Information

This appendix provides development support information, device part numbers, and support tool ordering information for the C5x. Each C5x support product is described in the TMS320 DSP Development Support Reference Guide. In addition, more than 100 third-party developers offer products that support the TI TMS320 family. For more information, refer to the TMS320 Third-Party Support Reference Guide. For information on pricing and availability, contact the nearest TI Field Sales Office or authorized distributor. See the list at the back of this book.

Topic
G.1 G.2 G.3

Page
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-2 Part Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-4 Hewlett-Packard E2442A Preprocessor C5x Interface . . . . . . . . . . . . G-8

Development Support and Part Order Information

G-1

Development Support

G.1 Development Support

This section describes the development support provided by Texas Instruments.

G.1.1 Software and Hardware Development Tools

TI offers an extensive line of development tools for the C5x generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C5x-based applications:
- Software Development Tools: - Assembler/linker - Simulator - Optimizing ANSI C compiler - Application algorithms - C/Assembly debugger and code profiler - Hardware Development Tools: - Emulator XDS510 - C5x Evaluation Module (EVM) - C5x DSP Starter Kit (DSK)

G.1.2 Third-Party Support

The TMS320 family is supported by products and services from more than 100 independent third-party vendors and consultants. These support products take various forms (both as software and hardware), from cross-assemblers, simulators, and DSP utility packages to logic analyzers and emulators. The expertise of those involved in support services ranges from speech encoding and vector quantization to software/hardware design and system analysis. To ask about third-party services, products, applications, and algorithm development packages, contact the third party directly. Refer to the TMS320 ThirdParty Support Reference Guide for addresses and phone numbers.

G-2

Development Support

G.1.3 Technical Training Organization (TTO) TMS320 Workshops

TMS320C5x DSP Design Workshop. This workshop is tailored for hardware and software design engineers and decision-makers who will be designing and utilizing the C5x generation of DSP devices. Hands-on exercises throughout the course give participants a rapid start in developing C5x design skills. Microprocessor/assembly language experience is required. Experience with digital design techniques and C language programming experience is desirable. These topics are covered in the C5x workshop:
-

DSP fundamentals C5x architecture/instruction set Use of the PC-based software simulator Use of the C5x assembler/linker C programming environment System architecture considerations Memory and I/O interfacing Serial ports and multiple processor features

For registration information, pricing, or to enroll, call (972)6445580.

G.1.4 Assistance
For assistance to TMS320 questions on device problems, development tools, documentation, software upgrades, and new products, you can contact TI. See If You Need Assistance in Preface for information.

Development Support and Part Order Information

G-3

Part Order Information

G.2 Part Order Information

This section describes the part numbers of C5x devices, development support hardware, and software tools.

G.2.1 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefix designators: TMX, TMP, or TMS. Each support tool has one of two possible prefix designators: TMDX or TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices and tools (TMS/TMDS). This development flow is defined below. Device Development Evolutionary Flow: TMX TMP The part is an experimental device that is not necessarily representative of the final devices electrical specifications. The part is a device from a final silicon die that conforms to the devices electrical specifications but has not completed quality and reliability verification. The part is a fully qualified production device.

TMS

Support Tool Development Evolutionary Flow: TMDX The development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS The development-support product is a fully qualified development support product. TMX and TMP devices, and TMDX development-support tools are shipped with the following disclaimer: Developmental product is intended for internal evaluation purposes. TMS devices and TMDS development-support tools have been fully characterized, and the quality and reliability of the device has been fully demonstrated. Texas Instruments standard warranty applies to these products. Note: It is expected that prototype devices (TMX or TMP) have a greater failure rate than standard production devices. Texas Instruments recommends that these devices not be used in any production system, because their expected end-use failure rate is still undefined. Only qualified production devices should be used.

G-4

Part Order Information

G.2.2 Device Nomenclature

TI device nomenclature includes the device family name and a suffix. Figure G1 provides a legend for reading the complete device name for any TMS320 family member.

Figure G1. TMS320 Device Nomenclature

TMS 320 (B) C Prefix TMX = Experimental device TMP = Prototype device TMS = Qualified device SM = High reliability (non 883C) SMJ = MILSTD883C 52 PJ (L) 100 MIPS

Device family 320 = DSP Family Boot loader option Technology C = CMOS E = CMOS EPROM LC = Low-Voltage CMOS (3.3V) VC = Low-Voltage CMOS (3V)

Temperature range H = 0 to 50C L = 0 to 70C A = -40 to 85C S = -55 to 100C M = -55 to 125C Package type FD = Ceramic leadless CC FN = Plastic leaded CC FZ = Ceramic CER-QUAD GB = Ceramic PGA J = Ceramic CER-DIP JD = Ceramic DIP side-brazed N = Plastic DIP PJ = 100-pin plastic EIAJ QFP PQ = 100/132-pin plastic BQFP PZ = 100-pin plastic TQFP PBK = 120/128-pin plastic TQFP PGE = 144-pin plastic TQFP Device C1x DSP: 10 14 15 16 17 C2x DSP: 25 26 C2xx DSP: 203 204 205 209 C3x DSP: 30 31 32 C4x DSP: 40 44 C5x DSP: 50 51 52 53 56 57 C54x DSP: 541 542 543 545 546 548 C8x DSP: 80 82

Development Support and Part Order Information

G-5

Part Order Information

G.2.3 Development Support Tools

Figure G2 provides a legend for reading the part number for any TMS320 hardware or software development tool. Table G1 lists the development support tools available for the C5x, the platform on which they run, and their part numbers.

Figure G2. TMS320 Development Tool Nomenclature

TMDS 32 4 28 1 Qualification status TMDX = Prototype TMDS = Qualified 0 0 2 Medium 2 = 5.25-inch floppy disk 8 = 1600 BPI magnetic tape

Device family 32 = TMS320 family

S/W format 0 = Object code 1 = Source code Sequence number

Product type 4 = Software 6 = Hardware 8 = Upgrade Model 11 = XDS/11 22 = XDS/22 88 = Upgrade kits

Generation 1 = C1x 2 = C2x 3 = C3x 4 = C4x 5 = C5x Format 1 = TI-tagged 5 = COFF

Operating system 02 = C1x VAX/VMS 08 = C1x IBM MS/PC-DOS 22 = C2x VAX/VMS 25 = C2x/C2xx/C5x SPARC 28 = C2x or C1x/C2x/C2xx/C5x IBM MS/PC-DOS 32 = C3x VAX/VMS 38 = C3x IBM MS/PC-DOS 42 = C4x VAX/VMS 48 = C4x IBM MS/PC-DOS 52 = C5x VAX/VMS 55 = C5x or C2xx/C5x SPARC 58 = C5x or C2xx/C5x IBM MS/PC-DOS

Software only. Hardware only.

G-6

Part Order Information

Table G1. TMS320C5x Development Support Tools Part Numbers

Development Tool Assembler/Linker C Compiler/Assembler/Linker C Compiler/Assembler/Linker Debugger/Emulation Software Debugger/Emulation Software Digital Filter Design Package DSP Starter Kit (DSK) Evaluation Module (EVM) Simulator (C language) Simulator (C language) XDS510XL Emulator XDS510WS Emulator Platform PC (DOSt, OS/2t) PC (DOSt, OS/2t) HP (HP-UXt) / SPARCt (Sun OSt) PC (DOSt, Windowst, OS/2t) SPARCt (Sun OSt) PC (DOSt) PC (DOSt) PC (DOSt, Windowst) PC (DOSt, Windowst) SPARCt (Sun OSt) PC (DOSt, OS/2t) SPARCt (Sun OSt) Part Number TMDS3242850-02 TMDS3242855-02 TMDS3242555-08 TMDS3240150 TMDS3240650 DFDP TMDS3200051 TMDS3260050 TMDS3245851-02 TMDS3245551-09 TMDS00510 TMDS00510WS TMDS3080002

3 V/5 V PC/SPARC JTAG Emulation Cable XDS510t / XDS510WSt

Includes XDS510 board and JTAG cable Includes XDS510WS box and JTAG cable

Development Support and Part Order Information

G-7

Hewlett-Packard E2442A Preprocessor C5x Interface

G.3 Hewlett-Packard E2442A Preprocessor C5x Interface

The Hewlett-Packard E2442A preprocessor C5x interface provides a mechanical and electrical connection between your target system and an HP logic analyzer. Preprocessor hardware captures processor signals and passes them to the logic analyzer at the appropriate time, depending on the type of measurement you are making. With the preprocessor plugged in, both state and timing analysis is available. Two connectors are loaded onto the preprocessor to facilitate communications with other debugging tools. A BNC connector, when used with the sequencer of the logic analyzer halts the processor on a condition. Then you can use the C5x HLL debugger to examine the state of the system (for example, microprocessor registers). Likewise, a 14-pin connector is available to receive signals from the XDS510 development system. These signals can be used when defining a trigger condition for the analyzer. The preprocessor includes software which automatically labels address, data, and status lines. Additionally, a disassembler is included. The disassembler processes state traces and displays the information on TMS320 mnemonics.

G.3.1 Capabilities
The preprocessor supports three modes of operation: in the first mode, State per Transfer, the preprocessor clocks the logic analyzer only when a bus transfer is complete. In this mode, wait and halt states are filtered out. In the second mode, CLKOUT1 clocks the logic analyzer every time the microprocessor is clocked. This mode captures all bus states. An example application would be to locate memory locations that do not respond to requests for data. In the third mode, you can use the preprocessor to make timing measurements. The JTAG TAP (test access port) controller can be monitored in realtime. TAP state can be viewed under the predefined label TAP.

G.3.2 Logic Analyzers Supported

The preprocessor C5x interface supports the following logic analyzers:
G-8

HP 1650A/B HP 16510B HP 16511B HP 16540/41(A/D) HP 16550A HP 1660A/61A/62A

Hewlett-Packard E2442A Preprocessor C5x Interface

G.3.3 Pods Required

There are eight pod-connectors on the preprocessor. Three are terminated and best used for state analysis as all signals needed for disassembly are available. The other five connectors are not terminated and contain all processor signals, including a second set of the signals needed for disassembly. This allows you to double probe these signals, making simultaneous state and timing measurements.

G.3.4 Termination Adapters (TAs)

Of the eight pods, three are terminated. You may need to order up to five termination adapters, depending on how many pods are connected at the same time.

G.3.5 Availability
For more information and availability of the Hewlett-Packard E2442A, contact: Hewlett-Packard Company 2000 South Park Place Atlanta, GA 30339 (404) 9807351

Development Support and Part Order Information

G-9

Appendix H Appendix A

Glossary
A
A0A15: External address pins for data/program memory or I/O devices. ABU: See autobuffering unit (ABU). ACC: See accumulator (ACC). ACCB: See accumulator buffer (ACCB). ACCH: See accumulator high byte (ACCH). ACCL: See accumulator low byte (ACCL). accumulator (ACC): A 32-bit register that stores the results of an arithmetic logic unit (ALU) operation and provides an input for subsequent ALU operations. The ACC is accessible in two halves: accumulator high (ACCH) and accumulator low (ACCL). accumulator buffer (ACCB): A 32-bit register that temporarily stores the 32-bit contents of the accumulator (ACC). The ACCB has a direct path back to the arithmetic logic unit (ALU) and can be arithmetically or logically acted upon with the ACC. accumulator high byte (ACCH): The higher 16 bits stored in the accumulator (ACC). See also accumulator. accumulator low byte (ACCL): The lower 16 bits stored in the accumulator (ACC). See also accumulator. address: The logical location of program code or data stored in memory.

addressing mode: The method by which an instruction calculates the location of its required data. address visibility (AVIS) bit: A 1-bit field that allows the internal program address to appear at the TMS320C5x pins so that the internal program address can be traced and the interrupt vector can be decoded in conjunction with IACK when the interrupt vectors reside in on-chip memory. At reset, AVIS = 0. This bit is stored in the processor mode status register (PMST).
H-1

Glossary

AFB: See auxiliary register file bus (AFB). ALU: See arithmetic logic unit (ALU). analog-to-digital (A/D) converter: An 8-bit successive-approximation converter with internal sample-and-hold circuitry that translates an analog signal to a digital signal. AR: See auxiliary register (AR). ARAU: See auxiliary register arithmetic unit ARAU). ARB: See auxiliary register buffer (ARB) bits. ARCR: See auxiliary register compare register (ARCR). arithmetic logic unit (ALU): A 32-bit 2s-complement arithmetic logic unit that has two 32-bit input ports and one 32-bit output port feeding the accumulator (ACC). Provides the logic for arithmetic and Boolean operations. ARP: See auxiliary register pointer (ARP) bits. ARR: See BSP address receive register (ARR). assembler: A software program that creates a machine-language program from a source file containing assembly language instructions, directives, and macro directives. The assembler substitutes absolute operation codes for symbolic operation codes, and absolute or relocatable addresses for symbolic addresses. assembly language instructions: The language in which computer operations are represented by mnemonics. autobuffering receiver enable (BRE) bit: A 1-bit field that enables/disables the autobuffering receiver. At reset, BRE = 0. This bit is stored in the BSP control extension register (SPCE). autobuffering receiver halt (HALTR) bit: A 1-bit field that enables/disables the autobuffer receiver. At reset, HALTR = 0. This bit is stored in the BSP control extension register (SPCE). autobuffering transmitter enable (BXE) bit: A 1-bit field that enables/disables the autobuffering transmitter. At reset, BXE = 0. This bit is stored in the BSP control extension register (SPCE). autobuffering transmitter halt (HALTX) bit: A 1-bit field that enables/disables the autobuffer transmitter. At reset, HALTX = 0. This bit is stored in the BSP control extension extension (SPCE).
H-2

Glossary

autobuffering unit (ABU): An on-chip module that allows the serial port interface to read or write directly to internal memory independently of the central processing unit (CPU). Autobuffering capability can be separately enabled for transmit and receive sections. When autobuffering is disabled, the operation is similar to that of the C5x standard serial port. auxiliary register (AR): Eight 16-bit memory-mapped registers (AR0AR7) that are used for indirect data address pointers, temporary storage, or integer arithmetic processing through the auxiliary register arithmetic unit (ARAU). Each AR is selected by the auxiliary register pointer (ARP). auxiliary register arithmetic unit (ARAU): An unsigned 16-bit arithmetic logic unit that calculates indirect addresses using the auxiliary, index, and compare registers as inputs. auxiliary register buffer (ARB) bits: A 3-bit field that holds the previous value contained in the auxiliary register pointer (ARP). These bits are stored in status register 1 (ST1). auxiliary register compare register (ARCR): A 16-bit memory-mapped register used as a limit to compare indirect adresses. auxiliary register file bus (AFB): The bus on which the currently selected auxiliary register (AR) addresses the data memory location. auxiliary register pointer (ARP) bits: A 3-bit field that selects the auxiliary register (AR) to use in indirect addressing. When the ARP is loaded, the previous ARP value is copied to the auxiliary register buffer (ARB). The ARP can be modified by memory-reference instructions when using indirect addressing, and by the MAR and LST instructions. These bits are stored in status register 0 (ST0). AVIS: See address visibility (AVIS) bit. AXR: See BSP address transmit register (AXR).

B
barrel shifter: A unit that rotates bits in a word. See also POSTSCALER and PRESCALER. BIG bit: A 1-bit field that specifies how the input/out (I/O) port wait-state register is mapped. This bit is stored in the wait-state control register (CWSR). At reset, BIG = 0. bit-reversed addressing: A method of indirect addressing that allows efficient I/O operations by resequencing the data points in a radix-2 FFT program. The direction of carry propagation in the ARAU is reversed.
Glossary
H-3

Glossary

BKR: See BSP receive buffer size register (BKR). BKX: See BSP transmit buffer size register (BKX). block move address register (BMAR): A 16-bit memory-mapped register that holds an address value for use with block moves or multiply/accumulates. block repeat active flag (BRAF) bit: A 1-bit field that indicates a block repeat is currently active. This bit is normally set when the RPTB instruction is executed and is cleared when the BRCR register decrements below 0. Writing a 0 to this bit deactivates block repeat. At reset, BRAF = 0. This bit is stored in the processor mode status register (PMST). block repeat counter register (BRCR): A 16-bit memory-mapped register that limits the number of times a block is repeated. block repeat program address end register (PAER): A 16-bit memorymapped register that contains the end address of the segment of code being repeated. block repeat program address start register (PASR): A 16-bit memorymapped register that contains the start address of the segment of code being repeated. BMAR: See block move address register (BMAR). BOB: See byte ordering bit (BOB). boot: The process of loading a program into program memory.

boot loader: A built-in segment of code that transfers code from an external source to program memory at power-up. BRAF: See block repeat active flag (BRAF) bit. BRCR: See block repeat counter register (BRCR). BRE: See autobuffering receiver enable (BRE) bit. BSP: See buffered serial port (BSP). BSP address receive register (ARR): An 11-bit memory-mapped register that stores the address for writing a word to be transferred from the data receive register (DRR) to C5x internal memory. When autobuffering is enabled (BRE = 1), the ARR is no longer available for software access as a memory-mapped register.
H-4

Glossary

BSP address transmit register (AXR): An 11-bit memory-mapped register that stores the address for reading a word to be transferred from C5x internal memory to the data transmit register (DXR). When autobuffering is enabled (BXE = 1), the AXR is no longer available for software access as a memory-mapped register. BSP control extension register (SPCE): A 16-bit memory-mapped register that contains status and control bits for the buffered serial port (BSP) interface. The 10 LSBs of the SPCE are dedicated to serial port interface control, whereas the 6 MSBs are used for autobuffering unit (ABU) control. BSP receive buffer size register (BKR): An 11-bit memory-mapped register that stores the address block size for writing a word to be transferred from the data receive register (DRR) to C5x internal memory. When autobuffering is enabled (BRE = 1), the BKR is no longer available for software access as a memory-mapped register. BSP transmit buffer size register (BKX): An 11-bit memory-mapped register that stores the address block size for reading a word to be transferred from C5x internal memory to the data transmit register (DXR). When autobuffering is enabled (BXE = 1), the BKX is no longer available for software access as a memory-mapped register. buffered serial port (BSP): An on-chip module that consists of a full-duplex, double-buffered serial port interface and an autobuffering unit (ABU). The double-buffered serial port of the BSP is an enhanced version of that available in other TMS320C5x devices (C50, C51, C52, and C53). The double-buffered serial port allows transfer of a continuous communication stream (8-,10-,12- or 16-bit data packets). Status and control of the BSP is specified in the BSP control extension register (SPCE). burst mode: A synchronous serial port mode in which a single word is transmitted following a frame synchronization pulse (FSX and FSR). butterfly: A kernel function that computes an N-point fast Fourier transform (FFT), where N is a power of 2. The combinational pattern of inputs resembles butterfly wings. BXE: See autobuffering transmitter enable (BXE) bit. byte ordering bit (BOB): A 1-bit field that affects host processor data and address transfers when using the host port interface. Only the host processor can toggle this bit. The BOB must be initialized before the first data or address register access. This bit is stored in the HPI control register (HPIC).
Glossary
H-5

Glossary

C
C: See carry (C) bit. CALU: See central arithmetic logic unit (CALU). CAR1: See circular buffer 1 auxiliary register (CAR1) bits. CAR2: See circular buffer 2 auxiliary register (CAR2) bits. carry (C) bit: A 1-bit field that stores the carry output of the arithmetic logic unit (ALU). At reset, C = 1. The C bit can be tested by conditional instructions. This bit is stored in status register 1 (ST1). CBCR: See circular buffer control register (CBCR). CBER1: See circular buffer 1 end register (CBER1). CBER2: See circular buffer 2 end register (CBER2). CBSR1: See circular buffer 1 start register (CBSR1). CBSR2: See circular buffer 2 start register (CBSR2). CENB1: See circular buffer 1 enable (CENB1) bit. CENB2: See circular buffer 2 enable (CENB2) bit. central arithmetic logic unit (CALU): A 32-bit arithmetic logic unit that executes 32-bit operations in a single machine cycle. The CALU consists of the arithmetic logic unit (ALU), multiplier (MULT), accumulator (ACC), accumulator buffer (ACCB), and scaling shifters (PRESCALERS, P-SCALER, and POSTSCALER). central processing unit (CPU): The module of the TMS320C5x that controls and interprets the machine-language program and its execution. The CPU consists of the central arithmetic logic unit (CALU), parallel logic unit (PLU), auxiliary register arithmetic unit (ARAU), and registers. circular buffer 1 auxiliary register (CAR1) bits: A 3-bit field that identifies which auxiliary register (AR) is assigned to circular buffer 1. These bits are stored in the circular buffer control register (CBCR). circular buffer 1 enable (CENB1) bit: A 1-bit field that enables/disables circular buffer 1. At reset, CENB1 = 0. This bit is stored in the circular buffer control register (CBCR). circular buffer 1 end register (CBER1): A 16-bit memory-mapped register that indicates the circular buffer 1 end address.
H-6

Glossary

circular buffer 1 start register (CBSR1): A 16-bit memory-mapped register that indicates the circular buffer 1 start address. circular buffer 2 auxiliary register (CAR2) bits: A 3-bit field that identifies which auxiliary register (AR) is assigned to circular buffer 2. These bits are stored in the circular buffer control register (CBCR). circular buffer 2 enable (CENB2) bit: A 1-bit field that enables/disables circular buffer 2. At reset, CENB2 = 0. This bit is stored in the circular buffer control register (CBCR). circular buffer 2 end register (CBER2): A 16-bit memory-mapped register that indicates the circular buffer 2 end address. circular buffer 2 start register (CBSR2): A 16-bit memory-mapped register that indicates the circular buffer 2 start address. circular buffer control register (CBCR): An 8-bit memory-mapped register that enables/disables the circular buffers (CENB1 and CENB2 bits) and defines which auxiliary registers (CAR1 and CAR2 bits) are mapped to the circular buffers. CLKDV: See internal transmit clock division factor (CLKDV) bits. CLKP: See clock polarity (CLKP) bit. clock modes: Options used by the clock generator to change the internal CPU clock frequency to a fraction or multiple of the frequency of the input clock signal. clock mode (MCM) bit: A 1-bit field that specifies the source of the clock for CLKX. At reset, MCM = 0. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC). clock polarity (CLKP) bit: A 1-bit field that indicates when the data is sampled by the receiver and sent by the transmitter. At reset, CLKP = 0. This bit is stored in the BSP control extension register (SPCE). CNF: See configuration control (CNF) bit. code: A set of instructions written to perform a task.

cold boot: The process of loading a program into program memory at power-up. configuration control (CNF) bit: A 1-bit field that indicates if on-chip dualaccess RAM block 0 (DARAM B0) is mapped to program or data space. At reset, CNF = 0. This bit is stored in status register 1 (ST1).
Glossary
H-7

Glossary

context save/restore: A save/restore of system status (status registers, accumulator, product register, temporary register, hardware stack, and auxiliary registers, etc.) when the device enters/exits a subroutine such as an interrupt service routine. continuous mode: A synchronous serial port mode in which only one frame synchronization pulse (FSX and FSR) is necessary to transmit several packets at maximum frequency. CPU: See central processing unit (CPU). current auxiliary register: The auxiliary register pointed to by the auxiliary register pointer (ARP). CWSR: See wait-state control register (CWSR).

D
D0D15: External data bus pins that transfer data between the C5x and external data/program memory or I/O devices. DAB: See direct address bus (DAB). DARAM: See dual-access RAM. data bus: A group of connections used to route data. data memory: A memory region used for storing and manipulating data. data memory address (dma): The seven LSBs of a direct addressed instruction that contains the immediate relative address within a 128-word data page. The seven LSBs are concatenated with the data memory page pointer (DP) to form the direct memory address of 16 bits. See also data memory page pointer (DP). data memory page pointer (DP) bits: A 9-bit field that specifies the current data memory page address. The DP bits are concatenated with the 7 LSBs of the instruction word to form the direct memory address of 16 bits. These bits are stored in status register 0 (ST0). data memory page 0: The first page in data memory space where the memory-mapped registers and the scratch-pad RAM block (B2) reside. data receive register (DRR): A 16-bit memory-mapped register that holds serial data copied from the receive shift register (RSR). When autobuffering is enabled (BRE = 1), the DRR is no longer available for software access as a memory-mapped register. See also data receive shift register (RSR).
H-8

Glossary

data receive shift register (RSR): A 16-bit register that holds serial data received from the DR pin. See also data receive register (DRR). data transmit register (DXR): A 16-bit memory-mapped register that holds serial data to be copied to the data transmit shift register (XSR). When autobuffering is enabled (BXE = 1), the DXR is no longer available for software access as a memory-mapped register. See also data transmit shift register (XSR). data transmit shift register (XSR): A 16-bit register that holds serial data to be transmitted from the DX pin (or TDX pin when TDM = 1). See also data transmit register (DXR) and TDM data transmit register (TDXR). DBMR: See dynamic bit manipulation register (DBMR). digital loopback (DLB) mode: A synchronous serial port test mode in which the DLB bit connects the receive pins to the transmit pins on the same device to test if the port is operating correctly. digital loopback mode (DLB) bit: A 1-bit field that puts the serial port in digital loopback mode. At reset, DLB = 0. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC). direct address bus (DAB): A 16-bit bus that provides the data address used by the central processing unit (CPU). direct memory access (DMA): A mode where a device other than the host processor contends for, and receives, mastership of the memory bus so that data transfers may take place independent of the host. DLB: See digital loopback mode (DLB) bit. dma: See data memory address (dma). DMA: See direct memory access (DMA). DP: See data memory page pointer (DP) bits. DRR: See data receive register (DRR). DSP interrupt (DSPINT) bit: A 1-bit field that enables/disables an interrupt from a host processor to the TMS320C57. The DSPINT bit is written from the host processor; a C57 write has no effect on the DSPINT bit. When DSPINT = 1, a C57 interrupt is generated. The host must write a 0 to the DSPINT bit while writing to the BOB or HINT bits, so that the host does not provoke an unwanted C57 interrupt. This bit is stored in the HPI control register (HPIC).
Glossary
H-9

Glossary

DSPINT: See DSP interrupt (DSPINT) bit. dual-access RAM (DARAM): Memory space that can be read from and written to in the same clock cycle. dynamic bit manipulation register (DBMR): A 16-bit memory-mapped register that masks the input to the parallel logic unit (PLU) in the absence of a long immediate value. DXR: See data transmit register (DXR).

E
enable extra index register (NDX) bit: A 1-bit field that determines if a modification or write to auxiliary register 0 (AR0) also modifies or writes to the index register (INDX), and the auxiliary register compare register (ARCR) to maintain compatibility with the TMS320C2x. This bit is stored in the processor mode status register (PMST). enable multiple TREGs (TRM) bit: A 1-bit field that indicates if an LT(A,D,P,S) instruction loads only TREG0 or loads all three of the temporary registers (TREG0, TREG1, and TREG2) to maintain compatibility with the TMS320C2x. The TRM bit allows the TMS320C5x to operate in either C2x-compatible mode (TRM = 0) or C5x-enhanced mode (TRM = 1) in conjunction with the use of TREG0, TREG1, and TREG2. The TRM bit affects the operation of all C2x-compatible instructions that modify TREG0. This bit is stored in the processor mode status register (PMST). external flag (XF) pin status bit: A 1-bit field that drives the level of the external flag (XF) pin. At reset, XF = 1.This bit is stored in status register 1 (ST1). external interrupt: A hardware interrupt triggered by a pin (INT1INT4).

F
fast Fourier transform (FFT): An efficient method of computing the discrete Fourier transform, which transforms functions between the time domain and frequency domain. The time-to-frequency domain is called the forward transform, and the frequency-to-time domain is called the inverse transformation. See also butterfly. FE: See format extension (FE) bit.
H-10

Glossary

FFT: See fast Fourier transform (FFT). FIG: See frame ignore (FIG) bit. FO: See format (FO) bit. format (FO) bit: A 1-bit field that specifies the word length of the serial port transmitter and receiver. The data is transferred with the MSB first. At reset, FO = 0. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC). format extension (FE) bit: A 1-bit field used in conjunction with the format bit (FO) to specify the word length of the BSP serial port transmitter and receiver. When FO = FE = 00, the format is 16-bit words; when FO = FE = 01, the format is 10-bit words; when FO = FE = 10, the format is 8-bit words; and when FO = FE = 11, the format is 12-bit words. For 8-,10-, and 12-bit words, the received words are right-justified and the sign bit is extended to form a 16-bit word. The words to transmit must be right-justified. At reset, FE = 0. This bit is stored in the BSP control extension register (SPCE). frame ignore (FIG) bit: A 1-bit field used only in transmit continuous mode with external frame and in receive continuous mode. At reset, FIG = 0. This bit is stored in the BSP control extension register (SPCE). frame synchronization mode (FSM) bit: A 1-bit field that specifies whether frame synchronization pulses (FSX and FSR) are required for serial port operation. At reset, FSM = 0. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC). frame synchronization polarity (FSP) bit: A 1-bit field that determines the status of the frame synchronization pulses. At reset, FSP = 0. This bit is stored in the BSP control extension register (SPCE). Free bit: A 1-bit field used in conjunction with the Soft bit to determine the state of the serial port clock when a breakpoint is encountered in the highlevel language debugger. At reset, Free = 0. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC). FSM: See frame synchronization mode (FSM) bit. FSP: See frame synchronization polarity (FSP) bit.
Glossary
H-11

Glossary

G
general-purpose input/output pins: Pins that can be used to supply input signals from an external device or output signals to an external device. These pins are not linked to specific uses; rather, they provide input or output signals for a variety of purposes. These pins include the generalpurpose BIO input pin and XF output pin. global data memory space: One of four memory spaces. The global data memory space can either share data with other processors within the system or serve as additional data memory space. global memory allocation register (GREG): An 8-bit memory-mapped register that specifies the size of the global memory space. At reset, the GREG is cleared. GREG: See global memory allocation register (GREG).

H
HALTR: See autobuffering receiver halt (HALTR) bit. HALTX: See autobuffering transmitter halt (HALTX) bit. hardware interrupt: An interrupt triggered through physical connections with on-chip peripherals or external devices. HINT bit: C57-to-Host Processor Interrupt. A 1-bit field that enables/disables an interrupt from the TMS320C57 to a host processor. At reset, HINT = 0. This bit is stored in the HPI control register (HPIC). HM: See hold mode (HM) bit. HOM: See host-only mode (HOM). hold mode (HM) bit: A 1-bit field that determines whether the central processing unit (CPU) can stop or continue when the HOLD signal initiates a power-down mode. At reset, HM = 1. This bit is stored in status register 1 (ST1). host-only mode (HOM): The mode that allows the host to access HPI memory while the TMS230C57 is in IDLE2 (all internal clocks stopped) or in reset mode. The external C57 clock may even be stopped. The host can therefore access the HPI RAM while the C57 is in its optimum configuration in terms of power consumption.
H-12

Glossary

host port interface (HPI): An on-chip module consisting of an 8-bit parallel port that interfaces a host processor to the TMS320C57. The HPI has two modes of operation, shared-access mode (SAM) and host-only mode (HOM). Status and control of the HPI is specified in the HPI control register (HPIC). See also shared-access mode (SAM) and host-only mode (HOM). HPI: See host port interface (HPI). HPIA: See HPI address register (HPIA). HPIAH: See HPI address register high byte (HPIAH). HPIAL: See HPI address register low byte (HPIAL). HPIC: See HPI control register (HPIC). HPICH: See HPI control register high byte (HPICH). HPICL: See HPI control register low byte (HPICL). HPI address register (HPIA): A 16-bit register that stores the address of the host port interface (HPI) memory block. The HPIA can be preincremented or postincremented. HPI address register high byte (HPIAH): The higher 16 bits stored in the HPI address register (HPIA). See also HPI address register (HPIA). HPI address register low byte (HPIAL): The lower 16 bits stored in the HPI address register (HPIA). See also HPI address register (HPIA). HPI control register (HPIC): A 16-bit register that contains status and control bits for the host port interface (HPI). HPI control register high byte (HPICH): The higher 16 bits stored in the HPI control register (HPIC). See also HPI control register (HPIC). HPI control register low byte (HPICL): The lower 16 bits stored in the HPI control register (HPIC). See also HPI control register (HPIC).

I
I/O port wait-state register (IOWSR): A 16-bit memory-mapped register that specifies the number of wait states for the input/out (I/O) port. The IOWSR can be mapped in one of two ways as specified by the BIG bit in the wait-state control register (CWSR). At reset, IOWSR = FFFF. IFR: See interrupt flag register (IFR).
Glossary
H-13

Glossary

IMR: See interrupt mask register (IMR). IN0 bit: Input 0 bit. A 1-bit field that allows the CLKR pin to be used as an input. IN0 reflects the current level of the CLKR pin of the device. This bit is stored in the SPC and TDM serial port control register (TSPC). IN1 bit: Input 1 bit. A 1-bit field that allows the CLKX pin to be used as an input. IN1 reflects the current level of the CLKX pin of the device. This bit is stored in the SPC and TDM serial port control register (TSPC). index register (INDX): A 16-bit memory-mapped register that specifies increment sizes greater than 1 for indirect addressing updates. In bitreversed addressing, the INDX defines the array size. INDX: See index register (INDX). instruction: The basic unit of programming that causes the execution of one operation; it consists of an opcode and operands along with optional labels and comments. instruction register (IREG): A 16-bit register that contains the actual instruction being executed. internal interrupt: A hardware interrupt caused by an on-chip peripheral. internal transmit clock division factor (CLKDV) bits: A 5-bit field that determines the internal transmit clock duty cycle. At reset, CLKDV = 00011. These bits are stored in the BSP control extension register (SPCE). interrupt: An exceptional condition that is caused either by an external event to the CPU or by a previously executed instruction that forces the current program to stop. The CPU executes instructions of an interrupt service routine (ISR) at an address corresponding to the source of the interrupt. After the CPU services the interrupt, the CPU resumes execution of the program at the instruction whose execution was interrupted. interrupt flag register (IFR): A 16-bit memory-mapped register that flags pending interrupts. The IFR may be read to identify pending interrupts and written to clear selected interrupts. A 1 read from any IFR bit position indicates a pending interrupt. A 1 written to any IFR bit position clears the corresponding interrupt. A 0 written to any IFR bit position has no effect. At reset, the IFR is cleared. interrupt mask register (IMR): A 16-bit memory-mapped register that masks external and internal interrupts. The IMR may be read and written to. A 1 written to any IMR bit position enables the corresponding interrupt (when INTM = 0).
H-14

Glossary

interrupt mode (INTM) bit: A 1-bit field that globally masks or enables all interrupts. When INTM = 0, all unmasked interrupts are enabled. When INTM = 1, all maskable interrupts are disabled. INTM has no effect on the nonmaskable RS and NMI interrupts. At reset, INTM = 1.This bit is stored in status register 0 (ST0). interrupt service routine (ISR): A module of code that is executed in response to a hardware or software interrupt. interrupt vector pointer (IPTR) bits: A 5-bit field that identifies the 2K page where the interrupt vectors currently reside in the system. The IPTR lets you remap the interrupt vectors to RAM for boot-loaded operations. At reset, IPTR = 0. These bits are stored in the processor mode status register (PMST). INTM: See interrupt mode (INTM) bit. IOWSR: See I/O Port Wait-State Register (IOWSR). IPTR: See interrupt vector pointer (IPTR) bits. IREG: See instruction register (IREG). ISR: See interrupt service routine (ISR).

L
latency: The delay between when a condition occurs and when the device reacts to the condition. Also, in a pipeline, the delay between the execution of two instructions that is necessary to ensure that the values used by the second instruction are correct. LSB: least significant bit. The lowest-order bit in a word.

M
maskable interrupts: A hardware interrupt that can be enabled or disabled through software. MCM: See clock mode (MCM) bit. MCS: See microcall stack (MCS). memory map: A map of the addressable memory space accessed by the TMS320C5x processor partitioned according to functionality (memory, registers, etc.).
Glossary
H-15

Glossary

memory-mapped registers: The TMS320C5x processor has 96 registers mapped into page 0 of the data memory space. There are 28 core CPU registers, 17 peripheral registers, 16 input/output (I/O) port registers, and 35 reserved registers. microcall stack (MCS): A single-word stack that temporarily stores the contents of the prefetch counter (PFC) while the PFC addresses data memory with the block move (BLDD/BLPD), multiply-accumulate (MAC/ MACD), and table read/write (TBLR/TBLW) instructions. microprocessor/microcomputer (MP/MC) bit: A 1-bit field that indicates if on-chip ROM is mapped into program address space. When MP/ MC = 0, the on-chip ROM is enabled. When MP/MC = 1, the on-chip ROM is not addressable. At reset, the MP/MC bit is set to the value corresponding to the logic level on the MP/MC pin. The level on the MP/MC pin is sampled at reset only and has no effect until the next reset. This bit is stored in the processor mode status register (PMST). mnemonic: An alphanumeric symbol designed to aid human memory; it commonly represents the operation code of an assembly language instruction name that the assembler translates into machine code. MP/MC: See microprocessor/microcomputer (MP/MC) bit. MSB: most significant bit. The highest-order bit in a word. MULT: See multiplier (MULT). multiplier (MULT): A 16-by-16-bit multiplier that generates a 32-bit product. The multiplier executes multiple operations in a single machine cycle and operates using either signed or unsigned 2s-complement arithmetic. The operand for the multiplier is specified by the value in temporary register 0 (TREG0). The result of the multiplier is stored in the product register (PREG).

N
nested interrupt: A higher-priority interrupt that must be serviced before completion of the current interrupt service routine (ISR). An executing ISR can set the interrupt mask register (IMR) bits to prevent being suspended by another interrupt. NDX: See enable extra index register (NDX) bit. nonmaskable interrupt: An interrupt that can be neither masked by the interrupt mask register (IMR) nor disabled by the INTM bit of status register ST0.
H-16

Glossary

O
off-chip: on-chip: A device external to the TMS320C5x device. An element or module of the TMS320C5x device.

opcode: operation code. In most cases, the first byte of the machine code that describes the type of operation and combination of operands to the central processing unit (CPU). operand: The part of an instruction that designates where the central processing unit (CPU) will fetch or store data. The operand consists of the arguments, or parameters, of an assembly language instruction, assembler directive, or macro directive. OV: See overflow (OV) bit. overflow: A condition in which the result of an arithmetic operation exceeds the capacity of the register used to hold that result. overflow (OV) bit: A 1-bit flag that indicates an arithmetic operation overflow in the arithmetic logic unit (ALU). At reset, OV = 0.This bit is stored in status register 0 (ST0). overflow mode (OVM) bit: A 1-bit field that determines if an overflow in the arithmetic logic unit (ALU) will wrap around or saturate. This bit is stored in status register 0 (ST0). OVLY: See RAM overlay (OVLY) bit. OVM: See overflow mode (OVM) bit.

P
PAER: See block repeat program address end register (PAER). parallel logic unit (PLU): A 16-bit logic unit that executes logic operations from either long immediate operands or the contents of the dynamic bit manipulation register (DBMR) directly upon data locations without affecting the contents of the accumulator (ACC) or product register (PREG). PASR: See block repeat program address start register (PASR). PC: See program counter (PC). PCM: See pulse coded modulation mode (PCM) bit.
Glossary
H-17

Glossary

PDWSR: See program/data wait-state register (PDWSR). PFC: See prefetch counter (PFC). pipelining: A design technique for reducing the effective propagation delay per instruction operation by partitioning the operation into a series of four independent stages, each of which performs a portion of the operation. PLU: See parallel logic unit (PLU). PM: See product shift mode (PM) bits. PMST: See processor mode status register (PMST). pop: Action of removing a word from a stack.

POSTSCALER: postscaling shifter. A 0- to 7-bit left barrel shifter used to postscale data coming out of the accumulator (ACC). PRD: See timer period register (PRD). prefetch counter (PFC): A 16-bit register that prefetches program instructions. The PFC contains the address of the instruction currently being prefetched and is updated when a new prefetch is initiated. PREG: See product register (PREG). PRESCALER: prescaling shifter. A 0- to 16-bit left barrel shifter used to prescale data coming into the arithmetic logic unit (ALU). This shifter is also used as a 0- to 16-bit right barrel shifter of the accumulator (ACC). The shift count is specified by a constant in the instruction or by the value in temporary register 1 (TREG1). processor mode status register (PMST): A 16-bit memory-mapped register that contains status and control bits. product register (PREG): A 32-bit register that holds the output from the multiplier. The high and low words of the PREG can be accessed individually. See also multiplier (MULT). product shift mode (PM) bits: A 2-bit field that defines the product shifter (P-SCALER) mode. These two bits determine the shift value (0-, 1-, 4-bit left shifter, 6-bit right shifter) for the output of the product register (PREG).These bits are stored in status register 1 (ST1).
H-18

Glossary

program/data wait-state register (PDWSR): (For the TMS320C50, C51, and C53) a 16-bit memory-mapped register that specifies the number of wait states for the program and data space. The higher byte of PDWSR specifies the data space wait states and the lower byte specifies the program space wait states. At reset, PDWSR = FFFF. (For the TMS320C52, C56, and C57) a 16-bit memory-mapped register that specifies the number of wait states for the program, data, and input/ output (I/O) space. Bits 02 of PDWSR specify the program space wait states, bits 35 specify the data space wait states, bits 68 specify the I/O space wait states, and bits 915 are reserved. At reset, PDWSR = FFFF. program controller: Logic circuitry that decodes instructions, manages the pipeline, stores the central processing unit (CPU) status, and decodes conditional operations. program counter (PC): A 16-bit register that identifies the current statement in the program. The PC addresses program memory sequentially and always contains the address of the next instruction to be fetched. The PC contents are updated following each instruction decode operation. P-SCALER: Product Shifter. A 0-, 1-, or 4-bit left shifter that removes extra signed bits (gained in the multiply operation) when fixed-point arithmetic is used; or a 6-bit right shifter that scales the products down to avoid overflow in the accumulation process. The shift mode is specified by the product shift mode (PM) bits. PSC: See timer prescaler counter (PSC) bits. pulse coded modulation mode (PCM) bit: A 1-bit field that enables/disables the BSP transmitter. This bit is stored in the BSP control extension register (SPCE). push: Action of placing a word onto a stack.

R
RAM overlay (OVLY) bit: A 1-bit field that determines if on-chip single-access RAM is addressable in data memory space. At reset, OVLY = 0. This bit is stored in the processor mode status register (PMST). receive buffer half received (RH) bit: A 1-bit flag that indicates which half of the receive buffer has been received. At reset, RH = 0. This bit is stored in the BSP control extension register (SPCE).
Glossary
H-19

Glossary

receive ready (RRDY) bit: A 1-bit flag that transitions from 0 to 1 to indicate the data receive shift register (RSR) contents have been copied to the data receive register (DRR) and that data can be read. A receive interrupt (RINT) is generated upon the transition. The RRDY bit can be polled in software in lieu of using serial port interrupts. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC). receiver reset (RRST) bit: A 1-bit flag that resets the serial port receiver. At reset, RRST = 0. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC). receive shift register full (RSRFULL) bit: A 1-bit flag that indicates if the serial port receiver has experienced overrun. This bit is stored in the serial port control register (SPC). register: A group of bits used for temporarily holding data or for controlling or specifying the status of a device. repeat counter register (RPTC): A 16-bit memory-mapped register that controls the repeated execution of a single instruction. reset: A means to bring the central processing unit (CPU) to a known state by setting the registers and control bits to predetermined values and signaling execution to start at a specified address. RH: See receive buffer half received (RH) bit. RINT: See serial port receive interrupt (RINT) bit. RPTC: See repeat counter register (RPTC). RRDY: See receive ready (RRDY) bit. RRST: See receiver reset (RRST) bit. RSR: See data receive shift register (RSR). RSRFULL: See receive shift register full (RSRFULL) bit.

S
SAM: See shared-access mode (SAM). SARAM: See single-access RAM (SARAM). scratch-pad RAM: Block 2 (B2) on data memory page 0 in local data space (32 words) of DARAM. Scratch-pad RAM supports dual-access operations and can be addressed via any data memory addressing mode.
H-20

Glossary

serial port control register (SPC): A 16-bit memory-mapped register that contains status and control bits for the serial port interface. The SPC is identical to the time-division multiplexed serial port control register (TSPC), except that bit 0 is reserved for the TDM bit. serial port interface: An on-chip full-duplex serial port interface that provides direct serial communication to serial devices with a minimum of external hardware, such as codecs and serial analog-to-digital (A/D) converters. Status and control of the serial port is specified in the serial port control register (SPC). serial port receive interrupt (RINT) bit: A 1-bit flag that indicates the data receive shift register (RSR) contents have been copied to the data receive register (DRR). This bit is stored in the interrupt flag register (IFR). serial port transmit interrupt (XINT) bit: A 1-bit flag that indicates the the data transmit register (DXR) contents has been copied to the data transmit shift register (XSR). This bit is stored in the interrupt flag register (IFR). shared-access mode (SAM): The mode that allows both the TMS320C57 and the host to access HPI memory. In this mode, asynchronous host accesses are synchronized internally and, in case of conflict, the host has access priority and the C57 waits one cycle. shared-access mode (SMOD) bit: A 1-bit field that enables/disables the shared access mode (SAM). This bit is stored in the HPI control register (HPIC). See also shared-access mode (SAM) and host-only mode (HOM). shifter: A unit that shifts bits in a word to the left or to the right. See also P-SCALER. sign-extension: The process of filling the high-order bits of a number with the sign bit, when loading a 16-bit number into a 32-bit field. sign-extension mode (SXM) bit: A 1-bit field that enables/disables sign extension of an arithmetic operation. This bit is stored in status register 1 (ST1). single-access RAM (SARAM): Memory space that only can be read from or written to in a single clock cycle. SMOD: See shared-access mode (SMOD) bit. Soft bit: A 1-bit field used in conjunction with the Free bit to determine the state of the serial port clock when a breakpoint is encountered in the highlevel language debugger. At reset, Soft = 0. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC).
Glossary
H-21

Glossary

software interrupt: An interrupt caused by the execution of an INTR, NMI, or TRAP instruction. SPC: See serial port control register (SPC). SPCE: See BSP control extension register (SPCE). stack: An 8-level-deep by 16-bit hardware stack used as a last-in, first-out memory for temporary variable storage; used during interrupt service routines (ISR) and calls to store the current program status. The area occupied by the stack is determined by the stack pointer and the application program. status register: A 16-bit register that contains status and control bits. SXM: See sign-extension mode (SXM) bit.

T
TADD: See TDM address (TADD). TC: See test/control (TC) bit. TCLK: See TDM clock (TCLK). TCR: See timer control register (TCR). TCSR: See TDM channel select register (TCSR). TDAT: See TDM data (TDAT). TDDR: See timer divide-down register (TDDR) bits. TDM: See time-division multiplexed (TDM) bit. TDM address (TADD): A single, bi-directional address line that identifies which devices on the four-wire serial bus should read in the data on the TDM data (TDAT) line. TDM channel select register (TCSR): A 16-bit memory-mapped register that specifies in which of the eight time slots (channels) a device on the four-wire serial bus is to transmit. A 1 in any one or more of bits 07 of the TCSR sets the device transmitter active during the corresponding time slot. Bits 815 are reserved. TDM clock (TCLK): A single, bi-directional clock line for TDM operation. The TDM receive clock (TCLKR) and TDM transmit clock (TCLKX) pins are externally connected to form the TCLK line.
H-22

Glossary

TDM data (TDAT): A single, bi-directional line from which all TDM data is carried. The TDM serial data receive (TDR) and TDM serial data transmit (TDX) pins are externally connected to form the TDAT line. TDM data receive register (TRCV): A 16-bit memory-mapped register that holds serial data copied from the TDM receive shift register (TRSR). When multiprocessing is enabled (TDM = 1), the TRCV is no longer available for software access as a memory-mapped register. See also TDM data receive shift register (TRSR). TDM data receive shift register (TRSR): A 16-bit register that holds serial data received from the TDM data (TDAT) line. See also TDM data receive register (TRCV). TDM data transmit register (TDXR): A 16-bit memory-mapped register that holds serial data to be copied to the data transmit shift register (XSR). When multiprocessing is enabled (TDM = 1), the TDXR is no longer available for software access as a memory-mapped register. See also data transmit shift register (XSR). TDM receive address register (TRAD): A 16-bit memory-mapped register that contains various information regarding the status of the TDM address (TADD) line and verifies the relationship between instruction cycles and TDM port timing. TDM receive interrupt (TRNT) bit: A 1-bit flag that indicates the TDM data receive shift register (TRSR) contents have been copied to the TDM data receive register (TRCV). This bit is stored in the interrupt flag register (IFR). TDM receive/transmit address register (TRTA): A 16-bit memorymapped register that specifies to which device(s) on the four-wire serial bus a given device can transmit. The lower byte of the TRTA specifies the receive address (RA) of the device and the higher byte specifies the transmit address (TA). The address is sent over the TDM address (TADD) line. TDM serial port control register (TSPC): A 16-bit memory-mapped register that contains status and control bits for the TDM serial port interface. The TSPC is identical to the serial port interface control register (SPC), except for the TDM bit 0. TDM transmit interrupt (TXNT) bit: A 1-bit flag that indicates the TDM data transmit register (TDXR) contents have been copied to the data transmit shift register (XSR). This bit is stored in the interrupt flag register (IFR). TDXR: See TDM data transmit register (TDXR).
Glossary
H-23

Glossary

temporary register: A 16-bit register that holds a temporary data value. See alsoTREG0, TREG1, and TREG2. test/control (TC) bit: A 1-bit flag that stores the results of the arithmetic logic unit (ALU) or parallel logic unit (PLU) test bit operations. The TC bit is affected by the APL, BIT, BITT, CMPR, CPL, LST #1, NORM, OPL, and XPL instructions. The status of the TC bit influences the execution of the conditional branch, call, and return instructions. This bit is stored in status register 1 (ST1). TIM: See timer counter register (TIM).

time-division multiplexed (TDM) bit: A 1-bit field that enables/disables the TDM serial port. This bit is stored in the TDM serial port control register (TSPC). time-division multiplexing (TDM): The process by which a single serial bus is shared by up to eight TMS320C5x devices with each device taking turns to communicate on the bus. There are a total of eight time slots (channels) available. During a time slot, a given device may talk to any combination of devices on the bus. timer control register (TCR): A 16-bit memory-mapped register that contains status and control bits for the on-chip timer. timer counter register (TIM): A 16-bit memory-mapped register that specifies the current count for the on-chip timer. The TIM is decremented once after each timer prescaler counter (PSC) decrement past 0. When the TIM is decremented past 0 or the timer is reset, the TIM is loaded with the contents of the timer period register (PRD) and an internal timer interrupt (TINT) is generated. timer divide-down register (TDDR) bits: A 4-bit field that specifies the timer divide-down ratio (period) for the on-chip timer. When the timer prescaler counter (PSC) is decremented past 0, the PSC is loaded with the contents of the TDDR. At reset, TDDR = 0000. These bits are stored in the timer control register (TCR). timer interrupt (TINT) bit: A 1-bit flag that indicates the timer counter register (TIM) has decremented past 0. This bit is stored in the interrupt flag register (IFR). timer period register (PRD): A 16-bit memory-mapped register that specifies the period for the on-chip timer. When the timer counter register (TIM) is decremented past 0, the TIM is loaded with the contents of the PRD.
H-24

Glossary

timer prescaler counter (PSC) bits: A 4-bit field that specifies the count for the on-chip timer. When the PSC is decremented past 0 or the timer is reset, the PSC is loaded with the contents of the timer divide-down register (TDDR) and the timer counter register (TIM) is decremented. These bits are stored in the timer control register (TCR). timer reload (TRB) bit: A 1-bit flag that resets the on-chip timer. When TRB = 1, the timer counter register (TIM) is loaded with the value in the timer period register (PRD) and the timer prescaler counter (PSC) is loaded with the value of the timer divide-down register (TDDR) bits. This bit is stored in the timer control register (TCR). timer stop status (TSS) bit: A 1-bit flag that stops and restarts the on-chip timer. At reset, TSS = 0 and the timer immediately starts timing. This bit is stored in the timer control register (TCR). TINT: See timer interrupt (TINT) bit. TRAD: See TDM receive address register (TRAD). transmit buffer half transmitted (XH) bit: A 1-bit flag that indicates which half of transmit buffer transmitted. The XH bit can be read when an XINT interrupt occurs (interrupt program or IFR polling). At reset, XH = 0. This bit is stored in the BSP control extension register (SPCE). transmit mode bit (TXM) bit: A 1-bit field that specifies the source of the frame synchronization transmit (FSX) pulse. At reset, TXM = 0. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC). transmit ready (XRDY) bit: A 1-bit flag that transitions from 0 to 1 to indicate the data transmit register (DXR) contents have been copied to the data transmit shift register (XSR) and that data is ready to be loaded with a new data word. A transmit interrupt (XINT) is generated upon the transition. The XRDY bit can be polled in software in lieu of using serial port interrupts. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC). transmit shift register empty (XSREMPTY) bit: A 1-bit flag that indicates if the serial port transmitter has experienced underflow. This bit is stored in the serial port control register (SPC). transmitter reset (XRST) bit: A 1-bit flag that resets the serial port transmitter. At reset, XRST = 0. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC). TRB: See timer reload (TRB) bit.
Glossary
H-25

Glossary

TRCV: See TDM data receive register (TRCV). TREG0: temporary register 0. A 16-bit memory-mapped register that holds an operand for the multiplier. See also multiplier (MULT). TREG1: temporary register 1. A 5-bit memory-mapped register that holds a dynamic prescaling shift count for data inputs to the arithmetic logic unit (ALU). See also PRESCALER. TREG2: temporary register 2. A 4-bit memory-mapped register that holds a dynamic bit pointer for the BITT instruction. TRM: See enable multiple TREGs (TRM) bit. TRNT: See TDM receive interrupt (TRNT) bit. TRSR: See TDM data receive shift register (TRSR). TRTA: See TDM receive/transmit address register (TRTA). TSPC: See TDM serial port control register (TSPC). TSS: See timer stop status (TSS) bit. TXM: See transmit mode (TXM) bit. TXNT: See TDM transmit interrupt (TXNT) bit.

W
wait state: A period of time that the CPU must wait for external program, data, or I/O memory to respond when reading from or writing to that external memory. The CPU waits one extra cycle (one CLKOUT1 cycle) for every wait state. wait-state control register (CWSR): A 5-bit memory-mapped register that controls the mapping of the program/data wait-state register (PDWSR), the input/output port wait-state register (IOWSR), and the number of wait states. At reset, CWSR = 011112. wait-state generator: A program that can be modified to generate a limited number of wait states for a given off-chip memory space (lower program, upper program, data, or I/O). Wait states are set in the wait-state control register (CWSR). warm boot: The process by which the processor transfers control to the entry address of a previously-loaded program. word: A word, as defined in this document, consists of a sequence of 16 adjacent bits (two bytes).
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Glossary

X
XF: See external flag (XF) pin status bit. XH: See transmit buffer half transmitted (XH) bit. XINT: See serial port transmit interrupt (XINT) bit. XRDY: See transmit ready (XRDY) bit. XRST: See transmitter reset (XRST) bit. XSR: See data transmit shift register (XSR). XSREMPTY: See transmit shift register empty (XSREMPTY) bit.

Z
zero fill: A method of filling the low- or high-order bits with zeros when a shift occurs.

Glossary

H-27

Summary of Updates in This Document

Appendix IA Appendix

Summary of Updates in This Document

This appendix provides a summary of the updates in this version of the document. Updates within paragraphs appear in a bold typeface.

Page:
33

Change or Add:
In the bottom half of Figure 31, the auxiliary register file MUX output now connects with the trailing wire bus found on the data bus.

Figure 31. Block Diagram of C5x DSP Central Processing Unit (CPU)
DATA BUS 7 LSB from IREG 3 ST0 [ARP] AR0 AR1 AR2 AR3 3 3 AR4 AR5 AR6 AR7 CBCR(8) CBSR1 CBSR2 CBER1 MUX I/O Ports PA0 CBER2 INDX ARCR 32 32 PRESCALER SFR(016) 32 Emulation DRB PRESCALER SFL(016) MULTIPLIER PREG(32) 32 MUX PSCALER (6,0,1,4) PLU TREG0 MUX Timer 9 ST0 [DP] MUX DBMR

Buffered Serial Port

Host Port Interface

MUX ARAU PA15 32 Data/Program MUX SARAM Data/Program DARAM B0 MUX Data DARAM B2 B1 MUX MUX POSTSCALER (07) ST1 [C] 32 PROGRAM BUS DATA BUS ALU(32) 32 MUX 32

ACCH

ACCL 32

ACCB(32)

Notes: All registers and data lines are 16-bits wide unless otherwise specified. Not available on all devices.

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Summary of Updates in This Document

Page:
411

Change or Add:
In Table 45, changed the reset values for the ARP bit and the OVM bit so both have a reset value of X. In other words, there is no reset value for the ARP bit and the OVM bit.

Table 45.
Bit 1513 Name ARP

Status Register 0 (ST0) Bit Summary

Reset value X

Function
Auxiliary register pointer. These bits select the auxiliary register (AR) to be used in indirect addressing. When the ARP is loaded, the previous ARP value is copied to the auxiliary register buffer (ARB) in ST1. The ARP can be modified by memory-reference instructions when you use indirect addressing, and by the MAR or LST #0 instruction. When an LST #1 instruction is executed, the ARP is loaded with the same value as the ARB. Overflow mode bit. This bit enables/disables the accumulator overflow saturation mode in the arithmetic logic unit (ALU). The OVM bit can be modified by the LST #0 instruction. OVM = 0 Disabled. An overflowed result is loaded into the accumulator without modification. The OVM bit can be cleared by the CLRC OVM instruction. Overflow saturation mode. An overflowed result is loaded into the accumulator with either the most positive (00 7FFF FFFFh) or the most negative value (FF 8000 0000h). The OVM bit can be set by the SETC OVM instruction.

11

OVM

OVM = 1

412

In Table 45, changed the reset value for the DP bit so it has a reset value of X. In other words, there is no reset value for the DP bit.

Table 45.
Bit 80 Name DP

Status Register 0 (ST0) Bit Summary (Continued)

Reset value X

Function
Data memory page pointer bits. These bits specify the address of the current data memory page. The DP bits are concatenated with the 7 LSBs of an instruction word to form a direct memory address of 16 bits. The DP bits can be modified by the LST #0 or LDP instruction.

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Summary of Updates in This Document

Page:
413

Change or Add:
In Table 46, changed the reset value for the ARB bit and the TC bit so they have no reset value.

Table 46. Status Register 1 (ST1) Bit Summary

Bit 1513 Name ARB Reset value X

Function
Auxiliary register buffer. This 3-bit field holds the previous value contained in the auxiliary register pointer (ARP) in ST0. Whenever the ARP is loaded, the previous ARP value is copied to the ARB, except when using the LST #0 instruction. When the ARB is loaded using the LST #1 instruction, the same value is also copied to the ARP. This is useful when restoring context (when not using the automatic context save) in a subroutine that modifies the current ARP. Test/control flag bit. This 1-bit flag stores the results of the arithmetic logic unit (ALU) or parallel logic unit (PLU) test bit operations. The TC bit is affected by the APL, BIT, BITT, CMPR, CPL, NORM, OPL, and XPL instructions. The status of the TC bit determines if the conditional branch, call, and return instructions execute. The TC bit can be modified by the LST #1 instruction.

11

TC

Summary of Updates in This Document

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Summary of Updates in This Document

Page:
52

Change or Add:
In Figure 51, changed the page 0 length to 128-WORD PAGE.

Figure 51. Direct Addressing

ST0 DP (9) IREG (16) 7 LSBs
6 0

9
15

16-bit data memory address

DP

dma

PAGE 511 PAGE 510

512 DATA PAGES

PAGE 3 PAGE 2

DAB

PAGE 1 PAGE 0

128-WORD PAGE

(MEMORYMAPPED REGISTERS AND DARAM B2)

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Summary of Updates in This Document

Page:
522

Change or Add:
In Example 513, added two new lines at the beginning of the example.

Example 513. Circular Addressing

mar ldp splk splk splk lar lacc lar lacc lar lacc lar lacc lar lacc lar lacc lar adrk lar adrk *,ar6 #,0 #200h,CBSR1 #203h,CBER1 #0Eh,CBCR ar6,#200h * ar6,#203h * ar6,#200h *+ ar6,#203h *+ ar6,#200h * ar6,#203h * ar6,#202h 2 ar6,#203h 2 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Circular buffer start register Circular buffer end register Enable AR6 pointing to buffer 1 Case 1 AR6 = 200h Case 2 AR6 = 203h Case 3 AR6 = 201h Case 4 AR6 = 200h Case 5 AR6 = 1FFh Case 6 AR6 = 200h Case 7 AR6 = 204h Case 8 AR6 = 200h

Summary of Updates in This Document

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Summary of Updates in This Document

Page:
632 Operands 644 Operands 683 Operands 685

Change or Add:
Changed the second operand for the ADD instruction. 0 shift 16 (defaults to 0) Changed the fourth operand for the AND instruction. 0 shift 16 Changed the operand for the BSAR instruction. 1 shift 16 Changed the description for the CALAD instruction.

Description

The current program counter (PC) is incremented by 3 and pushed onto the top of the stack (TOS). Then, the one 2-word instruction or two 1-word instructions following the CALAD instruction are fetched from program memory and executed before the call is executed. Then, the contents of the accumulator low byte (ACCL) are loaded into the PC. Execution continues at this address. The CALAD instruction is used to perform computed subroutine calls. CALAD is a branch and call instruction (see Table 68).

687

Changed the description for the CALLD instruction. Description The current program counter (PC) is incremented by 4 and pushed onto the top of the stack (TOS). Then, the one 2-word instruction or two 1-word instructions following the CALLD instruction are fetched from program memory and executed before the call is executed. Then, the program memory address (pma) is loaded into the PC. Execution continues at this address. The current auxiliary register (AR) and auxiliary register pointer (ARP) are modified as specified. The pma can be either a symbolic or numeric address. CALLD is a branch and call instruction (see Table 68).

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Summary of Updates in This Document

Page:
691

Change or Add:
Changed the description for the CCD instruction.

Description

If the specified conditions are met, the current program counter (PC) is incremented by 4 and pushed onto the top of the stack (TOS). Then, the one 2-word instruction or two 1-word instructions following the CCD instruction are fetched from program memory and executed before the call is executed. Then, the program memory address (pma) is loaded into the PC. Execution continues at this address. The pma can be either a symbolic or numeric address. Not all combinations of the conditions are meaningful. In addition, the NTC, TC, and BIO conditions are mutually exclusive. If the specified conditions are not met, control is passed to the next instruction. The CCD functions in the same manner as the CALLD instruction (page 687) if all conditions are true. CCD is a branch and call instruction (see Table 68).

6103 Opcode

Changed the opcode for the CRLT instruction to reflect the new values for bits 2, 1, and 0.
15 1 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 0 0 0

6115 Operands 6127

Changed the third operand for the LACC instruction. 0 shift 16 (defaults to 0) Changed the table Cycles for a Single Instruction (short immediate addressing).
Cycles for a Single Instruction (short immediate addressing) Operand ROM 2 DARAM 2 SARAM 2 External Memory 2+pcode

6129

Changed the table Cycles for a Single Instruction (short immediate addressing).
Cycles for a Single Instruction (short immediate addressing) Operand ROM 2 DARAM 2 SARAM 2 External Memory 2+pcode

6188 Operands

Changed the fourth operand for the OR instruction. 0 shift 16

Summary of Updates in This Document
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Summary of Updates in This Document

Page:
6261 Operands 6278 6282 Operands 86 811

Change or Add:
Changed the second operand for the SUB instruction. 0 shift 16 (defaults to 0) Changed the data memory address in Example 1 from 1905h to 1005h. Changed the fourth operand for the XOR instruction. 0 shift 16 In Figure 86, changed the word Off-chip to Reserved on the Program memory map for the range from 0040h to 8000h. In Table 86, changed the values in the Off-Chip column for the first and fifth rows.

Table 86. C57S Program Memory Configuration

832

910

Bit values RAM 0 0 CNF 0 1 MP/MC 0 0 ROM (2K-words) 000007FF 000007FF SARAM (6K-words) Off-chip Off-chip DARAM B0 (512-words) Off-chip Off-Chip 8000FFFF FE00FFFF 8000FDFF

Changed the last sentence in the fourth bullet.

- 32K words of global data memory are enabled initially in data spaces

8000h to FFFFh. After the code transfer is complete, the global memory is disabled before control is transferred to the destination address in program memory.

In Table 94, changed the sentences after Soft=0 and Soft=1. Also, add a sentence to the TSS register.

Table 94. Timer Control Register (TCR) Bit Summary

Bit 11 Name Soft Reset value 0 Function This bit is used in conjunction with the Free bit to determine the state of the timer when a halt is encountered. When the Free bit is cleared, the Soft bit selects the emulation mode. Soft = 0 Soft = 1 4 TSS 0 The timer stops immediately. The timer stops after decrementing to zero.

Timer stop status bit. This bit stops or starts the on-chip timer. At reset, the TSS bit is cleared and the timer immediately starts timing. Note that due to timer logic implementation, two successive writes of one to the TSS bit are required to properly stop the timer.

I-8

Summary of Updates in This Document

Page:
911

Change or Add:
Deleted the last sentence in the Notes section and replace it with the sentence indicated.

The current value in the timer can be read by reading the TIM; the PSC can be read by reading the TCR. Because it takes two instructions to read both registers, there may be a change between the two reads as the counter decrements. Therefore, when making precise timing measurements, it may be more accurate to stop the timer to read these two values. Due to timer logic implementation, two instructions are also required to properly stop the timer; therefore, two successive writes of one to the TSS bit should be made when the timer must be stopped. 962 Changed the XINT and RINT labels found in the lower right portion of Figure 935.

Figure 935. ABU Block Diagram

BCLKX BFSX

BDXR

SPCE WXINT BXNT

BDX BDR

BXSR BRSR

Serial Port Control Logic WRINT

Interrupt Control BRNT

Interrupt Logic

BCLKR BFSR BDRR BSPC

Serial Port Interface Module

Summary of Updates in This Document

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Summary of Updates in This Document

Page:
963

Change or Add:
Changed the last sentence in the first paragraph. The internal C5X memory used for autobuffering consists of a 2K-word block of single-access memory that can be configured as data, program, or both (as with other single-access memory blocks). This memory can also be used by the CPU as general purpose storage, however, this is the only memory block in which autobuffering can occur. Since the BSP is implemented on several different TMS320 devices, the actual base address of the ABU memory may not be the same in all cases. The 2K-word block of BSP memory is located at 800hFFFh in data memory or at 8000h87FFh in program memory as specified by the RAM and OVLY control bits.

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Summary of Updates in This Document

Page:
A4

Change or Add:
In Figure A2, changed the signal name on pin 80 to R/W.

Figure A-2. Pin/Signal Assignments for the C51, C52, C53S, and LC56 in 100-Pin TQFP
CLKOUT1 XF HOLDA TDO VDDC X1 X2/CLKIN CLKMD2 VSSI VSSI

VDDC VDDI VDDI

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

EMU0 EMU1/OFF VSSC TOUT * * * * RS READY HOLD BIO TRST VSSI VSSI MP/MC D15 D14 D13 D12 D11 D10 D9 D8 VDDD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DS VSSC

BR STRB R/W

PS IS

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

(PZ package) (Top view)

WE RD VDDA A15 A14 A13 A12 A11 A10 CLKMD1 VSSA VSSA TDI VDDI A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSSA

D7 D6 D5 D4 D3 D2 D1 D0 TMS VDDD TCK VSSD VSSD

VSSD VSSD

Note:

These pins are reserved for specific devices (see Table A6 on page A-12).

Summary of Updates in This Document

VDDA

INT1

INT2 INT3 INT4 NMI

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Summary of Updates in This Document

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A6

Change or Add:
In Figure A3, changed the signal name on pin 108 to X2/CLKIN.

Figure A3. Pin/Signal Assignments for the LC57 in 128-Pin TQFP

VDDI CKLOUT1 XF HOLDA BDX DX X2/CLKIN FSX HD5 CLKMD2 HD4 VSSI CLKMD3

VDDC VDDI

VDDC X1

DS HD2 VSSC

128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97

VSSC
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

STRB

HD7 BFSX HD6

VSSI TDO

BR HD3

R/W

PS IS

HINT EMU0 EMU1/OFF VSSC VSSC TOUT BCLKX CLKX VDDC BFSR BCLKR RS READY HOLD BIO VDDC VDDC IAQ TRST VSSI VSSI MP/MC D15 D14 D13 D12 D11 D10 D9 D8 VDDD VDDD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

(PBK package) (Top view)

WE HD1 RD HD0 HRDY VDDA A15 A14 A13 A12 A11 A10 CLKMD1 VSSA VSSA TDI HDS1 HDS2 VDDI VDDI A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSSA HCS

VSSD VSSD D7 D6 D5 D4 D3 D2 D1 D0 HCNTL0 TMS

HCNTL1 VDDD

HR/W INT1

VDDD TCK

INT3 INT4 HBIL

NMI DR

BDR FSR CLKR VDDA VDDA

VSSD VSSD

I-12

INT2

HAS

Summary of Updates in This Document

Page:
A7

Change or Add:
In Table A3, changed the signal name on pin 108 to X2/CLKIN and reorder the signal names.

Table A3. Signal/Pin Assignments for the LC57 in 128-Pin TQFP

Signal A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BCLKR BCLKX BDR BDX BFSR BFSX BIO BR CLKMD1 CLKMD2 Pin 67 68 69 70 71 72 73 74 75 76 85 86 87 88 89 90 11 7 59 122 10 119 15 106 84 115 Signal CLKMD3 CLKOUT1 CLKR CLKX D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DR DS DX EMU0 EMU1/OFF FSR Pin 107 125 61 8 42 41 40 39 38 37 36 35 30 29 28 27 26 25 24 23 58 100 121 2 3 60 Signal FSX HAS HBIL HCNTL0 HCNTL1 HCS HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HDS1 HDS2 HINT HOLD HOLDA HRDY HR/W IAQ INT1 INT2 INT3 INT4 Pin 117 64 56 43 45 65 93 95 99 105 114 116 118 120 80 79 1 14 123 92 51 18 52 53 54 55 Signal IS MP/MC NMI PS RD READY RS R/W STRB TCK TDI TDO TMS TOUT TRST VDDC VDDA VDDA VDDA VDDC VDDC VDDC VDDC VDDD VDDD VDDD Pin 101 22 57 102 94 13 12 103 104 48 81 111 44 6 19 9 91 63 62 16 17 110 128 31 32 46 Signal VDDD VDDI VDDI VDDI VDDI VSSA VSSA VSSA VSSC VSSC VSSC VSSC VSSD VSSD VSSD VSSD VSSI VSSI VSSI VSSI WE X1 X2/CLKIN XF Pin 47 77 78 126 127 66 82 83 4 5 97 98 33 34 49 50 20 21 112 113 96 109 108 124

Summary of Updates in This Document

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A10

Change or Add:
In Figure A5, corrected the signal names for pins 116, 2845, 5771, and 78141; changed the signal name on pin 122 to X2/CLKIN.

Figure A5. Pin/Signal Assignments for the C57S in 144-Pin TQFP

HINT EMU0 NC EMU1/OFF VSSC VSSC TOUT BCLKX CLKX VDDC BFSR BCLKR RS READY HOLD NC BIO VDDC VDDC IAQ TRST VSSI VSSI MP/MC D15 D14 D13 NC D12 D11 D10 D9 NC D8 VDDD VDDD

113 112 111 110 109

121 120 119 118

144 143 142

141 140 139 138

137 136 135 134

133 132 131 130

129 128 127 126

125 124 123 122

117 116 115 114

VDDC VDDI VDDI NC CKLOUT1 XF HOLDA BDX DX HD7 BFSX HD6 FSX HD5 CLKMD2 HD4 VSSI VSSI TDO NC VDDC X1 X2/CLKIN CLKMD3 NC BR HD3 NC STRB R/W PS IS DS HD2 VSSC VSSC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

(PGE package) (Top view)

108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 61 62 63 64 65 66 67 68 69 70 71 72

WE HD1 RD HD0 HRDY VDDA A15 NC A14 A13 A12 NC A11 A10 CLKMD1 VSSA VSSA TDI HDS1 HDS2 VDDI VDDI A9 A8 A7 NC A6 A5 A4 A3 NC A2 A1 A0 VSSA HCS

49 50 51 52

53 54 55 56

Note:

NC

These pins are not connected (reserved).

I-14

VSSD V SSD D7 D6 NC D5 D4 D3 NC D2 D1 D0 HCNTL0 TMS HCNTL1 VDDD VDDD TCK VSSD VSSD NC HR/W INT1 INT2 INT3 INT4 HBIL NMI DR BDR FSR CLKR V DDA V DDA HAS NC

57 58 59 60

Summary of Updates in This Document

Page:
A11

Change or Add:
In Table A5, corrected the signal names for pins 116, 2845, 5771, and 78141; changed the signal name on pin 122 to X2/CLKIN; reordered the signal names.

Table A5. Signal/Pin Assignments for the C57S in 144-Pin TQFP

Signal A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BCLKR BCLKX BDR BDX BFSR BFSX BIO BR CLKMD1 CLKMD2 CLKMD3 CLKOUT1 CLKR Pin 75 76 77 79 80 81 82 84 85 86 95 96 98 99 100 102 12 8 66 137 11 134 17 119 94 130 121 140 68 Signal CLKX D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DR DS DX EMU0 EMU1/OFF FSR FSX HAS HBIL HCNTL0 HCNTL1 HCS Pin 9 48 47 46 44 43 42 40 39 34 32 31 30 29 27 26 25 65 112 136 2 4 67 132 71 63 49 51 73 Signal HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HDS1 HDS2 HINT HOLD HOLDA HRDY HR/W IAQ INT1 INT2 INT3 INT4 IS MP/MC NMI PS RD READY RS R/W STRB Pin 105 107 111 118 129 131 133 135 90 89 1 15 138 104 58 20 59 60 61 62 113 24 64 114 106 14 13 115 116 Signal TCK TDI TDO TMS TOUT TRST VDDA VDDA VDDA VDDC VDDC VDDC VDDC VDDC VDDD VDDD VDDD VDDD VDDI VDDI VDDI VDDI VSSA VSSA VSSA VSSC VSSC VSSC VSSC Pin 54 91 126 50 7 21 69 70 103 10 18 19 124 144 35 36 52 53 87 88 142 143 74 92 93 5 6 109 110 Signal VSSD VSSD VSSD VSSD VSSI VSSI VSSI VSSI WE X1 X2/CLKIN XF { { { { { { { { { { { { { { { { Pin 37 38 55 56 22 23 127 128 108 123 122 139 3 16 28 33 41 45 57 72 78 83 97 101 117 120 125 141

These pins are not connected (reserved).

Summary of Updates in This Document

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Summary of Updates in This Document

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D2

Change or Add:
In Figure D1, changed the PD pin 5 from +5V to VDD.

Figure D1. Header Signals and Header Dimensions

TMS TDI PD (VDD) TDO TCK_RET TCK EMU0
1 3 5 7 9 11 13 2 4 6 8 10 12 14

TRST GND No pin (key) GND GND GND EMU1

Header Dimensions: Pin-to-pin spacing: 0.100 in. (X,Y) Pin width: 0.025 in. square post Pin length: 0.235 in., nominal

In Table D1, changed the voltage for pin 5 (the PD pin) from +5V to VDD.

Table D1.

XDS510 Header Signal Description

Pin 5 Signal PD State I Target State Description O Presence detect. Indicates that the emulation cable is connected and that the target is powered up. PD should be tied to VDD in the target system.

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Summary of Updates in This Document

Page:
D5

Change or Add:
In Figure D2, changed the voltages from +5V to VDD.

Figure D2. Emulator Cable Pod Interface

VDD 180 JP1 270

Q 74F175 D Q 33 258 33

TDO (Pin 7)

TMS (Pin 1) TDI (Pin 3)

GND (Pins 4,6,8,10,12)

VDD 10 MHz 10 k 10 k 1034 VDD 180 JP2 270 1004 1034

TCK (Pin 11) TRST (Pin 2)

EMU0 (Pin 13) EMU1 (Pin 14)

TCK_RET (Pin 9) PD (Pin 5)

100 CL 74

NOTE: All devices are 74AS, unless otherwise specified.

Summary of Updates in This Document

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Summary of Updates in This Document

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D7

Change or Add:
In Figure D4, changed the voltages from +5V to VDD.

Figure D4. Target-System Generated Test Clock

Greater than 6 inches VDD C5x EMU0 EMU1 TRST TMS TDI TDO TCK NC 13 14 2 1 3 7 11 9 Emulator header EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND System test clock GND GND GND GND GND 4 6 8 10 12 5 VDD

PD

I-18

Summary of Updates in This Document

D8

In Figure D5, changed the voltages from +5V to VDD.

Figure D5. Multiprocessor Connections

C5x TDO TRST TMS TCK TDI EMU0 EMU1 TDO TMS TRST TCK C5x TDI EMU0 EMU1 VDD VDD Emulator header 13 14 2 1 3 7 11 9 EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND GND GND GND GND GND 4 6 8 10 12 PD 5

Summary of Updates in This Document

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D9

Change or Add:
In Figure D6, changed the voltages from +5V to VDD.

Figure D6. Emulator Connections Without Signal Buffering

Less than 6 inches VDD C5x EMU0 EMU1 TRST TMS TDI TDO TCK 13 14 2 1 3 7 11 9 Emulator header EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND GND GND GND GND GND 4 6 8 10 12 PD 5 VDD

D10

In Figure D7, change the voltages from +5V to VDD.

Figure D7. Buffered Signals

Greater than 6 inches VDD C5x EMU0 EMU1 TRST TMS TDI TDO TCK 13 14 2 1 3 7 11 9 Emulator Header EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND GND GND GND GND GND 4 6 8 10 12 PD 5 VDD

I-20

Index
C2x instruction compatibility C-11 C2x to C5x software compatibility 5-6 C5x applications 1-4 characteristics 1-6 functional block diagram 2-2 IEEE Std. 1149.1 interface configurations key features 1-7 overview 1-5 C5x block diagram, CPU 3-3 ADD instruction description 6-32 summary 6-9 ADDB instruction description 6-36 summary 6-9 2-12 ADDC instruction description 6-37 summary 6-9 address bus pins A-13, H-1 address generation 4-2 address map, data page 0 8-17 address visibility (AVIS) bit H-1 See also AVIS bit addressing modes 5-1, H-1 circular 5-21 to 5-22 dedicated-register 5-17 to 5-18 direct 5-2 to 5-3 immediate 5-14 to 5-16 indirect 5-4 to 5-5 long immediate 5-15 memory-mapped register 5-19 to 5-22 short immediate 5-14 addressing program memory 4-5 ADDS instruction description 6-39 summary 6-9 ADDT instruction description 6-41 summary 6-9 ADRK instruction description 6-43 summary 6-13 AFB H-2 See also auxiliary register file bus (AFB) ALU H-2 See also arithmetic logic unit (ALU)

A
A/D converter H-2 A0A15 pin A-13, H-1 ABS instruction description 6-29 summary 6-9 ABU H-1 See also autobuffering unit (ABU) ACC H-1 See also accumulator (ACC) ACCB H-1 See also accumulator buffer (ACCB) ACCH H-1 See also accumulator high byte (ACCH) ACCL H-1 See also accumulator low byte (ACCL) accumulator (ACC) 3-11 to 3-14, H-1 accumulator buffer (ACCB) 3-11, H-1 accumulator high byte (ACCH) H-1 See also accumulator (ACC) accumulator low byte (ACCL) H-1 See also accumulator (ACC) ADCB instruction description 6-31 summary 6-9

Index-1

AND instruction description 6-44 summary 6-9 ANDB instruction description 6-47 summary 6-9 APAC instruction, description APL instruction description 6-49 summary 6-14 applications 1-4 AR H-2 See also auxiliary register (AR) ARAU H-2 See also auxiliary register arithmetic unit (ARAU) ARB bits 4-13, H-2 architecture 1-5, 2-1 bus structure 2-3 central processing unit (CPU) on-chip memory 2-6 on-chip peripherals 2-8 test/emulation 2-11 6-48

2-4, H-6

ARCR H-2 See also auxiliary register compare register (ARCR) arithmetic logic unit (ALU) ARP bits 4-11, H-2 3-11 to 3-14, H-2

autobuffering transmitter enable (BXE) bit H-2 See also BXE bit autobuffering transmitter halt (HALTX) bit H-2 See also HALTX bit autobuffering unit (ABU) 9-60, H-3 block diagram 9-62 control register 9-63 process 9-65 auxiliary register (AR) 3-21, H-3 auxiliary register arithmetic unit (ARAU) 2-5, 3-17 to 3-20, H-3 See also auxiliary register (AR) auxiliary register buffer (ARB) bits H-3 See also ARB bits auxiliary register compare register (ARCR) 3-19, 3-21, H-3 auxiliary register file bus (AFB) H-3 auxiliary register pointer (ARP) bits H-3 See also ARP bits auxiliary registers 5-4 circular buffer 1 4-7, 5-21 circular buffer 2 4-7, 5-21 AVIS bit 4-8, 4-38, 8-13, 8-14, H-3 AXR H-3 See also BSP address transmit register (AXR)

B
B instruction description 6-52 summary 6-17 BACC instruction description 6-53 summary 6-17 BACCD instruction description 6-54 summary 6-17 BANZ instruction description 6-55 summary 6-17 BANZD instruction description 6-57 summary 6-17 BCLKR pin A-21 BCLKX pin A-21 BCND instruction description 6-59 example 4-19, 4-20 summary 6-17

ARR H-2 See also BSP address receive register (ARR) assembler H-2 assembly language instructions 6-1, H-2 descriptions 6-23 instruction set summary 6-8 instructions not meaningful to repeat 4-27 nonrepeatable instructions 4-29 notations, instruction set descriptions 6-6 repeatable instructions 4-23 to 4-36 symbols and abbreviations instruction set descriptions 6-4 instruction set opcodes 6-2 symbols and notations 6-2 assistance G-3 H-2 H-2 autobuffering receiver enable (BRE) bit See also BRE bit autobuffering receiver halt (HALTR) bit See also HALTR bit Index-2

BCNDD instruction description 6-61 example 4-20 summary 6-17 BD instruction description 6-63 summary 6-17 BDR pin BDX pin BFSR pin BFSX pin BIG bit BIO pin A-21 A-21 A-21 A-21 9-20, A-15, H-12

3-24, 8-22, 9-17, H-3

BIT instruction description 6-64 summary 6-21 bit manipulation 3-11, 3-15 bit-reversed addressing 5-6, 5-12 auxiliary register modifications 5-13 step/bit pattern relationship 5-13 bit-reversed addressing BITT instruction description 6-66 summary 6-21 BKR H-4 See also BSP receive buffer size register (BKR) BKX H-4 See also BSP transmit buffer size register (BKX) BLDD instruction description 6-68 example 8-27 summary 6-20 BLDP instruction description 6-74 example 8-28 summary 6-20 block move address register (BMAR) block moves block repeat 8-26 3-22 H-4 3-21, H-4 3-21, H-4 H-3

block repeat active flag (BRAF) bit See also BRAF bit block repeat function 4-31

block repeat counter register (BRCR)

block repeat program address end register (PAER) 3-21, 4-31, H-4

block repeat program address start register (PASR) 3-21, 4-31, H-4 BLPD instruction description 6-77 example 8-29, 8-30 summary 6-20 BMAR H-4 See also block move address register (BMAR) BOB H-4 See also byte ordering bit (BOB) boot loader 8-32 boot routine selection 8-32 HPI boot mode 8-33 boot mode parallel EPROM boot 8-36 parallel I/O boot 8-37 serial boot 8-34 warm boot 8-38 boot ROM 8-3 boot routine selection 8-32, 8-33 parallel EPROM boot mode 8-36 parallel I/O boot mode 8-37 serial boot mode 8-34 warm boot mode 8-38 BR pin 8-20, 8-23, A-15 BRAF bit 4-9, H-4 branch execution 4-17 BRCR H-4 See also block repeat counter register (BRCR) BRE bit 9-64, H-4 BSAR instruction description 6-83 summary 6-9 BSP H-4 See also buffered serial port (BSP) BSP address receive register (ARR) 3-22, H-4 BSP address transmit register (AXR) 3-22, H-5 BSP control extension register (SPCE) 3-22, H-5 bit summary 9-58, 9-64 BRE bit 9-64, H-2 BXE bit 9-65, H-2 CLKDV bits 9-59, H-14 CLKP bit 9-58, H-7 diagram 9-57, 9-63 FE bit 9-58, H-11 FIG bit 9-58, H-11 FSP bit 9-59, H-11 HALTR bit 9-64, H-2

Index-3

BSP control extension register (SPCE) (continued) HALTX bit 9-64, H-2 PCM bit 9-58, H-19 reset status 4-48 RH bit 9-64, H-19 XH bit 9-65, H-25 BSP control register (BSPC), reset status 4-47 BSP operation system considerations 9-69 BSP receive buffer size register (BKR) 3-22, H-5 BSP transmit buffer size register (BKX) 3-22, H-5 buffered serial port (BSP) 2-10, 3-22, 9-53, H-5 autobuffering control register 9-63 autobuffering process 9-65 autobuffering unit (ABU) 9-60 power-down mode 9-73 registers 3-22 signal descriptions A-21 system considerations 9-69 buffered signals, JTAG D-10 bumpered quad flat-pack (BQFP) package A-1 burst mode (serial port) 9-37, H-5 bus protocol D-3 bus structure 2-3 BXE bit 9-65, H-5 byte ordering bit (BOB) H-5

C
C bit 4-14, H-6 example 3-13 C25 packages C-2 C25 to C5x clocking C-5 C25 to C5x execution times C-8 C25 to C5x pins/signals C-4 C25 to C5x software compatibility 4-42 C2x to C5x migration C-1 cable, target system to emulator D-1 to D-13 CALA instruction description 6-84 summary 6-17 CALAD instruction description 6-85 summary 6-18 CALL instruction description 6-86 summary 6-18 Index-4

CALLD instruction description 6-87 summary 6-18 CALU H-6 See also central arithmetic logic unit (CALU) CAR1 bits 4-7, H-6 CAR2 bits 4-7, H-6 carry (C) bit H-6 See also C bit CBCR H-6 See also circular buffer control register (CBCR) CBER1 H-6 See also circular buffer 1 end register (CBER1) CBER2 H-6 See also circular buffer 2 end register (CBER2) CBSR1 H-6 See also circular buffer 1 start register (CBSR1) CBSR2 H-6 See also circular buffer 2 start register (CBSR2) CC instruction description 6-89 summary 6-18 CCD instruction description 6-91 summary 6-18 CENB1 bit 4-7, H-6 CENB2 bit 4-7, H-6 central arithmetic logic unit (CALU) 2-4, 3-7 to 3-14, H-6 central processing unit (CPU) 2-4, 3-1, H-6 auxiliary register arithmetic unit (ARAU) 2-5, 3-17, H-3 central arithmetic logic unit (CALU) 2-4, 3-7, H-6 functional overview 3-2 memory-mapped registers 2-5, H-16 parallel logic unit (PLU) 2-4, 3-15, H-17 program controller 2-5, H-19 registers 3-21 circular addressing mode 5-21 to 5-22 circular buffer 3-20, 3-22, 5-21 circular buffer 1 auxiliary register (CAR1) bits H-6 See also CAR1 bits circular buffer 1 enable (CENB1) bit H-6 See also CENB1 bit circular buffer 1 end register (CBER1) 3-22, H-6 circular buffer 1 start register (CBSR1) 3-22, H-7

circular buffer 2 auxiliary register (CAR2) bits H-7 See also CAR2 bits circular buffer 2 enable (CENB2) bit H-7 See also CENB2 bit circular buffer 2 end register (CBER2) 3-22, H-7 circular buffer 2 start register (CBSR2) 3-22, H-7 circular buffer control register (CBCR) 3-15, 3-22, 4-6, H-7 bit summary 4-7 CAR1 bits 4-7, H-6 CAR2 bits 4-7, H-7 CENB1 bit 4-7, H-6 CENB2 bit 4-7, H-7 diagram 4-7 reset status 4-46 circular buffer registers 3-22, 5-21 clear control bit 6-93 CLKDV bits 9-59, H-7 CLKIN2 pin A-17 CLKMD1 pin A-17, A-18, A-19 CLKMD2 pin A-17, A-18, A-19 CLKMD3 pin A-17, A-19 CLKOUT1 pin A-17 CLKP bit 9-58, H-7 CLKR pin A-20 CLKR1 pin A-20 CLKR2 pin A-20 CLKX pin A-20 CLKX1 pin A-20 CLKX2 pin A-20 clock generator 2-8, 9-7 PLL options 9-8 standard options 9-7 clock mode (MCM) bit H-7 See also MCM bit clock modes 9-7, 9-8, H-7 clock polarity (CLKP) bit H-7 See also CLKP bit CLRC instruction description 6-93 summary 6-21 CMPL instruction description 6-95 summary 6-10 CMPR instruction description 6-96

summary 6-13 CNF bit 4-13, 8-8, 8-15, 8-32, H-7 conditional branch 4-17 conditional operations 4-17 configuration control (CNF) bit H-7 See also CNF bit contacting Texas Instruments xvi context save/restore H-8 continuous mode (serial port) 9-44, H-8 CPGA package C-2 CPL instruction description 6-98 summary 6-14 CPU H-8 See also central processing unit (CPU) CRGT instruction description 6-101 summary 6-10 CRLT instruction description 6-103 summary 6-10 crystals E-3 current auxiliary register (ARc), changed by auxiliary register arithmetic unit (ARAU) 5-5 CWSR H-8 See also wait-state control register (CWSR)

D
D bit 9-18 D0D15 pin A-13, H-8 DAB H-8 See also direct address bus (DAB) DARAM H-8 See also dual-access RAM (DARAM) data bus 2-3, H-8 data bus pins A-13, H-8 data memory 3-15, H-8 data memory address (dma) H-8 data memory page pointer (DP) bits H-8 See also DP bits data moves. See block moves data receive register (DRR) 3-24, 9-24, H-8 reset status 4-47 data receive shift register (RSR) 3-24, 9-24, H-9 data transmit register (DXR) 3-24, 9-24, H-9 reset status 4-47

Index-5

data transmit shift register (XSR) 3-24, 9-24, H-9 DBMR H-9 See also dynamic bit manipulation register (DBMR) dedicated-register addressing mode 5-17 to 5-18 using BMAR 5-17 using DBMR 5-18 delayed branches 4-19 development tool nomenclature G-6 development tools G-2 device nomenclature G-5 digital loopback mode (DLB) bit H-9 See also DLB bit direct address bus (DAB) H-9 direct addressing mode 5-2 to 5-3 direct memory access (DMA) 8-23, H-9 address ranges 8-24 master/slave configuration 8-23 division 6-267 DLB bit 9-31, 9-32, H-9 DMA H-9 See also direct memory access (DMA) dma H-9 See also data memory address (dma) DMOV instruction 8-27 description 6-105 summary 6-20 DP bits 4-12, H-9 DP register 5-2 to 5-4 DR pin A-20 DR1 pin A-20 DR2 pin A-20 DRB 5-2 DRR H-9 See also data receive register (DRR) DS pin A-14 DSP interrupt (DSPINT) bit H-9 See also DSPINT bit DSPINT bit H-10 dual-access RAM (DARAM) 2-6, 8-2, 8-18, H-10 DX pin A-20 DX1 pin A-20 DX2 pin A-20 DXR H-10 See also data transmit register (DXR) Index-6

dynamic bit manipulation register (DBMR) 3-22, H-10

3-15,

E
EMU0 pin A-24 EMU1/OFF pin A-24 emulator D-1 buffered signals D-10 bus protocol D-3 cable header D-2 cable pod D-4 designing the JTAG cable D-1 header signals D-2 signal buffering D-9 to D-10 signal timings D-6 timing D-11 timings D-6 unbuffered signals D-9 emulator cable pod, interface D-5 enable extra index register (NDX) bit H-10 See also NDX bit enable multiple TREGs (TRM) bit H-10 See also TRM bit EXAMPLE instruction, description 6-24 EXAR instruction description 6-107 summary 6-10 extended-precision arithmetic 3-12 external DMA. See direct memory access (DMA) external flag (XF) pin status bit H-10 See also XF bit external memory interface timings 8-39

F
fast Fourier transform (FFT) H-10 FE bit 9-58, H-10 FFT H-11 See also fast Fourier transform (FFT) FIG bit 9-58, H-11 FO bit 9-31, 9-32, H-11 format (FO) bit H-11 See also FO bit format extension (FE) bit H-11 See also FE bit frame ignore (FIG) bit H-11 See also FIG bit

frame synchronization mode (FSM) bit H-11 See also FSM bit frame synchronization polarity (FSP) bit H-11 See also FSP bit Free bit 9-10, 9-28, 9-37, H-11 FSM bit 9-30, 9-33, H-11 FSP bit 9-59, H-11 FSR pin 8-34, A-20 FSR1 pin A-20 FSR2 pin A-20 FSX pin A-20 FSX1 pin A-20 FSX2 pin A-20 functional overview 3-2

G
general-purpose I/O pins 9-20 BIO pin 9-20 XF pin 9-21 global data memory 8-20, H-12 addressing 8-20 configuration 8-20 global memory allocation register (GREG) 8-20 map 8-21 global memory allocation register (GREG) 3-23, 8-20, H-12 reset status 4-46 GREG H-12 See also global memory allocation register (GREG)

H
HALTR bit 9-64, H-12 HALTX bit 9-64, H-12 hardware development tools G-2, G-7 hardware stack 4-4, 4-42, H-22 hardware timer 2-8 Harvard architecture 1-5 HAS pin A-22 HBIL pin A-22 HCNTL0 pin A-22 HCNTL1 pin A-22 HCS pin A-22

HD0HD7 pin A-22 HDS1 pin A-23 HDS2 pin A-23 Hewlett-Packard interface G-8 HINT bit H-12 HINT pin A-23 HM bit 4-15, 4-38, 8-14, 8-24, H-12 hold mode (HM) bit H-12 See also HM bit HOLD pin 4-49, 8-23, A-15 HOLDA pin 4-45, 8-23, A-15 HOM H-12 See also host-only mode (HOM) host port interface (HPI) 2-9, 9-87, H-13 boot mode 8-33 registers 3-23 signal descriptions A-22 host processor interrupt (HINT) bit H-12 See also HINT bit host-only mode (HOM) H-12 HPI H-13 See also host port interface (HPI) HPI address register (HPIA) 3-23, H-13 HPI address register high byte (HPIAH) H-13 See also HPI address register (HPIA) HPI address register low byte (HPIAL) H-13 See also HPI address register (HPIA) HPI boot mode 8-33 HPI control register (HPIC) 3-23, H-13 BOB H-5 diagram 9-96 DSPINT bit H-9 HINT bit H-12 SMOD bit H-21 HPI control register high byte (HPICH) H-13 See also HPI control register (HPIC) HPI control register low byte (HPICL) H-13 See also HPI control register (HPIC) HPI modes host only (HOM) H-12 shared access (SAM) H-21 HPIA H-13 See also HPI address register (HPIA) HPIAH H-13 See also HPI address register high byte (HPIAH) HPIAL H-13 See also HPI address register low byte (HPIAL)

Index-7

HPIC H-13 See also HPI control register (HPIC) HPICH H-13 See also HPI control register high byte (HPICH) HPICL H-13 See also HPI control register low byte (HPICL) HR/W pin A-23 HRDY pin A-23

I
I/O addressing 8-22 buffered serial ports 2-10 general-purpose pins 9-20 host port 2-9 parallel ports 2-9, 9-22 serial ports 2-10 space 3-23, 8-22 TDM serial ports 2-10 I/O High bit 9-17 I/O Low bit 9-18 I/O port wait-state register (IOWSR) 3-24, 9-16, H-13 diagram 9-16 reset status 4-47 I/O space 3-23, 8-22 addressing 8-22 IACK pin 8-14, A-15 IAQ pin 8-14, 8-23, A-15 IDLE instruction description 6-108 summary 6-21 IDLE2 instruction 4-50 description 6-109 summary 6-21 IEEE 1149.1 D-3 IFR H-13 See also interrupt flag register (IFR) immediate addressing mode 5-14 to 5-16 long immediate 5-15 short immediate 5-14 IMR H-14 See also interrupt mask register (IMR) IN instruction description 6-110 Index-8

summary 6-20 IN0 bit 9-29, 9-35, H-14 IN1 bit 9-29, 9-35, H-14 index register (INDX) 3-19, 3-23, H-14 indirect addressing mode 3-17, 5-4 to 5-5 bit-reversed addressing 5-12 examples 5-10 to 5-13 format for instructions 5-7 opcode format 5-7 opcode format diagram 5-7 opcode format summary 5-7 operands 5-5 options 5-5 INDX H-14 See also index register (INDX) initialization CPU 4-45 peripherals 9-6 instruction. See assembly language instructions instruction classes B-1 instruction conditions branch 4-17 call 4-17 return 4-17 instruction cycles 6-25, B-1 instruction operands 8-13 instruction operation conditional branch 4-17 conditional call 4-18 conditional execution 4-20 conditional return 4-18 delayed conditional branches 4-19 delayed conditional calls 4-19 delayed conditional returns 4-19 multiconditional instructions 4-18 instruction register (IREG) 3-18, 3-23, 4-2, H-14 instruction set descriptions 6-23 latencies 7-24 summary 6-8 instruction set opcodes, summary 6-8 instruction set symbols and notations 6-2 instructions not meaningful to repeat 4-27 INT1 pin A-16 INT2 pin A-16 INT3 pin A-16 INT4 pin A-16

internal hardware summary 3-2 to 3-6 CPU 3-4 to 3-6 internal transmit clock division factor (CLKDV) bits H-14 See also CLKDV bits interrupt flag register (IFR) 3-23, 4-39, H-14 diagram 4-39 reset status 4-46 RINT bit H-21 TINT bit H-24 TRNT bit H-23 TXNT bit H-23 XINT bit H-21 interrupt mask register (IMR) 3-23, 4-40, H-14 diagram 4-40 interrupt mode (INTM) bit H-15 See also INTM bit interrupt service routine (ISR) H-15 interrupt trap 4-42 interrupt vector pointer (IPTR) bits H-15 See also IPTR bits interrupts 4-36 to 4-44, H-14 address location 4-37 context save 4-42 hardware H-12 latency 4-43, H-15 nested H-16 nonmaskable 4-41, H-16 operation 4-38 priorities 4-36, 4-37 registers 3-23 IFR. See interrupt flag register (IFR) IMR. See interrupt mask register (IMR) software initiated 4-41 user-maskable (external) 2-10, H-10 vector addresses 8-11, 8-12 vector locations 4-36 vectors 4-38, 8-11, 8-12 INTM bit 3-23, 4-12, 4-40, 8-32, H-15 INTR instruction description 6-112 summary 6-18 introduction 1-1 TMS320 family overview 1-2 TMS320C5x key features 1-7 TMS320C5x overview 1-5 IOWSR H-15 See also I/O port wait-state register (IOWSR)

IPTR bits 4-8, 4-37, 8-11, 8-12, H-15 IREG H-15 See also instruction register (IREG) IS pin A-14 ISR H-15 See also interrupt service routine (ISR)

J
JTAG D-1 scanning logic 2-11 to 2-12 signals D-3 JTAG emulator buffered signals D-10 connection to target system D-1 to D-13 no signal buffering D-9

K
key features 1-7

L
LACB instruction description 6-114 summary 6-10 LACC instruction description 6-115 summary 6-10 LACL instruction description 6-118 summary 6-10 LACT instruction description 6-121 summary 6-10 LAMM instruction description 6-123 summary 6-10 LAR instruction description 6-125 summary 6-13 latency instruction set 7-24 interrupts 4-43 pipeline 7-24 LDP instruction description 6-128 summary 6-13

Index-9

LMMR instruction description 6-131 example 8-31 summary 6-20 local data memory 8-15 address map 8-17 addressing 8-19 configuration 8-15 to 8-17 long immediate addressing 5-15 low-power mode 4-50 LPH instruction description 6-134 summary 6-14 LST instruction description 6-136 summary 6-21 LT instruction description 6-139 summary 6-14 LTA instruction description 6-141 summary 6-15 LTD instruction description 6-143 summary 6-15 LTP instruction description 6-146 summary 6-15 LTS instruction description 6-148 summary 6-15

M
MAC instruction 3-9 description 6-150 summary 6-15 MACD instruction description 6-154 summary 6-15 MADD instruction description 6-159 summary 6-15 MADS instruction description 6-163 summary 6-15 MAR instruction description 6-167 Index-10

summary 6-13 masked parts F-3 MCM bit 9-30, 9-33, H-15 MCS H-15 See also microcall stack (MCS) memories E-2 memory 2-6, 8-1 addressing modes 5-1 boot loader 8-32 direct memory access (DMA) 8-23 dual-access RAM (DARAM) 2-6 external 8-2 external memory interface timings 8-39 global data 8-20 I/O space 8-22 local data 8-15 management 8-26 maps 8-4 to 8-6 overview 8-2 program 2-6, 8-7 protection 2-7 single-access RAM (SARAM) 2-7 software wait-state generation 8-42 memory addressing modes 5-1 memory block moves 8-27 memory configuration local data memory 8-15 to 8-17 program memory 8-7 to 8-11 memory management 8-26 memory block moves 8-27 memory-to-memory moves 8-26 memory map H-15 memory protection feature 2-7, 8-14 memory-mapped register addressing mode 5-19 to 5-22 memory-mapped registers 2-5 CPU 8-18 defined H-16 I/O ports 8-19, 9-2 to 9-4 peripherals 8-19, 9-2 to 9-4 serial ports 8-19, 9-2 to 9-4 memory-to-memory moves 8-26 microcall stack (MCS) 5-15, H-16 microcomputer mode 4-9, 8-3 to 8-5 microprocessor mode 4-9, 8-3 to 8-5 microprocessor/microcomputer (MP/MC) bit H-16 See also MP/MC bit mnemonic H-16 See also assembly language instructions

MP/MC bit MP/MC pin

4-9, 8-7, H-16 8-3, 8-7, A-16

O
off-chip, defined on-chip, defined on-chip memory H-17 H-17 2-6

MPY instruction description 6-169 summary 6-16 MPYA instruction description 6-172 summary 6-16 MPYS instruction description 6-174 summary 6-16 MPYU instruction 3-10 description 6-176 summary 6-16 MULT H-16 See also multiplier (MULT) multiplier (MULT) 3-7, H-16 3-9 8-20, 8-23, D-8 multiply accumulate

on-chip peripherals 2-8, 9-1 buffered serial port (BSP) 2-10, 9-53 clock generator 2-8, 9-7 general-purpose I/O pins 9-20 to 9-21 host port interface (HPI) 2-9, 9-87 parallel I/O ports 2-9, 9-22 peripheral control 9-2 serial port interface 2-10, 9-23 software-programmable wait-state generators 2-8, 9-13 TDM serial port 2-10, 9-74 timer 2-8, 9-9 on-chip ROM 2-6, 8-2, 8-3, F-2 opcode See also assembler defined H-17 summary 6-8 operand H-17 OPL instruction description 6-185 summary 6-14 OR instruction description 6-188 summary 6-10 ORB instruction description 6-191 summary 6-11 4-22 oscillator/timer expanded options A-19 standard options A-18 OUT instruction description 6-192 summary 6-20

multiprocessing 8-20, 8-23 multiprocessor configuration

N
NDX bit 4-9, 5-6, H-16 NEG instruction description 6-178 summary 6-10 nested interrupt nested loops H-16 4-32

next instruction repeat function NMI instruction description 6-180 summary 6-18 NMI pin A-16 nomenclature G-4, G-5 nonrepeatable instructions NOP instruction description 6-181 summary 6-21 NORM instruction description 6-182 summary 6-10

4-29

OV bit

4-11, H-17

overflow (OV) bit H-17 See also OV bit overflow mode (OVM) bit See also OVM bit OVLY bit OVM bit 3-12, 4-11, H-17 H-17

4-8, 8-15, 8-32, H-17

Index-11

P
P bit 9-18 PAC instruction description 6-194 summary 6-16 packages C-2 PAER H-17 See also block repeat program address end register (PAER) parallel EPROM boot mode 8-36 parallel I/O boot mode 8-37 parallel I/O ports 2-9, 9-22 parallel logic unit (PLU) 2-4, 3-15 to 3-16, H-17 block diagram 3-15 parallelism 2-3, 2-5, 2-7, 6-27 part numbers, tools G-7 part-order information G-4 PASR H-17 See also block repeat program address start register (PASR) PC H-17 See also program counter (PC) PCM bit 9-58, H-17 PDWSR H-18 See also program/data wait-state register (PDWSR) peripheral control 9-2 peripheral reset 9-6 PFC H-18 See also prefetch counter (PFC) pinouts A-1 C50 A-8 C51 A-4, A-8 C52 A-2, A-4 C53 A-8 C53S A-4 C57S A-10 LC56 A-4 LC57 A-6 100-pin QFP A-2, A-3 100-pin TQFP A-4, A-5 128-pin TQFP A-6, A-7 132-pin BQFP A-8, A-9 144-pin TQFP A-10, A-11 pipeline defined H-18 latency H-15 Index-12

pipeline operation 7-1, 7-3 1-word instruction 7-3 2-word instruction 7-5 branch not taken 7-9 branch taken 7-6 external memory conflict 7-21 four phases 7-2 latency 7-24 memory-mapped registers 7-14 normal 7-3 structure 7-2 subroutine call and return 7-11 PLCC package C-3 PLU H-18 See also parallel logic unit (PLU) PM bits 3-7, 4-15, 6-254, H-18 PMST H-18 See also processor mode status register (PMST) POP instruction description 6-195 summary 6-21 POPD instruction description 6-197 summary 6-21 postscaling shifter H-18 power-down mode 4-50 IDLE instruction 4-50 IDLE2 instruction 4-50 PRD H-18 See also timer period register (PRD) prefetch counter (PFC) 5-15, H-18 PREG H-18 See also product register (PREG) preprocessor interface G-8 prescaling shifter H-18 priorities, interrupt 4-37 processor mode status register (PMST) 3-24, 4-7, H-18 AVIS bit 4-8, 8-13, 8-14, H-1 bit summary 4-8 BRAF bit 4-9, H-4 diagram 4-8 IPTR bits 4-8, 8-11, 8-12, H-15 MP/MC bit 4-9, 8-7, H-16 NDX bit 4-9, H-10 OVLY bit 4-8, 8-15, 8-32, H-19 RAM bit 4-8, 8-8, 8-32 reset status 4-46 TRM bit 4-9, H-10

product register (PREG) 3-7, 3-24, H-18 product shift mode (PM) bits H-18 See also PM bits program address bus (PAB) 4-2 program bus 2-3 program control 4-1 block repeat function 4-31 functional block diagram 4-2 interrupts 4-36 next instruction repeat function 4-22 power-down mode 4-50 reset 4-45 status and control registers 4-6 program controller 2-5, H-19 program counter (PC) 4-2, 8-11, 8-13, H-19 program execution 4-2, 8-27 program memory 2-6, 4-5, 8-7 address map 8-11 addressing 8-13 configuration 8-7 to 8-11 protection feature 8-14 program/data wait-state register (PDWSR) 3-24, 9-13, H-19 diagram 9-13, 9-14 reset status 4-47 PS pin A-14 PSC bits 9-10, H-19 p-scaler 3-7, H-19 set shift 6-254 PSHD instruction description 6-199 summary 6-21 pulse coded modulation mode (PCM) bit H-19 See also PCM bit PUSH instruction description 6-201 summary 6-21

Q
quad flat-pack (QFP) package A-1

R
R/W pin 8-39, A-14 RAM bit 4-8, 8-8, 8-32

RAM overlay (OVLY) bit H-19 See also OVLY bit RD pin A-14 read/write timings 8-39 READY pin A-14 receive buffer half received (RH) bit H-19 See also RH bit receive ready (RRDY) bit H-20 See also RRDY bit receive shift register full (RSRFULL) bit H-20 See also RSRFULL bit receiver reset (RRST) bit H-20 See also RRST bit regional technology centers G-3 register 3-21 autobuffering control 9-63 auxiliary (AR) 3-21, H-3 auxiliary register compare (ARCR) 3-19, 3-21, H-3 block move address (BMAR) 3-21, H-4 block repeat 3-21 block repeat counter (BRCR) H-4 block repeat program address end (PAER) H-4 block repeat program address start (PASR) H-4 BSP address receive (ARR) H-4 BSP address transmit (AXR) H-5 BSP control extension (SPCE) H-5 BSP receive buffer size (BKR) H-5 BSP transmit buffer size (BKX) H-5 buffered serial port (BSP) 3-22 circular buffer 3-22 circular buffer control (CBCR) 4-6, H-7 circular buffer end register (CBERx) H-6, H-7 circular buffer start (CBSRx) H-7 data receive (DRR) H-8 data receive shift (RSR) H-9 data transmit (DXR) H-9 data transmit shift (XSR) H-9 dynamic bit manipulation (DBMR) 3-22, H-10 global memory allocation (GREG) 3-23, 8-20, H-12 host port interface (HPI) 3-23 host port interface address (HPIA) H-13 host port interface control (HPIC) H-13 I/O port wait-state (IOWSR) H-13 index (INDX) 3-19, 3-23, H-14 instruction (IREG) 3-23, H-14 interrupt 3-23, 4-39, 4-40 interrupt flag (IFR) H-14

Index-13

register (continued) interrupt mask (IMR) H-14 memory-mapped 2-5, 8-17 prefetch (PFC) H-18 processor mode status (PMST) 3-24, 4-7, H-18 product (PREG) 3-24, H-18 program/data wait state (PDWSR) H-19 program/data wait-state (PDWSR) 9-13, 9-14 repeat counter (RPTC) 4-22, H-20 reset status 4-46 to 4-48 serial port 9-24 serial port control (SPC) H-21 serial port interface 3-24 software wait-state control (CWSR) H-26 software-programmable wait states 3-24 status 3-25, 4-10 TDM channel select (TCSR) H-22 TDM data receive (TRCV) H-23 TDM data receive shift (TRSR) H-23 TDM data transmit (TDXR) H-23 TDM receive address (TRAD) H-23 TDM receive/transmit address (TRTA) H-23 TDM serial port 3-25, 9-74 TDM serial port control (TSPC) H-23 temporary 3-25, H-24, H-26 timer 3-25 timer control (TCR) 9-10, H-24 timer counter (TIM) H-24 timer period (PRD) H-24 repeat counter register (RPTC) reset status 4-46 repeat function block 4-31 next instruction reset CPU 4-45 defined H-20 peripherals 9-6 RET instruction description 6-203 summary 6-18 RETC instruction description 6-204 example 4-18 summary 6-18 RETCD instruction description 6-206 summary 6-18 Index-14 3-21, 4-22, H-20

RETD instruction description 6-208 summary 6-18 RETE instruction description 6-209 summary 6-18 RETI instruction description 6-210 summary 6-18 RH bit RINT bit 9-64, H-20 3-14 H-20 right shift

ROL instruction description 6-211 summary 6-11 ROLB instruction description 6-212 summary 6-11 ROM codes 2-6, F-1 development flow F-3 submitting ROM code F-4 ROR instruction description 6-213 summary 6-11 RORB instruction description 6-214 summary 6-11 RPT instruction description 6-215 summary 6-22 RPTB instruction description 6-218 example 4-31, 4-32 summary 6-22 RPTC H-20 See also repeat counter register (RPTC) RPTZ instruction description 6-220 summary 6-22 RRDY bit RRST bit RS pin 9-29, 9-35, H-20 9-29, 9-34, H-20

4-22 4-23 to 4-36

repeatable instructions

4-45, A-16

RSR H-20 See also data receive shift register (RSR) RSRFULL bit RTCs G-3 9-28, 9-36, H-20

S
SACB instruction description 6-221 summary 6-11 SACH instruction description 6-222 summary 6-11 SACL instruction description 6-224 summary 6-11 SAM H-20 See also shared-access mode (SAM) SAMM instruction description 6-226 summary 6-11 SAR instruction description 6-228 summary 6-13 SARAM H-20 See also single-access RAM (SARAM) SATH instruction description 6-230 summary 6-11 SATL instruction description 6-232 summary 6-11 SBB instruction description 6-233 summary 6-11 SBBB instruction description 6-234 summary 6-11 SBRK instruction description 6-235 summary 6-13 scaling shifters 3-14 scratch-pad RAM 8-18, H-20 seminars G-3 serial boot mode 8-34 serial port control register (SPC) 3-24, 8-34, 9-24, H-21 bit summary 9-28 diagram 9-28 DLB bit 9-31, 9-32, H-9 FO bit 9-31, 9-32, H-11 Free bit 9-28, 9-37, H-11

FSM bit 9-30, 9-33, H-11 IN0 bit 9-29, 9-35, H-14 IN1 bit 9-29, 9-35, H-14 MCM bit 9-30, 9-33, H-7 reset status 4-47 RRDY bit 9-29, 9-35, H-20 RRST bit 9-29, 9-34, H-20 RSRFULL bit 9-28, 9-36, H-20 Soft bit 9-28, 9-37, H-21 TXM bit 9-30, 9-33, H-25 XRDY bit 9-29, 9-35, H-25 XRST bit 9-30, 9-34, H-25 XSREMPTY bit 9-29, 9-35, H-25 serial port interface 2-10, 3-24, 9-23, H-21 configuring 9-27 error conditions 9-46 operation 9-25 operation examples 9-50 receive operation burst mode 9-37 continuous mode 9-44 registers 3-24, 9-24 signal descriptions A-20 transmit operation burst mode 9-37 continuous mode 9-44 serial port receive interrupt (RINT) bit See also RINT bit serial port transmit interrupt (XINT) bit See also XINT bit H-21 H-21

serial ports buffered serial port (BSP) 9-53 serial port interface 9-23 time-division multiplexed (TDM) 9-74 set control bit 6-236 6-254 set p-scaler shift

SETC instruction description 6-236 summary 6-22 SFL instruction description 6-238 summary 6-11 SFLB instruction description 6-239 summary 6-11 SFR instruction description 6-240 summary 6-11

Index-15

SFRB instruction description 6-242 summary 6-11 shadow registers 2-10, 4-42, 6-210 shared-access mode (SAM) H-21 shared-access mode (SMOD) bit H-21 See also SMOD bit shifters H-3, H-21 postscaler H-18 prescaler H-18 product H-19 short immediate addressing 5-14 signal descriptions A-13 address and data bus A-13 buffered serial port (BSP) A-21 emulation/testing A-24 host port interface (HPI) A-22 initialization A-16 interrupt A-16 memory control A-14 multiprocessing A-15 oscillator/timer A-17 reset operation A-16 serial port interface A-20 supply A-16 signals buffered D-10 buffering for emulator connections D-9 to D-10 sign-extension H-21 sign-extension mode (SXM) bit H-21 See also SXM bit single-access RAM (SARAM) 2-7, 6-27, 8-2, 8-25, H-21 SMMR instruction description 6-244 example 8-31 summary 6-20 SMOD bit H-21 sockets E-2 Soft bit 9-10, 9-28, 9-37, H-21 software development tools G-2, G-7 software wait states C-7 software wait-state generation 8-42 software-programmable wait-state generators 2-8, 9-13 block diagram 9-19 I/O port wait-state register (IOWSR) 9-16 Index-16

logic for external program space 9-19 program/data wait-state register (PDWSR) 9-13 wait-state control register (CWSR) 9-17 software-programmable wait-state registers 3-24 SPAC instruction description 6-247 summary 6-16 SPC H-22 See also serial port control register (SPC) SPCE H-22 See also BSP control extension register (SPCE) SPH instruction description 6-248 summary 6-16 SPL instruction description 6-250 summary 6-16 SPLK instruction description 6-252 summary 6-14 SPM instruction description 6-254 summary 6-16 SQRA instruction description 6-255 summary 6-16 SQRS instruction description 6-257 summary 6-17 SST instruction description 6-259 summary 6-22 stack hardware 4-4, 4-42, H-22 microcall (MCS) 5-15, H-16 status and control registers 4-6, H-22 status register 0 (ST0) 3-25, 4-10, H-22 ARP bits 4-11, H-3 bit summary 4-11 diagram 4-11 DP bits 4-12, H-8 INTM bit 3-23, 4-12, 4-40, 8-32, H-15 OV bit 4-11, H-17 OVM bit 4-11, H-17 reset status 4-46 status register 1 (ST1) 3-25, 4-10, H-22 ARB bits 4-13, H-3 bit summary 4-13 C bit 4-14, H-6

status register 1 (ST1) (continued) CNF bit 4-13, 8-8, 8-15, 8-32, H-7 diagram 4-13 HM bit 4-15, 8-14, 8-24, H-12 PM bits 4-15, H-18 reset status 4-46 SXM bit 4-14, H-21 TC bit 3-21, 4-13, H-24 XF bit 4-15, H-10 STRB pin A-14 strobe signal (STRB) 8-24 SUB instruction description 6-261 summary 6-12 SUBB instruction description 6-265 summary 6-12 SUBC instruction description 6-267 summary 6-12 submitting ROM code F-4 SUBS instruction description 6-269 summary 6-12 SUBT instruction description 6-271 summary 6-12 support tools development G-6 device G-6 nomenclature G-4 SXM bit 3-14, 4-14, H-22 system migration C-1 instruction set C-11 on-chip peripheral interfacing C-10 packages and pin layout C-2 timing C-7

T
TADD H-22 See also TDM address (TADD) target system, connection to emulator target system clock D-7 TBLR instruction 8-26 description 6-273 example 8-29, 8-30 summary 6-20 D-1 to D-13

TBLW instruction 8-26 description 6-276 example 8-28, 8-29 summary 6-20 TC bit 3-21, 4-13, H-22 TCK pin A-24 TCLK H-22 See also TDM clock (TCLK) TCLKR pin A-20 TCLKX pin A-20 TCR H-22 See also timer control register (TCR) TCSR H-22 See also TDM channel select register (TCSR) TDAT H-22 See also TDM data (TDAT) TDDR bits 9-10, H-22 TDI pin A-24 TDM address (TADD) 9-77, H-22 TDM bit H-22 TDM channel select register (TCSR) 3-25, 9-75, H-22 TDM clock (TCLK) H-22 TDM data (TDAT) H-23 TDM data receive register (TRCV) 3-25, 9-75, H-23 TDM data receive shift register (TRSR) 3-25, 9-76, H-23 TDM data transmit register (TDXR) 3-25, 9-75, H-23 TDM receive address register (TRAD) 3-25, 9-75, H-23 TDM receive interrupt (TRNT) bit H-23 See also TRNT bit TDM receive/transmit address register (TRTA) 3-25, 9-75, H-23 TDM registers, diagram 9-78 TDM serial port control register (TSPC) 3-25, 9-75, H-23 DLB bit H-9 FO bit H-11 Free bit 9-28, 9-37, H-11 FSM bit H-11 IN0 bit 9-29, 9-35, H-14 IN1 bit 9-29, 9-35, H-14 MCM bit 9-30, 9-33, H-7 reset status 4-47

Index-17

TDM serial port control register (TSPC) (continued) RRDY bit 9-29, 9-35, H-20 RRST bit 9-29, 9-34, H-20 Soft bit 9-28, 9-37, H-21 TDM bit H-24 TXM bit 9-30, 9-33, H-25 XRDY bit 9-29, 9-35, H-25 XRST bit 9-30, 9-34, H-25 TDM serial port interface 2-10, 9-74 exception conditions 9-82 operation 9-76 operation examples 9-82 receive operation 9-80 registers 3-25, 9-74 transmit operation 9-80 TDM transmit interrupt (TXNT) bit See also TXNT bit TDO pin TDR pin TDX pin A-24 A-20 A-20 H-23

TDXR H-23 See also TDM data transmit register (TDXR) temporary register 0 (TREG0) 3-7, 3-25, 6-139, 6-141, 6-143, 6-146, 6-148, 6-169, 6-172, 6-174, 6-176, H-26 temporary register 1 (TREG1) 3-12, 3-14, 3-25, 6-41, 6-230, 6-232, 6-271, H-26 temporary register 2 (TREG2) test/control (TC) bit See also TC bit test/emulation 2-11 TFSR/TADD pin TFSX/TFRM pin third-party support A-20 A-20 A-1 G-2 H-24 3-25, 6-66, H-26

thin quad flat-pack (TQFP) package

TIM H-24 See also timer counter register (TIM) time-division multiplexed (TDM) bit See also TDM bit time-division multiplexing (TDM) basic operation 9-74 defined H-24 timer 2-8, 9-9 block diagram 9-9 operation 9-11 registers 3-25, 9-9 Index-18 H-24

timer control register (TCR) 3-25, 9-10, H-24 bit summary 9-10 diagram 9-10 Free bit 9-10 PSC bits 9-10, H-25 reset status 4-48 Soft bit 9-10 TDDR bits 9-10, H-24 TRB bit 9-10, H-25 TSS bit 9-10, H-25 timer counter register (TIM) 3-25, H-24 reset status 4-48 timer divide-down register (TDDR) bits H-24 See also TDDR bits timer interrupt (TINT) 9-9 rate 9-11 timer interrupt (TINT) bit H-24 See also TINT bit timer period register (PRD) 3-25, H-24 reset status 4-48 timer prescaler counter (PSC) bits H-25 See also PSC bits timer reload (TRB) bit H-25 See also TRB bit timer stop status (TSS) bit H-25 See also TSS bit timing BIO signal 9-20 emulator D-11 external memory interface 8-39 XF signal 9-21 TINT bit H-25 TMS pin A-24 TMS320 advantages 1-2 development 1-2 evolution 1-3 family overview 1-2 history 1-2 roadmap 1-3 typical applications 1-4 TMS320 ROM code submittal, figure F-3 TMS320C5x applications 1-4 characteristics 1-6 functional block diagram 2-2 IEEE Std. 1149.1 interface configurations 2-12 key features 1-7

TMS320C5x (continued) compatibility 1-7 CPU 1-8 instruction set 1-8 memory 1-7 on-chip peripherals 1-9 packages 1-9 power 1-7 program control 1-8 speed 1-7 test/emulation 1-9 number of parallel ports available 2-9 number of serial ports available 2-9 overview 1-5 tools, part numbers TOUT pin A-17 G-7

TRST pin A-24 TRTA H-26 See also TDM receive/transmit address register (TRTA) TSPC H-26 See also TDM serial port control register (TSPC) TSS bit 9-10, H-26 TXM bit 9-30, 9-33, H-26 TXNT bit H-26

U
user-maskable interrupts 2-10

V
H-25 vectors interrupt 8-12 reset 4-38

TRAD H-25 See also TDM receive address register (TRAD) transmit buffer half transmitted (XH) bit See also XH bit transmit mode (TXM) bit See also TXM bit transmit ready (XRDY) bit See also XRDY bit transmit reset (XRST) bit See also XRST bit H-25 H-25 H-25 H-25

W
wait-state control register (CWSR) H-26 BIG bit 3-24, 8-22, 9-17, H-3 bit summary 9-17 D bit 9-18 diagram 9-17 I/O High bit 9-17 I/O Low bit 9-18 P bit 9-18 reset status 4-47 warm boot mode 8-38 WE pin A-14 word moves 8-26 workshops G-3 3-24, 9-17,

transmit shift register empty (XSREMPTY) bit See also XSREMPTY bit TRAP instruction description 6-279 summary 6-19 TRB bit 9-10, H-25 TRCV H-26 See also TDM data receive register (TRCV) TREG0 H-26 See also temporary register 0 (TREG0) TREG1 H-26 See also temporary register 1 (TREG1) TREG2 H-26 See also temporary register 2 (TREG2) TRM bit TRNT bit 4-9, H-26 H-26

X
X1 pin A-17 X2/CLKIN pin A-17 XC instruction description 6-280 example 4-20, 4-21 summary 6-19 XF bit 4-15, H-27 XF pin 8-34, 9-21, A-15, H-12 XH bit 9-65, H-27

TRSR H-26 See also TDM data receive shift register (TRSR)

Index-19

XINT bit H-27 XOR instruction description 6-282 summary 6-12 XORB instruction description 6-285 summary 6-12 XPL instruction description 6-286 summary 6-14 XRDY bit 9-29, 9-35, H-27 XRST bit 9-30, 9-34, H-27 XSR H-27 See also data transmit shift register (XSR)

XSREMPTY bit

9-29, 9-35, H-27

Z
ZALR instruction description 6-289 summary 6-12 ZAP instruction description 6-291 summary 6-12 ZPR instruction description 6-292 summary 6-17

Index-20