STR-X6400 Application

STR-X6400 Application Note

Ver.0.1

CONTENTS

1. 2. 3. 4. 5. 6. 7. 8.

Introduction Features Line-up of STR-X6400 Series STR-X6400 Series Outline Drawings STR-X6400 Series Block Diagram Electrical Characteristics (STR-X6469) Application Circuit Functions of Each Terminal and Operation
8.1 VIN Terminal (Pin 3) 8.2 OCP Terminal (Pin 5) 8.3 FB/OLP Terminal (Pin 6) 8.4 Quasi-Resonant and Bottom-Skip Operation 8.5 Operation at Stand-by 8.6 Thermal Shutdown Circuit 8.7 Step-Drive Circuit 8.8 Typical Characteristics

P. 3 P. 3 P. 4 P. 5 P. 6 P. 7-8 P. 9 P. 10-24
P. 10-12 P. 13-15 P. 15-17 P. 18-21 P. 21-23 P. 23 P. 24 P. 24

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STR-X6400 Application Note

Ver.0.1

1. Introduction
The STR-X6400 series is a hybrid IC with a built-in MOSFET and a control IC, designed for fly-back converter SMPS (Switching Mode Power Supply) applications. The IC is suitable for simplifying and standardizing power supply The IC is also applicable systems, by reducing the number of external components, and simplifying circuit designs. for Quasi-Resonant, low frequency PRC, and Burst mode at stand-by designs.

Note: PRC stands for Pulse Ratio Control (ON width Control with fixed OFF-time)

2. Features
Newly developed SIP fully molded 7 pin package. Built-in Step-Drive circuit provides low noise switching. Built-in Bottom-Skip operation circuit operates from light to medium load ranges, and reduces switching losses. Built-in Intermittent Operation circuit provides an intermittent oscillation at light load, reducing input power. For protective functions, the STR-X6400 series has the same Overcurrent Protection (OCP), Overvoltage
Protection (OVP), and Thermal Shutdown (TSD) as those of the former series. components within the power supply and the IC itself. It also has Overload Protection (OLP); which operates as latch at over load in the secondary side, which reduces stresses on external

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STR-X6400 Application Note

Ver.0.1

3. Line-up of STR-X6400 Series

MOSFET VDSS[V] 650 RDS(ON) MAX[ohms] 0.73 TOFF(MIN1)/ TOFF(MIN2)[uS] 5.2/7.2

Type *3

VACINPUT[V] 220 WIDE 220 WIDE

Pout [W] *1 285 144 240 120

STR-X6456

STR-X6468

800

1.00

6.0/8.0

STR-X6459

650

0.385

WIDE

300

8.8/10.7

*1. The Pout (W) represents the thermal ratings, and the peak output power obtains by 120%~140% approximately. Where the output voltage is low and the ON-duty is narrow, the Pout (W) shall be smaller than that of above. *2. Preliminary. *3. A suffix parts do not have the Auto PRC function. Refer to the specifications for details.

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STR-X6400 Application Note

Ver.0.1

4. STR-X6400 Series Outline Drawings (Lead Forming LF1901)

5. . 5 0 2 2 . 0 2 5. . 5 0 2 3. 5 . 4 0 2 . . 3 2 0 2 3. 5 . 3 0 1 ( ) D mens ion be t i ween roo ts 1 . . 2 5 0 5 2- ( 1 . ) R 3 0 . 5 - .1 5 0 4. . 5 0 7 ( ) D mens ion be t i ween t ips
+ . 0 2

S T R
a

2 . 3 0 3

SK

1 . 3 - .1 3 0

+ . 0 2

0 . 5 -0 .1 7

+ . 0 2

R-e d n R-e d n

1 . 9 - .1 8 0 0 . 3 - .1 8 0
+ . 0 2

+ . 0 2

5- . 5 -0 .1 0 6 4xP . 7 . = ( . 8 ) 1 2 0 1 5 0 ( ) 2xP . 4 . = ( . 8 ) 2 5 0 1 5 0 ( ) D mens ion be t een roo ts i w 1 . . 5 6 0 2 ( . ) 5 5

+ . 0 2

0. 7
1 2 3 4 5 6 7

0. 7

3. . 3 0 5 0. 7

3. 3

7 . 0 5

0. 7
w S ide v ie

und p lan Gro

Material of terminal: Cu Material of Terminal:

Cu

Cu

Treatment of Ni Terminal: Ni Plating + Solder Dip Weight:

Treatment of terminal: Ni platingsolder dip

6.0g approx.

6.0g DWG No: Weight: Approx. 6.0g DWG.No TG3A-1901B

TG3A-1901B

Note 1: denote location where gate burr of 0.3 MAX is

1) 0.3 max Note1) produced denote the location where gate burr of 0.3 max is produced. mm Dimensions in mm

a. Type a. Number X6400 Type Number b. b. Lot Number Lot Number letter of Production 1st Year 1st letter The last digit of year The last digit of year 2nd letter Month 19 2nd letter Month of Production 10 O 11 N Jan~Sept Arabic Numerals 12 D (1 Oct to 9 for Jan. to Sep.,O for Oct. N for Nov. D for Dec.) O 3,4 3rd 4th letter Day Nov N 0131 Arabic Numerical Dec D 3, 4 letter
th

Unit:

mm

Date of production 01~31 Arabic Numerals

*Refer to the specifications for details.

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STR-X6400 Application Note

Ver.0.1

5. STR-X6400 Series Block Diagram 3

V LATCH REG Bias
R Q S
DRIVE REG

Control part
1
Delay D

Start/Stop OVP TSD

DRIVE Current M Burst OSC Control

S/GND ABS FB/OLP

OLP

OSC

OCP

Terminal Functions Terminal 1 2 3 4 5 6 7 Symbol D S /GND VIN ABS OCP FB/OLP BD Description Drain Terminal Source / Ground Terminal Power Supply Terminal Stand-by Terminal Overcurrent Protection Terminal Feedback / Overload Protection Detecting Terminal Bottom Detecting Terminal Functions MOSFET Drain MOSFET Source / Ground Power Supply for Control Circuit Stand-by Control Overcurrent Detection Signal Input Overload Detection and Constant Voltage Control Signal Input OFF-time Synchronization

Page. 6

BD1

Bottom Edge Detector

BD

BD2

5
OCP

STR-X6400 Application Note

Ver.0.1

6. Electrical Characteristics: STR-X6469 (Example)

Absolute Maximum Ratings (Ta = 25) Description Drain Current Maximum Switching Current Avalanche Energy Capacity Input Voltage to Control Part FB/OLP Terminal Current OCP Terminal Voltage BD Terminal Voltage ABS Terminal Voltage Power Dissipation at MOSFET Power Dissipation at Control Part (MIC) Internal Frame Temp. at Operation Operating Ambient Temp. Storage Temperature Channel Temperature Terminal 1-2 1-2 1-2 3-2 6-2 5-2 7-2 4-2 1-2 3-2
-

Symbol ID peak*1
ID MAX* EAS*3
2

Ratings
22 22

Unit A
A

Remarks Single Pulse

Ta=-20+125 Single Pulse

395

mJ

VDD=30V,L=50mH IL=3.9A

VIN

35 3 -1.5~5 -0.5~6 -0.5~6 46 2.8 0.8

IFBOLP VOCP VBD VABS PD1*4

PD2*5

mA V V V W
W

With Infinite Heat Sink Without Heat Sink

VINIIN Refer to Recommended Operating Temperature

TF Top Tstg Tch

-20~+125 -20~+125 -40~+125 +150

*1. Refer to the MOSFET S.O.A. curve on the specifications. *2. Refer to the Maximum Switching Current on the specifications. The Maximum Switching Current is the drain current determined by both the drive voltage of the IC and the Vth of the MOSFET. *3. Refer to the MOSFET Tch-EAS curve on the specifications. *4. Refer to the MOSFET Ta-PD1 curve on the specifications. *5. Refer to the MIC TF-PD2 curve on the specifications. Note: Refer to the specifications for details since the values are different for each product.

Page. 7

STR-X6400 Application Note Electrical Characteristics of Control Part (Ta=25) Parameter Operation Start Voltage Operation Stop Voltage Circuit Current at Operation Circuit Current at Non-Operation Maximum OFF-Time Minimum OFF-Time 1 *6 Minimum OFF-Tim 2 *6 OCP Terminal Threshold Voltage OCP Terminal Current BD Terminal Threshold Voltage 1 BD Terminal Threshold Voltage 2 BD Terminal Input Current Stand-by Mode Switching Time 1 *6 Stand-by Mode Switching Time 2 *6 ABS Terminal Threshold Voltage 1 ABS Terminal Threshold Voltage 2 ABS Terminal Charging Current ABS Terminal Discharging Current FB/OLP Terminal Threshold Voltage FB/OLP Terminal Current OLP Delay-Time OVP Operating Voltage Latch Circuit Holding Current *7 Latch Circuit Releasing Voltage *7 TSD Operating Temperature *8
*6 Refer to the specifications for details.

Ver.0.1 Unit V V mA A sec sec sec V A V V A sec sec V V A A V A ms V A V *9 Conditions

Terminal 3-2 3-2 3-2 3-2 5-2 5-2 7-2 7-2 7-2 4-2 4-2 4-2 4-2 6-2 6-2 6-2 3-2 3-2 3-2 -

(Example: STR-X6469) Ratings Symbol MIN TYP MAX VIN(ON) 16.3 17.9 19.9 9.3 41.0 5.4 7.0 -0.99 70 0.4 1.0 -100 2.1 5.2 0.85 2.8 135 10 6.8 70 20 25.5 8.0 140 10.2 47.0 6.0 8.0 -0.89 160 0.5 1.2 2.8 6.7 1.0 3.1 165 14 7.2 105 40 27.5 9.0 11.1 8 100 52.5 6.8 9.0 -0.79 340 0.6 1.4 100 3.6 8.7 1.15 3.4 195 18 7.7 135 60 29.8 170 10.5 -

VIN(OFF) IIN(ON) IIN(OFF) TOFF(MAX) TOFF(MIN1) TOFF(MIN2) VOCP IOCP VBD(1) VBD(2) IBD TSTB(1) TSTB(2) VABSTH(1) VABSTH(2) IABS(OUT) IABS(IN) VOLP IOLP TOLP VIN(OVP) IIN(H) VIN(La.OFF) Tj(TSD)

*7 Latch Circuit represents the circuit operated by OVP, TSD, and OLP. *8 Reference value. *9 Refer to the specifications for details since the values are different for each product.

Electrical Characteristics of MOSFET (Ta=25) Parameter Drain to Source Breakdown Voltage *10 Drain Leakage Current ON-Resistance *10 Switching Time Thermal Resistance *10 Terminal 1-2 1-2 1-2 1-2 Symbol VDSS IDSS RDS(ON) tf ch-F

(Example: STR-X6469) Ratings MIN 800 TYP MAX 300 0.66 400 0.99 Unit V A ohms nsec /W Channel - Internal Frame *10 Conditions

*10 Refer to the specifications for details since the values are different for each product.

Page. 8

AC Input
V1
SE series
Error Amplifier

7. Application Circuit

STR-X6400 Application Note

S1

GND

D D

V +

STR-X6400 series

V2

ROCP ROCP

Page. 9

BD

S2

Control part
FB/OLP

GND

2 OCP ABS

S/GND

Ver.0.1

STR-X6400 Application Note

Ver.0.1

8. Functions of Each Terminal and Operation

8.1. VIN Terminal (Pin 3)
8.1.1. Start-up Circuit The start-up circuit detects the voltage at the VIN terminal (Pin 3), and the circuit starts and stops the operation of the control IC. The power supply circuit (VIN terminal input) of the control IC employs a circuit as shown in Fig.1. At start-up of the power supply, C3 is charged through the start-up The R2 value should be selected to limit the current to no resistor R2.
1 D 3 VI N S/ N 2 GD D2 C3 R2 P

less than the holding current of the latch circuit (170A MAX), which will be described later, to flow at the minimum AC input voltage. However, when the R2 value is too large, the current charging C3 after AC input will be reduced. Thus, a longer time is required to reach the start voltage.

STR-X6400
Fig.1. Start-Up Circuit 1

The VIN terminal voltage falls immediately after the control circuit starts its operation, but the voltage drop ratio is reduced by increasing the C3 capacitance. Therefore, when the drive winding voltage is delayed in rising, the VIN terminal voltage does not reach the operational stop voltage to maintain start-up operation. C3. In general, a power supply operates with C3 values between 22~100F , and the R2 values of 33k~100k for wide input range of 100V, and 82k~330k for 200V input for start-up. As shown in Fig.2, circuit current, before control circuit start-up, is regulated at maximum 100A MAX(VIN=15V, Ta=25), and the higher value resistance Rs is applicable. The control circuit starts its operation via the Start-Up Circuit, as soon as the VIN terminal voltage reaches 17.9V(TYP), at which point the current consumption increases. When the VIN terminal voltage drops lower than 10.2V(TYP), the Under Voltage Lock Out (UVLO) function stops the 100 A M ) ( AX control operation, and returns to the start-up mode.
10 . V 2 ( TYP ) 1 V 5 17 . V 9 (TYP )

However, if C3

capacitance is too large, the time after AC input for operation start becomes longer since it takes longer to charge

IN

I N

V IN IN

Fig.2. VIN Terminal Vol. - Circuit Cur. IIN

Page. 10

STR-X6400 Application Note

8.1.2. Drive Windings After the control circuit starts its operation, drive winding D voltage, which being rectified, provides power to the IC. Fig.3 shows the start-up voltage waveform of the VIN terminal. The drive winding voltage does not rise up to the set voltage immediately after the control circuit starts its operation, and the VIN terminal voltage starts falling. Because the operational stop voltage is set as low as 11.1V(MAX), the drive winding voltage reaches stabilized voltage before falling to the operational stop voltage, and the control circuit continues operation. The correct drive winding voltage, during normal power supply operation, results from setting the number of the windings so that the final voltage of C3 shall be higher than the operational stop voltage [VIN(OFF) 11.1V(MAX)] and lower than the OVP operating voltage [VIN(OVP) 25.5V (MIN)]. In an actual power supply circuit, there may be a case where the VIN terminal voltage varies due to the value of secondary output current as shown in Fig.4. This is due to the low current of the STR-X6400, because the C3 is charged up to the peak value by the surge voltage generated after the MOSFET is turned OFF. In order to prevent this, add a resistor having several ohms to several tens of ohms (R7) in series with the rectifier diode as shown in Fig.5. The optimum resistance value of this additional resistor should be determined in accordance with the specs of a transformer, since the VIN terminal voltage is varied by the structural differences of the transformer. Furthermore, the variation of the VIN terminal voltage becomes worse due to an inaccurate coupling between the primary and the secondary winding of the transformer (the coupling between the drive winding D and the stabilizing output winding for the constant voltage control). Thus, in designing the transformer, drive winding D should be carefully designed.
11 .1V MAX ) (

Ver.0.1

17 .9V

V IN

Control Circuit Operation Start

(TYP )

Drive Winding Voltage

Operation Failure Time V in (A ) N C O

V IN

Fig.3. Waveform of VIN Terminal Vol. at Start-Up

R7 Without R7

R7 With R7 ou t
Fig.4. Output Current Iou t-VIN IOUT - V Terminal Vol.

I N

D2 3

R7 D

STR-X6400 S/ N GD 2

V IN

C3

Addition

Iou t Fig.5. Effective Auxiliary Power Supply Circuit to Output Current IOUT

Page. 11

STR-X6400 Application Note 8.1.3. Overvoltage Protection Circuit

operates, providing a latch mode, which stops its oscillation.

Ver.0.1

When the voltage exceeds 27.5V (TYP) across the VIN and the GND terminals, the OVP circuit of the control IC Generally, the VIN terminal voltage is supplied from the drive winding of the transformer, and the voltage is proportioned with the output voltage; thus, the circuit also operates at the overvoltage output in the secondary side, such as in the case of the voltage detection open circuit. In this case, the secondary output voltage when the overvoltage protection circuit operates is obtained from the formula shown below.

VOUT (OVP)

VOUT at Normal Operation VIN Terminal Voltage at Normal Operation

27.5V (TYP)

(1)

8.1.4. Latch Circuit The Latch Circuit is a circuit holds the oscillator output low, and stops the power supply circuit operation when the OVP, TSD, or OLP circuits operate. The holding current of the latch circuit is 170A MAX (Ta=25) when the VIN terminal voltage is minus 0.3V below the operational stop voltage. In order to avoid malfunction caused by noise, the delay time is set by a timer circuit incorporated in the IC. Thereafter, the latch circuit starts operation when the OVP, TSD, or OLP circuits operate longer than the set time. The VIN terminal voltage, however, will drop even after the latch circuit starts its operation, because the constant voltage (Reg.) circuit of the control circuit continues operation and maintains higher circuit current.

17.9V TYP 10.2V TYP

VIN
Fig.6. VIN terminal Vol. Waveform at Latch Circuit ON

Where the VIN terminal voltage falls lower than the operation stop voltage (10.2V TYP), the voltage starts rising as the circuit current becomes below 170A (Ta=25). Where the VIN terminal voltage reaches the operation start voltage (17.9V TYP), it falls as the circuit current is increased again. Consequently, the latch circuit prevents the

VIN terminal voltage from rising abnormally by controlling the voltage between 10.2V (TYP) and 17.9V (TYP). The Fig.6 shows the voltage waveform when the latch circuit is in operation. The cancellation of the latch circuit is made by reducing the VIN terminal voltage below 9V, and generally, it is restarted by AC input switch-off of the power supply.

Page. 12

STR-X6400 Application Note 8.2 OCP Terminal (Pin 5)

8.2.1 Minus Detecting Type The OCP circuit in the STR-X6400 series is a pulse-by-pulse type that detects the peak drain current of the MOSFET every pulse and reverses the oscillator output. As shown in Fig.7, the overcurrent detecting resistors R5, R4, and capacitor C5 are added as external components. The external components, R4 and C5, form a filter circuit to prevent surge current when the MOSFET is turned ON. The OCP circuit is to turn OFF the MOSFET when the OCP terminal voltage reaches the VOCP, due to the voltage generated in overcurrent detecting resistor R5, when the switching current flows into the MOSFET at turn-ON. The threshold voltage VOCP of the OCP terminal is set at 0.89V(TYP). The OCP circuit employs the minus detecting circuit, hence voltage V3 inside the MIC is created by dividing the voltage between V1 and R5 with divider RB1, RB2, and R4.
Reg.V1 RB1

Ver.0.1

P D

LOGIC

DRIVE

2 S/GND Filter V3
R5ROCP

RB2 OCP

C5 V4 R4

OCP V2

Fig.7. Minus Detecting Type OCP Circuit

Since the RB1 and RB2 are resistors inside the IC, the tolerance (rated as IOCP for the products) of those resistors is important, and its effects are minimized by using the smaller value for R4 (100 etc). 8.2.2 Notes for OCP Circuit The OCP circuit needs to be designed with consideration to the tolerance spread of ROCP(R5), VOCP, and IOCP. The tolerance of the OCP circuit (MAX/MIN of the drain current) is indicated as shown below: Drain Current MAX Detecting Resistor ROCP MINVOCP MIN, IOCP MAX (2) (3)

Drain Current MIN Detecting Resistor ROCP MAXVOCP MAX, IOCP MIN

To examine the above conditions, the samples of VOCP MIN or IOCP MAX are not to be made; therefore formula (2) and (3) are to be studied with calculating the ROCP from below formula (4) and (5), and by applying the ROCP, VOCP and IOCP with measuring the value experimentally.

Drain Current MAX ROCP ' =

VOCP ( S ) + R4 IOCP( S ) VOCP( S ) (4) ROCP 0.95 VOCP( MIN ) VOCP ( S ) + R4 IOCP(MAX )
(5)

Drain Current MIN ROCP ' =

VOCP( S ) + R4 IOCP( S ) VOCP( S ) ROCP 1.05 VOCP(MAX ) VOCP( S ) + R4 IOCP(MIN )

VOCP
R5 IOCP

*Consider the distribution of:

VOCP(S), IOCP(S): The measured value of the samples; VOCP, IOCP.

Refer to the measured circuit 2 on the specs

for the measuring. In case the samples measured values are required, please contact your

Page. 13

V5

STR-X6400 Application Note

nearest Sanken sales office.

Ver.0.1

ROCP: Assuming the typical value of the OCP resistor R5 as 5 for the ROCP distributions. The distribution of R4 is negligible since its effect is minor. The OCP circuit can be studied with the distributions (VOCP, IOCP, and ROCP) by employing the samples measured value and ROCP experimentally. 8.2.3 Overload The output characteristics of the secondary side, when the OCP circuit operates due to the overload of the secondary side output, are shown in Fig.8. The output voltage drops with overload, the drive winding voltage of the primary side also falls proportionally, and the VIN terminal voltage falls below shutdown voltage to stop the operation. In this case, as the circuit current also decreases simultaneously, and VIN terminal voltage rises by the Rs charging current, and the circuit re-operates intermittently, at the operational start voltage. However, where a transformer has many output windings and the coupling intermittent because the primary winding voltage does not drop. protection can be provided by the OLP circuit, as described later. 8.2.4 Compensation Circuit of Input for OCP Circuit In the STR-X6400 series, the OCP detects the peak value of the drain current of the MOSFET; therefore when the input voltage is large, the output voltage is increased at protection circuit operation, as shown in Fig.8. In order to prevent this, it is effective to lay out the circuit as shown in Fig.9 (resistor RH), and add a bias in proportion to the input voltage. The compensation is provided by dividing the voltage(VD) generated at the drive winding D with R4 and RH, and combining the voltage in proportion to the input voltage of the OCP terminal. In this case,
2 S/GND ROCP R5 V5 C5 R4 V4 RH OCP D STR - X6400 V + D P

Vout Vou t

No gap in AC by compensation AC AC High

A C AC

AC Low

Iout
Fig.8. Power Supply Output Overload

Iou t

Characteristics

is not sufficient, and even if the secondary output voltage drops in overload mode, the operation may not be Although the intermittent operation may not occur,

BD

Cont

assuming the voltage generated when the MOSFET is turned ON as VD, the voltage generated at R4 as VR4, and the voltage generated at ROCP[R5] as VROCP; then the V4 voltage imposed on the OCP terminal is compensated as shown below.

Compensated Current

V 4 = VROCP + VR 4 = VROCP + VD

R4 R4 + RH

Fig.9. OCP Compensation(6) Circuit

Page. 14

STR-X6400 Application Note

Ver.0.1

Winding No. of VD VD = (Voltage Input after smooting AC ) (7) Winding No. of Pr imary Windings
Where the R4 is 100, normally the RH is 8.2k~22k. The drain current, which is overloaded even if the input voltage is low, shall be decreased due to this compensation. The formula (6) does not include that the AC voltage and the peak value of the drain current, which are not in proportion to the voltage drop of R4 x IOCP; therefore, each fixed number needs to be adjusted in order to set the correct operating point of the OCP circuit, as calculated from formula (6).
W/o Compensation Fixed Pout

V4 Vol V4 V5. V5 Vol

After Compensation

R4 Compensated Vol. by R4

Pout

There are two advantages to adding this external circuit:

1). When the input voltage is large, the drain current of the MOSFET is controlled at low level; thus the voltage stress to the MOSFET at start-up and at light load is also reduced by lowering the surge voltage caused by the transformer.

VIN(AC)

Fig.10. Compensation for OCP Operation Point to Input Voltage

2). The current stress to the rectifier diodes of the secondary side is reduced since the output power is controlled.

8.3 FB/OLP Terminal (Pin 6)

The operation of FB/OLP terminal can be divided into; (1) at normal operation (constant voltage control circuit operation), (2) at overload operation, and at (3) power OFF. 8.3.1 Constant Voltage Control Circuit
+B

STR-X6400
D
Powe rMOSFE T Tu rnOFF Signal

S SE GND

Drain Current
GND

V8

LOGIC

DRIVE

GND
2 S/MICGND

Current Mirror IOLP

V4
FB/OLP R13 1k PC1 C14 R12 D5

OLP

V7 RFB C15 CFB

V6 V7
GND

CFB RFB

72V

Latch

PowerOFF Reset V6
ROCPR5

FB

V8
C5 V4 R4

OCP V2

Fig.11. Constant Voltage Control Circuit

The constant voltage control is made by varying the ON-time of the MOSFET, which is applied as the charging time to the internal CFB of the IC. During OFF-time, Quasi-Resonant operation synchronized with the reset signal from a transformer is applied. When there is no reset signal from the transformer, the OFF-time is determined by the PRC operation, which fixes the OFF-time by the internal oscillating circuit of the IC. The block diagram at the constant voltage control is shown in Fig.11, and Fig.12 shows the timing chart.

GND

OCP

(a) (a)Heavy Load

(b) (b)Light Load

Fig.12. Timing Chart of Constant Voltage Control

Page. 15

STR-X6400 Application Note

into the No.6 terminal by PC1.

Ver.0.1
The FB current is input to RFB, CFB, and FB comparator through the internal

The constant voltage control uses the control signal (FB current) flowing from the secondary side error-amplifiers(SE) current mirror circuit of the IC, and the input terminal of the FB comparator, the voltage waveform, which reversed drain current, is to the input. In the overload mode, as shown in Fig.12(a), the charging current to the CFB is decreased as the FB current decreases, and it lengthens the ON-width. During this interval, the control IC is Due to the protected by combining the current inputs to the FB comparator. While in the light load mode, as shown in Fig.12(b), the ON-width decreases as the charging current to the CFB increases with increasing the FB current. bias through RFB, the circuit is laid out to restrict the rapid increase of the FB current. 8.3.2 Constant Voltage Control and OLP Circuit The IOLP current (105A TYP) at the constant voltage control flows into the photo-coupler PC1 along with the FB current. The IOLP current (105A TYP) is supplied at the constant current circuit; therefore where the photo-coupler PC1 value is goes below IOLP, the terminal voltage is 3.1V approx. The current flowing to the photo-coupler is: At large load: IOLP+FB current (several tens A approx.) = 100~200A approx. (8) At medium load: At small load: IOLP+FB current (200A approx.) = 200~400A approx. IOLP+FB current (several hundreds A approx.) = 400~800A approx. (9) (10)

When the OLP operates, as shown in Fig.11, a Zener diode D5 and a capacitor C14 are to be connected in series to control the transient response at normal operation. A Zener diode having hard-break characteristics should be selected, and for the normal application, 5.6B (Rohm etc.) is recommended. 8.3.3 Overload Operation The output voltage of secondary side drops in the overload mode (when drain current is controlled by the OCP operation), and the error- amplifier of the secondary side and the photo-coupler PC1 are cut off. As a result of this, the FB/OLP terminal voltage starts increasing by IOLP as shown in Fig.13, and when the FB/OLP terminal voltage reaches VOLP (7.2V TYP), the oscillation stops and it switches the operation to the latch protection mode. Since the IOLP is the constant current circuit, the time to the latch protection can be calculated from:
C14 (Capacity of the Condenser) x V (Electrolytic Capacitor Charging Voltage) = I (IOLP current value) x t (Time) (12)
FB/OLP Flowing Cur. 0A
FBCur. IOLP

Normal Operation

Over Loaf OCP

Oscillation Stop VOLP 7.2V typ

FB/OLP Terminal Vol.

VzD5 3.1V typ

0V

Fig.13. Timing Chart at Overload

Due to the voltage dependency characteristics of the FB/OLP terminal voltage, the IOLP decreases while the FB/OLP terminal voltage increases. The application should be studied carefully, considering the actual load conditions, since the actual value and the value from the formula (12) may not match completely. Furthermore, at the start-up of the power supply, since the photo-coupler is cut off and the FB current value approaches zero, latch protection operation needs to be confirmed.

Page. 16

STR-X6400 Application Note

8.3.4 Operation at Power OFF Fig.14 shows the reset circuit. The capacitor is discharged by the internal The reset circuit does not start its
FB/OLP

Ver.0.1

reset circuit of the IC at power OFF.

1k 1k
5.6B

operation while the internal constant voltage circuit is operating.

PowerOff Reset Reset Circuit at

Power OFF

Fig.14. Reset Circuit

8.3.5 Notes for Additional Circuit Once the power is turned ON, this OLP circuit does not have the discharging route from the additional capacitor. Therefore, there may be a case where the OLP circuit operates even in the intermittent OCP operation. In order to provide a discharging path, the discharging The value of the resistor resistor is to be connected in parallel with the capacitor.
FB/O LP

1 k
5. 6B

is 100k~220k approx, assuming 5~20% of IOLP is diverted.

Fig.15. Discharging Resistance Circuit

8.3.6 Cancellation of OLP Circuit At overload or start-up mode, the OLP operation is cancelled by inserting the Zener diode having 5.6B between the FB/OLP terminals.

FB/OLP

1 k
5.6B

Fig.16. OLP Cancellation Circuit

Page. 17

STR-X6400 Application Note 8.4 Quasi-Resonant and Bottom-Skip Operation

8.4.1 Quasi-Resonant operation and BD Terminal
+

Ver.0.1

The Quasi-Resonant operation matches the timing of the MOSFET turn-ON to the bottom point of the voltage resonant waveform after a transformer releases the energy (i.e., 1/2 cycle of the resonant-frequency). As shown in the Fig.17, the voltage resonant capacitor C4 is connected between the Drain and the Source terminal, and the delay circuit C10, D3, R9, and R10 are to be connected between the drive winding D and the BD terminal (No.7). When the MOSFET is turned OFF, the Quasi-Resonant signals, which are derived from the fly-back voltage generated at the drive windings, operate both the internal BD1 and 2 of the IC, which provides the Quasi-Resonant operation.

C1

R2 Start-up Resistance D2 V Control BD

R7 D D

C2

R9

C10 R10

BD1

0.5V

BD2

1.2V

Fig.17. Quasi-Resonant and Delay Circuit

Due to the operation of the delay circuit, even if the energy release from the transformer is completed, the Quasi-Resonant signals imposed on the No.7 terminal do not drop immediately. This is because C10 is discharged by R10, and after a set period, the voltage drops to the threshold voltage VBD(1)0.5V and below. Consequently, the delay time is to set by adjusting C10 while monitoring the operating waveform, and the delay time is set to allow the MOSFET to turn ON when the VDS of the MOSFET is at its lowest level. In addition to this Quasi-Resonant operation, to allow control of the oscillating frequency at light to medium load, there is a built-in Bottom-Skip function, which increases the OFF-time in accordance with the load (Refer to Fig.21). The timing between the Quasi-Resonant and the Bottom-Skip shall be described below. When the Quasi-Resonant signal voltage imposed on the BD terminal is below VBD(2)1.2V, the internal oscilation circuit starts the ON-time controlled PRC operation with the fixed OFF-time (TOFF46sec). The PRC operation occurs when drive winding voltage is low, such as in start-up mode or short-circuit, and reduces current stress in the MOSFET as the frequency decreases. When the voltage is above VBD(2)1.2V(6.0V MAX) or over, the internal oscilation circuit operates, and switches the OFF-time to either TOFF(MIN1) or TOFF(MIN2), and it fixes the OFF-time during this period. When the voltage is held higher than VBD(1)0.5V after it exceeds the VBD(2) 1.2V, the MOSFET will remain OFF. Thus it prevents malfunction with the voltage difference of VBD(1) and VBD(2). Since the voltage imposed on the BD terminal is 6V (MAX), the Quasi-Resonant signals to the BD terminal are to be set below that voltage. The impedance of internal comparator is higher compared to that of the conventional STR-F6600 series; therefore the loss from the resistor is reduced by using higher resistor value for R9 and R10.

Page. 18

STR-X6400 Application Note

8.4.2 Waveform Input to the BD Terminal and Internal Standard Time As shown in Fig.18, the transition between the QuasiResonant and the Bottom-Skip mode compares TB1 and the internal standard time TOFF(MIN1)/TOFF(MIN2). The switching between the normal operations (the Quasi- Resonant and the Bottom-Skip), which will be described later, and the stand-by operation (Auto PRC and the intermittent oscillation) is achieved by comparing TB2 and internal standard time TSTB(1)/TSTB(2). 8.4.3 Bottom-Skip Operation
VDS
GND

Ver.0.1

TB2
VBD VBD(2) VBD(1)
GND
There is the Delay Time caused by the Step-drive and the Delay Time

inside the IC IC

TB Fig.18. Waveform of BD Terminal Input Vol.

During Bottom-Skip mode, the turn-ON operation is prohibited during TOFF(MIN1)/TOFF(MIN2) which is the internal standard time of the IC. The turn-ON operation is provided when the BD terminal voltage drops lower than VBD(1). The Quasi-Resonant operation (Fig.19(a) and Fig.20) is provided at heavy load, and at light and medium load, the Bottom-Skip operation (Fig.19(b) and Fig.21) skipping VDS is provided.

VDS IDS VBD TB1

M in mu i m OFF T me i
T OFF M I 1 ) ( N

IDS VBD (2 )

VDS

VBD (1 )

TB1
T OFF M I 2 ) ( N

Bo t to De tec tor m Ou tpu t Dr ive Ou tpu t

O N (a) Heavy Load

OFF

(b) Light Load

(a) ) eavy load (b) )L igh t load (b Light load (a Heavy load H Fig.19 Timing Chart of the Bottom-Skip Quasi-Resonant Operation
The switching between Fig.19 (a) and (b) is provided automatically by comparing the internal standard time TOFF(MIN1) or TOFF(MIN2) and TB1. The TB1 is described as the time from the MOSFET turn-OFF to the time when the TB1 exceeds VBD(2) and drops below VBD(1).
8.4.3.1 Fig.19(a) Quasi-Resonant TB1 becomes longer than TOFF(MIN1) at the Quasi-Resonant point, and when the load becomes lighter than this mode, TB1 becomes shorter, as the energy releasing time of the secondary side becomes shorter. Consequently, it switches to the Bottom-Skip mode where TB1 becomes shorter than TOFF(MIN1), and the internal standard time switches to TOFF(MIN2) automatically. 8.4.3.2 Fig.19(b) Bottom-Skip TB1 becomes shorter than TOFF(MIN2) at the Bottom-Skip mode, and when the load becomes heavier than this mode, TB1 becomes longer, as the energy releasing time of the secondary side becomes longer. Consequently, it switches back to the Quasi-Resonant mode where TB1 becomes longer than TOFF(MIN2), and the internal standard time switches

Page. 19

STR-X6400 Application Note

to TOFF(MIN1) automatically.
AC230V Po120W 2uS/div

Ver.0.1

VDS 200V/div

AC230V Po30W 2uS/div

VDS 200V/div

IDS 1A/div

IDS 1A/div

Fig.20 Waveform of Quasi-Resonant automatically. 8.4.4. Hysteresis Function

Fig.21 Waveform of Bottom-Skip

As described above, the internal standard time of the IC (TOFF(MIN1), TOFF(MIN2)) provides the Hysteresis operation

Internal Standard Time

Bottom-Skip TOFF(MIN2)

The fixed TOFF(MIN) without the Hysteresis function is shown in Fig.24. In this case, with the specific input/output conditions, it may have both the operations of the Bottom-Skip and the Quasi-Resonant. For example, the Bottom-Skip is provided where the load becomes lighter at the QuasiResonant operation and TB1 becomes shorter than TOFF(MIN), and where the Bottom-Skip is provided, it lowers the oscillating frequency and increases both the OFF-time and the ON-time. than TOFF(MIN) again. As a result, TB1 (that

TOFF(MIN1)

Quasi-Resonant

TB1 Fig.22. Switching of Operation Mode

TB1

appears in next OFF-time) becomes longer, and the Quasi-Resonant mode is provided, and TB1 becomes longer As described above, the operation may not be stable with the fixed TOFF(MIN); therefore the bottom may skip or not, and the magnetic noise may be generated from the transformer. In order to avoid such the problems, Hysteresis needs to be added to TOFF(MIN).

TB1

TB1

Lighter Load

Heavier Load

(a)Light Load Quasi-Resonant

(b)Heavier Load

TOFF(MIN2)
Operation Margin TOFF(MIN1) Quasi Resonant Bottom-Skip Quasi -Resonant

Quasi-Resonant
Quasi-Resonant

TOFF(MIN)
Bottom Skip

TOFF(MIN)

Bottom Skip

The operation modes of the Quasi-Resonant and the Bottom-Skip are not be fixed without the Hysteresis which TOFF(MIN) is fixd

Bottom Skip

Time
Fig.23. Hysteresis Function

Time

Fig.24. Without Hysteresis Function

As shown in Fig.23, switching to the Quasi-Resonant is prevented by adding this Hysteresis function which makes

Page. 20

STR-X6400 Application Note

Ver.0.1

TOFF(MIN) from shorter TOFF(MIN1) to longer TOFF(MIN2) when the Quasi-Resonant is switched to the Bottom-Skip. Thus, this mode is stabilized. The operation of switching from Quasi-Resonant from the Bottom-Skip mode is opposite to the above described and provides stable operation. The function of Hysteresis is shown in Fig.22. As shown in Fig.25, there is a case in which it does not turn ON at the second VDS bottom, and instead turns ON at the third VDS bottom depending on the design of the transformer and the input/output conditions. In this case, the operational

VDS IDS VBD

TB1
T OFF M I 2 ) ( N

mode is not fixed at the switching point of the second and the M inmu i m OFF T me i third VDS bottom, and the second and the third bottom may appear at random. This kind of Hysteresis function is not TOFF(MIN2) and matched to the application is to be used.

Bo t to mDe tec tor provided in this series, thus, the IC having TOFF(MIN1) and Ou tpu t Dr ive Ou tpu t
Fig.25. Waveform of Bottom-Skip

8.5 Operation at Stand-By

8.5.1 Switching Time of Stand-by (T STB(1)/T STB(2)) Mode and Operation Mode The STR-X6400 series has two types of built-in stand-by functions to match various load modes. The switching losses cannot be neglected at light load (several % of the load), since the oscillating frequency becomes more than 100kHz even at the Bottom-Skip operation. Therefore, the STR-X6400 series has a built-in Auto PRC function, which controls the ON-time automatically with a fixed OFF-time of 46sec (22kHz), and at the light load (0% to several % of the whole load), as shown in Fig.26. Furthermore, it switches to the intermittent (burst) oscillation at the ultra light load (0% to 0.2% of the whole load), as shown in Fig.27.

AC230V Po15W 10uS/div

VDS 200V/div VDS 200V/div

AC230V Po0.1W 500uS/div

IDS 1A/div

ABS 2V/div

I DS 1A/div

Fig.26. Waveform of PRC Operation

Fig.27. Waveform of Burst Operation

Page. 21

STR-X6400 Application Note

The switching between the normal operation (the Quasi-Resonant and the Bottom-Skip), and the stand-by operation (PRC and burst mode), is determined by comparing the internal standard time for stand-by TSTB(1)/TSTB(2) of the IC and TB2 (refer to Fig.18). depends on independent circuits .
8.5.1.1 Normal Operation to PRC Operation

Ver.0.1
Normal Operation Heavy Load
Quasi-Resonant

TOFF(MIN1) TOFF(MIN2)

Bottom-Skip

TSTB(1)
Light Load

TSTB(2) TSTB(1)

PRCFixed OFF-Times 22kHz approx.

As shown in

Fig.28, TSTB(1)/TSTB(2) and TOFF(1)/TOFF(2)

Ultra Light Load

ABSIntermittent Oscillation several 100Hz

Fig.28. Relationship of Each Operation Mode

TB2 is longer than TSTB(1) during the normal operation, and when the load becomes lighter than this mode, TB2 becomes shorter, as the energy releasing time of the secondary side becomes shorter. Consequently, it switches to the PRC operation, which will be described later. In this mode, TB2 becomes shorter than TSTB(1) and the internal standard time switches to TSTB(2) automatically. 8.5.1.2 PRC Operation to Normal Operation TB2 is shorter than TSTB(2) at the PRC operation, and when the load becomes heavier than this mode, TB2 becomes longer, as the energy releasing time of the secondary side becomes longer. Consequently, it switches to the normal operation where TB2 becomes longer than TSTB(2) and the internal standard time switches to TSTB(1) automatically.

As described above, the Hysteresis characteristic applies to TSTB(1)/TSTB(2) the same as TOFF(MIN1)/TOFF(MIN2). The conditions of each operation (normal: TSTB(1), PRC: TSTB(2)) are held in the internal circuit, until the next TB2 is input. During PRC operation, it switches to the intermittent oscillation, since the IC recognizes the mode as the ultra light load, condition of TB2<TSTB(1) continues for a certain period. 8.5.2 ABS Terminal (Pin 4) and Intermittent Oscillation The oscillation circuit for the intermittent (burst) oscillation is incorporated in the STR-X6400 series, and Fig.29 shows the timing chart. Fig.30 shows the circuit diagram during intermittent operation, and Fig.31 shows the flow chart. The capacitor C8 (4700pF to 0.1F approx.) is to be connected No.4 terminal. The discharging circuit (IABS(IN)) operates continuously at the No.4 terminal, and the charging circuit (IABS(OUT)) operates when the conditions of ultra light load, which will be described later, are satisfied. drain current. required. During ultra light load mode, when TB2 becomes shorter (refer to Fig.18) and satisfies the condition of TB2<TSTB(1), C8 starts charging (IABS(OUT)=165A(TYP)). When the ABS terminal voltage rises and reaches 3.1V (TYP), it stops the charging and oscillation ceases. Due to this, it prevents malfunction, since the condition of TB2<TSTB(1) is required for a certain period. Furthermore, C8 continues discharging until it reaches VABSTH(1)=1.0V(TYP) through the discharging circuit (IABS(IN)=14A(TYP)) simultaneously as the oscillation is stopped. During ultra light load mode, C8 is charged and discharged, and the intermittent cycle length is determined, and the soft-start is simultaneously provided for the The ABS terminal should be short-circuited to GND when the intermittent oscillation feature is not

Page. 22

STR-X6400 Application Note

Ver.0.1

Output Voltage

STR-X6400 series D
G

LOGIC

DRIVE TB2 TSTB(1)?

Burst OSC V9

Drain Current G

SoftStart period

S/GND

OCP Output
Burst OSCV9 G ABS terminal and OCP Comp1&2 G ABS V3

IABS( OUT) ABS

IABS( IN) C8 V3

VABSTH(2) V ABSTH(1)

OCP Comp.2

OCP Comp.

V2

OCP Output G

OCP ROCP

Fig.29. Timing Chart of Intermittent Oscillation

Fig.30. Block Diagram at Intermittent Oscillation

Normal Operation Discharging Capacitor C8

Soft-start is provided when the oscillation starts by making use of the ABS terminal voltage variation that from 3.1V to 1.0V. The Comp.1, which is shown in Fig.30, is the OCP circuit of the MOSFET. Soft-start operation uses the detecting voltage V3 generated from the drain current, to minus () input of the OCP Comp.2, and the ABS terminal voltage is connected to plus (+) input. The down slope of the C8 becomes the voltage that controls the drain current. Therefore, the drain current is restricted in proportion to the C8 voltage. Consequently, the magnetic noise from the transformer is controlled because of the controlled increase of drain current, as shown in Fig.29. The intermittent oscillation will occur if the TB2<TSTB(1) hold at the time when the ABS terminal voltage is discharged by VABSTH(1)= 1.0V(TYP). Where the load of C8 charge level is secondary side increases and the condition of TB2<TSTB(1) is not satisfied, the ABS terminal voltage drops to 0V as it returns to the normal operation. held by the internal circuit until next TB2 is generated.
NO

TB2 <TSTB(1) YES

Normal Operation Charging Capacitor C8

NO

ABS Terminal>3.1V

YES
Oscillation Stop Discharging at Capacitor C8

Oscillation Start with Soft-Start

NO

ABS Terminal1V

8.6 Thermal Shutdown Circuit

Fig.31. Flow Chart

YES

This circuit that makes the latch operate when the frame temperature of the IC is above 140(MIN).

Since the

control IC and the MOSFET are built-in the same package, it also operates with overheating of the MOSFET. In the conventional STR-F6600 series, both the control IC and the MOSFET are mounted on the same frame (substrate), however in the STR-X6400 series, they are mounted in the separated frames. temperature between the control IC and the MOSFET is to be noted. Therefore, the difference of the

Page. 23

STR-X6400 Application Note 8.7 Step-Drive Circuit

The STR-X6400 series reduces turn-On noises by adopting the step-drive circuit for the MOSFET drive circuit as shown in Fig.32. The drive current at turn-ON is controlled at low current by RG.1 and makes the gate voltage increase gradually, and the gate voltage shall be raised rapidly through Rg.1+Rg.2 after approximately 0.8sec. The MOSFET drive voltage adopts the constant voltage drive circuit maintaining VDRV=8.4VTYP, and it is not affected by VIN. turned OFF. The MOSFET gate charge is discharged rapidly through Rg.3 when the MOSFET is
RG3
DRIVE REG

Ver.0.1

Control part
Delay RG1 RG2 D

S/GND

Fig.32. Step-drive Circuit

Consequently, in the STR-X6400 series, the MOSFET gate voltage is switched with a two-step waveform, and this provides an ideal drive, storing the sufficient gate voltage at normal drive by controlling the gate voltage and restricting the surge current flowing at turn-ON.

8.8 Typical Characteristics

The comparison of the conventional STR-F6600 and the STR-X6400 series, for oscillating frequency is shown in Fig.33, and Fig.34 shows its power efficiency. Both series provide the Quasi-Resonant mode at the maximum load; therefore, almost the same oscillating frequency and power efficiency are achieved. However, at medium load, there is a difference in the oscillating frequency and the power efficiency between those two series since the STR-F6600 series provides the Quasi-Resonant, and the STR-X6400 series provides the Bottom-Skip operation. Furthermore, at the ultra light load, because of the fact that the frequency of the STR-F6600 is above 200kHz, and the frequency of the STR-X6400 series provides intermittent oscillation approximately at 300Hz. The intermittent oscillating frequency at that time is approximately 7kHz, which reduces the switching losses considerably.

Oscillating Frequency [kHz]

220 200 180
STR-X6400 at AC240V STR-F6600 at AC240V

100 Power Efficiency [%] 90 80 70 60 50 40 30 20

Hysteresis Action

160 fkHz 140 120 100 80 60 40 20 0

Quasi-Resonant

Bottom-Skip PRC
BURST
0 20 40 60 80 PoutW

STR-X6400 at AC240V (Load LightHeavy) STR-F6600 at AC240V

10 0 0 20 40 60 80 PoutW 100 120

100

120

Fig.33. Typical Characteristics of Oscillating Frequency

Fig.34. Typical Characteristics of Power Efficiency

Page. 24