Embedded System Design (EC55)

Sunil MP Assistant Professor

Department of Electronics and Communication Sri Bhagawan Mahaveer Jain College of Engineering Jain University 2011-2012

Embedded System Design

2011/2012-ECE Department,SBMJCE

Unit 1
INTRODUCTION TO EMBEDDED SYSTEM
GENERAL PURPOSE PC: The following figure gives a generic architecture of a general purpose PC.

Large Scale Embedded Systems also will have similar structures as of a general purpose PC, Which is shown above. But, one basic difference in the hardware of a PC and an embedded system is that, in an embedded system there won't be any unwanted parts (generic parts, which are not used by the specific purpose for which the system is designed for). Some examples from the above figure are Graphics interface, Audio/Video interface etc.
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SYSTEM DESIGN VS SYSTEM ANALYSIS: The difference between these could be understood clearly from the following figure

We can represent the existence of any system as per the above figure. The system generates certain outputs from certain inputs in certain environmemental conditions. Now, if you have Input, output and the environmemental condition then, obtaining the system is System Design. Rather, if you have Input, System and Environmemental condition, then obtaining the Output is System Analysis.

GENERAL PURPOSE PC VS EMBEDDED SYSTEMS:

Many components are common In a PC, we need to write application specific programs for the purpose that we want An Embedded System is a system whose main function is not computational, but which is controlled by a computer embedded within it

General purpose PC with extra components will not make an Embedded System. But it would be an embedded system if it is converted permanently into an identifiable system and customized such that its sole purpose is to control a specific system.

Range of products which falls into this category is too much - It ranges from Toys to Space crafts. Embedded systems find applications in many areas like Toys, House utilities (Air Conditioner, Washing Machine, Oven, Burglar alarms etc.), Vehicle Industry (Car control etc), Industries (Networking, Other control systems, Factory automation etc), In simple words, anything that uses a microprocessor/microcontroller other than a general purpose PC is an embedded system. But one interesting point among all these is that the user may not be aware that a processor/controller is present in that.
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GENERIC BLOCK DIAGRAM OF AN EMBEDDED SYSTEM

EMBEDDED SYSTEM We can define embedded system as; it is a system that has embedded software and computer hardware, which makes it a system dedicated for a specific part of an application. Some of examples of an embedded system are in home utilities, office and in vehicles

REAL TIME SYSTEMS An operation within a larger dynamic system is called a real-time operation if the combined reaction- and operation-time of a task operating on current events or input, is no longer than the maximum delay allowed, in view of circumstances outside the operation is called a realtime systems.

Embedded System Design

2011/2012-ECE Department,SBMJCE

REAL TIME EMBEDDED SYSTEM RTES is precisely the union of subsystems to discharge a specific task coherently. RTES as a generic term may mean a wide variety of systems in the real world. A number of systems coexist to discharge a specific function in real time. EMBEDDED SYSTEM HARDWARE

Different parts/components of embedded system hardware are shown in the above block diagram.

Embedded System Design

2011/2012-ECE Department,SBMJCE

1. PROCESSOR Processor is generally used to control/configure other parts of the system. Embedded systems are

controlled by one or more main processing cores that are typically Microcontroller, Microprocessor, DSP, Single Purpose Processor and Application-specific processors. General-purpose Microprocessors Must add RAM, ROM, I/O ports, and timers externally to make them functional Make the system bulkier and much more expensive Have the advantage of versatility on the amount of RAM, ROM, and I/O ports

Microcontroller The fixed amount of on-chip ROM, RAM, and number of I/O ports makes them ideal for many applications in which cost and space are critical In many applications, the space it takes, the power it consumes, and the price per unit are much more critical considerations than the computing power.

Embedded System Design

2011/2012-ECE Department,SBMJCE

8-bit microcontrollers Motorolas 6811 Intels 8051 Zilogs Z8 Microchips PIC

Single-purpose processors A single-purpose processor is a digital circuit designed to execute exactly one program. For example, consider the digital camera. All of the components other than the microcontroller are single-purpose processors. The JPEG codec, for example, executes a single program that compresses and decompresses video frames. An embedded system designer creates a singlepurpose processor by designing a custom digital circuit. Using a single-purpose processor in an embedded system results in several design metric benefits and drawbacks, which are essentially the inverse of those for general purpose processors. Performance may be fast, size and power may be small, and unit-cost may be low for large quantities, while design time and NRE costs may be high, flexibility is low, unit cost may be high for small quantities, and performance may not match general-purpose processors for some applications. Application-specific processors An application-specific instruction-set processor (or ASIP) can serve as a compromise between the above processor options. An ASIP is designed for a particular class of applications with common characteristics, such as digital-signal processing, telecommunications, embedded control, etc. The designer of such a processor can optimize the datapath for the application class, perhaps adding special functional units for common operations, and eliminating other infrequently used units.
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Using an ASIP in an embedded system can provide the benefit of flexibility while still achieving good performance, power and size.

Digital-signal processors (DSPs) are a common class of ASIP, so demand special mention. A DSP is a processor designed to perform common operations on digital signals, which are the digital encodings of analog signals like video and audio. These operations carry out common signal processing tasks like signal filtering, transformation, or combination.

2. POWER SUPPLY Rectifiers, Regulators, Battery are the main power sources used. It generates specific voltages required by different parts of the system. There would be more than one voltage. Proper isolation to be provided between different power supplies. Voltage and current requirements vary according to the logic families used in the system. It should be of very high efficiency. It should support features like Power Sequencing, Power Redundancy, Hot swap Capacity, Inrush Current control etc. Normally there would be a Poweronreset generation circuit along with the power supply circuit. There should be methods for power saving operation

Power Supply Design for Microcontroller from AC source

Transformer - steps down high voltage AC mains to low voltage AC.

Embedded System Design

2011/2012-ECE Department,SBMJCE

Rectifier - converts AC to DC, but the DC output is varying. Smoothing - smoothes the DC from varying greatly to a small ripple. Regulator - eliminates ripple by setting DC output to a fixed voltage. 3. RESET CIRCUITRY: It is used to reset the system initially or during some fault situations. Different types of reset a) Power-on Reset (POR) b) External Reset -MCLR Reset during normal operation -MCLR Reset during SLEEP c) Watchdog Timer (WDT) Reset d) Software RESET When the microcontroller powers up, it must start running its program from its. This will only happen if explicit circuitry is built in to detect power-up and force the Program Counter to zero. A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified.

(a) Power-on Reset (b) Power-on Reset, with discharge diode and protective resistor. (c) User Reset button.

Embedded System Design

2011/2012-ECE Department,SBMJCE

WATCHDOG TIMER The watchdog timer is designed to automatically reset the MCU if the program malfunctions, by stopping or getting stuck in loop. This could be caused by an undetected bug in the program, an unplanned sequence of inputs or supply fault. A separate internal oscillator and counter automatically generate a reset about every 18 ms, unless this is disabled in the configuration word. If the watchdog timer is enabled, it should be regularly reset by an instruction in the program loop to prevent the reset. If the program hangs, and the watchdog timer reset instruction not executed, the MCU will restart, and (possibly) continue correctly, depending on the nature of the fault.

4. CLOCK/OSCILATOR It generates timing for the entire system. Clock would be generated by using crystal, oscillator circuits, components like resistor,

Capacitor along with some circuit inside the processor. Accuracy, stability, Noise etc are some of the parameters to be looked into. Clock frequency, duty cycle, rise and fall time, jitter etc are some factors affecting the System operation.

Oscillator Types The main oscillator in microcontrollers can be a i) ii) iii) Crystal oscillator RC oscillator An external clock.

Some devices also have an internal RC oscillator. Increasing the oscillator frequency shortens the length of the machine cycles and therefore the time needed for executing instructions, but also increases power consumption. The types of oscillator can be selected by the configuration bits. These also select specific modes of operation for crystal or ceramic oscillators.
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i).CRYSTAL/CERAMIC RESONATOR OPERATION

If greater precision is required, especially if the program uses the hardware timers to make accurate measurements or generate precise output signals, a crystal (XTAL-Y1) oscillator is needed.
ii). RC OSCILLATOR MODE

The RC oscillator frequency is a function of the supply voltage, the resistor (R1) and capacitor (C1) values and the operating temperature. In addition to this, the

types

will also

affect

the

oscillation

frequency, especially for low CEXT values.

oscillator frequency will vary from unit to unit due to normal process parameter variation. Further -more, the difference in lead frame capacitance between package

iii). EXTERNAL CLOCK INPUT OPERATION

OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current.

The EC Oscillator modes require an external clock source to be connected to the

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5. MEMORY It is an important part of a microcontroller system, can be classified into two types: program memory and data memory. Program memory stores the program written by the programmer and is usually nonvolatile. Data memory stores the temporary data used in a program and is usually volatile There are basically 6 types of memories, 3 are summarized as follows: i) RAM
RAM, random access memory, is a general purpose memory that usually stores the user data in a program. RAM memory is volatile in the sense that it cannot retain data in the absence of power i.e., data is lost after the power is turned off. Most microcontrollers have some amount of internal RAM, 256 bytes being a common amount, although some microcontrollers have more, some less. Memory can usually be extended by adding external memory chips.

ii) ROM
ROM, read only memory, usually holds program or fixed user data. ROM is nonvolatile. If power is removed from ROM and then reapplied, the original data will still be there. ROM memory is programmed during the manufacturing process, and the user cannot change its contents. ROM memory is only useful if you have developed a program and wish to create several thousand copies of it.

iii) FLASH EEPROM

Flash EEPROM, a version of EEPROM memory, has become popular in microcontroller applications and is used to store the user program. Flash EEPROM is nonvolatile and usually very fast. The data can be erased and then reprogrammed using a suitable programming device. Some microcontrollers have only 1K flash EEPROM while others have 32K or more.

6. TIMERS Timers are important parts of any microcontroller. A timer is basically a counter which is driven from either an external clock pulse or the microcontrollers internal oscillator. A timer can be 8 bits or 16 bits wide. Data can be loaded into a timer under program control, and the timer
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can be stopped or started by program control. Most timers can be configured to generate an interrupt when they reach a certain count usually when they overflow. The user program can use an interrupt to carry out accurate timing-related Operations inside the microcontroller. 7. INTERRUPTS Interrupts are an important concept in microcontrollers. An interrupt causes the microcontroller to respond to external and internal (e.g., a timer) events very quickly. When an interrupt occurs, the microcontroller leaves its normal flow of program execution and jumps to a special part of the program known as the interrupt service routine (ISR). The program code inside the ISR is executed, and upon return from the ISR the program resumes its normal flow of execution. 8. REAL-TIME CLOCK A real-time clock enables a microcontroller to receive absolute date and time information continuously. Built-in real-time clocks are not common in most microcontrollers, since the same function can easily be implemented by either a dedicated real-time clock chip or a program written for this purpose. It keeps the "real time", which would be used by certain processes in the system. It is basically a timer circuit. It should keep the time even without system power. Main requirement for this is the power availability even if the system is powered down. Small batteries, high value capacitors can be used for this. Charge storage capacity of the battery/capacitor and power dissipation of the circuitry decides the time for which the circuit works without system power.

9. INPUT, OUTPUT, I/O INTERFACES These are used for reading data, controlling some outputs, interacting with some other systems etc. Could be parallel or serial.
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Normally implemented as general purpose ports. Could be internal or external to the processor. If external, extra hardware is required to implement. There would be switches, LEDs, Relays, Connectors Safety (User safety as well as system safety) is a major concern of this design as this is the part which has a direct contact with the user.

There would be ports for system control, Network connectivity, debugging code downloading etc.

10. INTERRUPT HANDLER As the name implies, it handles different interrupts in the system. As in the previous cases, it also could be internal or external to the processor and external hardware is required if it is external. This should control Interrupt Priority, masking, Vector etc.

11. APPLICATION SPECIFIC ICS (ASICS) Used for special applications. May need Special Controls/Configurations etc. Processor would do these.

EMBEDDED SOFTWARE IN A SYSTEM

(1) The human learns machine code. This is what programmers used to do sometimes in the very early days, laboriously writing each instruction in the binary code of the computer, exactly as the computer would then read it. This is incredibly slow, tedious and error-prone, but at least the programmer relates directly to the needs and capabilities of the computer. Machine code The instruction is in a language that is understood by that particular microprocessor. The binary code that is understood by the microprocessor is called machine code and consists of streams of binary bits. They are fed from the RAM or ROM memory chips in blocks of 8, 16, 32 or 64 depending on the microprocessor in use.
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The program is not friendly: 11000110 00010101 hardly compares with Add 15H to the number 25H for easy understanding. There is nothing about 11000110 which reminds us of its meaning add the following number to the number stored in the accumulator so a program would need to be laboriously decoded byte by byte. Assembly language, the second generation language

Assembly language was designed to do the same work as machine code but be much easier to use. It replaced all the ones and zeros wit letters that were easier to remember but it is still a low-level language. The assembly equivalent of our machine code example 11000110 00010101 is the code ADD A, m. This means add any number, m to the value stored in the accumulator. We can see immediately that it would be far easier to guess the meaning of ADD A, m than 11000110 00010101 and so it makes programming much easier. If we had to choose letters to represent the add command, ADD A, m was obviously a good choice. The code ADD A, m is called a mnemonic.

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Embedded System Design

2011/2012-ECE Department,SBMJCE

Assembler: An assembler is a software tool designed to simplify the task of writing computer programs. It translates symbolic code into executable object code. This object code may then be programmed into a microcontroller and executed. Assembly language programs translate directly into CPU instructions which instruct the processor what operations to perform. Therefore, to effectively write assembly programs, you should be familiar with both the microcomputer architecture and the assembly language. This is a compromise position. Every one of the computers instructions set is given a mnemonic. This is usually a three- or four-letter word that can be used to represent directly one instruction from the instruction set. The programmer then writes the program using the instruction mnemonics. The programmer has to think at the level of the computer, as he/she is working directly with its instructions, but at least the programmer has the mnemonics to use, rather than actually working with the computer machine code. Assembly and machine code are not portable. This means that they are designed to be used on a particular microprocessor and are generally not able to be used on another type. They also require the programmer to have knowledge of the internal layout or architecture of the microprocessor. Third-generation languages The third-generation languages were intended to make life easier. They were designed to improve the readability by using English words which would make it easier to understand and to sort out any faults (bugs) in the program. The process of removing bugs is called debugging. In addition, they should relieve the programmer of any need to understand the internal architecture of the microprocessor and so the program should be totally portable. Ideally the programmer should not even need to know what processor is being used. These languages are called highlevel and are all procedural. This is as if we go some way to asking the computer to learn our language. In an HLL, instructions are written in a form that relates in a recognizable way to our own language. Another computer program, either a compiler or an interpreter, then converts that program into the machine code that the computer can comprehend. The programmer now has a much easier time and can write very sophisticated programs. The following figure shows overview of generation of languages from first generation to third generation
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User is now, however, separated from the resources of the computer, and the program may be comparatively inefficient in terms of its use of memory and in its execution speed. Compilers In assembly language, we used an assembler program to convert the mnemonics to machine code. We usually refer to the conversions being from source code to object code but it means the same thing. In any high-level language, we use a compiler to produce the machine code. The compiler will also carry out the useful extras like error and syntax checking that we met with the assemblers. Compilers and assemblers are both software that is, they are programs designed to do a specific job. If we were using a PIC Microcontroller, and wished to program it using a particular language, say C, then we would have to purchase a C18 compiler. It would do just this job and nothing else. We could not adapt it in any way to accept a different high-level language or target it at different controllers.

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Embedded System Design

2011/2012-ECE Department,SBMJCE

LIBRARIES, LINKERS AND LOADERS LIBRARIES

When the designer has struggled through the process of devising assembly code for a particularly nasty formula it would make sense to store the answer away to allow its use on another occasion. A collection of these solutions is called a library LINKERS Slotting these ready-made library routines into the main programs is performed by a linker which is another piece of software. The linker therefore joins or links together many separate pieces of code into one program ready for use. LOADERS The last job to be done is to load it into some RAM ready for use. Another piece of software is used to determine which addresses in the microprocessor system memory are available. This is called a loader. A loader also converts labels to their final addresses.
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The program development process

We will be studying this one in detail in the 6 th and 7 th chapter

Characteristics of Embedded systems: 1) Single-functioned: An embedded system usually executes only one program, repeatedly. For example, a pager is always a pager. In contrast, a desktop system executes a variety of programs, like spreadsheets, word processors, and video games, with new programs added frequently. 2) Tightly constrained: All computing systems have constraints on design metrics, but those on embedded systems can be especially tight. A design metric is a measure of an implementations features, such as cost, size, Performance and power. Embedded systems often must cost just a few dollars, must be sized to fit on a single chip, must perform fast enough to process data in real-time, and must consume minimum power to extend battery life or prevent the necessity of a cooling fan. 3) Reactive and real-time: Many embedded systems must continually react to changes in the systems environment, and must compute certain results in real time without delay. For example, a car's cruise controller continually monitors and reacts to speed and brake sensors. It must compute acceleration or decelerations amounts repeatedly
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within a limited time; a delayed computation result could result in a failure to maintain control of the car. In contrast, a desktop system typically focuses on computations, with relatively infrequent reactions to input devices. In addition, a delay in those computations, while perhaps inconvenient to the computer user, typically does not result in a system
failure.

Design challenge optimizing design metrics The embedded-system designer must of course construct an implementation that fulfills desired functionality, Unit cost: The monetary cost of manufacturing each copy of the system, excluding NRE cost. NRE cost (Non-Recurring Engineering cost): The monetary cost of designing the system. Once the system is designed, any number of units can be manufactured without incurring any additional design cost. Size: The physical space required by the system, often measured in bytes for software, and gates or transistors for hardware. Performance: The execution time or throughput of the system. Power: The amount of power consumed by the system, which determines the lifetime of a battery, or the cooling requirements of the IC, since more power means more heat. Flexibility: The ability to change the functionality of the system without incurring heavy NRE cost. Software is typically considered very flexible. Time-to-market: The amount of time required to design and manufactures the system to the point the system can be sold to customers. Time-to-prototype: The amount of time to build a working version of the system, which may be bigger or more expensive than the final system implementation, but can be used to verify the systems usefulness and correctness and to refine the system's functionality.
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Correctness: Our confidence that we have implemented the systems functionality correctly. We can check the functionality throughout the process of designing the system, and we can insert test circuitry to check that manufacturing was correct. Safety: The probability that the system will not cause harm.

DESIGN PROCESSES
1. 2. 3. 4. 5. 6. 7. Abstraction Hardware and Software architecture Extra functional Properties System Related Family designs Modular Design Mapping User Interfaces Design 8. Refinements

1. Abstraction: Each problem component first abstracted. Application software abstracted as concurrently running multiple threads and interrupt service threads 2. Hardware and Software architecture Assumed to consists multiple layers Each architectural layer be well understood before a design

3. Extra functional Properties Extra functionalities required in the system being developed be well understood from the design 4. System Related Family designs Families of related systems developed earlier taken into consideration during designing 5. Modular Design
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Decomposition of software into modules that are to be implemented.

2011/2012-ECE Department,SBMJCE

Embedded System Design

 (i) (ii) (iii)

Modules should be such that they can be composed (coupled or integrated) later. Effective Modular design should ensure effective function independence, cohesion and Coupling.

Be clearly understood and maintain continuity. Appropriate protection strategies are necessary for each module. A module is not permitted to change or modify module functionality.

For example, protection from a device driver modifying the configuration of another device

6. Mapping Mapping into various representations done considering the software requirements. For example, data flow in the same path during the program flow can be mapped together as a single entity. Transform and transaction mapping

7. User Interfaces Design Designed as per user requirements, analysis of the environment and system functions. Interface design validation- Customer validation

8. Refinements Each component and module design needs to be refined iteratively till it becomes the most appropriate for implementation by the software team

Five levels of abstraction from top level to bottom level in the design process
1. Requirements 2. Specifications 3. Architecture 4. Components 5. System Integration

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Embedded System Design

2011/2012-ECE Department,SBMJCE

1. Requirements

Complete clarity of required purpose, inputs, outputs, functioning, design metrics and Validation requirements for finally developed systems specifications. Consistency in the requirements

2. Specifications Clear specifications of Customer expectations from the product. Needs specifications for hardware, for example, peripherals, devices processor and memory specifications data types and processing specifications 3. Architecture data flow graphs program models software architecture layers and hardware architecture interfaces design system integration

Software architectural layers How the different elements -Data structures, databases, algorithms, control functions, state transition functions, process, data and program flow are to be organized What shall be design of data structures and databases that would be most appropriate for the given problem? Whether data organized as a tree- like structure will be appropriate? What will be the design of the components in the data?

4. Components
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Processor, ASIP and single purpose processors in the system

2011/2012-ECE Department,SBMJCE

Embedded System Design

Memory RAM, ROM or internal and external flash or secondary memory in the system

Peripherals and devices internal and external to the system Ports and buses in the system Power source or battery in the system

5. System Integration System integration is the bringing together of the component subsystems into one system and ensuring that the subsystems function together as a system

SYSTEM-ON-CHIP DESIGN & USE OF VLSI CIRCUITS DESIGN TECHNOLOGY

SoC as a complex integrated circuit, or integrated chipset, which combines the major functional elements or subsystems of a complete end product into a single entity. All interesting SoC designs include at least one programmable processor, and very often a combination of at least one RISC control processor and one DSP. They also include on-chip communications structures - processor bus (es), peripheral bus (es), and perhaps a high-speed system bus. Multi-Processor Systems-on-Chip (MPSoC), which combine the advantages of parallel processing with the high integration levels of SoCs, emerged as a viable solution to meet the demand for computational power required by applications such as network and media processors. The design of MPSoC typically involves integration of heterogeneous hardware and software IP components. The SoC world from SoC implementations using custom, ASIC or Application-Specific Standard Part (ASSP) design approaches, to include the design and use of complex reconfigurable logic parts with embedded processors and other application-oriented blocks of intellectual property. These complex FPGAs (Field-Programmable Gate Arrays) are offered by several vendors, including Xilinx (Virtex-II PRO Platform FPGA) and Altera (SOPC), but are referred to by several names: highly programmable SoCs, system-on-a-programmable-chip, embedded FPGAs.

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We can define; embedded systems are being designed on a single chip, called system on chip (SoC). SoC is a new design innovation for embedded systems.

An embedded processor is a part of the SoC VLSI circuit

A SoC is embedded with the following components: o o o o o o o o o o Multiple processors Memories Multiple standard source solutions (IP-Intellectual property) Cores and Other logic analog units A SoC may also have a network protocol embedded in to it. It may embed an encryption function unit. It can embed discrete cosine transforms for signal processing applications. It may also embedded FPGA cores (Field programmable Gate Array)

Recently exemplary GPPs called ARM 7, ARM 9 which embeds onto a VLSI chip, have been developed by ARM & Texas Instruments.

IC technology & VLSI circuits design technology Every processor must eventually be implemented on an IC. IC technology involves the manner in which we map a digital (gate-level) implementation onto an IC. An IC (Integrated Circuit), often called a chip, is a semiconductor device consisting of a set of connected transistors and other devices. A number of different processes exist to build semiconductors, the most popular of which is CMOS.IC technology is independent from processor technology; any type of processor can be mapped to any type of IC technology, semiconductors consist of numerous layers. The bottom layers form the transistors. The middle layers form logic gates. The top layers connect these gates with wires.
i) Full-custom/VLSI

ii) Semi-custom ASIC

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Embedded System Design

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Full-custom/VLSI

In a full-custom IC technology, we optimize all layers for our particular embedded systems digital implementation. Such optimization includes placing the transistors to minimize interconnection lengths, sizing the transistors to optimize signal transmissions and routing wires among the transistors. Once we complete all the masks, we send the mask specifications to a fabrication plant that builds the actual ICs. Full-custom IC design, often referred to as VLSI (Very Large Scale Integration) design VLSI Levels of Abstraction

Semi-custom ASIC

In Semi-custom ASIC (Application-Specific IC) technology, the lower layers are fully or partially built, leaving us to finish the upper layers. In a gate array technology, the masks for the transistor and gate levels are already built. The remaining task is to connect these gates to achieve our particular implementation. In a standard cell technology, logic-level cells have their mask portions pre-designed, usually by hand.

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Classification and Development Skills Requirements for the Embedded Systems Some of the criteria used in the classification of embedded systems are 1. 2. 3. 4. 5. Based on Generation Based on functionality and performance requirements Based on Complexity requirements Based on deterministic behavior Based on triggering

Based on functionality and performance requirements, embedded systems are classified as Stand-alone Embedded Systems Real-time Embedded Systems Networked Information Appliances Mobile Devices

Based on Complexity requirements, embedded systems are classified as 1. Small Scale Embedded Systems 2. Median Scale Embedded Systems 3. Large Scale Embedded Systems
]

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1. Small Scale Embedded Systems Designed with a single 8- or 16-bit microcontroller; Little hardware and software complexities and involve board-level design. Tools for development of embedded software Editor, assembler and cross assembler, integrated development environment (ISE) specific to the microcontroller or processor used C or Java used for developing C program compilation is done into the assembly, and executable codes are then appropriately located in the system memory. Software fits within the memory available and keeps in view the need to limit power dissipation when system is running continuously. Skills required for Small Scale Embedded System Designer Full understanding of a microcontroller with a basic knowledge of computer architecture, digital electronic design, software engineering, data communication, control engineering, motors and actuators, sensors and measurements, analog electronic design and IC design and manufacture. Specific skills will be needed in specific situations. For example, control engineering knowledge will be needed for design of control systems and analog electronic design knowledge will be needed when designing the system interfaces. Computer architecture and organization. Interfacing the memories. Burning the executable machine codes in PROM or ROM. Use of decoders and demultiplexers. Use of Direct memory accesses. Use of Ports and device-drivers. Device drivers in assembly. Simple and sophisticated buses. Timers. Interrupt servicing mechanism. C programming elements. Memory optimization. Selection of hardware and microcontroller. Use of ICE (In-Circuit-Emulators), cross assemblers and testing equipment. Debugging the software and hardware bugs by using test vectors. Basic knowledge in the other areas-software engineering, data communication, control engineering, motors and actuators, sensors and measurements, analog electronic design and IC design and manufacture

2. Median Scale Embedded Systems Designed with a single or few 16- or 32- bit microcontrollers or DSPs or Reduced Instruction Set Computers (RISCs).
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Employs the readily available single purpose processors. Employ the readily available IPs for the various functionsfor example, for the bus interfacing, Both hardware and software complexities Programming tools: C/C++/Visual, C++/Java, RTOS, and Source code engineering tool, Simulator, Debugger and Integrated Development Environment (IDE). Software tools provide the solutions to the hardware complexities.

Skills required for Median Scale Embedded System Designer 'C'/C++/Java programming and RTOS programming and program modeling skills Programming the Tasks or threads and their scheduling by RTOS. Programming priorities and Cooperative and preemptive scheduling Use of Inter processor communication functions. Use of shared data, and programming the critical sections and re-entrant functions. Use of semaphores, mailboxes, queues, sockets and pipes. Handling of interrupt-latencies and meeting task deadlines. Use of various RTOS functions. Use of physical and virtual device drivers. Designer must have access to an RTOS programming tool with Application Programming Interfaces (APIs) for the specific microcontroller to be used

3. Large Scale Embedded Systems Enormous hardware and software complexities and may need scalable processors or configurable processors and programmable logic arrays. Used for cutting edge applications that need hardware and software co-design and components integration in the final system Constrained by the processing speeds available in their hardware units. Certain software functions such as encryption and deciphering algorithms, discrete cosine transformation and inverse transformation algorithms, TCP/IP protocol stacking and network driver functions implemented in the hardware to obtain additional speeds by saving time Software implements some of the functions of the hardware resources in the system. Development tools for these systems may not be readily available at a reasonable cost or may not be available at all. In some cases, a compiler or retargetable compiler might have to be developed for these.

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Skills required for Large Scale Embedded System Designer Team is needed to co-design and solve the high level complexities of the hardware and software design. An embedded system hardware engineer should have full skills in hardware units and basic knowledge of 'C'/C++ and Java, RTOS and other programming tools. Software engineer should have basic knowledge in hardware and a thorough knowledge of 'C', RTOS and other programming tools. A final optimum design solution is then obtained by system integration.

EMBEDDED SYSTEM APPLICATIONS We can categorize applications of Embedded System into various categories as mentioned 1. Aerospace-Navigation Systems, Automatic landing systems, Flight altitude controls, engine controls, space exploration etc.. 2. Automotive-Fuel Injection Control, Passenger environmental controls, antilock braking systems, air bag controls, GPS mapping, Music system, Air conditioner etc 3. Home Utilities-Ovens, Washing Machine, Digital Watch, Security Alarm, Sound Recorder etc 4. Industrial- Elevator Controls, Robots, Engine Control etc.. 5. Medical- Imaging Systems, Patient monitors, Heart pacers, ECG etc.. 6. Office Automation- FAX machines, Telephones, Cash Registers 7. Communications- Switches, Hubs, pagers, cellular phones, cable TV terminals, fax and transreceivers, video games and so on. 8. Computer Peripherals- Printers, scanners, displays, modems, Hard Disk Drives, CDROM drives 9. Military Applications 10. Industrial Instrumentation Process controller, DC motor controller, robotic systems, CNC machine controller, close loop engine controller, industrial moisture recorder cum controller. 11. Scientific digital storage system, CRT display controller, spectrum analyzer.

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Unit 2 Devices and Communication Buses for Devices Network

PORT A port is a device to receive the bytes from external peripherals or devices or processors or controllers for reading them later using instructions executed on the processor or to send the bytes to external peripheral or device or processor using instructions executed on processor INPUT AND OUTPUT DEVICE Input and output devices are essential for all kinds of systems. An Embedded System connects to external devices like printer, multiline display unit, keypad or modem through ports. A device connects and accesses from and to the system processor through either a parallel or serial I/O port. A device port may be full duplex or half duplex. Each port has an assigned port address

Types of Input and Output Devices Input and output devices can be classified into the following I/O types. i Synchronous Serial I/O devices ii Serial UART I/O devices iii Parallel Port I/O devices Synchronous Serial I/O devices Synchronous Serial communication is defined as a Byte or a Frame of data is transmitted or received at constant time intervals with uniform phase differences. Synchronous serial Input Devices . Synchronous serial Output Devices

Synchronous Serial Input Device (Serial Bits and a clock signal used for synchronization of a port input)

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Synchronous Serial Output Device (Device Serial Bits and synchronization clock signal at a port output)

Serial UART I/O devices The serial UART communicate may be defined as a Byte or frame of data transmitted or received at variable time intervals Asynchronous Serial UART input Asynchronous Serial UART output Parallel Port I/O devices In this communication any number of ports could be connected with the device and the data communication is bidirectional in nature. i. Single Bit Input and Output a. Parallel Port Single Bit Input b. Parallel Port Single Bit Output ii. Parallel Port input and Output a. Parallel Port Input b. Parallel Port Output
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Examples

SYNCHRONOUS, ISO-SYNCHRONOUS AND ASYNCHRONOUS COMMUNICATIONS FROM SERIAL DEVICES. Synchronous Communication In this means of communication byte or frame of data received or transmitted at constant time intervals with uniform phase differences. Bits of a data frame are sent in a fixed maximum time intervals. Handshaking between sender and receiver is not provided during communication. Example Frames sent over LAN. Characteristics The main features of the synchronous communication are Bytes maintain a constant phase difference. No sending of bytes at random time intervals.
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A clock must be present at transmitter to send the data. Moreover, the clock information is sent to the receiver (i.e.) it is not always implicit to the receiver.

Communication Protocols used Most often synchronous serial communication is used for data is transmission between physical devices. It can be complex and has to be as per the communication protocol followed. Example HDLC (High Level Data Link Control) Synchronization ways Ten ways by which the synchronous signals with the clocking info transmitted from transmitter to the receiver are as shown below.

Iso-Synchronous Iso-synchronous communication is a special case of synchronous communication. In contrast with the synchronous communication where bits of data frame are sent in a fixed maximum time interval, the Iso-synchronous communication may have varied maximum time intervals.

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Asynchronous In the asynchronous communication Byte or a Frame of data is received or sent at variable time intervals with phase difference. The asynchronous communication technique is a transmission technique which is most widely used by personal computers to provide connectivity to printer, modems fax machines etc. This allows a series of bytes to be sent along a single wire (actually a ground wire is required to complete the circuit). The data is sent as a series of bits. A shift registers (in either hardware or software) is used to serialize each information byte into the series of bits which are then sent on the wire using an I/O port and a bus driver to connect to the cable.

Characteristics Bytes or Frames of data is sent or received at variable time intervals. Handshaking between sender and receiver is provided during communication. A clock is needed at the transmitter to send the data The clock data is not sent to the receiver (i.e.) it is always implicit to the receiver. UART (Universal Asynchronous Receiver Transmitter) The Universal Asynchronous receiver Transmitter (UART) controller is the key component of the serial communication subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART reassembles the bits into complex bytes.

Block diagram of the Universal Asynchronous Receiver/Transmitter (UART)

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Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. Instead, the sender and receiver must agree on timing parameters in advance and special bits are added to each word which is used to synchronized the sending and receiving bits. When a word is given to the UART for Asynchronous transmissions, a bit called the "Start Bit" is added to the beginning of each word that is to be transmitted. After the Start Bit, the individual bits of the word of data are sent, with the Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly the same amount of time as all of the other bits and the receiver *looks" at the wire at approximately halfway through the period assigned to each bit to determine if the bit is l or 0. The sender does not know when the receiver has "looked" at the value of the bit. The sender only knows when the clock says o begin transmitting the next bit of the word. When the entire data word has been sent, the transmitter may add a Parity Bit that the transmitter generates. The Parity Bit may be used by the receiver to perform simple error checking. Then at least one Stop Bit is sent by the transmitter.

When the receiver has received all of the bits in the data word. It may check for the Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be used) and then the receiver looks for a Stop Bit. If the Stop bit does not appear when it is supposed to the UART considers the entire word to be garbled and will report a Framing Error to the host processor when the data word is read. The usual cause of a Framing Error is that the sender and receiver clocks were not running at the same speed, or that the signal was interrupted. Regardless of whether that data was received correctly or not the UART automatically discards the Start, Parity and Stop bits. If the sender and receiver are configured identically, these bits are not passed to the host.

Exemplary Protocol RS232C

In telecommunications, RS-232 (Recommended Standard 232) is the traditional name for a series of standards for serial binary single-ended data and control signals connecting between a DTE (Data Terminal Equipment) and a DCE (Data Circuit-terminating Equipment) The current version of the standard is EIA/TIA-232-F Connections to modems, printers, mice, data storage, power supplies, and other peripheral devices. Point-to-point wiring & protocol Allows for bidirectional transmission (need two wires for this)
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 No shared clock RS232C Connector Can be simpler 9 pin and 25-pin in case of IBM COM port

TxD: - This pin carries data from the computer to the serial device RXD: - This pin carries data from the serial device to the computer DTR signals: - DTR is used by the computer to signal that it is ready to communicate with the serial device like modem. In other words, DTR indicates to the Dataset (i.e., the modem or DSU/CSU) that the DTE (computer) is ON. DSR: - Similarly to DTR, Data set ready (DSR) is an indication from the Dataset that it is ON. DCD: - Data Carrier Detect (DCD) indicates that carrier for the transmit data is ON. RTS: - This pin is used to request clearance to send data to a modem CTS: - This pin is used by the serial device to acknowledge the computer's RTS Signal. In most situations, RTS and CTS are constantly on throughout the communication session. Clock signals (TC, RC, and XTC): - The clock signals are only used for synchronous communications. The modem or DSU extracts the clock from the data stream and provides a
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steady clock signal to the DTE. Note that the transmit and receive clock signals do not have to be the same, or even at the same baud rate.

DTE and DCE

RS232C communication is between a DTE (computer) COM (communication) port and a DCE (modem) port. DTE stands for 'Data Terminal Equipment'. DCE stands for 'Data Communication Equipment'. RS232C is a standard for interfacing signals between DCE and DTE. Data Bits RxD and TxD lines As per UART standard formats on RxD and TxD lines

VOLTAGE LEVELS It does not use the conventional 0 and 5 volt levels implemented in TTL and CMOS designs. Drivers have to supply +5 to +15 volts for a logic 0 and 5 to 15 volts for a logic 1. This means that extra power supplies are needed to drive the RS232 voltage levels. Typically, a +12 volt and a 12 volt power supply are used to drive the RS232 outputs MAXIMUM DATA RATE The standard defines a maximum data rate of 20k bits/second. This is unnecessarily slow for many of todays applications. RS232 products manufactured by Dallas Semiconductor guarantee up to 250k bits/second and typically can communicate up to 350k bits/second. MAXIMUM CABLE LENGTH RS232 standard has been replaced by a maximum load capacitance specification of 2500 pF. To determine the total length of cable allowed, one must determine the total line capacitance.. the maximum cable length is approximately 80 feet. If a longer cable length is required, the user would need to find a cable with a smaller mutual capacitance.

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Data packet format on RS232 serial communication corresponding to ASCII character

HDLC (HIGH LEVEL DATA LINK CONTROL) The HDLC protocol is a general purpose protocol which operates at the data link layer of the OSI reference model. The protocol uses the service of a physical layer, and provides either a best effort or reliable communications path between the transmitter and receiver (i.e. with acknowledged data transfer) the type of service provided depends upon the HDLC mode which is used. Each piece of data is encapsulated in an HDLC frame by adding a trailer and a header. The header contains an HDLC address and 4n HDLC field. The trailer is founds the end of the frame, and contains Cyclic Redundancy check (CRC) which detects any errors which may occur during transmission. The frames are separated by HDLC flag sequence which are transmitted between each frame and whenever there is no data to be transmitted.

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Modes of operation The HDLC protocol is a general data link control protocol capable of supporting a range of modes of operation. The two most prevalent modes are The best effort or datagram service In this mode, the packets are carried in a UI frame, and a best effort delivery is performed (i.e., there is no guarantee that the packet carried by the frame will be delivered). The link layer does not provide error recovery of lost frames. This mode is used for point to point links carrying a network protocol which itself uses datagram packets (example IP), The control field of HDLC follows the address field and is the second part of all HDLC frames. The Asynchronous Balanced Mode (ABM). This provides a reliable data point to point data link service and may be used to provide a service which supports either a datagram or reliable network protocol. In this mode, the packets are carried in numbered frames which are acknowledged by the receiver using numbered supervisory frames. Error recovery (example, checkpoint or go back n error recovery) is employed to ensure a well ordered and reliable flow of frames. The HDLC Address field The first byte(s) of a frame transmitted using the High Level Control (HDLC) Protocol is used to carry an address field. This field is typically a single byte, but extension is possible allowing a number of byes to be used. The address format is shown in the figure below

The address consists of three parts A Service Access Point (SAP) which is usually set to zero, but used in some variants of HDLC to identify one of the number of data link protocol entities. A Command/Response bit to indicate whether the frame relates to information frame (Iframes) being sent from the node or received by the node. An address extension 6ir which is usually set to true to indicate that the address is of length one byte. When set to false it indicates an additional byte follows. The address field is mainly used when HDLC issued in a mode which provides reliable data transfer using numbered control frames.

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Control Field of HDLC The control field of HDLC follows the address field and is the Second part of all HDLC frames. The best effort service is provided through the use of U (un-numbered) frames consisting of a single byte. All frames carry a field of size I bit is known as the "poll/final" bit and is used by the check pointing procedure to verify correct transmission.

HDLC defines currently two formats for frames which carry sequence numbers. These types of frames are used to provide the reliable data link service. Two types of numbered frames are supported. S (supervisory) frames containing only an acknowledge number (N(R)). I (information) frame carrying data and containing both a send sequence number (N(S)) and acknowledgment number (N(R)). Flags HDLC is a data link protocol which uses a unique bit sequence to delimit the start and end of each PDU transported by the data link layer service. In HDLC, frames are delimited by a sequence of bits known as a flag. The flag sequence is a unique 8 bit sequence of the for 0111 1110. The way in which this is performed is described in the text and diagrams which follow.

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Sophisticated Interfacing Features in Device Ports

A device port may not be as simple as the one for a stepper motor port or for serial line UART. May be a sophisticated I/O device or Port. Examples I/O devices for fast I/Os, fast serializations and de-serializations, fast transceiver and real time video processing system I/Os.

The main features are:

Low voltage gates Schmitt trigger gates Power managing gates Dynamically controlled impedance matching SerDes subunit PCS and PCM subunit PMA subunit

Low voltage gates:

LVTTL (Low Voltage TTL) and LVCMOS (Low Voltage CMOS) gates may be used at the device ports for 1.5 V I/O HSTL (High Speed Trans-receiver Logic) and SSTL (Stub-series Terminated Logic) standards. HSTL for high-speed operations.

Schmitt trigger at Port:

Conditioning of the signal by noise elimination Example, 5V Schmitt trigger circuit property ---on a transition from 0 to 1 occurs, if the voltage level exceeds 2/3 of 5V level, then only then there is transition to 1. ---When a transition from 1 to 0 occurs, if the voltage level lowers below 1/3 of 5V level, then only then there is there a transition to 0

Power managing gates:

Data Gate at the ports-- a programmable ON/OFF switch for power management and Makes it possible to reduce power consumption by reducing unnecessary toggling of inputs when the device port is operated at fast speeds and not in use. Dynamically controlled impedance matching: to eliminate line reflections

SerDes subunit:

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Device for I/O may integrate a SerDes (serialization and De-serialization) Subunit. SerDes is a standard subunit at in a device where the bytes placed at 'transmit holding buffer' serialize on transmission and once the bits are received these de-serialize.
Embedded System Design 2011/2012-ECE Department,SBMJCE

Physical Coding Sub-layer (PCS) and PCM subunit:

Analog audio and video signals pulse code modulated (PCM) at the sub-layer. PCS sub-layer directly provides the codes from the analog inputs within the device itself The codes then saved in the device data buffers Advantage of an in-built PCS No need of external PCM coding, in background operations, fast coding High Systems performance for multimedia inputs at the devices.
I/O integration to an analog Physical Media Attachment (PMA) Unit for connecting direct inputs and outputs of voice, music, video and images. In-built PMA the device directly connects to the physical media. PMA is needed for real- time processing of video and audio inputs at the device

PMA subunit:

Need for Communication Interfaces

The need for providing communication interfaces arises due to the following reasons: The embedded system needs to sends data to a host. The host will analyze of data and present the data through a Graphical User Interface (GUI). The embedded system may need to communicate with another embedded system to transmit or receive data. Providing a standard communication interface is preferable rather than providing a proprietary interface. A number of embedded systems may need to be networked to share data. Network interfaces need to be provided in such a case. An embedded system may need to be connected to the internet so that anyone can access the embedded system. An example is a real-time weather monitoring system. The weather monitoring system can be Internet enabled using TCP/IP protocol stack and HTTP server. Mobile devices such as cell phones and palmtops need to interact with other devices such as PCs and laptops for data synchronization. When the palmtop comes near the laptop, automatically the two can form a network to exchange data. For some embedded systems, the software may need up-gradation after it is installed in the field. The software can be upgraded through communication interfaces. Due to these reasons, providing communication interfaces based on standard protocols is a must. Not surprisingly, many microcontrollers have on-chip communication interfaces such as a serial interface to meet these requirements.
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Communication Protocol at an embedded system

IO port bits sent after first formatted according to a specified protocol, which is to be followed when communicating with another device through an IO port or channel. A protocol defines how the frame bits are: Sent synchronously or Iso synchronously or asynchronously and at what rate(s)? Proceeded by the header bits? How the receiving device address communicated so that only destined device activates and receives the bits? How can the transmitting device address defined so that receiving device comes to know the source when receiving data from several sources? How the frame-length defined so that receiving device know the frame-size in advance? Frame-content specifications Are the sent frame bits specify the control or device configuring or commend or data? Frame bits minimum and maximum length permitted per frame Line supply ,impedances and line-Connectors specifications Different types of Communication Protocol Synchronous communication HDLC, Frame Relay

Asynchronous communication RS232C, UART, X.25, ATM, DSL and ADSL

File transfer, Boot Protocols TELNET (Tele network), FTP (file transfer protocol), DNS (domain network server), IMAP 4 (Internet Message Exchange Application Protocol) and Bootp (Bootstrap protocol).

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 Internet appliances application protocols and Web protocols HTTP (hyper texttransfer protocol), HTTPS (hyper text transfer protocol Secure Socket Layer), SMTP (Simple Mail Transfer Protocol), POP3 (Post office Protocol version 3), ESMTP (Extended SMTP),

SERIAL BUS COMMUNICATION PROTOCOLS 1-Wire protocol SPI I2C CAN USB FireWire IEEE 1394 Bus

PARALLEL BUS DEVICE PROTOCOLS PCI Bus ARM BUS

INTERNET ENABLED SYSTEMS NETWORK PROTOCOLS ETHERNET PROTOCOL LIN

WIRELESS AND MOBILE SYSTEM PROTOCOL IrDA (Infrared Data Association) Bluetooth 2.4 GHz 802.11 WLAN 802.11b Wi-Fi
ZigBee 900 MHz

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Serial Data Communication

Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is a synchronous serial data link that is standard across many Motorola microprocessors and other peripheral chips. It provides support for a high bandwidth (1 mega baud) network connection amongst CPUs and other devices supporting the SPI. The SPI is essentially a three-wire plus slave selects serial bus for eight or sixteen bit data transfer applications. The three wires carry information between devices connected to the bus. Each device on the bus acts simultaneously as a transmitter and receiver. Two of the three lines transfer data (one line for each direction) and the third is a serial clock. Some devices may be only transmitters while others only receivers. Generally, a device that transmits usually possesses the capability to receive data also. An SPI display is an example of a receive-only device while EEPROM is a receiver and transmit device. The devices connected to the SPI bus may be classified as Master or Slave devices. A master device initiates an information transfer on the bus and generates clock and control signals. A slave device is controlled by the master through a slave select (chip enable) line and is active only when selected. Generally, a dedicated select line is required for each slave device. The same device can possess the functionality of a master and a slave but at any point of time, only one master can control the bus in a multi-master mode configuration. Any slave device that is not selected must release (make it high impedance) the slave output line. The SPI bus employs a simple shift register data transfer scheme: Data is clocked out of and into the active devices in a first-in, first-out fashion. It is in this manner that SPI devices transmit and receive in full duplex mode. Serial Peripheral Interface (SPI) is a 4-wire full-duplex synchronous serial data link:
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o SCLK: Serial Clock o MOSI: Master Out Slave In -Data from Master to Slave o MISO: Master In Slave Out -Data from Slave to Master o SS: Slave Select

All lines on the SPI bus are unidirectional: The signal on the clock line (SCLK) is generated by the master and is primarily used to synchronize data transfer. The master-out, slave-in (MOSI) line carries data from the master to the slave and the master-in, slave-out (MISO) line carries data from the slave to the master. Each slave device is selected by the master via individual select lines. Information on the SPI bus can be transferred at a rate of near zero bits per second to 1 Mbits per second. Data transfer is usually performed in eight/sixteen bit blocks. All data transfer is synchronized by the serial clock (SCLK). One bit of data is transferred for each clock cycle. Four clock modes are defined for the SPI bus by the value of the clock polarity and the clock phase bits. The clock polarity determines the level of the clock idle state and the clock phase determines which clock edge places new data on the bus.

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SPI Communication
SPI creates a data loop between two devices. Data leaving the master exits on the SDO (serial data output) line. Data entering the master enters on the serial data input, SDI line. A clock (SCK) is generated by the master device. It controls when and how quickly data is exchanged between the two devices. allows the possibility of having more than one slave and simplifies the communications. When the SS signal goes low at a slave device, only that slave is accessed by SPI.

SS allows a master device to control when a particular slave is being addressed. This

When operating in SPI mode, module uses 4 registers: SSPSTAT - status register SSPCON - control register SSPBUF - buffer register SSPSR - shift register The first three registers are writable/readable and can be changed at any moment, while the forth register, since not available, is used for converting data into serial format

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SSPSR - shift register Shift register (SSPRS) is directly connected to the microcontroller pins and used for data transmission in serial format. The SSPRS register has its input and output and shifts the data in and out of device.

In other words, each bit appearing on input (receive line) simultaneously shifts
another bit toward output (transmit line) i.e., the data travels in a loop to the next shift register. The data is shifted out the SDO pin of one device and into the SDI pin of the other. SSPBUF register The SSPBUF register (Buffer) is a part of memory used to temporarily hold the data written to the SSPRS until the received data is ready. Upon receiving all 8 bits of data, that byte is moved to the SSPBUF register. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored. Since having been the most accessed, this register is considered the most important from the programmers point of view. Control register The control block determines when an SPI transfer can take place. When referring to the master device this section transmits a clock and slave select signal. The Slave device waits for these signals and uses them when processing the SPI data. In the master device, the slave select signal must be controlled by your code. It is a standard I/O line that is brought low when you wish to initiate an SPI transfer. When you finish the transfer, return the I/O line to the high state. A transfer is usually one byte long.

Steps for data transmitting and receiving in SPI Step-1

Data to transmit should be written to the buffer register SSPBUF. Immediately after that, if the SPI module operates in master mode, the microcontroller will automatically start performing the operation. If the SPI module operates as Slave, the Microcontroller will not perform anything until the SCK pin detects clock signal.

Step-2
This data is now moved to the SSPSR register and the SSPBUF register is not cleared.

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Step 3
Synchronized with clock signal, this data is shifted to the output pin (MSB bit first) while the register is simultaneously being filled with bits through input pin. In Master mode, the Microcontroller itself generates clock, while the Slave mode uses external clock (pin SCK). Step 4. The SSPSR register is full once the 8 bits of data have been received. It is indicated by setting the BF and SSPIF bits. The received data (that byte) is automatically moved from the SSPSR register to the SSPBUF register. Since data transfer via serial communication is performed automatically, the rest of the program is normally executed while data transfer is in progress. In that case, the function of the SSPIF bit is to generate interrupt when one byte transmission is completed. Step 5. At last, the data stored in the SSPBUF register is ready for use and moved to any register available.

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SPI READ-WRITE TIMING DIAGRAM ABD DATA FLOW CHART

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Bus Configuration and SPI Protocol of Multiple Slaves

Multiple slave devices can be connected in parallel or daisy chained utilizing the same SPI bus. 1. Parallel Configuration For the parallel connection, each device on the bus should have a separate CS line, while SCK, SDI and SDO lines are connected in parallel as shown in below Figure

2. Daisy Chain Configuration In this configuration CS and SCK lines connected in parallel, and each SDO pin of previous chip is connected to SDI pin. Daisy Chaining simplifies the connection by reducing the length and connections of the data lines, but restricts access to a single device in chain. In other words, all the devices in chain will be involved in a write or read operation. We can consider that every device in the chain is a portion of one big shift register, where serial data is shifted out on each clock going through all the Slaves, from Slave0 to slave1 and all the way down to the last Slave (N-1) in this chain as shown in figure.

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IC
2 2 2

I C is an Inter-IC Serial bus. Originally I C Bus developed by Philips in the 80s, the I C bus was designed to link a small number of devices on a single card, such as to manage the tuning of a car radio or TV. The maximum allowable capacitance was set at 400 pF to allow proper rise and fall times for optimum clock and data signal integrity with a top speed of 100 kbps. In 1992 the standard bus speed was increased to 400 kbps, to keep up with the everincreasing performance requirements of new ICs.
2

The 1998 I C specification, increased top speed to 3.4 Mbits/sec.

2

All I C devices are designed to be able to communicate together on the same two-wire bus and system functional architecture is limited only by the imagination of the designer. But while its application to bus lengths within the confines of consumer products such as PCs, cellular phones, car radios or TV sets grew quickly, only a few system integrators were using it to span a room or a building.
2

The I C bus is now being increasingly used in multiple card systems, such as a blade
2

servers, where the I C bus to each card needs to be isolatable to allow for card insertion and removal while the rest of the system is in operation, or in systems where many more devices need to be located onto the same card, where the total device and trace capacitance would have exceeded 400 pF.
2

New bus extension & control devices help expand the I C bus beyond the 400 pF limit of about 20 devices and allow control of more devices, even those with the same address. These new devices are popular with designers as they continue to expand and increase the
2

range of use of I C devices in maintenance and control applications.

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I C Features Only two bus lines are required:

A serial data line (SDA) and a serial clock line (SCL).

Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers.

Its a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer.

Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 3.4 Mbit/s in the High-speed mode.

On-chip filtering (50 ns) rejects spikes on the bus data line to preserve data integrity. The number of ICs that can be connected to the same bus segment is limited only by the maximum bus capacitive loading of 400 pF.

The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device is recognized by a unique address (whether its a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

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I2C Hardware architecture

HARDWARE CONFIGURATION The bus wires are named SDA (serial data) and SCL (serial clock). These two bus wires have the same configuration. They are pulled-up to the logic high level by resistors connected to a single positive supply, usually +3.3 V or +5 V but designers are now moving to +2.5 V and towards 1.8 V in the near future. All the connected devices have open-collector (open-drain for CMOS - both terms mean only the lower transistor is included) driver stages that can transmit data by pulling the bus low, and high impedance sense amplifiers that monitor the bus voltage to receive data. Unless devices are communicating by turning on the lower transistor to pull the bus low, both bus lines remain high. To initiate communication a chip pulls the SDA line low. It then has the responsibility to drive the SCL line with clock pulses, until it has finished, and is called the bus master.
2

I C Communication Procedure One IC that wants to talk to another must:

2

1) Wait until it sees no activity on the I C bus. SDA and SCL are both high. The bus is 'free'.

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2) Put a message on the bus that says 'its mine' - I have STARTED to use the bus. All other ICs then LISTEN to the bus data to see whether they might be the one who will be called up (addressed). 3) Provide on the CLOCK (SCL) wire a clock signal. It will be used by all the ICs as the reference time at which each bit of DATA on the data (SDA) wire will be correct (valid) and can be used. The data on the data wire (SDA) must be valid at the time the clock wire (SCL) switches from 'low' to 'high' voltage. 4) Put out in serial form the unique binary 'address' (name) of the IC that it wants to communicate with. 5) Put a message (one bit) on the bus telling whether it wants to SEND or RECEIVE data from the other chip. 6) ask the other IC to ACKNOWLEDGE (using one bit) that it recognized its address and is ready to communicate. 7) After the other IC acknowledges all is OK, data can be transferred. 8) The first IC sends or receives as many 8-bit words of data as it wants. After every 8-bit data word the sending IC expects the receiving IC to acknowledge the transfer is going OK. 9) When all the data is finished the first chip must free up the bus and it does that by a special message called 'STOP'. It is just one bit of information transferred by a special 'wiggling' of the SDA/SCL wires of the bus.

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START and STOP conditions

Within the procedure of the I2C-bus, unique situations arise which are defined as START (S) and STOP (P) conditions A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition.

The first seven bits of the first byte make up the slave address. The eighth bit is the LSB (least significant bit). It determines the direction of the message. A zero in the least significant position of the first byte means that the master will write information to a selected slave. A one in this position means that the master will read information from the slave. When an address is sent, each device in a system compares the first seven bits after the START condition with its address. If they match, the device considers itself addressed by the master as a slave-receiver or Slave-transmitter, depending on the R/W bit.

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I2C Read and Write Operations

I2C Write

I2C Read

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BUS ARBITRATION AND CLOCK GENERATION

So far we have seen the operation of the bus from the master's point of view and using only one master on the bus. The I2C bus was originally developed as a multi-master bus. This means that more than one device initiating transfers can be active in the system. When using only one master on the bus there is no real risk of corrupted data, except if a slave device is malfunctioning or if there is a fault condition involving the SDA / SCL bus lines.

CLOCK GENERATION
All masters generate their own clock on the SCL line to transfer messages on the I2Cbus. Data is only valid during the HIGH period of the clock. A defined clock is therefore needed for the bit-by-bit arbitration procedure to tak place. Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and, once a device clock has gone LOW, it will hold the SCL line in that state until the clock HIGH state is reached However, the LOW to HIGH transition of this clock may not change the state of the SCL line if another clock is still within its LOW period. The SCL line will therefore be held LOW by the device with the longest LOW period. Devices with shorter LOW periods enter a HIGH wait-state during this time. When all devices concerned have counted off their LOW period, the clock line will be released and go HIGH.
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There will then be no difference between the device clocks and the state of the SCL line, and all the devices will start counting their HIGH periods.

The first device to complete its HIGH period will again pull the SCL line LOW. In this way, a synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period.

Clock synchronization during the arbitration procedure.

BUS ARBITRATION
A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time of the START condition which results in a defined START condition to the bus. Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting a LOW level will switch off its DATA output stage because the level on the bus doesnt correspond to its own level. Arbitration can continue for many bits. Its first stage is comparison of the address bits. to address the same device, arbitration continues with comparison of the data-bits if they are master-transmitter, or acknowledge-bits if they are master-receiver. Because address and data information on the I2C-bus is determined by the winning master, no information is lost during the arbitration process. A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration. If a master also incorporates slave function and it loses

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arbitration during the addressing stage, its possible that the winning master is trying to address it. The losing master must therefore switch over immediately to its slave mode.

Figure shows the arbitration procedure for two masters. Of course, more may be involved (depending on how many masters are connected to the bus). The moment there is a difference between the internal data level of the master generating DATA 1 and the actual level on the SDA line, its data output is switched off, which means that a HIGH output level is then connected to the bus. This will not affect the data transfer initiated by the winning master. Since control of the I2C-bus is decided solely on the address or master code and data sent by competing masters, there is no central master, nor any order of priority on the bus. A complete data transfer:

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CAN-CONTROLLER AREA NETWORK

The Controller Area Network (CAN) is a serial bus communications protocol developed by Bosch (an electrical equipment manufacturer in Germany) in the early 1980s. Thereafter, CAN was standardized as ISO-11898 and ISO-11519, establishing itself as the standard protocol for in-vehicle networking in the auto industry. In the early days of the automotive industry, localized stand-alone controllers had been used to manage various actuators and electromechanical subsystems. By networking the electronics in vehicles with CAN, however, they could be controlled from a central point, the engine control unit (ECU), thus increasing functionality, adding modularity, and making diagnostic processes more efficient. Early CAN development was mainly supported by the vehicle industry, as it was used in Passenger cars, boats, trucks, and other types of vehicles. Today the CAN protocol is used in many other fields in applications that call for networked embedded control, including industrial automation, medical applications, building automation, weaving machines, and production machinery. CAN offer an efficient communication protocol between sensors, actuators, controllers, and other nodes in real-time applications, and is known for its simplicity, reliability, and high performance. The CAN protocol is based on a bus topology, and only two wires are needed for communication over a CAN bus (CANH and CANL). The bus has a multimaster structure where each device on the bus can send or receive data. Only one device can send data at any time while all the others listen. If two or more devices attempt to send data at the same time, the one with the highest priority is allowed to send its data while the others return to receive mode.

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The above figure shows a CAN bus with n nodes. The CAN protocol is based on CSMA/ CD/AMP (Carrier-Sense Multiple Access/Collision Detection with Arbitration on Message Priority) protocol, which is similar to the protocol used in Ethernet LAN. When Ethernet detects a collision, the sending nodes simply stop transmitting and waits random amount of time before trying to send again. CAN protocol, however, solve the collision problem using the principle of arbitration, where only the highest priority node is given the right to send its data.

Some of the CAN protocol features are:

CAN bus is multimaster. When the bus is free, any device attached to the bus can start sending a message. CAN bus protocol is flexible. The devices connected to the bus have no addresses, which means messages are not transmitted from one node to another based on addresses. Instead, all nodes in the system receive every message transmitted on the bus, and it is up to each node to decide whether the received message should be kept or discarded. A single message can be destined for a particular node or for many nodes, depending on how the system is designed. Another advantage of having no addresses is that when a device is added to or removed from the bus, no configuration data needs to be changed (i.e., the bus is hot pluggable). CAN bus offers remote transmit request (RTR), which means that one node on the bus is able to request information from the other nodes. Thus instead of waiting for a node to continuously send information, a request for information can be sent to the node. For example, in a vehicle, where the engine temperature is an important parameter, the system can be designed so the temperature is sent periodically over the bus. However, a more elegant solution is to request the temperature as needed, since it minimizes the bus traffic while maintaining the networks integrity.

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CAN bus communication speed is not fixed. Any communication speed can be set for the devices attached to a bus.

All devices on the bus can detect an error. The device that has detected an error immediately notifies all other devices.

Multiple devices can be connected to the bus at the same time, and there are no logical limits to the number of devices that can be connected. In practice, the number of units that can be attached to a bus is limited by the buss delay time and electrical load.

Dominant and Recessive State:

The data on CAN bus is differential and can be in two states: dominant and recessive. Figure shows the state of voltages on the bus. The bus defines a logic bit 0 as a dominant bit and a logic bit 1 as a recessive bit. When there is arbitration on the bus, a dominant bit state always wins out over a recessive bit state. In the recessive state, the differential voltage CANH and CANL is less than the minimum threshold (i.e., less than receiver input and less than transmitter output). In the dominant state, the differential voltage CANH and CANL is greater than the minimum threshold.

BUS Termination
A CAN bus is terminated to minimize signal reflections on the bus. The ISO-11898 requires that the bus has a characteristic impedance of 120 ohms. The bus can be terminated by one of the following methods: Standard termination Split termination Biased split termination
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CAN protocol (Layered Structure of a CAN Node)

Many network protocols are described using the seven-layer Open Systems Interconnection (OSI) model. The CAN protocol includes the Application layer, data link layer, and the physical layer of the OSI reference model as shown in figure.

The Physical Layer defines how signals are actually transmitted. Within this specification the physical layer is not defined so as to allow transmission medium and signal level implementations to be optimized for their application.

The Transfer Layer represents the kernel of the CAN protocol. It presents messages received to the object layer and accepts messages to be transmitted from the object layer. The transfer layer is responsible for bit timing and synchronization, message framing, arbitration, acknowledgement, error detection and signaling, and fault confinement.

The Object Layer is concerned with message filtering as well as status and message handling.

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Messages: Information on the bus is sent in fixed format messages of different but limited length. When the bus is free any connected unit may start to transmit a new message. Information Routing: In CAN systems a CAN node does not make use of any information about the system configuration (e.g. station addresses). This has several important consequences. System Flexibility: Nodes can be added to the CAN network without requiring any change in the software or hardware of any node and application layer. Message Routing: The content of a message is named by an IDENTIFIER. The IDENTIFIER does not indicate the destination of the message, but describes the meaning of the data, so that all nodes in the network are able to decide by MESSAGE FILTERING whether the data is to be acted upon by them or not. Multicast: As a consequence of the concept of MESSAGE FILTERING any number of nodes can receive and simultaneously act upon the same message. Data Consistency: Within a CAN network it is guaranteed that a message is simultaneously accepted either by all nodes or by no node. Thus data consistency of a system is achieved by the concepts of multicast and by error handling. Bit rate The speed of CAN may be different in different systems. However, in a given system the bit-rate is uniform and fixed. Priorities: The IDENTIFIER defines a static message priority during bus access. Remote Data Request: By sending a REMOTE FRAME a node requiring data may request another node to send the corresponding DATA FRAME. The DATA FRAME and the corresponding REMOTE FRAME are named by the same IDENTIFIER. Multimaster: When the bus is free any unit may start to transmit a message. The unit with the message of highest priority to be transmitted gains bus access.

Arbitration: Whenever the bus is free, any unit may start to transmit a message. If 2 or more units start transmitting messages at the same time, the bus access conflict is resolved by bitwise arbitration using the IDENTIFIER. The mechanism of arbitration guarantees that neither information nor time is lost. If a DATA FRAME and a REMOTE FRAME with the same IDENTIFIER are initiated at the same time, the DATA FRAME prevails over the REMOTE
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FRAME. During arbitration every transmitter compares the level of the bit transmitted with the level that is monitored on the bus. If these levels are equal the unit may continue to send. When a recessive level is sent and a dominant level is monitored, the unit has lost arbitration and must withdraw without sending one more bit. Safety: In order to achieve the utmost safety of data transfer, powerful measures for error detection, signaling and self-checking are implemented in every CAN node. Error Detection: For detecting errors the following measures have been taken: Monitoring (transmitters compare the bit levels to be transmitted with the bit levels detected on the bus) Cyclic Redundancy Check Bit Stuffing Message Frame Check

Performance of Error Detection The error detection mechanisms have the following properties: All global errors are detected. All local errors at transmitters are detected. Up to 5 randomly distributed errors in a message are detected. Burst errors of length less than 15 in a message are detected. Errors of any odd number in a message are detected.

Fault Confinement CAN nodes are able to distinguish short disturbances from permanent failures. Defective nodes are switched off. Connections The CAN serial communication link is a bus to which a number of units may be connected. This number has no theoretical limit. Practically the total number of units will be limited by delay times and/or electrical loads on the bus line. Single Channel The bus consists of a single bidirectional channel that carries bits. From this data resynchronization information can be derived. The way in which this channel is implemented is not fixed in this specification. E.g. single wire (plus ground), two differential wires, optical fibres, etc.
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Bus values The bus can have one of two complementary logical values: dominant or recessive. During simultaneous transmission of dominant and recessive bits, the resulting bus value will be dominant. For example, in case of a wired-AND implementation of the bus, the dominant level would be represented by a logical 0 and the recessive level by a logical 1. Physical states (e.g. electrical voltage, light) that represent the logical levels Acknowledgement All receivers check the consistency of the message being received and will acknowledge a consistent message and flag an inconsistent message.

MESSAGE TRANSFER
Frame Types
Message transfer is manifested and controlled by four different frame types: 1. A DATA FRAME carries data from a transmitter to the receivers. 2. A REMOTE FRAME is transmitted by a bus unit to request the transmission of the DATA FRAME with the same IDENTIFIER. 3. An ERROR FRAME is transmitted by any unit on detecting a bus error. 4. An OVERLOAD FRAME is used to provide for an extra delay between the preceding and the succeeding DATA or REMOTE FRAMEs

DATA FRAME The data frame is in two formats: standard (having an 11-bit ID) and extended (having a 29-bit ID). The data frame is used by the transmitting device to send data to the receiving device, and the data frame is the most important frame handled by the user. Figure shows the data frames structure. A standard data frame starts with the start of frame (SOF) bit, which is followed by an 11-bit identifier and the remote transmission request (RTR) bit. The identifier and the RTR form the 12-bit arbitration field. The control field is 6 bits wide and indicates how many bytes of data are in the data field. The data field can be 0 to 8 bytes. The data field is followed by the CRC field, which checks whether or not the received bit sequence is corrupted. The ACK field is 2 bits and is used by the transmitter to receive acknowledgment of a valid
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frame from any receiver. The end of the message is indicated by a 7-bit end of frame (EOF) field.

Start of Frame (SOF) The start of frame field indicates the beginning of a data frame and is common to both standard and extended formats. Arbitration Field Arbitration is used to resolve bus conflicts that occur when several devices at once start sending messages on the bus. The arbitration field indicates the priority of a frame, and it is different in the standard and extended formats. In the standard format there are 11 bits, and up to 2032 IDs can be set. The extended format ID consists of 11 base IDs plus 18 extended IDs. Up to 2032 x 218 discrete IDs can be set. During the arbitration phase, each transmitting device transmits its identifier and compares it with the level on the bus. If the levels are equal, the device continues to transmit. If the device detects a dominant level on the bus while it is trying to transmit a recessive level, it quits transmitting and becomes a receiving device. After arbitration only one transmitter is left on the bus, and this transmitter continues to send its control field, data field, and other data.
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The process of arbitration is illustrated in below figure by an example consisting of three nodes having identifiers: Node 1: 11100110011 Node 2: 11100111111 Node 3: 11100110001

Assuming the recessive level corresponds to 1 and the dominant level to 0, the arbitration is performed as follows: All the nodes start transmitting simultaneously, first sending SOF bits. Then they send their identifier bits. The 8th bit of Node 2 is in the recessive state, while the corresponding bits of Nodes 1 and 3 are in the dominant state. Therefore Node 2 stops transmitting and returns to receive mode. The receiving phase is indicated by a gray field. The 10th bit of Node 1 is in the recessive state, while the same bit of Node 3 is in dominant state. Thus Node 1 stops transmitting and returns to receive mode. The bus is now left to Node 3, which can send its control and data fields freely.

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Control Field The control field is 6 bits wide, consisting of 2 reserved bits and 4 data length code (DLC) bits, and indicates the number of data bytes in the message being transmitted. This field is coded as shown in Table, where up to 8 transmit bytes can be coded with 6 bits.

Data Field The data field carries the actual content of the message. The data size can vary from 0 to 8 bytes. The data is transmitted with the MSB first. CRC Field The CRC field, consisting of a 15-bit CRC sequence and a 1-bit CRC delimiter, is used to check the frame for a transmission error. The CRC calculation includes the start of frame, arbitration field, control field, and data field. The calculated CRC and the received CRC sequence are compared, and if they do not match, an error is assumed. ACK Field The ACK field indicates that the frame has been received normally. This field consists of 2 bits, one for ACK slot and one for ACK delimiter.

CAN bus Maximum speed and bus length

The ISO-11898 CAN bus specifies that a device on that bus must be able to drive a fortymeter cable at 1Mb/s. A much longer bus length can usually be achieved by lowering the bus speed. Figure shows the variation of bus length with the communication speed. For example, with a bus length of one thousand meters we can have a maximum speed of 40Kb/s.

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Applications of CAN
1. Automotive Application 2. Industrial Applications 3. Embedded Applications Automotive Application: The automotive industry uses CAN as the in vehicle network (IVN) for the Engine management the body electronics like doors and roof control, air conditioning, lighting control, as well as the entertainment control. Industrial Applications: The CAN based warehouse automation system. The dataflow, flow of goods etc are implemented using CAN CAN is used in Fluid packaging Machines. Embedded Applications: CAN can be used in Coffee Machines CAN used in sports action camera CAN network is embedded in boilers and solar power systems CAN based measurement systems are used in petrol pumps

USB
The Universal Serial Bus (USB) is one of the most common interfaces used in electronic consumer products today, including PCs, cameras, GPS devices, MP3 players, modems, printers, and scanners, to name a few. The USB was originally developed by Compaq, Microsoft, Intel, and NEC, and later by Hewlett-Packard, Lucent, and Philips as well. The USB is a high-speed serial interface that can also provide power to devices, connected to it. A USB bus supports up to 127 devices (limited by the 7-bit address) connected through a four-wire serial cable of up to three or even five meters in length. Many USB devices can be connected to the same bus with hubs, which can have 4, 8, or even 16 ports. A device can be plugged into a hub which is plugged into another hub, and so on. According to the specification, the maximum distance of a device from its host is about thirty meters.
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The maximum power available to an external device is limited to about 100mA at 5.0V. Two types of connectors are specified and used: Type A and Type B
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USB is a four-wire interface implemented using a four-core shielded cable.

Two of the pins, Data+ and Data-, form a twisted pair and carry differential data signals and some single-ended data states.

USB signals are bi-phase, and signals are sent from the host computer using the NRZI (non-return to zero inverted) data encoding technique. In this technique, the signal level is inverted for each change to logic 0. The signal level for logic 1 is not changed. A 0 bit is stuffed after every six consecutive ones in the data stream to make the data dynamic (this is called bit stuffing because the extra bit lengthens the data stream).

NRZI data

A packet of data transmitted by the host is sent to every device connected to the bus, traveling downward through the chain of hubs. All the devices receive the signal, but
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only one of them, the addressed one, accepts the data. Conversely, only one device at any time can transmit to the host, and the data travels upward through the chain of hubs until it reaches the host. USB devices attached to the bus may be full-custom devices, requiring a full-custom device driver, or they may belong to a device class. Device classes enable the same device driver to be used for several devices having similar functionalities. For example, a printer device has the device class 0X07, and most printers use drivers of this type

Some common USB terms are

Endpoint: An endpoint is either a source or a sink of data. A single USB device can have a number of endpoints, the limit being sixteen IN and sixteen OUT endpoints. Transaction: A transaction is a transfer of data on the bus. Pipe: A pipe is a logical data connection between the host and an endpoint.

Speed Identification on the USB Bus

At the device end of the bus, a 1.5K pull-up resistor is connected from the D+ or D- line to 3.3V. On a full-speed bus, the resistor is connected from the D+ line to 3.3V On a low-speed bus the resistor is from D- line to 3.3V.

When no device is plugged in, the host will see both data lines as low. Connecting a device to the bus will pull either the D+ or the D- line to logic high, and the host will know that a device is plugged into the bus. The speed of the device is determined by observing which line is pulled high.

USB States
Some of the USB bus states are: Idle: The bus is in idle state when the pulled-up line is high and the other line is low. This is the state of the lines before and after a packet transmission. Detached: When no device is connected to the bus, the host sees both lines as low. Attached: When a device is connected to the bus, the host sees either D+ or D- go to logic high, which means a device has been plugged in.

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USB Bus Communication

USB is a host-centric connectivity system where the host dictates the use of the USB bus. Each device on the bus is assigned a unique USB address, and no slave device can assert a signal on the bus until the host asks for it. When a new USB device is plugged into a bus, the USB host uses address 0 to ask basic information from the device. Then the host assigns it a unique USB address. After the host asks for and receives further information about the device, such as the name of the manufacturer, device capabilities, and product ID, two-way transactions on the bus can begin.

Packets
Data is transmitted on a USB bus in packets. A packet starts with a sync pattern to allow the receiver clock to synchronize with the data. The data bytes of the packet follow, ending with an end of packet signal. A packet identifier (PID) byte immediately follows the sync field of every USB packet. A PID itself is 4 bits long, and the 4 bits are repeated in a complemented form. There are seventeen different PID values

There are four packet formats, based on which PID is at the start of the packet: Token packets, Data packets, Handshake packets, and Special packets.

Figure shows the format of a token packet, which is used for OUT, IN, SOF (start of frame), and SETUP. The packet contains a 7-bit address, a 4-bit ENDP (endpoint number), a 5-bit CRC checksum, and an EOP (end of packet).

A data packet is used for DATA0, DATA1, DATA2, and MDATA data transactions. The packet format is shown in Figure and consists of the PID, 01024 bytes of data, a 2-byte CRC checksum, and an EOP.

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Data Flow Types

Data can be transferred on a USB bus in four ways:

1. bulk transfer, 2. interrupt transfer, 3. isochronous transfer, and 4. Control transfer. Bulk transfers are designed to transfer large amounts of data with error-free delivery and no guarantee of bandwidth. If an OUT endpoint is defined as using bulk transfers, then the host will transfer data to it using OUT transactions. Similarly, if an IN endpoint is defined as using bulk transfers, then the host will transfer data from it using IN transactions. In general, bulk transfers are used where a slow rate of transfer is not a problem. The maximum packet size in a bulk transfer is 8 to 64 packets at full speed, and 512 packets at high speed (bulk transfers are not allowed at low speeds). Interrupt transfers are used to transfer small amounts of data with a high bandwidth where the data must be transferred as quickly as possible with no delay. Note that interrupt transfers have nothing to do with interrupts in computer systems. Interrupt packets can range in size from 1 to 8 bytes at low speed, from 1 to 64 bytes at full speed, and up to 1024 bytes at high speed. Isochronous transfers have a guaranteed bandwidth, but error-free delivery is not guaranteed. This type of transfer is generally used in applications, such as audio data transfer, where speed is important but the loss or corruption of some data is not. An isochronous packet may contain 1023 bytes at full speed or up to 1024 bytes at high speed (isochronous transfers are not allowed at low speeds). A control transfer is a bidirectional data transfer, using both IN and OUT endpoints. Control transfers are generally used for initial configuration of a device by the host. The maximum packet size is 8 bytes at low speed, 8 to 64 bytes at full speed, and 64 bytes at high speed. A control transfer is carried out in three stages: SETUP, DATA, and STATUS.

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Enumeration:
When a device is plugged into a USB bus, it becomes known to the host through a process called enumeration. The steps of enumeration are: When a device is plugged in, the host becomes aware of it because one of the data

lines (D+ or D-) becomes logic high. The host sends a USB reset signal to the device to place the device in a known state. The reset device responds to address 0. The host sends a request on address 0 to the device to find out its maximum packet size using a Get Descriptor command. The device responds by sending a small portion of the device descriptor. The host sends a USB reset again. The host assigns a unique address to the device and sends a Set Address request to the device. After the request is completed, the device assumes the new address. At this point the host is free to reset any other newly plugged-in devices on the bus. The host sends a Get Device Descriptor request to retrieve the complete device descriptor, gathering information such as manufacturer, type of device, and maximum control packet size. The host sends a Get Configuration Descriptors request to receive the devices configuration data, such as power requirements and the types and number of interfaces supported. The host may request any additional descriptors from the device. The initial communication between the host and the device is carried out using the control transfer type of data flow. Initially, the device is addressed, but it is in an unconfigured state. After the host gathers enough information about the device, it loads a suitable device driver which configures the device by sending it a Set Configuration request. At this point the device has been configured, and it is ready to respond to device-specific requests (i.e., it can receive data from and send data to the host).

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Descriptors All USB devices have a hierarchy of descriptors that describe various features of the device: the manufacturer ID, the version of the device, the version of USB it supports, what the device is, its power requirements, the number and type of endpoints, and so forth. The most common USB descriptors are: Device descriptors Configuration descriptors Interface descriptors HID descriptors Endpoint descriptors

Different versions of USB USB 1.1 defines two speeds: 12Mbps (full speed) and 1.5Mbps (low speed) and Two types of connectors: Series A and Series B.

USB 2.0 defines three speeds: 480Mbps (high speed), 12Mbps and 1.5Mbps. It is completely backwards compatible with USB 1.1.

Wireless USB Wireless extension of USB 2.0 and it operates at UWB (ultra wide band) 3.1 GHZ to 10.6 GHz frequencies. For short-range personal area network (high speed 480 Mbps 3 meter or 110 Mbps 10 meter channel)

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PARALLEL DATA COMMUNICATION

The original 8-bit parallel port was developed by IBM in 1981 as a faster interface to dot matrix printers than the standard one-bit serial port.

Advantage Number of 8 bits over the wires in parallel. High data transfer rate

Disadvantage More number of wires Capacitive effect Capacitive effect in parallel wires reduces the length up to which communication in parallel can take place. High capacitance results in delay for the bits at the other end undergoing transition from 0 to 1 or 1 to 0. High capacitance can also result in noise and cross talk (induced signals) between the wires.

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PCI Parallel Bus

Parallel bus enables a host computer or system to communicate simultaneously 32-bit or 64bit with other devices or systems, for example, to a network interface card (NIC) or graphic card In Computer system PCI- When the I/O devices in the distributed embedded subsystems are networked all can communicate through a common parallel bus. PCI connects at high speed to other subsystems having a range of I/O devices at very short distances (<25 cm) using a parallel bus without having to implement a specific interface for each I/O device. PCI protocol specifies the ways of interaction between the different components of a computer. PCI driver can access the hardware automatically as well as by the programmer assigned addresses. Automatically detects the interfacing systems and assigns new addresses. Thus, simplified addition and deletion (attachment and detachment) of the system peripherals. Each device may use a FIFO controller with a FIFO buffer for maximum throughput.

PCI device identification

Sixteen16-bit register in a PCI device identifies this number to let that device auto- detect it. Another sixteen16-bit register identifies a device ID number. These two numbers let allow the device to carry out its auto-detection by its host computer. A device identifies its address space by three identification numbers, (i) I/O port (ii) Memory locations and (iii) Configuration registers of total 256B with a four 4-byte unique ID. Each PCI device has address space allocation of 256 bytes to access it by the host computer

PCI Bridge
PCI bus interface switches a processor communication with the memory bus to PCI bus. In most systems, the processor has a single data bus that connects to a switch module PCI bridge
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Some processors integrate the switch module onto the same integrated circuit as the processor to reduce the number of chips required to build a system and thus the system cost. Communicates with the memory through a memory bus (a set of address, control and data buses), a dedicated set of wires that transfer data between these two systems. A separate I/O bus connects the PCI switch to the I/O devices.

Different versions of PCI Bus

PCI
32-bit 33 MHz throughput = 133 MBps, full component level, Connector (94-pin connector with 50 signals) 64-bit bus, 66 MHz option

PCI-X

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Maximum 264 MBps throughput, uses 8, 16, 32, or 64 bit transfers 6U cards contain additional pins for user defined I/Os
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Live insertion support (Hot-Swap), Supports two independent buses on the back plane (on different connectors) Supports Ethernet, Infiniband, and Star Fabric support (Switched fabric based systems) Compact PCI (cPCI)

Two super speed versions

PCI Super V2.3 264/528 MBps 3.3V (on 64- bit bus), and 132/264 (on 32-bit bus) and PCI-X Super V1.01a for 800MBps 64- bit bus 3.3Volt.

WIRELESS AND MOBILE SYSTEM PROTOCOL

IrDA (Infrared Data Association) Bluetooth 2.4 GHz 802.11 WLAN 802.11b Wi-Fi ZigBee 900 MHz

IrDA (Infrared Data Association)

Infrared:
Infrared (IR) light is electromagnetic radiation with a wavelength longer than that of visible light, starting from the nominal edge of visible red light at 0.7um, and extending conventionally to 300um. These wavelengths correspond to a frequency range of approximately 430 to 1 THz, and include most of the thermal radiation emitted by objects near room temperature. Microscopically, IR light is typically emitted or absorbed by molecules when they change their rotational-vibrational movements. Infrared interfaces are now commonplace for a number of devices such as palmtops, cell phones, digital cameras, printers, keyboards, mice, LCD projectors, ATMs, smart cards, etc. Infrared interface provides a low-cost, short range, point-to-point communication between two devices. Infrared Data Association (IrDA), a nonprofit industry association founded in 1993, released the specifications for low-cost infrared communication between devices. The block diagram of IrDA module As shown in figure below, the device will have an infrared transceiver. The transmitter is a LED and the receiver is a photodiode. For low data rates, the processor of the embedded system itself
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can be used whereas for high data rates, a different processor may be needed. The data to be sent on the infrared link is packetized and encoded as per the IrDA protocols and sent over the air to the other device. The receiving device will detect the signal, decode and de-packetize the data.

Protocol Architecture: As shown in figure below, for communication through infrared interface, the physical layer (IrPHY) and data link layer (IrLAP) are specified in the standards. Link management is done through IrLMP, above which the application layer protocols will be running.

Physical layer: IrPHY specifies the data rates and the mode of communication. IrDA has two specifications, IrDA data and IrDA control. IrDA data has a range of 1m whereas for IrDA control has a range of 5m both with bidirectional communication. A host such as PC can communicate with 8 peripherals using IrDA protocols. Data link layer: The data link layer is called the IrLAP. Master/Slave protocol is used for communication between two devices. The device that starts the communication is the master. The master sends the command and the slave sends a response. Link management layer: This layer facilitates a device to query the capabilities of other devices. If also provides the software capability to share IrLAP between multiple tasks. Higher layers: The higher layer protocols are application specific. IrCOMM protocol emulates the standard serial port. When two devices such as palmtop and mobile phone both fitted with infrared interface come face to face, they can exchange the data using the application layer protocol. Supports data transfer rates of up to 4 Mbps Supports bi-directional serial communication over viewing angle between 15 and distance of nearly 1 m
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 At 5 m, the IR transfer data can be up to data transfer rates of 75 kbps Should be no obstructions or wall in between the source and receiver Communication setup latency is just few milliseconds

Bluetooth 2.4 GHz

Bluetooth is a proprietary open wireless technology standard for exchanging data over short distances from fixed and mobile devices, creating personal area networks (PANs) with high levels of security. Created by telecoms vendor Ericsson in 1994, it was originally conceived as a wireless alternative to RS-232 data cables. It can connect several devices, overcoming problems of synchronization. Features of Bluetooth: It is a low cost technology It has very low power consumption It is based on radio transmission in the ISM band It caters to short ranges It is based on open standards formulated by a consortium of industries and a large number of equipment vendors are committed to this technology Bluetooth System Specifications: Radio frequency: Bluetooth uses the unlicensed ISM (Industrial, Scientific and Medical) band, 2400 - 2483.5 MHz, thereby maximizing communication compatibility worldwide. This requirement for global usage was the key driver for this choice of spectrum. Modulation: Uses Gaussian frequency shift keying, GFSK, with modulation index limited to 0.28-0.35 (corresponding to a max frequency deviation of 140-175 kHz). Frequency Hopping Spread Spectrum: Bluetooth adopts the use of FHSS to hop at up to 1600 hops/sec, amongst 79 channels, spaced at 1 MHz separation. Transmission Power: Three power classes are supported by the standard. In practice almost all Bluetooth devices developed to date support only one of these options, most being the low power, short range, option. Class 3 - 1mW (0dBm) with a 'typical range' of 10m Class 2 - 2.5mW (4dBm) with a 'typical range' of 20m
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 Class 1 - 100mW (20dBm) with a 'typical range' of 100m Network Topology: Bluetooth enabled devices form a network known as piconet. In a piconet, there will be one master and up to seven active slaves. Communication between the master slaves can be point-topoint or point-to-multipoint. Point-to-point communications between Master and Slave:

Point-to-multipoint communications between master and multiple slaves:

Scatternet: Several piconets can overlap and form a scatternet

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Communication between Master and Slave: The Master and Slave communicate in the form of packets. Each packet is transmitted in a time slot. Each time slot is of 625us duration. These slots are numbered from 0 to 227-1. Master starts the transmission in even slots by sending a packet addressed to a slave and the slave sends the packets in odd numbered slots. A packet generally occupies one time slot; the hop frequency will be the same for the entire packet. If the Master starts the transmission in slot 0 using frequency f1, the slave transmits in slot 1 using frequency f2; mater transmits in slot 2 using frequency f3, and so on. Applications Wireless control of and communication between a mobile phone and a hands-free headset. Wireless Bluetooth headset and Intercom. Wireless communication with PC input and output devices, the most common being the mouse, keyboard and printer. Replacement of previous wired RS-232 serial communications Wireless bridge between two Industrial Ethernet

ZigBee 900 MHz

IEEE standard 802.15.4 protocol. Physical layer radio operates 2.4 GHz band carrier frequencies with DSSS (direct sequence spread spectrum). Communication latency 30 ms Supports range up to 70 m. Data transfer rate supported 250 kbps. Supports sixteen channels.

ZigBee network feature:

Self-organizing and supports peer-to-peer and mesh networks-Self-organizing means detects nearby ZigBee device and establishes communication and network.

Peer-to-peer and mesh networks- Each node at network function as requesting device as
well as responding device. Mesh network means the each nodes network function as a mesh.
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ZigBee network:
ZigBee router- Transfers packets received from a neighboring source to nearby node in the path to destination. Coordinator - Connects one ZigBee network with another, or connects to WLAN or cellular network. end devices- Transceiver of data. ZigBee supporting devices: large number of sensors, Lighting devices, air conditioning, industrial controller and other devices for home , office automation and their remote control and formation of WPAN (wireless personal area network)

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Unit 3. Device drivers and interrupts servicing mechanism:

Interrupts are probably the most important aspect of any embedded system design and potentially can be responsible for many problems when debugging a system. Although they are simple in concept, there are many pitfalls that the unwary can fall into. What is an interrupt? We all experience interrupts at some point during our lives and find that they either pose no problem at all or they can very quickly cause stress and our performance decreases. For example-Take a car mechanic working in a garage who not only has to work on the cars but also answer the phone. The normal work of servicing a car continues throughout the day and the only other task is answering the phone. Not a problem, you might think but each incoming phone call is an interrupt and requires the mechanic to stop the current work, answer the call and then resume the current work. The time it takes to answer the call depends on what the current activity is. If the call requires the mechanic to simply put down a tool and pick up the phone, the overhead is short. If the work is more involved, and the mechanic needs to support a component's weight so it can be let go and then need to clean up a little before picking up the phone, the overhead can be large. It can be so long that the caller rings off and the phone call is missed. The mechanic then has to restart the work. If the mechanic receives a lot of phone calls, it is possible that more time is spent in getting ready to answer the call and restarting the work than is actually spent performing the work. In this case, the current work will not be completed on time and the overall performance will be greatly reduced. We can relate the above example to an embedded system-With an embedded design, the mechanic is the processor and the current work is the foreground or current task that it is executing. The phone call is the interrupt and the time taken to respond to it is the interrupt latency. If the system is not designed correctly, coping with the interrupts can prevent the system from completing its work or miss an interrupt. In either case, this usually causes problems with the system and it will start to misbehave. In the same way that humans get irrational and start to go away from normal behavior patterns when continually interrupted while trying to complete some other task, embedded systems can also start misbehaving! It is therefore
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essential to understand how to use interrupts and perhaps when not to, so that the embedded system can work correctly. The impact of interrupts and their processing does not stop there either. It can also affect the overall design and structure of the system, particularly of the software that will be running on it. In a well designed embedded system, it is important to actively design it with interrupts in mind and to define how they are going to be used. Interrupt: An interrupt is an event from either an internal or external source where a processor will stop its current processing or switch to a different instruction sequence in response to an event that has occurred either internally or externally Or An interrupt is an input to a microprocessor that temporarily redirects the program flow. An interrupt can n o w the processor when an analog-to digital converter (ADC) has new data, when a timer rolls over, when a direct memory access (DMA) transfer is complete, when another processor wants to communicate, or when almost any asynchronous event happens. The interrupt hardware is initialized and programmed by the system software. When an interrupt is acknowledged, that process is performed by hardware internal to the processor and the interrupt controller integrated circuit What is the importance of Interrupt? In particular, suppose the program running on a microprocessor must, among other tasks, read and process data from a peripheral whenever that peripheral has new data; such processing is called servicing. If the peripheral gets new data at unpredictable intervals, then how can the program determine when the peripheral has new data? The most straightforward approach is to interleave the microprocessors other tasks with a routine that checks for new data in the peripheral, perhaps by checking for a 1 in a particular bit in a register of the peripheral. This repeated checking by the microprocessor for data is called polling. Polling is simple to implement, but this repeated checking wastes many clock cycles, so may not be acceptable in many cases, especially when there are numerous peripherals to be checked. We could check at less-frequent intervals, but then we may not process the data quickly enough. 1. Polling consumes a lot of CPU horsepower. Whether the peripheral is ready for service or not, processor timeusually a lot of processor timeis spent endlessly asking do you need service yet?
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2. Polled code is generally an unstructured mess. Nearly every loop and long complex calculation has a call to the polling routines so that a devices needs never remain unserviced for long. ISRs, on the other hand, concentrate all of the codes involvement with each device into a single area. 3. Polling leads to highly variable latency. If the code is busy handling something else (just doing a floating point add on an 8-bit CPU might cost hundreds of microseconds) the device is ignored. Properly managed interrupts can result in predictable latencies of no more than a handful of microseconds. To overcome the limitations of polling, most microprocessors come with a feature called external interrupt. A microprocessor with this feature has a pin, say Int. At the end of executing each machine instruction, the processors controller checks Int. If Int is asserted, the microprocessor jumps to a particular address at which a subroutine exists that service the interrupt. This subroutine is called an Interrupt Service Routine, or ISR. Such I/O is called interrupt-driven I/O. One might wonder if interrupts have really solved the problem with polling, namely of wasting time performing excessive checking, since the interrupt pin is "polled" at the end of every microprocessor instruction. However, in this case, the polling of the pin is built right into the microprocessors controller hardware, and therefore can be done simultaneously with the execution of an instruction, resulting in no extra clock cycles. Interrupts allow the microcontroller to interact with its environment. If your microcontroller does not have interrupts you must poll peripherals to determine if they require servicing. It is much more efficient to have peripheral devices inform, or interrupt, the controller when they require servicing.

What is the Structure of an Interrupt? Different microcontrollers have rather different interrupt structures. Inevitably they have more than one interrupt source, usually with some internally generated and others external. A generic structure, which illustrates the main hardware principles, is shown in Figure. At the left we see one of several sources, Interrupt X. If an interrupt occurs, it sets an S-R bistable. The occurrence of the interrupt, even if it is only momentary, is thus recorded. The output of the bistable, the latched version of the interrupt, is called the interrupt flag. This is then gated with an enable signal, Interrupt X Enable. If this is high, then the interrupt signal progresses to an OR
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gate. If it is low, the interrupt signal gets no further. If enabled, it is ORed with other enabled interrupt inputs of the microcontroller. The OR gate output will go high if any interrupt input is high. There is then a further gating of the OR gate output, this time with a Global Interrupt Enable. Only if that value is high can any interrupt signal reach the CPU. When the CPU has responded to an interrupt, As the CPU always responds if it occurs, there is less point in storing it as a flag, and this is sometimes therefore not done.

it is necessary to clear the interrupt flag. In some processors this is done automatically by the CPU, in others it must be done within the program. How CPU response to an interrupt? In general, when an interrupt occurs, the on-chip hardware performs the following functions: It saves the program counter (the address the processor was executing when the interrupt occurred) on the stack. Some processors save other information as well, such as register contents. It executes an interrupt acknowledge cycle to get a vector from the interrupting peripheral, depending on the processor and the specific type of interrupt. It branches to a predetermined address specific to that particular interrupt.

The destination address is the interrupt service routine (ISR, or sometimes ISP for interrupt service process). The ISR performs whatever functions are required and then returns. When the return code is executed, the processor performs the following tasks: It retrieves the return address and any other saved information from the stack. It resumes execution at the return address.
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Interrupt-driven I/O using fixed ISR location

1. Microprocessor is executing its program, say current program counter (PC) =100. 2. Peripheral1s input device stores new data in register at 0x8000. 3. Peripheral1 asserts Int to request servicing by microprocessor of the new data. 4. Microprocessor stops executing its program and stores state, including PC. 5. Microprocessor jumps to fixed location of ISR at program memory location 16 (sets PC=16) 6. ISR reads data from 0x8000, modifies the data, and writes to 0x8001. 7. ISR returns, causing restoration of the microprocessor state, thus setting PC= 100+1 = 101 8. Microprocessor resumes executing its program. Interrupt-driven I/O using vectored interrupt.

1. Microprocessor is executing its program, say current program counter (PC)=100. 2. Peripheral1s input device stores new data in register at 0x8000. 3. Peripheral1 asserts Int to request servicing by microprocessor of the new data. 4. Microprocessor stops executing its program and stores state, including PC. 5. Microprocessor asserts Inta 6. Peripheral1 puts its interrupt address vector 16 on the system bus 7. Microprocessor jumps to the address of ISR read from the data bus, in this case 16. 8. ISR reads data from 0x8000, modifies the data, and writes to 0x8001. 9. ISR returns, causing restoration of the microprocessor state, thus setting PC= 100+1 = 101 10. Microprocessor resumes executing its program.
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Context, context Switching

Context A context of a program must include program counter as well as the program status word, stack pointer and may include the processor registers. The context may be at a register set or at the separate memory block for the stack. A register set or memory block can hold context information Present CPU state, which means registers and May include ID of the process interrupted and Functions local variables. Current Program Context

Context Switching New program executes with new context of called routine

Context Switching on Interrupts Context switching means saving the context of interrupted routine (or function) or task and retrieving or loading the new context of the called routine or task to be executed next.

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Context switching in case of multiple interrupts

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Example with respect to PIC MCU Let us assume that an interrupt has occurred, and both its local enable and the global enable are set. The interrupt is therefore detected by the CPU and it executes a special section of program called the Interrupt Service Routine (ISR). The CPU completes the instruction it is currently executing and saves the value of the Program Counter on the top of the Stack. Thus, it will know where to come back to when the ISR is complete. To avoid other interrupts possibly interrupting this interrupt, it also clears the Global Interrupt Enable. The ISR must start at the interrupt vector ie., program memory location. Therefore, when an interrupt occurs, this value is loaded into the Program Counter and program execution then continues from the reset vector. In any processor, the ISR must end with a special return from interrupt instruction. When this return instruction is detected, the CPU sets the GIE to 1, loads the Program Counter from the top of the Stack and then resumes program execution. Thus, it returns to the instruction which follows the instruction during which the interrupt was detected.

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Interrupt latency. The time between the interrupt occurring and the CPU responding to it is called the interrupt latency. The latency is dependent on certain aspects of hardware and ultimately can also depend on the characteristics of the program running Interrupt Vectors: All processors require an interrupt vector when an interrupt is acknowledged. The interrupt vector tells the processor where to go to service the interrupt. On some processors, the vector can be an actual instruction that is executed just as if it occurred in ordinary code. Other processors expect a number that is translated by the processor into an address.

There are mainly three methods of generating a vector to the processor: 1. From an external interrupt controller, 2. From an internal interrupt controller, 3. From the peripheral itself.

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There are mainly two sources of interrupt: hardware and software. Hardware interrupts include a signal to a pin, timer overflow, and serial port interrupts. Software interrupts are commands given by the programmer, such as the SWI instruction There are two different interrupt types: maskable and non-maskable. A maskable interrupt can be disabled and enabled While non-maskable interrupts cannot be disabled and are therefore always enabled. Most 8 bit microcontrollers use vectored arbitration interrupts. Vectored arbitration means that when a specific interrupt occurs the interrupt handler automatically branches to an address associated with that interrupt. The servicing of interrupts in general is dictated by the status of the GIE (Global Interrupt Enable). GIE is cleared when an interrupt occurs and all interrupts are delayed until it is set. Synchronous and Asynchronous Interrupt Acknowledgement Interrupts are asynchronous: they are events that can occur during, after, or before an instruction cycle. Interrupt acknowledgement can be either synchronous or asynchronous. Most interrupt acknowledgement is synchronous, the instruction currently being executed is completed before the interrupt is acknowledged. Theoretically, when the processor acknowledges an interrupt asynchronously it halts execution of the current instruction and immediately services the interrupt. The only asynchronously acknowledged interrupt is RESET. Since RESET erases the state of the machine, it is a moot point whether the CPU actually halts execution of the current instruction or not. When the processor acknowledges an interrupt synchronously, it finishes executing the current instruction and, before it performs a fetch for the next instruction, it services the interrupt.

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ISR Deadline
For every source there may be a maximum period only up to which the service of its all ISR instructions can be kept pending. This period defines the Deadline period, Td during which the execution must be completed.

Short ISR and functions, which run at later instances so that the other ISR deadlines are not missed

Interrupt latency = T should be such that a deadline of a new event ISR is not missed
Example Video Video frames in video conferencing reach after every 1 15 s. The device on getting the frame interrupts the system and the interrupt service deadline is 1 15 s, else the next frame will be missed
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16-bit timer A 16-bit timer device on overflow raises TF interrupt on transition of counts from 0xFFFF to 0x0000. To be responded by executing an ISR for TF before the next overflow of the timer occurs, else the counting period between 0x0000 after overflow and 0x000 after next to next overflow will not be accounted. If timer counts increment every 1s, the interrupt service deadline is 216 s = 65536 s. To keep the ISR as short as possible In case of multiple interrupt sources To service the in-between pending interrupts and leave the functions that can be executed afterwards later for a later time. Use of interrupt service threads, which are the second level interrupt handlers. When this principle is not adhered to, a specific interrupting source may not be serviced within in the deadline (maximum permissible pending time) for that Assignment of priorities to Meet Service Deadlines By following an Earlier Deadline First strategy for assigning the priorities to the ISRs and Tasks, the service deadlines are met. Software overriding of Hardware Priorities to Meet Service Deadlines It is first decided among the ISRs that have been assigned higher priority by in the user software. If user assigned priorities are, and then if these equal then among the that highest priority, which is pre-assigned by at the processor internal- hardware.

Interrupt sources
There are many sources for interrupts varying from simply asserting an external pin to error conditions within the processor that require immediate attention. HARDWARE INTERRUPTS Internal interrupts Internal interrupts are those that are generated by on-chip peripherals such as serial and parallel ports. With an external peripheral, the device will normally assert an external pin which is connected to an interrupt pin on the processor. With internal peripherals, this connection is already made. Some integrated processors allow some flexibility concerning these hardwired connections and allow the priority level to be adjusted or even masked out or disabled altogether. Examples of Internal Hardware Device Sources 1 Parallel Port
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2. UART Serial Receiver Port - [Noise, Overrun, Frame-Error, IDLE, RDRF in 68HC11] 3. Synchronous Receiver byte Completion 4. UART Serial Transmit Port-Transmission Complete, [For example, TDRE (transmitter data register Empty] 5. Synchronous Transmission of byte completed 6. ADC Start of Conversion 7. ADC End of Conversion 8. Pulse-Accumulator overflows 9. Real Time Clock time-outs 10. Watchdog Timer Reset 11. Timer Overflow on time-out 12. Timer comparison with Output compares Registers 13. Timer capture on inputs

External interrupts External interrupts are the common method of connecting external peripherals to the processor. They are usually provided through external pins that are connected to peripherals and are asserted by the peripheral. For example, a serial port may have a pin that is asserted when there is data present within its buffers. The pin could be connected to the processor interrupt pin so that when the processor sees the data ready signal as an interrupt. The corresponding interrupt service routine would then fetch the data from the peripheral before restoring the previous processing. 1. INTR in 8086 and 80x86 The device provides the ISR Address or Vector Address or Type externally on data bus after interrupt at INTR pin 2. External hardware related interrupt at INTR Pin in 80x86 processor 3. External Hardware Device Nonmaskable Interrupts with Internal Vector Address Generation. Non-Maskable Pin NMI in 8086 Exceptions Many processor architectures use the term exception as a more generic term for an interrupt. While the basic definition is the same (an event that changes the software flow to process the event) an exception is extended to cover any event, including internal and external

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interrupts, that causes the processor to change to a service routine. Typically, exception processing is normally coupled with a change in the processors mode RESET Microcontrollers vary widely in the types of interrupts they can detect. Some general types are widely available in one form or another. The only universal interrupt is RESET and some simple chips support no other interrupts. The RESET interrupt prompts the chip to behave as if the power has been cycled. It does not actually cycle the power to the chip. This means that the contents of volatile memory, typically data memory, can remain intact. The reset vector contains the address of the first instruction that will be executed by the CPU. On most chips, RESET causes the CPU to halt execution immediately and restart itself. On some chips, RESET may finish the current instruction. Each microcontroller performs a series of actions when it detects a RESET. TIMER A TIMER interrupt occurs when a timer overflow is detected. For example, In the Microchip PIC there is a TMR0 interrupt which is generated when the TMR0 8 bit timer overflows. An overflow occurs when the timer goes from 1111 1111 to 0000 0000. The timer is usually incremented every instruction cycle. TIMER interrupts in general provide access to an external clock. This is useful in applications where timing is critical. For control applications, for example, it is important to sample input data at specific time Software interrupts Software interrupt are related to software detecting computational error or exceptional condition during execution and there up on executing a SWI (software interrupt) instruction, which causes processor interrupt of ongoing routine. The advantage of an interrupt is that it includes a mechanism to change the program flow and in some processor architectures, to change into a more protected state. This means that an interrupt could be used to provide an interface to other software such as an operating system. This is the function that is provided by the software interrupt. It is typically an instruction or set of instructions that allows a currently executing software sequence to change flow and return using the more normal interrupt mechanism. S
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Two types of Interrupt Sources:

Maskable Interrupt sources

Maskable sources of interrupt provides for masking and unmasking the interrupt service (diversion to the ISR). Execution of a device interrupt source or source group can be masked. On a pin, an external interrupt request can be masked. Execution of a software interrupt (trap or exception or signal) can be masked. Most interrupt sources are maskable.

Non-maskable Interrupt Sources (NMIs)

A few specific interrupt cannot be masked. A few specific interrupt can be declared non-maskable within few clock cycle of processor reset, else that is maskable.

Direct memory access

Commonly, the data being accumulated in a peripheral should be first stored in memory before being processed by a program running on the microprocessor. Such temporary storage to await processing is called buffering. For example, packet-data from an Ethernet card is stored in main memory and is later processed by the different software layers (such as IP stacks). We could write a simple interrupt service routine on the microprocessor, such that the peripheral device would interrupt the microprocessor whenever it had data to be stored in memory. The ISR

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would simply transfer data from the peripheral to the memory, and then resume running its application. For example, as we discussed in Interrupt-driven I/O using vectored interrupt. In that topic an example in which Peripheral1 interrupts the microprocessor when receiving new data. The microprocessor jumps to ISR location 16, which moves the data from 0x8000 in the peripheral to 0x0001 in memory. Then the ISR returns. However, recall that jumping to an ISR requires the microprocessor to store its state (i.e., register contents), and then to restore its state when returning from the ISR. This storing and restoring of the state may consume many clock cycles, and is thus somewhat inefficient. Furthermore, the microprocessor cannot execute its regular program while moving the data, resulting in further inefficiency.

The I/O method of direct memory access (DMA) eliminates these inefficiencies. In DMA, we use a separate single-purpose processor, called a DMA controller, whose sole purpose is to transfer data between memories and peripherals. Briefly, the peripheral requests servicing from the DMA controller, which then requests control of the system bus from the microprocessor. The microprocessor merely needs to relinquish control of the bus to the DMA controller. The microprocessor does not need to jump to an ISR, and thus the overhead of storing and restoring the microprocessor state is eliminated. Furthermore, the microprocessor can execute its regular program while the DMA controller has bus control, as long as that regular
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program doesnt require use of the bus (at which point the microprocessor would then have to wait for the DMA to complete). A system with a separate bus between the microprocessor and cache may be able to execute for some time from the cache while the DMA takes place. We set up a system for DMA as follows. As shown in below Figure we connect the peripheral to the DMA controller rather than the microprocessor. Note that the peripheral does not recognize any difference between being connected to a DMA controller device or a microprocessor device; all it knows is that it asserts a request signal on the device, and then that device services the peripherals request. We connect the DMA controller to two special pins of the microprocessor. One pin, which well call Hreq (bus Hold Request), is used by the DMA controller to request control of the bus. The other pin, which well call Hlda (Hold Acknowledge), is used by the microprocessor to acknowledge to the DMA controller that bus control has been granted. Thus, unlike the peripheral, the microprocessor must be specially designed with these two pins in order to support DMA. The DMA controller also connects to all the system bus signals, including address, data, and control lines.

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Arbitration during Multiple Interrupt

Several situations existed in which multiple peripherals might request service from a single resource. For example, multiple peripherals might share a single microprocessor that services their interrupt requests. As another example multiple peripherals might share a single DMA controller that services their DMA requests. In such situations, two or more peripherals may request service simultaneously. We therefore must have some method to arbitrate among these contending requests, i.e., to decide which one of the contending peripherals gets service, and thus which peripherals need to wait. Several methods exist, 1. Priority arbiter One arbitration method uses a single-purpose processor, called a priority arbiter. We illustrate a priority arbiter arbitrating among multiple peripherals using vectored interrupt to request servicing from a microprocessor, as illustrated in below Figure, each of the peripherals makes its request to the arbiter. The arbiter in turn asserts the microprocessor interrupt, and waits for the interrupt acknowledgment. The arbiter then provides an acknowledgement to exactly one peripheral, which permits that peripheral to put its interrupt vector address on the data bus (which, as youll recall, causes the microprocessor to jump to a subroutine that services that peripheral). Priority arbiters typically use one of two common schemes to determine priority among peripherals: fixed priority or rotating priority. In fixed priority arbitration, each peripheral has a unique rank among all the peripherals. The rank can be represented as a number, so if there are four peripherals, each peripheral is ranked 1, 2, 3 or 4. If two peripherals simultaneously seek servicing, the arbiter chooses the one with the higher rank. In rotating priority arbitration (also called round-robin), the arbiter changes priority of peripherals based on the history of servicing of those peripherals. For example, one rotating priority scheme grants service to the least-recently serviced of the contending peripherals. This scheme obviously requires a more complex arbiter. We prefer fixed priority when there is a clear difference in priority among peripherals. However, in many cases the peripherals are somewhat equal, so arbitrarily ranking them could cause high-ranked peripherals to get much more servicing than low ranked ones. Rotating priority ensures a more equitable distribution of servicing in this case. 1. Microprocessor is executing its program. 2. Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so asserts Ireq2. 3. Priority arbiter sees at least one Ireq input asserted, so asserts Int. 4. Microprocessor stops executing its program and stores its state. 5. Microprocessor asserts Inta. 6. Priority arbiter asserts Iack1 to acknowledge Peripheral1. 7. Peripheral1 puts its interrupt address vector on the system bus 8. Microprocessor jumps to the address of ISR read from data bus, ISR executes and returns
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(and completes handshake with arbiter). 9. Microprocessor resumes executing its program.

Arbitration using a priority arbiter. 2. Daisy-chain arbitration The daisy-chain arbitration method builds arbitration right into the peripherals. A daisychain configuration is shown in below Figure, again using vectored interrupt to illustrate the method. Each peripheral has a request output and an acknowledge input, as before. But now each peripheral also has a request input and an acknowledge output. A peripheral asserts its request output if it requires servicing, OR if its request input is asserted; the latter means that one of the "upstream" devices is requesting servicing. Thus, if any peripheral needs servicing, its request will flow through the downstream peripherals and eventually reach the microprocessor. Even if more than one peripheral requests servicing, the microprocessor will see only one request. The microprocessor acknowledges connects to the first peripheral. If this peripheral is requesting service, it proceeds to put its interrupt vector address on the system bus. But if it doesnt need service, then it instead passes the acknowledgement upstream to the next peripheral, by asserting its acknowledge output. In the same manner, the next peripheral may either begin being serviced or may instead pass the acknowledgement along. Obviously, the peripheral at the front of the chain, i.e., the one to which the microprocessor acknowledge is connected, has highest priority, and the peripheral at the end of the chain has lowest priority. We prefer a daisy-chain priority configuration over a priority arbiter when we want to be able to add or remove peripherals from an embedded system without redesigning the system. Although conceptually we could add as many peripherals to a daisy-chain as we desired, in reality the servicing response time for peripherals at the end of the chain could become intolerably slow. In contrast to a daisy-chain, a priority arbiter has a fixed number of channels; once they are all used, the system needs to be redesigned in order to accommodate more peripherals. However, a daisy-chain has the drawback of not supporting more advanced priority schemes, like rotating priority. A second drawback is that if a peripheral in the chain stops working, other peripherals may lose their access to the processor.
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Arbitration using a Daisy-chain

Device driver
A device driver has a set of routines (functions) used by a high-level language programmer, which does the interaction with the device hardware, sends control commands to the device, communicates data to the device and runs the codes for reading device data. Does the interrupt service for any event related to the device and use the system and IO buses required for the device service. Device driver can be considered software layer between an application program and the device Device driver routine Each device in a system needs device driver routine with number of device functions. An ISR relates to a device driver command (device-function). The device driver uses SWI to call the related ISR (device-function routine) The device driver also responds to device hardware interrupts.

Device types, Physical and Virtual device functions Device Types

For each type of device, there is a set of the generic commands. For example, for char device one set of commands and for block device there can be another set. Types of Physical and Virtual devices in a system are char, block, loop back device, file, pipe, socket, RAM disk, sound, video and media. Virtual device driver Definition: A virtual-device driver is the component of a device driver that communicates directly between an application and memory or a physical device. Virtual device driver controls the flow of data Allows more than one application to access the same memory or physical device without conflict. Virtual Devices Besides the physical devices of a system, drivers are also used in a system for virtual devices.
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 Physical device drivers and virtual device drivers have analogies. Like physical device, virtual device drivers may also have functions for device connect or open, read, write and close.

Virtual Device Examples Pipe device: A device from to which the blocks of characters are send from one end and accessed from another ends in FIFO mode (first-in first-out) after a connect function is executed. Socket device: A device from to which (a) the blocks of characters are send from one end with a set of the port (application) and sender addresses, (b) accessed from another end port (application) and receiver addresses, (c) access is in FIFO mode (first-in first-out) only after a connect function is executed to connect two sockets. Multiple functions in a Timer device A timer device control registers needs to be programmed by a device function. A timer Device performs does timing functions as well as counting functions. It also performs does the delay function and periodic system calls.

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Unit 4
SOFTWARE PROGRAMMING IN ASSEMBLY LANGUAGE (ALP) AND IN HIGH LEVEL LANGUAGE C, C++ and JAVA
Assembly Language Programming Assembly language lies in between the high level and low level languages. The assembly language uses mnemonic codes for writing the programs. Assembler is the tool which is used to convert the assembly language in the machine language. Advantages It gives a precise control of the processor internal devices and full use of processor specific features in its instruction set and its addressing mode. The machine codes are compact. This is because the codes for declaring the conditions, rules, and data type do not exist. The system thus needs a smaller memory. Excess memory needed does not depend on the programmer data type selection and rule-declarations. It is also not the compiler specific and library functions specific. Device driver codes may need only a few assembly instructions. For example, consider a small embedded system, a timer device in a microwave oven or an automatic washing machine or an automatic chocolate vending machine. High Level Language All the programming languages currently used are the high level languages. The constructs of the programming language are common language english like structures. Interpreter and the Compilers are the system programs which are used to convert the high level language in the machine odes. Advantages The development cycle is short for complex systems l. Data type declarations provide programming ease 2. Type checking makes the program less prone to error 3. Control structures and conditional Statements make the program-flow path design tasks simple. 4. Portability of non-processes specific codes exists. Additional advantages of C as a high level languages It is a language between low (assembly) and high level language. Inserting the assembly language codes in- between is called ln-line assembly. A direct hardware control is thus also feasible by in-line assembly, and the complex part of the program can be in high-level language.
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Difference between Embedded C and Conventional C The C language is used for desktop application while embedded C is used for microcontroller application. The C language uses the desktop OS memory, while embedded C uses the controllers inbuilt or any externally attached memory. In the case of controller we have very limited resources (controllers RAM, ROM, IO ports, etc.) so one must be very careful about declaring and using the variable. At any instant of time you need to be care full that you are not using the space more than the available one in the controller or else the program will get crash, or you may not get the exact result. The embedded C needs a different platform then C. Almost every family of controllers needs a different platform to write their codes. A convention C code generates an OS compatible .exe file while embedded C code generates a .hex file which has the machine codes to be dumped in the memory of the controller. In C we use header files like stdio.h, which yield the output to be visible on OS itself. In embedded C everything is same but the output files are directly loaded on the controllers to test them. The C language is use to make a program for host interaction while embedded C is use to implement the host on the controller which interact with the other peripherals.

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C PROGRAM ELEMENTS
HEADER AND SOURCE FILES AND PREPROCESSOR DIRECTIVES The 'C' program elements are header and source files and preprocessor directives are as follows: Include Directive for the Inclusion of Files (Header File) Any C program first includes the header and source files that are readily available Including Header Files: It is a preprocessor directive, which includes the contents (codes or data) of a set of source files. The pre-processor directives will be #include <string.h> and # include <math.h> Also included are the header files for the codes in assembly, and for the IO operations (conio.h), for the OS functions and RTOS functions for conventional C. In embedded C we have the device-specific header files declared using statements like #include<p18xxxx.h>. The header file includes the names of various special function registers used in the program. We can then optionally declare the other source files to be included in our main program, using the #include statement, followed by the filenames.

Whether to Use Headers or Not? As a professionally embedded systems developer one can write a standalone C code, requiring no header files, and it will compile correctly However, this requires a through study of the target microcontroller architecture, it is difficult to remember the on-chip resources, it is advisable to use the header files which defines all the on-chip resources for the target microcontroller, Source Files Source files are program files for the functions of application software. The source files need to be compiled. A source file will also possess the preprocessor directives of the

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application and have the first function from where the processing will start. This function is called main function. Its codes start with void main ().The main calls other functions Preprocessor Directives Preprocessor Global Variables: # define volatile Boolean X" is a preprocessor directive. It means, it is a directive before processing to consider X a global variable of Boolean data type and is volatile. Preprocessor Constants: "# define false 0" is a preprocessor directive. It means it is a directive before processing to assume 'false' as 0.

Functions The functions executes a named set of codes with values passed by, the calling program through its arguments. Also returns a data object when It is not declared as void, It has the context saving and retrieving overheads. Main Function Declarations of functions and data types, typedef and either (i) Executes a named set of codes, calls a set of functions, and calls on the interrupts the ISRs (ii) Starts an OS Kernel Recursive Function A function that calls itself. It must be a reentrant function also, Most often its use is avoid in embedded systems due to memory constraints. Reentrant Function Reentrant function is usable by the several tasks and routines synchronously

Use of Data Types

Whenever a data is named, it will have the address (es) allocated at the memory. The number of addresses allocated depends upon the data type, 'C' allows the following primitive data type

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unsigned char total, sum=150; These are 8-bit unsigned variables with a range 0255. In the above example, two 8-bit variables named total and sum are created and sum is assigned a decimal value 150

Use of Data Structures

A data structure is an important element of any program. A few important data structure are stack, one-dimensional array, queue, circular queue, pipe, a table (two dimensional arrays) lookup table, hash table and list. The following section gives the uses and shows exemplary uses of queues, stacks, a arrays lists and trees

Queue
It is a structure with a series of elements with the first element waiting for an operation. An operation can be done only in the first in first out (FIFO) mode. lt is used when an element is not to be accessible by any index and pointer directly, but only through the FIFO. An element can be inserted only at the end in the series of elements waiting for an operation. There are two pointers, one for deleting after the operation and other for inserting. Both increment after an operation. Example Print buffer. Each character to be printed in FIFO mode

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A queue at a memory block with two pointers to point its two elements at the front and back. A data word always retrieves in FIFO mode from a queue

A circular queue at a memory block with two pointers to point its two elements at the front and back. A pointer on reaching a limit of the block returns to the start of the block.

Stack
It is a structure with a series of elements with its last element waiting for an operation. An operation can be done only in the last in first out (LIFO) mode. It is used when an element is not to be accessible by any index or pointer directly, but only through the LIFO. An element can be pushed (inserted) only at the top in the series of elements still waiting for an operation. There is only one pointer used for pop (deleting) after the operation as well as for push (inserting). Pointers increment or decrement after an operation. It depends on insertion or deletion. Example Pushing of variables on interrupt or call to another function.

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Array (One Dimensional Vector)

It is a structure with a series of elements with each element accessible by an identifier name and an index. Its element can be used and operated easily. It is used when each element of the structure is to be given a distinct identity by an index for easy operation. Index stars from 0 and is +ve integers. For example, Unsigned int Total [5]; Creates an array of type unsigned int, with name Total and has five elements. The first element of an array is indexed with 0. Thus, in the above example, Total [0] refers to the first element of this array and Total [4] refers to the last element. The array total is stored in memory in five consecutive locations as follows:

Data can be stored in the array by specifying the array name and index. For example, to store 25 in the second element of the array, we have to write Total [1] = 25; Similarly, the contents of an array can be read by specifying the array name and its index. For example, to copy the third array element to a variable called temp, we have to write Temp = Total [2];

Multi-dimensional Array
It is a structure with a series of elements each having another sub-series of elements. Each element is accessible by identifier name and two or more indices. It is used when every element of the structure is to be given a distinct identity by two or more indices for easy operation. The dimension of an array equals the number of indices that are needed to distinctly identify an array-element. Indices start from 0 and are +ve integers

Example

Matrix or a pixel in an image frame. In C programming language, we can also declare arrays with multiple dimensions. Onedimensional arrays are usually called vectors and two-dimensional arrays are called
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matrices. A two-dimensional array is declared by specifying the data type of the array, array name, and the size of each dimension. In the following example, a twodimensional array named P having three rows and four columns is created. Altogether the array has 12 elements. The first element of the array is P [0][0] and the last element is P[2][3]. The structure of this array is shown below: Unsigned char P[i][j] ;

Here i=2 three rows and j=3 four columns

Strings
Strings are character arrays with a null terminator. Strings can either be declared by enclosing the string in double quotes or by specifying each character of the array within single quotes and can then be terminated with a null character. In the following example, the two string declarations are identical and both occupy five locations in memory: Example Unsigned char Mystring [ ] = "COMP"; And Unsigned char Mystring [ ] = {'C', 'O', 'M', 'P', '\0'};

List
Each element has a pointer to its next element. Only the first element is identifiable and it is done by list-top pointer (Header). No other 'element is identifiable and hence is not accessible directly. By going through the first element, and then consecutively through all the succeeding elements, an element can be read, or read and deleted, or can be added to a neighboring element or replaced by another element. Example A series of tasks which are active, each task has pointer for the next task.

Tree
It has two or more branches each having a daughter element. Each daughter element has two or more daughter elements. Only the root element is identifiable and it is done by the treetop pointer (Header).
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No other element is identifiable and hence is not accessible directly. By traversing the root element, then proceeding continuously through all the succeeding daughters, a tree element can be read or read and deleted, or can be added to another daughter or replaced by another element. A tree has data elements arranged as branches The last daughter called node has no further daughters A binary tree is a tree with a maximum of two daughters (branches) in each element. Example An example is a directory. It has number of file folders. Each file folder has a number of file folders and so on. In the end is a file.

Table
A two-dimensional array (matrix) and is an important data set that is allocated Three pointers in table table base, column index and destination index pointers can retrieve any element of the table There is always a base pointer for a table. Base pointer points to its first element at the first column first row. There are two indices, one for a column and other for a row.

Look up Table An important data set A lookup table can be said a two-dimensional array (matrix) with first column can be said to hold the pointers, one pointer in each row and second column the values pointed by first column in each row. First and second columns are at different non adjacent addresses.

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Each row has pointer in first column and from pointed memory block the addressed data is traced

Hash Table A data set that is a collection of pairs of a key and a corresponding value. A hash table has a key or name in one column. The corresponding value or object is at the second column. The keys may be at non-consecutive memory addresses. When look-up tables store like a hash. If the first column of a table is used as a key (pointer to the value) and the second column as a value, we call that table as look-up table.

Use of Modifiers
The actions of modifiers are as follows: Modifier 'auto' or No modifier, if outside a function block, means that there is ROM allocation for the variable by the locator if it is initialized in the program. RAM is located by the locator, if it is not initialized in the program. Modifier 'auto' or No modifier, if inside a function block, means that there is ROM allocation for the variable by the locator if it is initialized in the program. There is no RAM allocation by the locator. Modifier unsigned is modifier for a short or int or long data type. It is a directive to permit only the positive values of 16, 32 or 64 bits respectively. Modifier static declaration is inside a function. Modifier register declaration is inside a function block Modifiers interrupt. It directs the compiler to save all processor registers on entry to the function codes and restore them on return from that function. Modifier extern' It directs the compiler to look for the data type declaration or the function in a module other than the one currently in use. Use of Conditions Loops and Infinite Loops: Conditional statements are used many times If a defined condition (s) is fulfilled, the statements within the curly braces after the condition are executed. Otherwise the program proceeds to the next statement or to the next set of statements. Sometimes a set of statements is repeated in a loop. Generally, in case of array, the index changes and the same set is repeated for another element of the array. Infinite loops are never desired in usual programming. The program will never end and never exit or proceed further to the codes after the loop Infinite loop is a feature in embedded system Programming

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USE OF FUNCTION CALLS

Functions are useful in such a way that they are used to execute repeated codes as a separate program. The function contains various parts like declaration, calling and definition of the function. A special function for starting the program execution is 'void main (void). Given below are the steps to be followed when using a function in the program. Declaring a function Just as each variable has to have a declaration each function must be declared. Consider an example. Declare a function as follows: Int Mult(int a, int b, int c) Here int specifies the returned data type. The Mult is the function name. There are arguments inside the brackets. Defining the statements in the function Just as each variable has to be given the contents or value each function statements consider the statement of the function 'Mult. These are within a pair of curly braces as follows: Int a :: Mult (int a, int b)
{...}

The last statement in a function is for the return and may also before returning an element. Call to a function Consider an example: if (delay_F= =true && SSTDelayEnable== true) TSR_Delay ( ); There is several times call and on fulfilling a condition. The call can occur can be repeatedly made. On each call, the values of the arguments given within the pair of bracket pass for use in the function statements. Passing the Values (element) The values are copied into the arguments of the functions. When the function is executed in this way, it does not change a variable's value at the called program. A function can only use the copied values in its own variables through the arguments. Consider statement, Mult (int a, int b, int c) { } Multiple function calls in cyclic order in the main One of the most common methods is for the multiple function calls to be made in a cyclic order infinite loop of the main. The following diagram illustrates:

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USE OF POINTERS Pointers are an important part of the C language and they hold the memory addresses of variables. Pointers are declared same as any other variables but with the character (*) before the variable name. In general, pointers can be created to point to (or hold the addresses of) character variables, integer variables, long variables, floating point variables, or they can point to functions. In the following example, an unsigned character pointer named pnt is declared: unsigned char *pnt; When a new pointer is created, its content is initially unspecified and it does not hold the address of any variable. We can assign the address of a variable to a pointer using the (&) character: pnt = &Count; *pnt = 10; Which is same as Count = 10;
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In C language, we can perform pointer arithmetic that may involve the following: Comparing two pointers Adding or subtracting a pointer and an integer value Subtracting two pointers Assigning one pointer to another one Comparing a pointer to null

EMBEDDED PROGRAMMING IN C++ Objected Oriented Programming An objected o oriented languages is used when there is a need for reusability of the defined object or set of objects that are common within a program between many applications. When a large program is to be made an object-oriented language offers many advantages. Data encapsulation, design of reusable software components and inheritance are the advantages derived from the OOPs. An object-oriented language provides or defining the objects and methods that manipulate the objects modifying their definitions. It provides for the data and methods for encapsulation. An object can be characterized by the following: An identity, a reference to a memory block that holds its state and behavior. A state (its data property fields and attributes). A behavior (method or methods that manipulate the state of the object). In a procedure-based language, like FORTRAN, COBOL, Pascal and C, large programs are split into simpler functional blocks and statements. In an object- oriented language like Smalltalk, C++ or Java, logical groups (also known as classes) are first made. Each group defines the data and the methods of using the data. A set of these groups then gives an application program. Each group has internal user-level fields for the data and the methods of processing that data at these fields. Each group can then create many objects by copying the group and making it functional. Each object is functional. Each object can interact with other objects to process the user's data.

The language provides for formation of classes by the definition of a group of objects
having similar attributes and common behavior.

A class creates the objects. An object is an instance of a class.

Embedded Programming in C++ Embedded system codes can optimized when using an OOP language by the following:
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Declare private as many classes as possible. It helps in optimizing the generated codes. Use char, int and boolean (scalar data types) in place of the objects (reference data types) as arguments and use local variables as much as feasible. Recover memory already used once by changing the reference to an object A special compiler for an embedded system can facilitate the disabling of specific features provided in C++. Embedded C++ is a version of C++ that provides for a selective disabling of the above features so that there is a less runtime overhead and less runtime library. The solutions for the library functions in an embedded C++ compiler are also reentrant. So using embedded C++ compilers or the special Programming advantages of C++ A class binds all the member functions together for creating objects. The objects will have memory Disadvantages of C++ Program codes become lengthy, particularly when certain features of the standard C ++ are used. Examples of these features are as follows: Template. Multiple inheritances (Deriving a class from many parents). Exceptional handling. Virtual base classes. Classes for IO Streams. [Two library functions are cin (for character(s) in) and cout character (s) out). The I/O 'stream class library provides for the input and output streams of characters (bytes).It supports pipes, sockets and file management features.

Java programming
Starts from coding for the classes. A class has members. A field is like a variable or struc in C. A method defines the operations on the fields, similar to function in C. Class instance fields and instance methods are the members, whose new instances are also created as when the objects are created from the class. Class is a named set of codes that has a number of members data fields (variables), methods (functions), etc. so that object can be created from it.

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The operations are done on the objects by passing the messages to the objects in objectoriented programming. Each class is a logical group with an identity, a state and a behavior specification. Java Class inherits members when a Java class is extended from a parent class called super class. The inherited instance fields and methods can be overridden by redefining them in extended class. Methods can be overloaded by redefining them for different number of arguments. Interface has only the methods and corresponding data fields and the methods do not have implementation in the Interface. A Java class which is interfaced to an Interface implements the abstract methods specified at the Interface

Inheritance in Java programming

Interface in Java programming

Primitive data types in Java programming

Java Class uses: Byte (8-bit), shot (16-bit), int (32-bit, long (64-bit, float, double, char (16-bit). Reference data types Java Class uses reference data types. A reference can be Class type in which there are groups of fields and methods to operate on the fields. A reference can be Array type in which there are groups of objects as array elements. Exception classes Many inbuilt Exception classes The occurrences of exceptional conditions are handled when exception is thrown. It is also possible to define exception conditions in a program so that exceptions are thrown from try block codes and caught by catch exception method.

Java Features
Java is completely an OOP language Application program consists of classes and interfaces There is a huge class library on the network that makes program development quick Java has extensibility Java programs posses the ability to run under restricted permissions Multiple threads in Java Program Java has in-built support for creating multiple threads It obviates the need for an operating system (OS) based scheduler for handling the tasks Java generates the byte codes These are executed on an installed JVM (Java Virtual Machine) on a machine. Virtual machine takes the Java byte codes in the input and runs on the given platform (processor, system and OS). [Virtual machine (VM) in embedded systems is stored at the ROM.] Therefore, Java codes can host on diverse platforms.
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Java Platform Independence Feature Platform independence in hosting the compiled codes permits Java for network applications. Platform independence gives portability with respect to the processor and the OS used. Java is considered as write once and run anywhere. Java is the language for most Web applications and allows machines of different types to communicate on the Web. Java is easier to learn by a C++ programmer. Java does not permit pointer manipulation instructions. So it is robust in the sense that memory leaks and memory related errors do not occur. A memory leak occurs, for example, when attempting to write to the end of a bounded array. Java does not permit dual way of object manipulation by value and reference. There are no struc, enum, typedef and union. Java does not permit multiple inheritances. Java does not permit operator overloading except for + sign used for string concatenation.

Some disadvantages
Java byte codes that are generated need a larger memory when a method has more than 3 or 4 local variables. An embedded Java system may need a minimum of 512 kB ROM and 512 Kb RAM because of the need to first install JVM and then run the application.

Ways to overcome the disadvantages

Use of J2ME (Java 2 Micro Edition) or Java Card or Embedded Java helps in reducing the code size to 8 kB for the usual applications like smart card.

OPTIMIZATION OF MEMORY NEEDS When codes are made compact and fitted in small memory areas without affecting the code performance, it is called memory optimization. It also reduces the total number of CPU cycles, and thus the total energy requirements. The following are used for optimizing the use of memory in a system. Use declaration as unsigned byte If there is a variable, which always has a value between 0 and 255. When using data structures, limit the maximum size of queues, lists and stacks size to 256. Byte arithmetic takes less time than integer arithmetic. Follow a rule that uses unsigned bytes for a short and a short for an integer It is used to optimize use of the RAM and ROM available in the system. Avoid if possible the use of 'long' integers and 'double' precision floating point values.

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Avoid use of library functions if a simpler coding is possible Library functions are the general functions. Uses of general function need more memory in several cases. Follow a rule that avoids use of library functions in case a generalized function is expected to take more memory when its coding is simple. When the designer knows fully the instruction set of the target processor, assembly codes must be used. This also allows the efficient use of memory. The device driver programs in assembly especially provide efficiency due to the need to use the bit set reset instructions for the control and status registers. Assembly coding also helps in coding for atomic operations. A modifier register can be used in the C program for-fast access to a frequently used variable. Only the few assembly codes for using the device IO port address, control and status registers are needed. The best use is made of available features for the given applications Calling a function calls context saving on a memory stack and on return the context is retrieved This involves time and can increase the worst-case interrupt latency. There is a modifier inline. When the inline modifier is used the compiler inserts actual codes at all the places where these operators. This reduces the time and stack overhead in the function call and return. But this is at the cost more ROM being needed for the codes. If used it increases the size of the program but gives faster speed. Using the modifier directs the compiler to put the codes for the functions instead f calling the functions. As a rule use in line modifier for all the frequently use small sets of codes in the function or the operator overloading functions if the ROM is available in the system A vacant ROM memory is unused resource why not use it for reducing the worst-case interrupt latency by eliminating the time taken frequent and retrieval of a program context? As long as shared data problem does arise, the use of global variables can be optimized. These are not used as the arguments for passing the values. A good function is one that has arguments to be passed. The passed values are saved on the stacks in case of interrupt service calls and other function calls. Besides obviating the need for repeated declarations, the use of global variables will thus reduce the worst case interrupt-latency and the time and stack overheads in the function call and return. But this is at the cost of the codes for eliminating shared data problem. When a variable is declared static, the processor accesses with less instruction than from the stack. As a rule, use global variables if shared data problem are tackled and use static variables in case it needs saving frequently on the stack.

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Unit 6 & 7 Development process of an embedded system and Tools

Consists of cycles of editing-testing debugging. Processor and hardware part once chosen remains fixed, the application software codes have to be perfected by a number of runs and tests. While the cost of the processor is quite small, the cost of developing a final targeted system is quite high Needs a larger time frame than the hardware circuit design

Host and Target Machines During development process, a host system is used Then locating and burning the codes in the target board.
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Target board hardware and software later copied to get the final embedded system Final system function exactly as the one tested and debugged and finalized during the development process

Host system at PC or workstation or laptop

Host is a high performance processor with caches, large RAM memory It should have o ROMBIOS (read only memory basic input-output system) o very large memory on disk o keyboard o display monitor o mouse o network connection o Program development kit for a high level language program or IDE o Host processor compiler and cross compiler o Cross assembler. o Programmer Software

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Linking and Locating Software

Linker Links the compiled codes of application software, object codes from library and OS kernel functions. Linking necessitates because of the number of codes to be linked for the final binary file. For example, standard codes for to program a delay task, must link with the assembled codes. The delay code sequential from a beginning address. The assembly software codes also sequential from another beginning address. Both the codes have to at the distinct addresses as well as at the available addresses in the system. Linker links these After linking, re-allocation of the sequences of placing the codes before actually placement of the codes in the memory Linked file in binary for run on a computer commonly known as executable file or simply '.exe' file. Loader Program loaded in a computer RAM. Loader program performs the task of reallocating the codes after finding the physical memory addresses available at a given instant Loader a part of the operating system and places codes into the memory after reading the '.exe' file. Step necessary because the available memory addresses may not start from 0x0000, and binary codes have to be loaded at the different addresses during the run. Loader finds the appropriate start address. In a computer, after the loader loads into a section of RAM and after loading the program ready to run Locator When the code embeds into ROM or flash, a system design process is locating these codes as a ROM image.
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Codes are permanently placed at the actually available addresses in the ROM. Embedded systems no separate program to keep track of the available addresses at different times during the running, as in a computer.

Various software tools and chain of actions of linker at host and locator in an embedded system

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Target System and final systems

o Target system differs from a final system, target system interfaces with the computer as well works as a standalone system o In target system might be repeated downloading of the codes during the development phase. o Target system copy made that later on functions as embedded system o Designer later on simply copies it into final system or product. o Final system may employ ROM in place of flash, EEPROM or EPROM in embedded system.

Software Development Tools

Software development tools are computer programs, and they usually run on personal computers, helping the programmer (or system developer) to create and/or modify or test application programs. Some common software development tools are

Text editors Assemblers/compilers Simulators High-level language simulators Integrated development environments (IDEs)

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Text Editors
A text editor is a program that allows us to create or edit programs and text files. Windows operating system has a text editor program called Notepad. Using Notepad, we can create a new program file, modify an existing file, or display or print the contents of a file. It is important to realize that programs used for word processing, such as the Microsoft Word, cannot be used as a text editor. This is because word processing programs are not true text editors, because they embed word formatting characters, such as bold, italic, underline, and so on, inside the text. Most assemblers and compilers come with built-in text editors. Using these editors, we can create a program and then assemble or compile it without having to exit from the editor. These editors also provide additional features, such as automatic key word highlighting, syntax checking, parenthesis matching, comment-line identification, and so on. Different parts of a program can be shown in different colors to make the program more readable. For example, comments can be shown in one color, key words in another color, etc. Such features help to eliminate syntax errors during the programming stage, thus speeding up the overall development process.

Assemblers and Compilers

Assemblers generate executable code from assembly language programs, and that generated code can then be loaded into the flash program memory of a microcontroller. Similarly, compilers generate executable code from high-level language programs. Some of the commonly used compilers for the PIC18 microcontrollers are BASIC, C, and Pascal. Assembly language is used in applications where the processing speed is very critical and the microcontroller is required to respond to external and internal events in the shortest possible time. The main disadvantage of assembly language is that it is difficult to develop complex programs using it. In addition, assembly language programs cannot be maintained easily. High-level languages, on the other hand, are easier to learn, and complex programs can be developed and tested in a much shorter time. High-level programs are also maintained more easily than assembly language programs.

Simulators
A simulator is a computer program that runs on a PC without any microcontroller hardware, and it simulates the behavior of the target microcontroller by interpreting the user

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program instructions using the target microcontroller instruction set. Simulators can display the contents of registers, memory, and the status of inputoutput ports of the target microcontroller as the user program is interpreted. The user can set breakpoints to stop the execution of the program at desired locations and then examine the contents of various registers at the breakpoint. In addition, the user program can be executed in a single-step mode so that the memory and registers can be examined as the program executes one instruction at a time each time a key is pressed. Some assembler programs also contain built-in simulators to enable programmers to develop and simulate their programs before loading onto a physical microcontroller chip. Some of the popular PIC18 microcontroller tools with built-in simulator are MPLAB IDE High-Level Language Simulators High-level language simulators are also known as source-level debuggers, and like simulators, they are programs that run on a PC and locate errors in high-level programs. We can set breakpoints in high-level statements, execute the program up to the breakpoint, and then display the values of program variables, the contents of registers, and memory locations at that breakpoint. A source-level debugger can also invoke hardware-based debugging activity using a hardware debugger device. For example, the user program on the target microcontroller can be stopped, and the values of various variables and registers can be examined.

Integrated Development Environments

IDEs are powerful PC-based programs that have everything; hence, it is possible to edit, assemble, compile, link, simulate, source-level debug, and Download the generated executable code to the physical microcontroller chip (using a programmer device). These programs are in the form of graphical user interface (GUI), where the user can select various options from the program without having to exit the program. IDEs can be extremely
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useful during the development phases of microcontroller-based systems. Most PIC18 high-level language compilers are in the form of an IDE, thus enabling the programmer to do most tasks within a single software development tool. For developing or testing an embedded system application, a particular development cycle is followed which consists of several stages. An Integrated Development Environment (IDE) allows for implementation of all such steps of a development cycle. Typically, a development cycle has following steps: a. The code is written/edited in an Editor program. b. The Compiler/Assembler/Linker programs generate relevant support files like .hex, .obj etc. c. The code is loaded into Simulator/Debugger program. d. The code is analyzed by Simulation or Debugging. If an error occurs, the code is re-edited and the whole cycle is repeated.

Some typical software tool Features:

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Comprehension, Navigation and browsing, Editing, Debugging,

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Configuring (disabling and enabling specific C++ features Compiling Searches and lists the definitions, symbols, hierarchy of the classes, and class inheritance trees Symbols include the class members Searches and lists the dependencies of symbols and defined symbols, variables and functions

Monitors, enables and disables the implementation virtual functions. Finds the full effect of any code change on the source code. Searches and lists the dependencies and hierarchy of included header files. Navigates to and from o Between the implementation and symbol declaration. o Between the overridden and overriding methods.

Browses through o Information regarding instantiation (object creation) of a class. o encapsulation of variables among the members o Public, private and protected visibility of the members. o object component relationships

Automatically removes error and unused tasks. Provides easy and automated search and replacement

Some IDEs and Compilers for different Microcontroller Families

1. PIC Microcontroller from Microchip Microchip's IDE - MPLAB IDE Microchip's C18 C Compiler 2. 8051 Microcontroller Kiel assembler Proview ASM51 3. Atmel and Atmega Microcontroller AVR Studio

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Hardware Development Tools

Numerous hardware development tools are available for the PIC18 microcontrollers. Some of these products are manufactured by Microchip Inc. and some by third-party companies. The popular hardware development tools are Development boards Device programmers ICDs ICE Breadboards

Development Boards Development boards are invaluable microcontroller development tools. Simple development boards contain just a microcontroller and the necessary clock circuitry. Some sophisticated development boards contain LEDs, LCD, push buttons, serial ports, USB port, power supply circuit, device programming hardware, and so on. Programmer/Burner After the program has been written and translated into executable code, the resulting HEX file is loaded onto the target microcontroller's program memory with the help of a device programmer. The type of device programmer depends on the type of microcontroller to be programmed. A programmer/burner is a hardware device accompanied with software which is used to transfer the machine language code to the microcontroller/EEPROM from the PC. The compiler/assembler converts the code written in languages like assembly, C, java etc to machine language code (which is understandable by the machines/microcontrollers) and stores it in a hex file. A programmer acts as an interface between the PC and the target controller. The API/software of the programmer reads data from the hex file stored on the PC and feeds it into the controllers memory. The target controller on which the program needs to be burned is placed on the programmer using a ZIP socket. The software transfers the data from the PC to the hardware using serial, parallel or USB port. Parallel Programmer uses the parallel port of the PC. They are low cost programmer but not widely used.
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Serial Programmers uses the serial port to interact with PC via RS232 protocols. They are more popular among hobbyist working on PC. However both the serial and parallel programmers will become obsolete in near future. The major reason being unavailability of parallel and serial ports in the PCs & Laptops in the coming years. USB Programmer uses the USB interface to transfer the data from PC. The main advantage of the USB burner is that they are powered from the PC itself and there is no need of any additional supply. The USB programmers have already become popular and will soon replace the serial and parallel programmer. The programmer generally contains a microcontroller which is preprogrammed to take data from the PC and program the target controller. The programmer burns the target controller using any of the protocols like SPI, parallel interfacing, I2C/TWI or CAN. The speed of burning depends on the way of programmer is interfaced with PC and the protocols used to burn the target controller. The conventional method to burn a controller is to take it out from the circuit, place it on burner and then dump the hex file into the controller using the API. In order to remove this problem of removing the controller from the circuit every time it needs to be programmed, The controllers have now been upgraded with In System Programmer (ISP) feature. This allows burning/programming a controller without removing the controller from the circuit it is used in. The latest controllers are coming with the feature like bootloader memory which allows self burning capabilities, i.e. such controllers do not need any additional
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programmer hardware. They need only an API to transfer the program to the target controller. This API can also be incorporated in the compiler and hence the compiler can directly burn the target controllers.

In-Circuit Debuggers
An ICD is hardware that is connected between a PC and the target microcontroller test system and is used to debug real-time applications quickly and easily. With in-circuit debugging, A monitor program runs in the microcontroller in the test circuit. The programmer can set breakpoints on the Controller, run code, single-step the program, examine variables and registers on the real device, and change their values if required. An ICD uses some memory and I/O pins of the target PIC microcontroller during the debugging operations. With some ICDs, only the assembly language programs can be debugged. Some more powerful debuggers enable highlevel language programs to be debugged. In-Circuit Emulators The ICE is one of the oldest and the most powerful devices for debugging a microcontroller system. It is also the only tool that substitutes its own internal processor for the one in the target system. Like all ICDs, the emulator's primary function is target access the ability to examine and change the contents of registers, memory, and I/O. As the ICE replaces the CPU, it generally does not require working a CPU on the target system to provide this capability. This makes the ICE by far the best tool for troubleshooting new or defective systems. Breadboards Building an electronic circuit requires connecting the components as shown in the relevant circuit diagram, usually by soldering the components together on a strip board or a PCB. This PCB approach is appropriate for circuits that have been tested and are functioning as desired and also when the circuit is being made permanent. However, making a PCB design for just a few applications for instance, while still developing the circuit is not economical. Instead, while the circuit is still under development, the components are usually assembled on a solderless breadboard. The nice thing about the breadboard design is that the circuit can be modified very easily and quickly and different ideas can be tested without having to solder any components. The components can easily be removed, and the breadboard can be used for other projects after the circuit has been tested and works satisfactorily.

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Boot Loader
A Bootloader is the first program which executes (before the main program) whenever a system is initialized. In Personal computer it is used to boot he OS of the system. In case of microcontrollers, a bootloader enriches the capabilities of the microcontroller and makes them self programmable device. While working with microcontroller a common problem faced is to program the controller? Different controllers follow different protocols to program their ROM and hence every controller has a different programmer, which is difficult to be made. A universal programmer on the other hand is quite costly. With the upgrading era of technology, todays microcontrollers are not only growing powerful but also incorporate technically superior functionality which makes them more flexible and quite easy to use. The bootloader is one of them. A bootloader is a small section in the ROM of the controller which executes first when it is initialized. Generally the bootloader are written to empower a controller with self burning capabilities. The bootloader program can access any of inbuilt peripherals like USB, USART, CAN, SPI, etc. to exchange the data and this capability is used to write the flash memory. In automotive industries the controllers are encapsulated in a metal case and leaves accessibility to few pins only... In such cases the controller is programmed with the bootloader program using CAN interface at the time of manufacturing and then it is pasted in the circuits, which provides an ease to update the code with time. The bootloader can be inserted into a controller by using an external or any conventional burner and then depending on the type of bootloader the controller starts responding to the interface. So whenever the controller is reinitialized the program counter jumps to the bootloader section and then it waits there for the instruction, which is fed from external device. In case there is no bootloader the program counter will go on 0000H (starting position of the flash memory) and start executing the instructions which are written in the memory of the device.

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If the program counter enters the bootloader section then after executing the bootloader, there must be an instruction in the bootloader which will force the program counter to go to 0000H. Mostly the bootloader resides in the bottom most area of the ROM but there are some cases where the boot loader can be configured in the top (like in PIC18F).The starting and ending address of the bootloader in the ROM depends on the product. Hex File Format The Intel hex (ihex) generally known as hex file, is a format used to store machine language code in hexadecimal form. It is widely used format to store programs to be transferred to microcontrollers, ROM and EEPROM. The compilers convert the programs written in assembly, C etc into corresponding hex files, which are dumped into the controllers using burners/programmers. This article explores the details of the hex file format. The microcontroller understands machine language consisting of zeroes and ones. Its difficult rather practically impossible for humans to write codes in zeros and ones. Hence we use some high level languages like C, C++, Java, etc. And later a compiler is used to convert these codes into machine language which are stored in a hex file format. A hex file is a text file with the extension .hex

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Issues in Hardware and Software design and Co design

In the traditional embedded system development approach, the hardware software partitioning is done at an early stage and engineers from the software group take care of the software architecture development and implementation, whereas engineers from the hardware group are responsible for building the hardware required for the product .there is less interaction between the two teams and the development happens either serially or in parallel. Once the hardware and software are ready, the integration is performed. the increasing competition in the commercial market and the need for reduced timetomarket the product calls for a level approach for embedded system design in which the hardware and software are co-developed instead of independly developing both. During the co-design process, the product requirements captured from the customer are converted into system level needs or processing requirements at this point of time it is not segregated as either hardware requirements or software requirement, instead it is specified as functional requirement. The system level processing requirements are then transferred into
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functions which can be simulated design. The partition of system level processing requirements into hardware and software takes place during the architecture design phase. each system level processing requirements is mapped as either hardware and/or software requirement. The partitioning is performed based on the hardware software trades-offs. We will discuss the various hardware software trade-offs in hardware software co-design in a separate topic. The architectural design results in the detailed behavioral description of the hardware requirement and the definition of the software required for the hardware. The preprocessing requirement behavior is usually captured using computational models and ultimately the models representing the software processing requirements are translated into firmware implementation using programming languages.

Fundamental issue in hardware software co-design

The hardware software co-design is a problem statement and when we try to solve tis problem statement in real life we may come across multiple issues in the design. The following section illustrates some of the fundamental issues in the hardware software co-design. Selecting the model: In hardware software co-design, model are used for capturing and describing the system characteristics model is a formal system consisting of objects and composition rules .It is hard t make a decision on which model should be followed in a particular system design .Most often designers switch between a variety of models from the requirements specification to the implementation aspect of the system design. The reason being, the objective varies with each phase: for ex at the specification stage, only the functionality of the system is in focus and not the implementation information. When the design moves to the implementation aspect, the information about the system composition is revealed and the designer has t switch t a model capable of capturing the systems structure. Selecting the Architecture: A model only captures the system characteristics and does not provide information on how the system can be manufactured?.The architecture specifies how a system is going to implement in terms of the number and types of different components and the interconnecting among them. controller architecture .Data path Architecture, complex instruction set computing(CISC),reduced instruction set computing(RISC),very long instruction word computing(VLIW),single instruction multiple data(SIMD),multiple instruction multiple data(MIMD),etc.. are the commonly used architectures in system design .some of them fall into application specific architectures class(like controller architecture).while other fall into either general purpose
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architecture

class(CISC,RISC,etc..)

or

parallel

processing

class

like(VLIW,SIMD,MIMD,etc.). The controller architecture implements the finite state machine model using a state register and two combinational circuits .the stage register holds the present state and the combinational circuits implement the logic for next state and output. The data path architecture is best suited for implementing the data flow graph model where the output is generated as a result of a set of predefined computations on the input data. A data path represents a channel between the input and output and in data path architecture the data path may contain registers, counters, register files, memories and ports along with high speed arithmetic units. Ports connect the data path to multiple buses. Most of the time the arithmetic units are connected in parallel with pipeline support for bringing high performance. The finite state machine Datapath (FSMD) architecture combines the controller architecture with data path architecture .it implements a controller with data path ..The controller generates the control input whereas the data path process the data. The data path contains two types I/O ports, out of which one acts as the control port for receiving /sending the control signals from /to the controller unit and the Second I/O port interfaces the data path with external world for data input and data output .normally the data path is implemented in a chip and the I/O pins of the chip acts as the data input output ports for the chip resident data path. The complex instruction set computing architecture uses an instruction set representing complex operations. It is responsible for a CISC instruction set to perform a large complex operation (e.g. reading a register value and comparing it with a given value and then transfer the program execution to a new address location (the CNJE instruction for 8051 ISA)) with a single instruction .The use of a access and program memory size requirement. However it requires additional silicon for implementing microcode decoder for decoding the CISC instructions. the datapath for the CISC processor is complexion the other hand ,reduced instruction set computing (RISC) architecture uses instruction set representing simple operations and it require the execution of multiple RISC instructions to perform an complex operation. The data path of RISC architecture contains a large

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register file for storing the operands and output .RISC instructions set is designed to operate on register .RISC architecture supports extensive pipelining. The very long instructions word (VLIW) architecture implements multiple functional units(ALUs,multipliers,etc)in the datapath. The VLIW instructions package one standards instruction per functional unit of the data path. Parallel processing architecture implements multiple concurrent processing elements (PEs) and each processing elements may associate a data path containing register and local memory. Single instruction multiple data(SIMD) and Multiple Instruction

Data(MIMD) architectures are examples for parallel processing architecture .In SIMD architecture ,a single instructions is executed in parallel with the help of the processing elements .The scheduling of the instructions execution and controlling of each PE is performed through a single controller .The SIMD architecture forms the basis of reconfigurable processor. on the other hand the processing elements f the MIMD architecture execute different instructions at given point of time. The MIMD architecture forms the basis of multiprocessor systems. The PEs in a multiprocessor system communicates through mechanism like shared memory and message passing. Selecting the language: A programming language captures a computational model and maps it into architecture .There is no hard and fast rule to specify this languages should be used for capturing this model. A model can be captured using multiple programming languages like C,C++,C#,Java,etc for software implementations and languages like VHDK,System C,Veilog,etc for hardware implemention.on other hand, a single languages can be used for capturing a variety of models, Certain languages are good in capturing certain computational models. For example C++ is a good candidate for capturing an object oriented model..The only pre-requisite in selecting a programming language for capturing a model is that the language should capture the model easily. Partitioning system requirement into hardware and software so far we discussed about the models for capturing the system requirements and the architecture for implementing the system. from an implementation perspective ,it may be possible to implement the system requirement in either hardware or software .it is a tough decision making task to figure out which on to opt. various hardware software trade-offs are used for making decision on the hardware software partitioning.
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Hardware implementation advantages

(i)Reduced memory for the program. (ii) Reduced number of chips but at an increased cost. (iii) Simple coding for the device drivers. (iv) Internally embedded codes, which are more secure than at the external ROM (v) Energy dissipation can be controlled by controlling the clock rate and voltage

Software implementation advantages

(i)Easier to change when new hardware versions become available. (ii) Programmability for complex operations. (iii) Faster development time. (iv) Modularity and portability. (v) Use of standard software engineering, modeling and RTOS tools. (vi) Faster speed of operation of complex functions with high-speed microprocessors. (vii) Less cost for simple systems

Testing on Host machine

Goals of the typical testing process are: a) Find the bugs early in the development process. b) Exercise all code including exceptions. c) Develop reusable, edit, test debug process. d) Store results. All of this hard to do on target system therefore use host PC system as much as possible.

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Hardware dependent code of two sides of figure is compiled from the same source. Hardware and hardware-dependent code on the right has been replaced with test scaffold software on the right. scaffold software provides all functionalities and calls to hardware as in hardware independent code. Scaffold software takes its instruction from keyboard or from a file and produces output onto the display. This technique creates a clean division between the code that directly interfaces with the hardware and rest of the code. Then, hardware is disconnected to allow simulation of hardware. This technique hides the ugliness of bit manipulations, assertion logic etc..

Laboratory Tools
Volt-Ohm meter Oscilloscope Logic Analyzer Bit Rate meter System Monitor Codes Logic Probe Digital IC tester Soldering gun or Machine Frequency generator

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1. Volt-Ohm meter
An ohm meter and volt meter can be simply that, or it can be part of another, more common, electrical testing device called a multi-meter. An ohm meter uses a small electrical current to check the continuity of a circuit, also on different settings it can also tell how much resistance is in a circuit. Use an ohm meter to check continuity in motors, cables, or fuses. If a circuit has a break in continuity, it is called "open" .Voltmeters and ohm-meter can be used to test the hardware. It has two leads. One end each is connected to the meter and other points between which voltage or resistance is to be measured. The knob position is set for volt to check the power supply voltage at source, voltage levels at chip power input pins and port pins initial and final voltage levels after the software runs. The knob position is set for ohm to check broken connections and improper ground connections.

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2. Oscilloscope
An oscilloscope is a test instrument which allows you to look at the 'shape' of electrical signals by displaying a graph of voltage against time on its screen. It is like a voltmeter with the valuable extra function of showing how the voltage varies with time. A graticule with a 1cm grid enables you to take measurements of voltage and time from the screen. The graph, usually called the trace, is drawn by a beam of electrons striking the phosphor coating of the screen making it emit light, usually green or blue. This is similar to the way a television picture is produced. Oscilloscopes contain a vacuum tube with a cathode (negative electrode) at one end to emit electrons and an anode (positive electrode) to accelerate them so they move rapidly down the tube to the screen. This arrangement is called an electron gun. The tube also contains electrodes to deflect the electron beam up/down and left/right. The electrons are called cathode rays because they are emitted by the cathode and this gives the oscilloscope its full name of cathode ray oscilloscope or CRO. A dual trace oscilloscope can display two traces on the screen, allowing you to easily compare the input and output of an amplifier for example. It is well worth paying the modest extra cost to have this facility.

Uses 1. It can be used as a noise detection tool and as a voltmeter.

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2. It is used in detection of sudden change in transition between o and 1 state during a clock period. This debugs a bus malfunction.

3. Logic Analyzers
A logic analyzer is a power too; that captures signal and displays these on its screen to debug real time triggering conditions. It helps in sequentially finding the signals as the instructions execute with respect to a reference. Logic analyzers in timing mode can tell how long things take to occur, shows signal patterns and finds out whether certain events occur. Logic analyzers in state mode can capture traces, listings of instructions that the microprocessor performed when the clock event occurs in a system. Sampling and Digitizing a Signal using Logic analyzer Signal acquisition: Sampling input signal Digitizing it to convert to digital data Assembling it into a waveform record Logic analyzer converts incoming data into ones and zeros Uses comparator with user-selectable threshold Samples data at regular time intervals Shortcomings of logic analyzers: 1. Cannot stop microprocessor at a breakpoint to single step the logic, view the registers, and change the memory contents and so on. 2. Memory contents can be known only if the microprocessor happens to read or write them. Contents of uP registers are invisible. 3. If program crashes, contents of memory, registers or anything else cannot be examined. 4. LA sees only what was fetched. It cannot see inside the uP to see which instructions it reads out of the cache. Advantages of Logic analyzers over emulators: 1. LAs have better trace filters and more sophisticated triggering mechanisms. 2. LAs run in timing mode. 3. LAs work with any processor.
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4. With LAs as many as few connections can be made. With emulator all the signals which can be a major project must be connected.

Advantages of Logic analyzers over Oscilloscope: Oscilloscope samples incoming signal at regular time intervals. Stores sample amplitude into 8-bit digital value. Preserves amplitude information Signal is analog in nature LA monitors multiple channels simultaneously Signal is digital in nature Provides timing relationship information Both are powerful analysis, troubleshooting tools

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DESIGN EXAMPLES & CASE STUDY MATERIAL

I.

Design an Embedded System with the following available Components

Microcontroller, Crystal, Resistors, Capacitors, Switches, LEDs, Buzzer, LCD, Sensors, keypad Design Specification Number of people entered into and coming out of an exhibition hall are to be counted For every entry and exit there should be a different indication Number of people inside the hall at a given point of time is to be displayed It should have option to set maximum limit There should be alarm if the number of people inside the hall crosses a maximum limit There should be provision to reset the count The design should contain detailed block diagram of the system with the microcontroller and the minimum requirement to run a particular Microcontroller, if any Power supply requires design it, with the available source is only AC 230. POWER SUPPLY

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Explanation:

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I. Design an embedded System i) Memory and Graphical LCD with SPI interface ii) Real Time Clock (RTC) with I2C interface iii) Temperature Sensor with I2C interface iv) CAN Bus between two Controllers v) USB protocol vi) Keypad interface Design a system, Explain how exactly these devices can be interfaced with Microcontroller Microcontroller-A---- Temperature Sensor and RTC should be interfaced Microcontroller-B-----Graphical LCD, Keypad and Memory Should be interfaced Microcontroller-A and Microcontroller-B should be inter connected with CAN bus Use power from USB Cable to the Microcontroller and to entire System and do the minimum Configuration to run a Microcontroller

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II. DIGITAL CAMERA

1. Specifications a) CCD Array Camera records the pictures using a charge coupled devices (CCD) array. The array consisting of large number of horizontal rows and vertical columns of CCD cells for the picture In each row of cells, a number of CCD cell unexposed to the picture but used for off-set corrections in the each-row output from the picture cells. b) IOs-Controllers, LCD display, Switches and buttons. A set of controllers to control shutter, flash, auto focus and eye-ball image control. LCD display for graphics and GUI Switches and buttons for inputs at camera. User gives commands for switching on the camera, flash, shutter, adjust brightness, contrast, color, save and transfer.
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When a button for opening the shutter is pressed, a flash lamp glows and a self-timer circuit switches off the lamp automatically.

c) Picture transfer Ports JPEG file for a picture can be copied or transferred to a memory stick using a controller A picture jpg can be copied to a computer connected through USB port controller.

2. Requirements a) Purpose Digital recording and display of pictures Processing to get the pictures of required brightness, contrast and color. Permanent saving of picture in file in a standard format at a flash-memory stick or card Transfer files to a computer and printer through a USB port

b) Inputs Intensity and color values for each picture horizontal and vertical row and columns of pixels in a picture frame. Intensity and color values for unexposed (dark) area in each horizontal rows and columns of pixels. User control inputs c) Outputs Encoded file for a picture Permanent store of the picture at a file on flash memory stick Screen display of picture from the file after decoding File output to an interfaced computer and printer.

Digital camera hardware architecture Microcontroller or ASIP (Application Specific Instruction Set Processor) Multiple processors (CCDSP, DSP, Pixel Processor and others) RAM for storing temporary variables and stack ROM for application codes and RTOS codes for scheduling the tasks Timer, Flash memory for storing user preferences, ADC, DAC and Interrupt controller USB controller Direct Memory Access controller LCD controller Battery and external charging circuit
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Digital Camera Software components CCD signal processing for off-set correction JPEG coding JPEG decoding Pixel processing before display Memory and file systems Light, flash and display device drivers LCD, USB and Bluetooth Port device- drivers for port operations for display, printer and computer communication control

3. Functions of the system

A color LCD dot matrix displays the picture before shooting enables manual adjustment of view of the picture. For shooting a shutter button pressed a charge-coupled device (CCD) array placed at the focus generates a byte stream in output after operations by ADC on analog output of each CCD cell. A file creates after encoding (compression) and pixel co-processing. The byte stream is preprocessed and then encoded in a standard format using a CODEC. The encoded picture file saved for permanent record. A memory stick saves the file. The file is used for display of recorded picture using a display processor and can be copied or transferred to a memory stick and to computer or printer connected through USB port. The LCD displays picture file after it is decoded (decompressed) using the CODEC. Text such as picture-title, shooting date and time and serial number are also displayed. The DAC gets the input from pixel processor, which gets the inputs from JPEG file for the saved images and also gets input directly from the CCDSP through pixel processor or the frame in present view USB port is used for transferring and storing pictures on a computer. Alternatively, Bluetooth or IR port can be used for interfacing the computer Design metrics Power Dissipation: Battery operation--Battery recharging after 400 pictures Resolution: High-resolution pictures--with options of 2592 1944 pixels Performance: Shooting a 4M pixels--still picture in 0.5 s. 25 pictures per m Process Deadlines: Exposing camera process maximum 0.1 s. --Flash synchronous with shutter opening and closing. Picture display latency maximum 0.5 s. User Interfaces: Graphic at LCD or touch screen display on LCD and commands by camera user through fingers on touch screen and switches and buttons
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III. Automatic Chocolate vending machine

1. Specifications

a) Alphanumeric keypad and Display Alphanumeric keypad on the top of the machine. A child interaction with it when buying a chocolate. Owner commands and interaction with the machine. LCD display unit on the top of the machine. Displays menus, entered text, pictograms, and welcome, thank and other messages, and time and date. Child as well as the ACVM owner GUIs with the machine using keypad and display.

b) Coin insertion and delivery slots, and Internet port Coin insertion slot so that the child can insert the coins to buy a chocolate Delivery slot to collect the chocolate, and coins if refunded Internet connection port so that owner can interact with ACVM from remote.

c) Reprogram of the codes and relocation of the codes The system ROM or flash or EPROM whenever the following happens: (i) the price of chocolate increases, (ii) The message lines or menus or advertisement graphics needs to be changed or (iii) machine features change.

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Basic system in ACVM block diagram

ACVM Requirements a) Purpose To sell chocolate through an ACVM from which children can automatically purchase the chocolates.
The payment is by inserting the coins of appropriate amount into a coin-slot

b) Inputs Coins of different denominations through a coin slot User commands c) Outputs Chocolate and signal to the system that subtracts the cost from the value of amount collected Display of the menus for GUIs, time and date, advertisements, welcome and thank messages

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Functions of the system A child sends commands to the system using a GUI (graphic user interface). GUI consists of the LCD display and keypad units. The child inserts the coins for cost of chocolate and the machine delivers the chocolate.
If the coins are not inserted as per the cost of chocolate in reasonable times then all coins are refunded.

If the coins are inserted of amount more than the cost of chocolate, the excess amount is refunded along with chocolate. The coins for the chocolates purchased collect inside the machine in a collector channel, so that owner can get the money, again through appropriate commands using the GUI. USB wireless modem enables communication through Internet to the ACVM owner

ACVM hardware Microcontroller or ASIP (Application Specific Instruction Set Processor) RAM for storing temporary variables and stack ROM for application codes and RTOS codes for scheduling the tasks Flash memory for storing user preferences, contact data, user address, user date of birth, user identification code, answers of FAQs ACVM specific hardware to sort the coins of different denomination and each denomination Main Power supply 220 V 50 Hz or 110 V 60 Hz. Internal circuits drive by supply of 5 V 50mA for electronic and 12 V 2 A for mechanical systems. Timer and Interrupt controller A TCP/IP port (Internet broadband connection) to the ACVM for remote control and for getting ACVM status reports by owner.

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ACVM Software components Keypad input read Display Read coins Interrupt handler and Interrupt Service routine Deliver chocolate TCP/IP stack processing TCP/IP stack communication

Software architecture (ISRs and Tasks) for ACVM

Design metrics Power Dissipation: As required by mechanical units, display units and computer system Performance: One chocolate in two minutes and 256 chocolates before next filling of chocolates into the machine.[Assumed] Process Deadlines: Machine waits for maximum 30 s for the coins and machine should deliver the chocolate within 60 s. User Interfaces: Graphic at LCD or touch screen display on LCD and commands by children or machine owner through fingers on keypad or touch screen

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IV.

SMART CARD
1. Requirements Purpose Enabling authentication and verification of card and card holder by a host Enabling GUI at host machine to interact with the card holder/user for the required transactions, for example, financial transactions with a bank or credit card transactions Inputs Received header and messages at IO port. Port IO from host through the antenna Outputs Transmitted headers and messages at Port IO through antenna

Functions of the system The card inserts at a host machine. The radiations from the host activate a charge pump at the card. The charge pump powers the SoC circuit consisting of card processor, memory, timer, interrupt handler and IO port. On power up, system reset signals reset Task to start. The reset Task sends the messages request Header and request start for waiting task, task_ReadPort. Task_ReadPort sends requests for host identification and reads through the Port_IO the host-identification message and request for card identification. task_PW sends through Port_IO the requested card identification after system receives the host identity through Port_IO. Task_Appl then runs required API. The requestApplClose message closes the application. The card can now be withdrawn All transactions between cardholder/ user now takes place through GUIs using at the host control panel (screen or touch screen or LCD display panel).

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Hardware Architecture A plastic card in ISO standard dimensions, 85.60 mm x 53.98 x 0.80 mm. It is an embedded SoC Microcontroller or a smart card processor Philips Smart XA or an ASIP Processor. Needs 8 kB+ internal RAM and 32 kB EPROM and 2/3 wire protected memory. CPU special features, for example, a security lock CPU locks certain section of memory protect 1 kB or more data from modification and access by any external source or instruction outside that memory Other way of protecting - CPU access through the physical addresses, which are different from logical address used in the program. Standard ROM 8 kB for usual or 64 kB when using advanced cryptographic features Full or part of ROM bus activates take place after a security check only. ROM Contains: i. Fabrication key and Personalization key ii. RTOS codes iii. Application codes iv. Utilization lock EEPROM or Flash scalable only needed part unlocks when storing P.I.N., unlocking P.I.N., access condition, card-user data, post activation application run generated nonvolatile data, invalidation lock to invalidate card after the expiry date or server instruction RAM run time temporary variables Chip-supply system using charge pump I/O system

Software Architecture Needs cryptographic software, needs special features in its operating system over and above the MS DOS or UNIX system features. Protected environment -OS stored in the protected part of ROM. A restricted run-time environment. OS, every method, class and run time library should be scalable. Optimum Code-size
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Limited use of data types; multidimensional arrays, long 64-bit integer and floating points and very limited use of the error handlers, exceptions, signals, serialization, debugging and profiling.

Three-layered file system for the data master file to store all file headers (file status, access conditions and the file lock) A header means file status, access conditions and the file lock. Dedicated file second file to hold a file grouping and headers of the immediate successor

Elementary file third file to hold the file header and its file data.

Design metrics Power Source and Dissipation: Radiation powered contact less Code size: optimum. card system memory needs should not exceed 64 kB memory. Limited use of data types; multidimensional arrays, long 64-bit integer and floating points and very limited use of the error handlers, exceptions, signals, serialization, debugging and profiling. File system(s): Three-layered file system for data File management: There is either a fixed length file management or a variable file length management with each file with a predefined offset. Microcontroller hardware: Generates distinct coded physical addresses for the program and data logical addresses. Protected once writable memory space Validity: System is embedded with expiry date, after which the card authorization through the hosts disables. Extendibility: The system expiry date is extendable by transactions and authorization of master control unit (for example, bank server). Performance: Less than 1s for transferring control from the card to host machine. Process Deadlines: None. User Interfaces: At host machine, graphic at LCD or touch screen display on LCD and commands for card holder (card user) transactions. STUDY THESE FOLLOWING 2 BY YOURSELF BY REFERING RAJKAMAL TEXBOOK I. II. MOBILE PHONE ROBOTS
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